1 /* 2 * OHCI HCD (Host Controller Driver) for USB. 3 * 4 * (C) Copyright 1999 Roman Weissgaerber <weissg@vienna.at> 5 * (C) Copyright 2000-2004 David Brownell <dbrownell@users.sourceforge.net> 6 * 7 * [ Initialisation is based on Linus' ] 8 * [ uhci code and gregs ohci fragments ] 9 * [ (C) Copyright 1999 Linus Torvalds ] 10 * [ (C) Copyright 1999 Gregory P. Smith] 11 * 12 * 13 * OHCI is the main "non-Intel/VIA" standard for USB 1.1 host controller 14 * interfaces (though some non-x86 Intel chips use it). It supports 15 * smarter hardware than UHCI. A download link for the spec available 16 * through the http://www.usb.org website. 17 * 18 * This file is licenced under the GPL. 19 */ 20 21 #include <linux/module.h> 22 #include <linux/moduleparam.h> 23 #include <linux/pci.h> 24 #include <linux/kernel.h> 25 #include <linux/delay.h> 26 #include <linux/ioport.h> 27 #include <linux/sched.h> 28 #include <linux/slab.h> 29 #include <linux/errno.h> 30 #include <linux/init.h> 31 #include <linux/timer.h> 32 #include <linux/list.h> 33 #include <linux/usb.h> 34 #include <linux/usb/otg.h> 35 #include <linux/dma-mapping.h> 36 #include <linux/dmapool.h> 37 #include <linux/reboot.h> 38 #include <linux/workqueue.h> 39 #include <linux/debugfs.h> 40 41 #include <asm/io.h> 42 #include <asm/irq.h> 43 #include <asm/system.h> 44 #include <asm/unaligned.h> 45 #include <asm/byteorder.h> 46 47 #include "../core/hcd.h" 48 49 #define DRIVER_VERSION "2006 August 04" 50 #define DRIVER_AUTHOR "Roman Weissgaerber, David Brownell" 51 #define DRIVER_DESC "USB 1.1 'Open' Host Controller (OHCI) Driver" 52 53 /*-------------------------------------------------------------------------*/ 54 55 #undef OHCI_VERBOSE_DEBUG /* not always helpful */ 56 57 /* For initializing controller (mask in an HCFS mode too) */ 58 #define OHCI_CONTROL_INIT OHCI_CTRL_CBSR 59 #define OHCI_INTR_INIT \ 60 (OHCI_INTR_MIE | OHCI_INTR_RHSC | OHCI_INTR_UE \ 61 | OHCI_INTR_RD | OHCI_INTR_WDH) 62 63 #ifdef __hppa__ 64 /* On PA-RISC, PDC can leave IR set incorrectly; ignore it there. */ 65 #define IR_DISABLE 66 #endif 67 68 #ifdef CONFIG_ARCH_OMAP 69 /* OMAP doesn't support IR (no SMM; not needed) */ 70 #define IR_DISABLE 71 #endif 72 73 /*-------------------------------------------------------------------------*/ 74 75 static const char hcd_name [] = "ohci_hcd"; 76 77 #define STATECHANGE_DELAY msecs_to_jiffies(300) 78 79 #include "ohci.h" 80 81 static void ohci_dump (struct ohci_hcd *ohci, int verbose); 82 static int ohci_init (struct ohci_hcd *ohci); 83 static void ohci_stop (struct usb_hcd *hcd); 84 85 #if defined(CONFIG_PM) || defined(CONFIG_PCI) 86 static int ohci_restart (struct ohci_hcd *ohci); 87 #endif 88 89 #ifdef CONFIG_PCI 90 static void quirk_amd_pll(int state); 91 static void amd_iso_dev_put(void); 92 #else 93 static inline void quirk_amd_pll(int state) 94 { 95 return; 96 } 97 static inline void amd_iso_dev_put(void) 98 { 99 return; 100 } 101 #endif 102 103 104 #include "ohci-hub.c" 105 #include "ohci-dbg.c" 106 #include "ohci-mem.c" 107 #include "ohci-q.c" 108 109 110 /* 111 * On architectures with edge-triggered interrupts we must never return 112 * IRQ_NONE. 113 */ 114 #if defined(CONFIG_SA1111) /* ... or other edge-triggered systems */ 115 #define IRQ_NOTMINE IRQ_HANDLED 116 #else 117 #define IRQ_NOTMINE IRQ_NONE 118 #endif 119 120 121 /* Some boards misreport power switching/overcurrent */ 122 static int distrust_firmware = 1; 123 module_param (distrust_firmware, bool, 0); 124 MODULE_PARM_DESC (distrust_firmware, 125 "true to distrust firmware power/overcurrent setup"); 126 127 /* Some boards leave IR set wrongly, since they fail BIOS/SMM handshakes */ 128 static int no_handshake = 0; 129 module_param (no_handshake, bool, 0); 130 MODULE_PARM_DESC (no_handshake, "true (not default) disables BIOS handshake"); 131 132 /*-------------------------------------------------------------------------*/ 133 134 /* 135 * queue up an urb for anything except the root hub 136 */ 137 static int ohci_urb_enqueue ( 138 struct usb_hcd *hcd, 139 struct urb *urb, 140 gfp_t mem_flags 141 ) { 142 struct ohci_hcd *ohci = hcd_to_ohci (hcd); 143 struct ed *ed; 144 urb_priv_t *urb_priv; 145 unsigned int pipe = urb->pipe; 146 int i, size = 0; 147 unsigned long flags; 148 int retval = 0; 149 150 #ifdef OHCI_VERBOSE_DEBUG 151 urb_print(urb, "SUB", usb_pipein(pipe), -EINPROGRESS); 152 #endif 153 154 /* every endpoint has a ed, locate and maybe (re)initialize it */ 155 if (! (ed = ed_get (ohci, urb->ep, urb->dev, pipe, urb->interval))) 156 return -ENOMEM; 157 158 /* for the private part of the URB we need the number of TDs (size) */ 159 switch (ed->type) { 160 case PIPE_CONTROL: 161 /* td_submit_urb() doesn't yet handle these */ 162 if (urb->transfer_buffer_length > 4096) 163 return -EMSGSIZE; 164 165 /* 1 TD for setup, 1 for ACK, plus ... */ 166 size = 2; 167 /* FALLTHROUGH */ 168 // case PIPE_INTERRUPT: 169 // case PIPE_BULK: 170 default: 171 /* one TD for every 4096 Bytes (can be upto 8K) */ 172 size += urb->transfer_buffer_length / 4096; 173 /* ... and for any remaining bytes ... */ 174 if ((urb->transfer_buffer_length % 4096) != 0) 175 size++; 176 /* ... and maybe a zero length packet to wrap it up */ 177 if (size == 0) 178 size++; 179 else if ((urb->transfer_flags & URB_ZERO_PACKET) != 0 180 && (urb->transfer_buffer_length 181 % usb_maxpacket (urb->dev, pipe, 182 usb_pipeout (pipe))) == 0) 183 size++; 184 break; 185 case PIPE_ISOCHRONOUS: /* number of packets from URB */ 186 size = urb->number_of_packets; 187 break; 188 } 189 190 /* allocate the private part of the URB */ 191 urb_priv = kzalloc (sizeof (urb_priv_t) + size * sizeof (struct td *), 192 mem_flags); 193 if (!urb_priv) 194 return -ENOMEM; 195 INIT_LIST_HEAD (&urb_priv->pending); 196 urb_priv->length = size; 197 urb_priv->ed = ed; 198 199 /* allocate the TDs (deferring hash chain updates) */ 200 for (i = 0; i < size; i++) { 201 urb_priv->td [i] = td_alloc (ohci, mem_flags); 202 if (!urb_priv->td [i]) { 203 urb_priv->length = i; 204 urb_free_priv (ohci, urb_priv); 205 return -ENOMEM; 206 } 207 } 208 209 spin_lock_irqsave (&ohci->lock, flags); 210 211 /* don't submit to a dead HC */ 212 if (!test_bit(HCD_FLAG_HW_ACCESSIBLE, &hcd->flags)) { 213 retval = -ENODEV; 214 goto fail; 215 } 216 if (!HC_IS_RUNNING(hcd->state)) { 217 retval = -ENODEV; 218 goto fail; 219 } 220 retval = usb_hcd_link_urb_to_ep(hcd, urb); 221 if (retval) 222 goto fail; 223 224 /* schedule the ed if needed */ 225 if (ed->state == ED_IDLE) { 226 retval = ed_schedule (ohci, ed); 227 if (retval < 0) { 228 usb_hcd_unlink_urb_from_ep(hcd, urb); 229 goto fail; 230 } 231 if (ed->type == PIPE_ISOCHRONOUS) { 232 u16 frame = ohci_frame_no(ohci); 233 234 /* delay a few frames before the first TD */ 235 frame += max_t (u16, 8, ed->interval); 236 frame &= ~(ed->interval - 1); 237 frame |= ed->branch; 238 urb->start_frame = frame; 239 240 /* yes, only URB_ISO_ASAP is supported, and 241 * urb->start_frame is never used as input. 242 */ 243 } 244 } else if (ed->type == PIPE_ISOCHRONOUS) 245 urb->start_frame = ed->last_iso + ed->interval; 246 247 /* fill the TDs and link them to the ed; and 248 * enable that part of the schedule, if needed 249 * and update count of queued periodic urbs 250 */ 251 urb->hcpriv = urb_priv; 252 td_submit_urb (ohci, urb); 253 254 fail: 255 if (retval) 256 urb_free_priv (ohci, urb_priv); 257 spin_unlock_irqrestore (&ohci->lock, flags); 258 return retval; 259 } 260 261 /* 262 * decouple the URB from the HC queues (TDs, urb_priv). 263 * reporting is always done 264 * asynchronously, and we might be dealing with an urb that's 265 * partially transferred, or an ED with other urbs being unlinked. 266 */ 267 static int ohci_urb_dequeue(struct usb_hcd *hcd, struct urb *urb, int status) 268 { 269 struct ohci_hcd *ohci = hcd_to_ohci (hcd); 270 unsigned long flags; 271 int rc; 272 273 #ifdef OHCI_VERBOSE_DEBUG 274 urb_print(urb, "UNLINK", 1, status); 275 #endif 276 277 spin_lock_irqsave (&ohci->lock, flags); 278 rc = usb_hcd_check_unlink_urb(hcd, urb, status); 279 if (rc) { 280 ; /* Do nothing */ 281 } else if (HC_IS_RUNNING(hcd->state)) { 282 urb_priv_t *urb_priv; 283 284 /* Unless an IRQ completed the unlink while it was being 285 * handed to us, flag it for unlink and giveback, and force 286 * some upcoming INTR_SF to call finish_unlinks() 287 */ 288 urb_priv = urb->hcpriv; 289 if (urb_priv) { 290 if (urb_priv->ed->state == ED_OPER) 291 start_ed_unlink (ohci, urb_priv->ed); 292 } 293 } else { 294 /* 295 * with HC dead, we won't respect hc queue pointers 296 * any more ... just clean up every urb's memory. 297 */ 298 if (urb->hcpriv) 299 finish_urb(ohci, urb, status); 300 } 301 spin_unlock_irqrestore (&ohci->lock, flags); 302 return rc; 303 } 304 305 /*-------------------------------------------------------------------------*/ 306 307 /* frees config/altsetting state for endpoints, 308 * including ED memory, dummy TD, and bulk/intr data toggle 309 */ 310 311 static void 312 ohci_endpoint_disable (struct usb_hcd *hcd, struct usb_host_endpoint *ep) 313 { 314 struct ohci_hcd *ohci = hcd_to_ohci (hcd); 315 unsigned long flags; 316 struct ed *ed = ep->hcpriv; 317 unsigned limit = 1000; 318 319 /* ASSERT: any requests/urbs are being unlinked */ 320 /* ASSERT: nobody can be submitting urbs for this any more */ 321 322 if (!ed) 323 return; 324 325 rescan: 326 spin_lock_irqsave (&ohci->lock, flags); 327 328 if (!HC_IS_RUNNING (hcd->state)) { 329 sanitize: 330 ed->state = ED_IDLE; 331 if (quirk_zfmicro(ohci) && ed->type == PIPE_INTERRUPT) 332 ohci->eds_scheduled--; 333 finish_unlinks (ohci, 0); 334 } 335 336 switch (ed->state) { 337 case ED_UNLINK: /* wait for hw to finish? */ 338 /* major IRQ delivery trouble loses INTR_SF too... */ 339 if (limit-- == 0) { 340 ohci_warn(ohci, "ED unlink timeout\n"); 341 if (quirk_zfmicro(ohci)) { 342 ohci_warn(ohci, "Attempting ZF TD recovery\n"); 343 ohci->ed_to_check = ed; 344 ohci->zf_delay = 2; 345 } 346 goto sanitize; 347 } 348 spin_unlock_irqrestore (&ohci->lock, flags); 349 schedule_timeout_uninterruptible(1); 350 goto rescan; 351 case ED_IDLE: /* fully unlinked */ 352 if (list_empty (&ed->td_list)) { 353 td_free (ohci, ed->dummy); 354 ed_free (ohci, ed); 355 break; 356 } 357 /* else FALL THROUGH */ 358 default: 359 /* caller was supposed to have unlinked any requests; 360 * that's not our job. can't recover; must leak ed. 361 */ 362 ohci_err (ohci, "leak ed %p (#%02x) state %d%s\n", 363 ed, ep->desc.bEndpointAddress, ed->state, 364 list_empty (&ed->td_list) ? "" : " (has tds)"); 365 td_free (ohci, ed->dummy); 366 break; 367 } 368 ep->hcpriv = NULL; 369 spin_unlock_irqrestore (&ohci->lock, flags); 370 return; 371 } 372 373 static int ohci_get_frame (struct usb_hcd *hcd) 374 { 375 struct ohci_hcd *ohci = hcd_to_ohci (hcd); 376 377 return ohci_frame_no(ohci); 378 } 379 380 static void ohci_usb_reset (struct ohci_hcd *ohci) 381 { 382 ohci->hc_control = ohci_readl (ohci, &ohci->regs->control); 383 ohci->hc_control &= OHCI_CTRL_RWC; 384 ohci_writel (ohci, ohci->hc_control, &ohci->regs->control); 385 } 386 387 /* ohci_shutdown forcibly disables IRQs and DMA, helping kexec and 388 * other cases where the next software may expect clean state from the 389 * "firmware". this is bus-neutral, unlike shutdown() methods. 390 */ 391 static void 392 ohci_shutdown (struct usb_hcd *hcd) 393 { 394 struct ohci_hcd *ohci; 395 396 ohci = hcd_to_ohci (hcd); 397 ohci_writel (ohci, OHCI_INTR_MIE, &ohci->regs->intrdisable); 398 ohci_usb_reset (ohci); 399 /* flush the writes */ 400 (void) ohci_readl (ohci, &ohci->regs->control); 401 } 402 403 static int check_ed(struct ohci_hcd *ohci, struct ed *ed) 404 { 405 return (hc32_to_cpu(ohci, ed->hwINFO) & ED_IN) != 0 406 && (hc32_to_cpu(ohci, ed->hwHeadP) & TD_MASK) 407 == (hc32_to_cpu(ohci, ed->hwTailP) & TD_MASK) 408 && !list_empty(&ed->td_list); 409 } 410 411 /* ZF Micro watchdog timer callback. The ZF Micro chipset sometimes completes 412 * an interrupt TD but neglects to add it to the donelist. On systems with 413 * this chipset, we need to periodically check the state of the queues to look 414 * for such "lost" TDs. 415 */ 416 static void unlink_watchdog_func(unsigned long _ohci) 417 { 418 unsigned long flags; 419 unsigned max; 420 unsigned seen_count = 0; 421 unsigned i; 422 struct ed **seen = NULL; 423 struct ohci_hcd *ohci = (struct ohci_hcd *) _ohci; 424 425 spin_lock_irqsave(&ohci->lock, flags); 426 max = ohci->eds_scheduled; 427 if (!max) 428 goto done; 429 430 if (ohci->ed_to_check) 431 goto out; 432 433 seen = kcalloc(max, sizeof *seen, GFP_ATOMIC); 434 if (!seen) 435 goto out; 436 437 for (i = 0; i < NUM_INTS; i++) { 438 struct ed *ed = ohci->periodic[i]; 439 440 while (ed) { 441 unsigned temp; 442 443 /* scan this branch of the periodic schedule tree */ 444 for (temp = 0; temp < seen_count; temp++) { 445 if (seen[temp] == ed) { 446 /* we've checked it and what's after */ 447 ed = NULL; 448 break; 449 } 450 } 451 if (!ed) 452 break; 453 seen[seen_count++] = ed; 454 if (!check_ed(ohci, ed)) { 455 ed = ed->ed_next; 456 continue; 457 } 458 459 /* HC's TD list is empty, but HCD sees at least one 460 * TD that's not been sent through the donelist. 461 */ 462 ohci->ed_to_check = ed; 463 ohci->zf_delay = 2; 464 465 /* The HC may wait until the next frame to report the 466 * TD as done through the donelist and INTR_WDH. (We 467 * just *assume* it's not a multi-TD interrupt URB; 468 * those could defer the IRQ more than one frame, using 469 * DI...) Check again after the next INTR_SF. 470 */ 471 ohci_writel(ohci, OHCI_INTR_SF, 472 &ohci->regs->intrstatus); 473 ohci_writel(ohci, OHCI_INTR_SF, 474 &ohci->regs->intrenable); 475 476 /* flush those writes */ 477 (void) ohci_readl(ohci, &ohci->regs->control); 478 479 goto out; 480 } 481 } 482 out: 483 kfree(seen); 484 if (ohci->eds_scheduled) 485 mod_timer(&ohci->unlink_watchdog, round_jiffies(jiffies + HZ)); 486 done: 487 spin_unlock_irqrestore(&ohci->lock, flags); 488 } 489 490 /*-------------------------------------------------------------------------* 491 * HC functions 492 *-------------------------------------------------------------------------*/ 493 494 /* init memory, and kick BIOS/SMM off */ 495 496 static int ohci_init (struct ohci_hcd *ohci) 497 { 498 int ret; 499 struct usb_hcd *hcd = ohci_to_hcd(ohci); 500 501 if (distrust_firmware) 502 ohci->flags |= OHCI_QUIRK_HUB_POWER; 503 504 disable (ohci); 505 ohci->regs = hcd->regs; 506 507 /* REVISIT this BIOS handshake is now moved into PCI "quirks", and 508 * was never needed for most non-PCI systems ... remove the code? 509 */ 510 511 #ifndef IR_DISABLE 512 /* SMM owns the HC? not for long! */ 513 if (!no_handshake && ohci_readl (ohci, 514 &ohci->regs->control) & OHCI_CTRL_IR) { 515 u32 temp; 516 517 ohci_dbg (ohci, "USB HC TakeOver from BIOS/SMM\n"); 518 519 /* this timeout is arbitrary. we make it long, so systems 520 * depending on usb keyboards may be usable even if the 521 * BIOS/SMM code seems pretty broken. 522 */ 523 temp = 500; /* arbitrary: five seconds */ 524 525 ohci_writel (ohci, OHCI_INTR_OC, &ohci->regs->intrenable); 526 ohci_writel (ohci, OHCI_OCR, &ohci->regs->cmdstatus); 527 while (ohci_readl (ohci, &ohci->regs->control) & OHCI_CTRL_IR) { 528 msleep (10); 529 if (--temp == 0) { 530 ohci_err (ohci, "USB HC takeover failed!" 531 " (BIOS/SMM bug)\n"); 532 return -EBUSY; 533 } 534 } 535 ohci_usb_reset (ohci); 536 } 537 #endif 538 539 /* Disable HC interrupts */ 540 ohci_writel (ohci, OHCI_INTR_MIE, &ohci->regs->intrdisable); 541 542 /* flush the writes, and save key bits like RWC */ 543 if (ohci_readl (ohci, &ohci->regs->control) & OHCI_CTRL_RWC) 544 ohci->hc_control |= OHCI_CTRL_RWC; 545 546 /* Read the number of ports unless overridden */ 547 if (ohci->num_ports == 0) 548 ohci->num_ports = roothub_a(ohci) & RH_A_NDP; 549 550 if (ohci->hcca) 551 return 0; 552 553 ohci->hcca = dma_alloc_coherent (hcd->self.controller, 554 sizeof *ohci->hcca, &ohci->hcca_dma, 0); 555 if (!ohci->hcca) 556 return -ENOMEM; 557 558 if ((ret = ohci_mem_init (ohci)) < 0) 559 ohci_stop (hcd); 560 else { 561 create_debug_files (ohci); 562 } 563 564 return ret; 565 } 566 567 /*-------------------------------------------------------------------------*/ 568 569 /* Start an OHCI controller, set the BUS operational 570 * resets USB and controller 571 * enable interrupts 572 */ 573 static int ohci_run (struct ohci_hcd *ohci) 574 { 575 u32 mask, temp; 576 int first = ohci->fminterval == 0; 577 struct usb_hcd *hcd = ohci_to_hcd(ohci); 578 579 disable (ohci); 580 581 /* boot firmware should have set this up (5.1.1.3.1) */ 582 if (first) { 583 584 temp = ohci_readl (ohci, &ohci->regs->fminterval); 585 ohci->fminterval = temp & 0x3fff; 586 if (ohci->fminterval != FI) 587 ohci_dbg (ohci, "fminterval delta %d\n", 588 ohci->fminterval - FI); 589 ohci->fminterval |= FSMP (ohci->fminterval) << 16; 590 /* also: power/overcurrent flags in roothub.a */ 591 } 592 593 /* Reset USB nearly "by the book". RemoteWakeupConnected was 594 * saved if boot firmware (BIOS/SMM/...) told us it's connected, 595 * or if bus glue did the same (e.g. for PCI add-in cards with 596 * PCI PM support). 597 */ 598 if ((ohci->hc_control & OHCI_CTRL_RWC) != 0 599 && !device_may_wakeup(hcd->self.controller)) 600 device_init_wakeup(hcd->self.controller, 1); 601 602 switch (ohci->hc_control & OHCI_CTRL_HCFS) { 603 case OHCI_USB_OPER: 604 temp = 0; 605 break; 606 case OHCI_USB_SUSPEND: 607 case OHCI_USB_RESUME: 608 ohci->hc_control &= OHCI_CTRL_RWC; 609 ohci->hc_control |= OHCI_USB_RESUME; 610 temp = 10 /* msec wait */; 611 break; 612 // case OHCI_USB_RESET: 613 default: 614 ohci->hc_control &= OHCI_CTRL_RWC; 615 ohci->hc_control |= OHCI_USB_RESET; 616 temp = 50 /* msec wait */; 617 break; 618 } 619 ohci_writel (ohci, ohci->hc_control, &ohci->regs->control); 620 // flush the writes 621 (void) ohci_readl (ohci, &ohci->regs->control); 622 msleep(temp); 623 624 memset (ohci->hcca, 0, sizeof (struct ohci_hcca)); 625 626 /* 2msec timelimit here means no irqs/preempt */ 627 spin_lock_irq (&ohci->lock); 628 629 retry: 630 /* HC Reset requires max 10 us delay */ 631 ohci_writel (ohci, OHCI_HCR, &ohci->regs->cmdstatus); 632 temp = 30; /* ... allow extra time */ 633 while ((ohci_readl (ohci, &ohci->regs->cmdstatus) & OHCI_HCR) != 0) { 634 if (--temp == 0) { 635 spin_unlock_irq (&ohci->lock); 636 ohci_err (ohci, "USB HC reset timed out!\n"); 637 return -1; 638 } 639 udelay (1); 640 } 641 642 /* now we're in the SUSPEND state ... must go OPERATIONAL 643 * within 2msec else HC enters RESUME 644 * 645 * ... but some hardware won't init fmInterval "by the book" 646 * (SiS, OPTi ...), so reset again instead. SiS doesn't need 647 * this if we write fmInterval after we're OPERATIONAL. 648 * Unclear about ALi, ServerWorks, and others ... this could 649 * easily be a longstanding bug in chip init on Linux. 650 */ 651 if (ohci->flags & OHCI_QUIRK_INITRESET) { 652 ohci_writel (ohci, ohci->hc_control, &ohci->regs->control); 653 // flush those writes 654 (void) ohci_readl (ohci, &ohci->regs->control); 655 } 656 657 /* Tell the controller where the control and bulk lists are 658 * The lists are empty now. */ 659 ohci_writel (ohci, 0, &ohci->regs->ed_controlhead); 660 ohci_writel (ohci, 0, &ohci->regs->ed_bulkhead); 661 662 /* a reset clears this */ 663 ohci_writel (ohci, (u32) ohci->hcca_dma, &ohci->regs->hcca); 664 665 periodic_reinit (ohci); 666 667 /* some OHCI implementations are finicky about how they init. 668 * bogus values here mean not even enumeration could work. 669 */ 670 if ((ohci_readl (ohci, &ohci->regs->fminterval) & 0x3fff0000) == 0 671 || !ohci_readl (ohci, &ohci->regs->periodicstart)) { 672 if (!(ohci->flags & OHCI_QUIRK_INITRESET)) { 673 ohci->flags |= OHCI_QUIRK_INITRESET; 674 ohci_dbg (ohci, "enabling initreset quirk\n"); 675 goto retry; 676 } 677 spin_unlock_irq (&ohci->lock); 678 ohci_err (ohci, "init err (%08x %04x)\n", 679 ohci_readl (ohci, &ohci->regs->fminterval), 680 ohci_readl (ohci, &ohci->regs->periodicstart)); 681 return -EOVERFLOW; 682 } 683 684 /* use rhsc irqs after khubd is fully initialized */ 685 hcd->poll_rh = 1; 686 hcd->uses_new_polling = 1; 687 688 /* start controller operations */ 689 ohci->hc_control &= OHCI_CTRL_RWC; 690 ohci->hc_control |= OHCI_CONTROL_INIT | OHCI_USB_OPER; 691 ohci_writel (ohci, ohci->hc_control, &ohci->regs->control); 692 hcd->state = HC_STATE_RUNNING; 693 694 /* wake on ConnectStatusChange, matching external hubs */ 695 ohci_writel (ohci, RH_HS_DRWE, &ohci->regs->roothub.status); 696 697 /* Choose the interrupts we care about now, others later on demand */ 698 mask = OHCI_INTR_INIT; 699 ohci_writel (ohci, ~0, &ohci->regs->intrstatus); 700 ohci_writel (ohci, mask, &ohci->regs->intrenable); 701 702 /* handle root hub init quirks ... */ 703 temp = roothub_a (ohci); 704 temp &= ~(RH_A_PSM | RH_A_OCPM); 705 if (ohci->flags & OHCI_QUIRK_SUPERIO) { 706 /* NSC 87560 and maybe others */ 707 temp |= RH_A_NOCP; 708 temp &= ~(RH_A_POTPGT | RH_A_NPS); 709 ohci_writel (ohci, temp, &ohci->regs->roothub.a); 710 } else if ((ohci->flags & OHCI_QUIRK_AMD756) || 711 (ohci->flags & OHCI_QUIRK_HUB_POWER)) { 712 /* hub power always on; required for AMD-756 and some 713 * Mac platforms. ganged overcurrent reporting, if any. 714 */ 715 temp |= RH_A_NPS; 716 ohci_writel (ohci, temp, &ohci->regs->roothub.a); 717 } 718 ohci_writel (ohci, RH_HS_LPSC, &ohci->regs->roothub.status); 719 ohci_writel (ohci, (temp & RH_A_NPS) ? 0 : RH_B_PPCM, 720 &ohci->regs->roothub.b); 721 // flush those writes 722 (void) ohci_readl (ohci, &ohci->regs->control); 723 724 ohci->next_statechange = jiffies + STATECHANGE_DELAY; 725 spin_unlock_irq (&ohci->lock); 726 727 // POTPGT delay is bits 24-31, in 2 ms units. 728 mdelay ((temp >> 23) & 0x1fe); 729 hcd->state = HC_STATE_RUNNING; 730 731 if (quirk_zfmicro(ohci)) { 732 /* Create timer to watch for bad queue state on ZF Micro */ 733 setup_timer(&ohci->unlink_watchdog, unlink_watchdog_func, 734 (unsigned long) ohci); 735 736 ohci->eds_scheduled = 0; 737 ohci->ed_to_check = NULL; 738 } 739 740 ohci_dump (ohci, 1); 741 742 return 0; 743 } 744 745 /*-------------------------------------------------------------------------*/ 746 747 /* an interrupt happens */ 748 749 static irqreturn_t ohci_irq (struct usb_hcd *hcd) 750 { 751 struct ohci_hcd *ohci = hcd_to_ohci (hcd); 752 struct ohci_regs __iomem *regs = ohci->regs; 753 int ints; 754 755 /* Read interrupt status (and flush pending writes). We ignore the 756 * optimization of checking the LSB of hcca->done_head; it doesn't 757 * work on all systems (edge triggering for OHCI can be a factor). 758 */ 759 ints = ohci_readl(ohci, ®s->intrstatus); 760 761 /* Check for an all 1's result which is a typical consequence 762 * of dead, unclocked, or unplugged (CardBus...) devices 763 */ 764 if (ints == ~(u32)0) { 765 disable (ohci); 766 ohci_dbg (ohci, "device removed!\n"); 767 return IRQ_HANDLED; 768 } 769 770 /* We only care about interrupts that are enabled */ 771 ints &= ohci_readl(ohci, ®s->intrenable); 772 773 /* interrupt for some other device? */ 774 if (ints == 0) 775 return IRQ_NOTMINE; 776 777 if (ints & OHCI_INTR_UE) { 778 // e.g. due to PCI Master/Target Abort 779 if (quirk_nec(ohci)) { 780 /* Workaround for a silicon bug in some NEC chips used 781 * in Apple's PowerBooks. Adapted from Darwin code. 782 */ 783 ohci_err (ohci, "OHCI Unrecoverable Error, scheduling NEC chip restart\n"); 784 785 ohci_writel (ohci, OHCI_INTR_UE, ®s->intrdisable); 786 787 schedule_work (&ohci->nec_work); 788 } else { 789 disable (ohci); 790 ohci_err (ohci, "OHCI Unrecoverable Error, disabled\n"); 791 } 792 793 ohci_dump (ohci, 1); 794 ohci_usb_reset (ohci); 795 } 796 797 if (ints & OHCI_INTR_RHSC) { 798 ohci_vdbg(ohci, "rhsc\n"); 799 ohci->next_statechange = jiffies + STATECHANGE_DELAY; 800 ohci_writel(ohci, OHCI_INTR_RD | OHCI_INTR_RHSC, 801 ®s->intrstatus); 802 803 /* NOTE: Vendors didn't always make the same implementation 804 * choices for RHSC. Many followed the spec; RHSC triggers 805 * on an edge, like setting and maybe clearing a port status 806 * change bit. With others it's level-triggered, active 807 * until khubd clears all the port status change bits. We'll 808 * always disable it here and rely on polling until khubd 809 * re-enables it. 810 */ 811 ohci_writel(ohci, OHCI_INTR_RHSC, ®s->intrdisable); 812 usb_hcd_poll_rh_status(hcd); 813 } 814 815 /* For connect and disconnect events, we expect the controller 816 * to turn on RHSC along with RD. But for remote wakeup events 817 * this might not happen. 818 */ 819 else if (ints & OHCI_INTR_RD) { 820 ohci_vdbg(ohci, "resume detect\n"); 821 ohci_writel(ohci, OHCI_INTR_RD, ®s->intrstatus); 822 hcd->poll_rh = 1; 823 if (ohci->autostop) { 824 spin_lock (&ohci->lock); 825 ohci_rh_resume (ohci); 826 spin_unlock (&ohci->lock); 827 } else 828 usb_hcd_resume_root_hub(hcd); 829 } 830 831 if (ints & OHCI_INTR_WDH) { 832 spin_lock (&ohci->lock); 833 dl_done_list (ohci); 834 spin_unlock (&ohci->lock); 835 } 836 837 if (quirk_zfmicro(ohci) && (ints & OHCI_INTR_SF)) { 838 spin_lock(&ohci->lock); 839 if (ohci->ed_to_check) { 840 struct ed *ed = ohci->ed_to_check; 841 842 if (check_ed(ohci, ed)) { 843 /* HC thinks the TD list is empty; HCD knows 844 * at least one TD is outstanding 845 */ 846 if (--ohci->zf_delay == 0) { 847 struct td *td = list_entry( 848 ed->td_list.next, 849 struct td, td_list); 850 ohci_warn(ohci, 851 "Reclaiming orphan TD %p\n", 852 td); 853 takeback_td(ohci, td); 854 ohci->ed_to_check = NULL; 855 } 856 } else 857 ohci->ed_to_check = NULL; 858 } 859 spin_unlock(&ohci->lock); 860 } 861 862 /* could track INTR_SO to reduce available PCI/... bandwidth */ 863 864 /* handle any pending URB/ED unlinks, leaving INTR_SF enabled 865 * when there's still unlinking to be done (next frame). 866 */ 867 spin_lock (&ohci->lock); 868 if (ohci->ed_rm_list) 869 finish_unlinks (ohci, ohci_frame_no(ohci)); 870 if ((ints & OHCI_INTR_SF) != 0 871 && !ohci->ed_rm_list 872 && !ohci->ed_to_check 873 && HC_IS_RUNNING(hcd->state)) 874 ohci_writel (ohci, OHCI_INTR_SF, ®s->intrdisable); 875 spin_unlock (&ohci->lock); 876 877 if (HC_IS_RUNNING(hcd->state)) { 878 ohci_writel (ohci, ints, ®s->intrstatus); 879 ohci_writel (ohci, OHCI_INTR_MIE, ®s->intrenable); 880 // flush those writes 881 (void) ohci_readl (ohci, &ohci->regs->control); 882 } 883 884 return IRQ_HANDLED; 885 } 886 887 /*-------------------------------------------------------------------------*/ 888 889 static void ohci_stop (struct usb_hcd *hcd) 890 { 891 struct ohci_hcd *ohci = hcd_to_ohci (hcd); 892 893 ohci_dump (ohci, 1); 894 895 flush_scheduled_work(); 896 897 ohci_usb_reset (ohci); 898 ohci_writel (ohci, OHCI_INTR_MIE, &ohci->regs->intrdisable); 899 free_irq(hcd->irq, hcd); 900 hcd->irq = -1; 901 902 if (quirk_zfmicro(ohci)) 903 del_timer(&ohci->unlink_watchdog); 904 if (quirk_amdiso(ohci)) 905 amd_iso_dev_put(); 906 907 remove_debug_files (ohci); 908 ohci_mem_cleanup (ohci); 909 if (ohci->hcca) { 910 dma_free_coherent (hcd->self.controller, 911 sizeof *ohci->hcca, 912 ohci->hcca, ohci->hcca_dma); 913 ohci->hcca = NULL; 914 ohci->hcca_dma = 0; 915 } 916 } 917 918 /*-------------------------------------------------------------------------*/ 919 920 #if defined(CONFIG_PM) || defined(CONFIG_PCI) 921 922 /* must not be called from interrupt context */ 923 static int ohci_restart (struct ohci_hcd *ohci) 924 { 925 int temp; 926 int i; 927 struct urb_priv *priv; 928 929 spin_lock_irq(&ohci->lock); 930 disable (ohci); 931 932 /* Recycle any "live" eds/tds (and urbs). */ 933 if (!list_empty (&ohci->pending)) 934 ohci_dbg(ohci, "abort schedule...\n"); 935 list_for_each_entry (priv, &ohci->pending, pending) { 936 struct urb *urb = priv->td[0]->urb; 937 struct ed *ed = priv->ed; 938 939 switch (ed->state) { 940 case ED_OPER: 941 ed->state = ED_UNLINK; 942 ed->hwINFO |= cpu_to_hc32(ohci, ED_DEQUEUE); 943 ed_deschedule (ohci, ed); 944 945 ed->ed_next = ohci->ed_rm_list; 946 ed->ed_prev = NULL; 947 ohci->ed_rm_list = ed; 948 /* FALLTHROUGH */ 949 case ED_UNLINK: 950 break; 951 default: 952 ohci_dbg(ohci, "bogus ed %p state %d\n", 953 ed, ed->state); 954 } 955 956 if (!urb->unlinked) 957 urb->unlinked = -ESHUTDOWN; 958 } 959 finish_unlinks (ohci, 0); 960 spin_unlock_irq(&ohci->lock); 961 962 /* paranoia, in case that didn't work: */ 963 964 /* empty the interrupt branches */ 965 for (i = 0; i < NUM_INTS; i++) ohci->load [i] = 0; 966 for (i = 0; i < NUM_INTS; i++) ohci->hcca->int_table [i] = 0; 967 968 /* no EDs to remove */ 969 ohci->ed_rm_list = NULL; 970 971 /* empty control and bulk lists */ 972 ohci->ed_controltail = NULL; 973 ohci->ed_bulktail = NULL; 974 975 if ((temp = ohci_run (ohci)) < 0) { 976 ohci_err (ohci, "can't restart, %d\n", temp); 977 return temp; 978 } 979 ohci_dbg(ohci, "restart complete\n"); 980 return 0; 981 } 982 983 #endif 984 985 /*-------------------------------------------------------------------------*/ 986 987 #define DRIVER_INFO DRIVER_VERSION " " DRIVER_DESC 988 989 MODULE_AUTHOR (DRIVER_AUTHOR); 990 MODULE_DESCRIPTION (DRIVER_INFO); 991 MODULE_LICENSE ("GPL"); 992 993 #ifdef CONFIG_PCI 994 #include "ohci-pci.c" 995 #define PCI_DRIVER ohci_pci_driver 996 #endif 997 998 #if defined(CONFIG_ARCH_SA1100) && defined(CONFIG_SA1111) 999 #include "ohci-sa1111.c" 1000 #define SA1111_DRIVER ohci_hcd_sa1111_driver 1001 #endif 1002 1003 #ifdef CONFIG_ARCH_S3C2410 1004 #include "ohci-s3c2410.c" 1005 #define PLATFORM_DRIVER ohci_hcd_s3c2410_driver 1006 #endif 1007 1008 #ifdef CONFIG_ARCH_OMAP 1009 #include "ohci-omap.c" 1010 #define PLATFORM_DRIVER ohci_hcd_omap_driver 1011 #endif 1012 1013 #ifdef CONFIG_ARCH_LH7A404 1014 #include "ohci-lh7a404.c" 1015 #define PLATFORM_DRIVER ohci_hcd_lh7a404_driver 1016 #endif 1017 1018 #if defined(CONFIG_PXA27x) || defined(CONFIG_PXA3xx) 1019 #include "ohci-pxa27x.c" 1020 #define PLATFORM_DRIVER ohci_hcd_pxa27x_driver 1021 #endif 1022 1023 #ifdef CONFIG_ARCH_EP93XX 1024 #include "ohci-ep93xx.c" 1025 #define PLATFORM_DRIVER ohci_hcd_ep93xx_driver 1026 #endif 1027 1028 #ifdef CONFIG_SOC_AU1X00 1029 #include "ohci-au1xxx.c" 1030 #define PLATFORM_DRIVER ohci_hcd_au1xxx_driver 1031 #endif 1032 1033 #ifdef CONFIG_PNX8550 1034 #include "ohci-pnx8550.c" 1035 #define PLATFORM_DRIVER ohci_hcd_pnx8550_driver 1036 #endif 1037 1038 #ifdef CONFIG_USB_OHCI_HCD_PPC_SOC 1039 #include "ohci-ppc-soc.c" 1040 #define PLATFORM_DRIVER ohci_hcd_ppc_soc_driver 1041 #endif 1042 1043 #ifdef CONFIG_ARCH_AT91 1044 #include "ohci-at91.c" 1045 #define PLATFORM_DRIVER ohci_hcd_at91_driver 1046 #endif 1047 1048 #ifdef CONFIG_ARCH_PNX4008 1049 #include "ohci-pnx4008.c" 1050 #define PLATFORM_DRIVER usb_hcd_pnx4008_driver 1051 #endif 1052 1053 #if defined(CONFIG_CPU_SUBTYPE_SH7720) || \ 1054 defined(CONFIG_CPU_SUBTYPE_SH7721) || \ 1055 defined(CONFIG_CPU_SUBTYPE_SH7763) 1056 #include "ohci-sh.c" 1057 #define PLATFORM_DRIVER ohci_hcd_sh_driver 1058 #endif 1059 1060 1061 #ifdef CONFIG_USB_OHCI_HCD_PPC_OF 1062 #include "ohci-ppc-of.c" 1063 #define OF_PLATFORM_DRIVER ohci_hcd_ppc_of_driver 1064 #endif 1065 1066 #ifdef CONFIG_PPC_PS3 1067 #include "ohci-ps3.c" 1068 #define PS3_SYSTEM_BUS_DRIVER ps3_ohci_driver 1069 #endif 1070 1071 #ifdef CONFIG_USB_OHCI_HCD_SSB 1072 #include "ohci-ssb.c" 1073 #define SSB_OHCI_DRIVER ssb_ohci_driver 1074 #endif 1075 1076 #ifdef CONFIG_MFD_SM501 1077 #include "ohci-sm501.c" 1078 #define SM501_OHCI_DRIVER ohci_hcd_sm501_driver 1079 #endif 1080 1081 #if !defined(PCI_DRIVER) && \ 1082 !defined(PLATFORM_DRIVER) && \ 1083 !defined(OF_PLATFORM_DRIVER) && \ 1084 !defined(SA1111_DRIVER) && \ 1085 !defined(PS3_SYSTEM_BUS_DRIVER) && \ 1086 !defined(SM501_OHCI_DRIVER) && \ 1087 !defined(SSB_OHCI_DRIVER) 1088 #error "missing bus glue for ohci-hcd" 1089 #endif 1090 1091 static int __init ohci_hcd_mod_init(void) 1092 { 1093 int retval = 0; 1094 1095 if (usb_disabled()) 1096 return -ENODEV; 1097 1098 printk (KERN_DEBUG "%s: " DRIVER_INFO "\n", hcd_name); 1099 pr_debug ("%s: block sizes: ed %Zd td %Zd\n", hcd_name, 1100 sizeof (struct ed), sizeof (struct td)); 1101 1102 #ifdef DEBUG 1103 ohci_debug_root = debugfs_create_dir("ohci", NULL); 1104 if (!ohci_debug_root) { 1105 retval = -ENOENT; 1106 goto error_debug; 1107 } 1108 #endif 1109 1110 #ifdef PS3_SYSTEM_BUS_DRIVER 1111 retval = ps3_ohci_driver_register(&PS3_SYSTEM_BUS_DRIVER); 1112 if (retval < 0) 1113 goto error_ps3; 1114 #endif 1115 1116 #ifdef PLATFORM_DRIVER 1117 retval = platform_driver_register(&PLATFORM_DRIVER); 1118 if (retval < 0) 1119 goto error_platform; 1120 #endif 1121 1122 #ifdef OF_PLATFORM_DRIVER 1123 retval = of_register_platform_driver(&OF_PLATFORM_DRIVER); 1124 if (retval < 0) 1125 goto error_of_platform; 1126 #endif 1127 1128 #ifdef SA1111_DRIVER 1129 retval = sa1111_driver_register(&SA1111_DRIVER); 1130 if (retval < 0) 1131 goto error_sa1111; 1132 #endif 1133 1134 #ifdef PCI_DRIVER 1135 retval = pci_register_driver(&PCI_DRIVER); 1136 if (retval < 0) 1137 goto error_pci; 1138 #endif 1139 1140 #ifdef SSB_OHCI_DRIVER 1141 retval = ssb_driver_register(&SSB_OHCI_DRIVER); 1142 if (retval) 1143 goto error_ssb; 1144 #endif 1145 1146 #ifdef SM501_OHCI_DRIVER 1147 retval = platform_driver_register(&SM501_OHCI_DRIVER); 1148 if (retval < 0) 1149 goto error_sm501; 1150 #endif 1151 1152 return retval; 1153 1154 /* Error path */ 1155 #ifdef SM501_OHCI_DRIVER 1156 error_sm501: 1157 #endif 1158 #ifdef SSB_OHCI_DRIVER 1159 error_ssb: 1160 #endif 1161 #ifdef PCI_DRIVER 1162 pci_unregister_driver(&PCI_DRIVER); 1163 error_pci: 1164 #endif 1165 #ifdef SA1111_DRIVER 1166 sa1111_driver_unregister(&SA1111_DRIVER); 1167 error_sa1111: 1168 #endif 1169 #ifdef OF_PLATFORM_DRIVER 1170 of_unregister_platform_driver(&OF_PLATFORM_DRIVER); 1171 error_of_platform: 1172 #endif 1173 #ifdef PLATFORM_DRIVER 1174 platform_driver_unregister(&PLATFORM_DRIVER); 1175 error_platform: 1176 #endif 1177 #ifdef PS3_SYSTEM_BUS_DRIVER 1178 ps3_ohci_driver_unregister(&PS3_SYSTEM_BUS_DRIVER); 1179 error_ps3: 1180 #endif 1181 #ifdef DEBUG 1182 debugfs_remove(ohci_debug_root); 1183 ohci_debug_root = NULL; 1184 error_debug: 1185 #endif 1186 1187 return retval; 1188 } 1189 module_init(ohci_hcd_mod_init); 1190 1191 static void __exit ohci_hcd_mod_exit(void) 1192 { 1193 #ifdef SM501_OHCI_DRIVER 1194 platform_driver_unregister(&SM501_OHCI_DRIVER); 1195 #endif 1196 #ifdef SSB_OHCI_DRIVER 1197 ssb_driver_unregister(&SSB_OHCI_DRIVER); 1198 #endif 1199 #ifdef PCI_DRIVER 1200 pci_unregister_driver(&PCI_DRIVER); 1201 #endif 1202 #ifdef SA1111_DRIVER 1203 sa1111_driver_unregister(&SA1111_DRIVER); 1204 #endif 1205 #ifdef OF_PLATFORM_DRIVER 1206 of_unregister_platform_driver(&OF_PLATFORM_DRIVER); 1207 #endif 1208 #ifdef PLATFORM_DRIVER 1209 platform_driver_unregister(&PLATFORM_DRIVER); 1210 #endif 1211 #ifdef PS3_SYSTEM_BUS_DRIVER 1212 ps3_ohci_driver_unregister(&PS3_SYSTEM_BUS_DRIVER); 1213 #endif 1214 #ifdef DEBUG 1215 debugfs_remove(ohci_debug_root); 1216 #endif 1217 } 1218 module_exit(ohci_hcd_mod_exit); 1219 1220