1 /* SPDX-License-Identifier: GPL-2.0 */ 2 /* 3 * ISP1362 HCD (Host Controller Driver) for USB. 4 * 5 * COPYRIGHT (C) by L. Wassmann <LW@KARO-electronics.de> 6 */ 7 8 /* ------------------------------------------------------------------------- */ 9 /* 10 * Platform specific compile time options 11 */ 12 #if defined(CONFIG_BLACKFIN) 13 14 #include <linux/io.h> 15 #define USE_32BIT 0 16 #define MAX_ROOT_PORTS 2 17 #define USE_PLATFORM_DELAY 0 18 #define USE_NDELAY 1 19 20 #define DUMMY_DELAY_ACCESS \ 21 do { \ 22 bfin_read16(ASYNC_BANK0_BASE); \ 23 bfin_read16(ASYNC_BANK0_BASE); \ 24 bfin_read16(ASYNC_BANK0_BASE); \ 25 } while (0) 26 27 #undef insw 28 #undef outsw 29 30 #define insw delayed_insw 31 #define outsw delayed_outsw 32 33 static inline void delayed_outsw(unsigned int addr, void *buf, int len) 34 { 35 unsigned short *bp = (unsigned short *)buf; 36 while (len--) { 37 DUMMY_DELAY_ACCESS; 38 outw(*bp++, addr); 39 } 40 } 41 42 static inline void delayed_insw(unsigned int addr, void *buf, int len) 43 { 44 unsigned short *bp = (unsigned short *)buf; 45 while (len--) { 46 DUMMY_DELAY_ACCESS; 47 *bp++ = inw(addr); 48 } 49 } 50 51 #else 52 53 #define MAX_ROOT_PORTS 2 54 55 #define USE_32BIT 0 56 57 /* These options are mutually eclusive */ 58 #define USE_PLATFORM_DELAY 0 59 #define USE_NDELAY 0 60 61 #define DUMMY_DELAY_ACCESS do {} while (0) 62 63 #endif 64 65 66 /* ------------------------------------------------------------------------- */ 67 68 #define USB_RESET_WIDTH 50 69 #define MAX_XFER_SIZE 1023 70 71 /* Buffer sizes */ 72 #define ISP1362_BUF_SIZE 4096 73 #define ISP1362_ISTL_BUFSIZE 512 74 #define ISP1362_INTL_BLKSIZE 64 75 #define ISP1362_INTL_BUFFERS 16 76 #define ISP1362_ATL_BLKSIZE 64 77 78 #define ISP1362_REG_WRITE_OFFSET 0x80 79 80 #define REG_WIDTH_16 0x000 81 #define REG_WIDTH_32 0x100 82 #define REG_WIDTH_MASK 0x100 83 #define REG_NO_MASK 0x0ff 84 85 #ifdef ISP1362_DEBUG 86 typedef const unsigned int isp1362_reg_t; 87 88 #define REG_ACCESS_R 0x200 89 #define REG_ACCESS_W 0x400 90 #define REG_ACCESS_RW 0x600 91 #define REG_ACCESS_MASK 0x600 92 93 #define ISP1362_REG_NO(r) ((r) & REG_NO_MASK) 94 95 #define ISP1362_REG(name, addr, width, rw) \ 96 static isp1362_reg_t ISP1362_REG_##name = ((addr) | (width) | (rw)) 97 98 #define REG_ACCESS_TEST(r) BUG_ON(((r) & ISP1362_REG_WRITE_OFFSET) && !((r) & REG_ACCESS_W)) 99 #define REG_WIDTH_TEST(r, w) BUG_ON(((r) & REG_WIDTH_MASK) != (w)) 100 #else 101 typedef const unsigned char isp1362_reg_t; 102 #define ISP1362_REG_NO(r) (r) 103 104 #define ISP1362_REG(name, addr, width, rw) \ 105 static isp1362_reg_t ISP1362_REG_##name = addr 106 107 #define REG_ACCESS_TEST(r) do {} while (0) 108 #define REG_WIDTH_TEST(r, w) do {} while (0) 109 #endif 110 111 /* OHCI compatible registers */ 112 /* 113 * Note: Some of the ISP1362 'OHCI' registers implement only 114 * a subset of the bits defined in the OHCI spec. 115 * 116 * Bitmasks for the individual bits of these registers are defined in "ohci.h" 117 */ 118 ISP1362_REG(HCREVISION, 0x00, REG_WIDTH_32, REG_ACCESS_R); 119 ISP1362_REG(HCCONTROL, 0x01, REG_WIDTH_32, REG_ACCESS_RW); 120 ISP1362_REG(HCCMDSTAT, 0x02, REG_WIDTH_32, REG_ACCESS_RW); 121 ISP1362_REG(HCINTSTAT, 0x03, REG_WIDTH_32, REG_ACCESS_RW); 122 ISP1362_REG(HCINTENB, 0x04, REG_WIDTH_32, REG_ACCESS_RW); 123 ISP1362_REG(HCINTDIS, 0x05, REG_WIDTH_32, REG_ACCESS_RW); 124 ISP1362_REG(HCFMINTVL, 0x0d, REG_WIDTH_32, REG_ACCESS_RW); 125 ISP1362_REG(HCFMREM, 0x0e, REG_WIDTH_32, REG_ACCESS_RW); 126 ISP1362_REG(HCFMNUM, 0x0f, REG_WIDTH_32, REG_ACCESS_RW); 127 ISP1362_REG(HCLSTHRESH, 0x11, REG_WIDTH_32, REG_ACCESS_RW); 128 ISP1362_REG(HCRHDESCA, 0x12, REG_WIDTH_32, REG_ACCESS_RW); 129 ISP1362_REG(HCRHDESCB, 0x13, REG_WIDTH_32, REG_ACCESS_RW); 130 ISP1362_REG(HCRHSTATUS, 0x14, REG_WIDTH_32, REG_ACCESS_RW); 131 ISP1362_REG(HCRHPORT1, 0x15, REG_WIDTH_32, REG_ACCESS_RW); 132 ISP1362_REG(HCRHPORT2, 0x16, REG_WIDTH_32, REG_ACCESS_RW); 133 134 /* Philips ISP1362 specific registers */ 135 ISP1362_REG(HCHWCFG, 0x20, REG_WIDTH_16, REG_ACCESS_RW); 136 #define HCHWCFG_DISABLE_SUSPEND (1 << 15) 137 #define HCHWCFG_GLOBAL_PWRDOWN (1 << 14) 138 #define HCHWCFG_PULLDOWN_DS2 (1 << 13) 139 #define HCHWCFG_PULLDOWN_DS1 (1 << 12) 140 #define HCHWCFG_CLKNOTSTOP (1 << 11) 141 #define HCHWCFG_ANALOG_OC (1 << 10) 142 #define HCHWCFG_ONEINT (1 << 9) 143 #define HCHWCFG_DACK_MODE (1 << 8) 144 #define HCHWCFG_ONEDMA (1 << 7) 145 #define HCHWCFG_DACK_POL (1 << 6) 146 #define HCHWCFG_DREQ_POL (1 << 5) 147 #define HCHWCFG_DBWIDTH_MASK (0x03 << 3) 148 #define HCHWCFG_DBWIDTH(n) (((n) << 3) & HCHWCFG_DBWIDTH_MASK) 149 #define HCHWCFG_INT_POL (1 << 2) 150 #define HCHWCFG_INT_TRIGGER (1 << 1) 151 #define HCHWCFG_INT_ENABLE (1 << 0) 152 153 ISP1362_REG(HCDMACFG, 0x21, REG_WIDTH_16, REG_ACCESS_RW); 154 #define HCDMACFG_CTR_ENABLE (1 << 7) 155 #define HCDMACFG_BURST_LEN_MASK (0x03 << 5) 156 #define HCDMACFG_BURST_LEN(n) (((n) << 5) & HCDMACFG_BURST_LEN_MASK) 157 #define HCDMACFG_BURST_LEN_1 HCDMACFG_BURST_LEN(0) 158 #define HCDMACFG_BURST_LEN_4 HCDMACFG_BURST_LEN(1) 159 #define HCDMACFG_BURST_LEN_8 HCDMACFG_BURST_LEN(2) 160 #define HCDMACFG_DMA_ENABLE (1 << 4) 161 #define HCDMACFG_BUF_TYPE_MASK (0x07 << 1) 162 #define HCDMACFG_BUF_TYPE(n) (((n) << 1) & HCDMACFG_BUF_TYPE_MASK) 163 #define HCDMACFG_BUF_ISTL0 HCDMACFG_BUF_TYPE(0) 164 #define HCDMACFG_BUF_ISTL1 HCDMACFG_BUF_TYPE(1) 165 #define HCDMACFG_BUF_INTL HCDMACFG_BUF_TYPE(2) 166 #define HCDMACFG_BUF_ATL HCDMACFG_BUF_TYPE(3) 167 #define HCDMACFG_BUF_DIRECT HCDMACFG_BUF_TYPE(4) 168 #define HCDMACFG_DMA_RW_SELECT (1 << 0) 169 170 ISP1362_REG(HCXFERCTR, 0x22, REG_WIDTH_16, REG_ACCESS_RW); 171 172 ISP1362_REG(HCuPINT, 0x24, REG_WIDTH_16, REG_ACCESS_RW); 173 #define HCuPINT_SOF (1 << 0) 174 #define HCuPINT_ISTL0 (1 << 1) 175 #define HCuPINT_ISTL1 (1 << 2) 176 #define HCuPINT_EOT (1 << 3) 177 #define HCuPINT_OPR (1 << 4) 178 #define HCuPINT_SUSP (1 << 5) 179 #define HCuPINT_CLKRDY (1 << 6) 180 #define HCuPINT_INTL (1 << 7) 181 #define HCuPINT_ATL (1 << 8) 182 #define HCuPINT_OTG (1 << 9) 183 184 ISP1362_REG(HCuPINTENB, 0x25, REG_WIDTH_16, REG_ACCESS_RW); 185 /* same bit definitions apply as for HCuPINT */ 186 187 ISP1362_REG(HCCHIPID, 0x27, REG_WIDTH_16, REG_ACCESS_R); 188 #define HCCHIPID_MASK 0xff00 189 #define HCCHIPID_MAGIC 0x3600 190 191 ISP1362_REG(HCSCRATCH, 0x28, REG_WIDTH_16, REG_ACCESS_RW); 192 193 ISP1362_REG(HCSWRES, 0x29, REG_WIDTH_16, REG_ACCESS_W); 194 #define HCSWRES_MAGIC 0x00f6 195 196 ISP1362_REG(HCBUFSTAT, 0x2c, REG_WIDTH_16, REG_ACCESS_RW); 197 #define HCBUFSTAT_ISTL0_FULL (1 << 0) 198 #define HCBUFSTAT_ISTL1_FULL (1 << 1) 199 #define HCBUFSTAT_INTL_ACTIVE (1 << 2) 200 #define HCBUFSTAT_ATL_ACTIVE (1 << 3) 201 #define HCBUFSTAT_RESET_HWPP (1 << 4) 202 #define HCBUFSTAT_ISTL0_ACTIVE (1 << 5) 203 #define HCBUFSTAT_ISTL1_ACTIVE (1 << 6) 204 #define HCBUFSTAT_ISTL0_DONE (1 << 8) 205 #define HCBUFSTAT_ISTL1_DONE (1 << 9) 206 #define HCBUFSTAT_PAIRED_PTDPP (1 << 10) 207 208 ISP1362_REG(HCDIRADDR, 0x32, REG_WIDTH_32, REG_ACCESS_RW); 209 #define HCDIRADDR_ADDR_MASK 0x0000ffff 210 #define HCDIRADDR_ADDR(n) (((n) << 0) & HCDIRADDR_ADDR_MASK) 211 #define HCDIRADDR_COUNT_MASK 0xffff0000 212 #define HCDIRADDR_COUNT(n) (((n) << 16) & HCDIRADDR_COUNT_MASK) 213 ISP1362_REG(HCDIRDATA, 0x45, REG_WIDTH_16, REG_ACCESS_RW); 214 215 ISP1362_REG(HCISTLBUFSZ, 0x30, REG_WIDTH_16, REG_ACCESS_RW); 216 ISP1362_REG(HCISTL0PORT, 0x40, REG_WIDTH_16, REG_ACCESS_RW); 217 ISP1362_REG(HCISTL1PORT, 0x42, REG_WIDTH_16, REG_ACCESS_RW); 218 ISP1362_REG(HCISTLRATE, 0x47, REG_WIDTH_16, REG_ACCESS_RW); 219 220 ISP1362_REG(HCINTLBUFSZ, 0x33, REG_WIDTH_16, REG_ACCESS_RW); 221 ISP1362_REG(HCINTLPORT, 0x43, REG_WIDTH_16, REG_ACCESS_RW); 222 ISP1362_REG(HCINTLBLKSZ, 0x53, REG_WIDTH_16, REG_ACCESS_RW); 223 ISP1362_REG(HCINTLDONE, 0x17, REG_WIDTH_32, REG_ACCESS_R); 224 ISP1362_REG(HCINTLSKIP, 0x18, REG_WIDTH_32, REG_ACCESS_RW); 225 ISP1362_REG(HCINTLLAST, 0x19, REG_WIDTH_32, REG_ACCESS_RW); 226 ISP1362_REG(HCINTLCURR, 0x1a, REG_WIDTH_16, REG_ACCESS_R); 227 228 ISP1362_REG(HCATLBUFSZ, 0x34, REG_WIDTH_16, REG_ACCESS_RW); 229 ISP1362_REG(HCATLPORT, 0x44, REG_WIDTH_16, REG_ACCESS_RW); 230 ISP1362_REG(HCATLBLKSZ, 0x54, REG_WIDTH_16, REG_ACCESS_RW); 231 ISP1362_REG(HCATLDONE, 0x1b, REG_WIDTH_32, REG_ACCESS_R); 232 ISP1362_REG(HCATLSKIP, 0x1c, REG_WIDTH_32, REG_ACCESS_RW); 233 ISP1362_REG(HCATLLAST, 0x1d, REG_WIDTH_32, REG_ACCESS_RW); 234 ISP1362_REG(HCATLCURR, 0x1e, REG_WIDTH_16, REG_ACCESS_R); 235 236 ISP1362_REG(HCATLDTC, 0x51, REG_WIDTH_16, REG_ACCESS_RW); 237 ISP1362_REG(HCATLDTCTO, 0x52, REG_WIDTH_16, REG_ACCESS_RW); 238 239 240 ISP1362_REG(OTGCONTROL, 0x62, REG_WIDTH_16, REG_ACCESS_RW); 241 ISP1362_REG(OTGSTATUS, 0x67, REG_WIDTH_16, REG_ACCESS_R); 242 ISP1362_REG(OTGINT, 0x68, REG_WIDTH_16, REG_ACCESS_RW); 243 ISP1362_REG(OTGINTENB, 0x69, REG_WIDTH_16, REG_ACCESS_RW); 244 ISP1362_REG(OTGTIMER, 0x6A, REG_WIDTH_16, REG_ACCESS_RW); 245 ISP1362_REG(OTGALTTMR, 0x6C, REG_WIDTH_16, REG_ACCESS_RW); 246 247 /* Philips transfer descriptor, cpu-endian */ 248 struct ptd { 249 u16 count; 250 #define PTD_COUNT_MSK (0x3ff << 0) 251 #define PTD_TOGGLE_MSK (1 << 10) 252 #define PTD_ACTIVE_MSK (1 << 11) 253 #define PTD_CC_MSK (0xf << 12) 254 u16 mps; 255 #define PTD_MPS_MSK (0x3ff << 0) 256 #define PTD_SPD_MSK (1 << 10) 257 #define PTD_LAST_MSK (1 << 11) 258 #define PTD_EP_MSK (0xf << 12) 259 u16 len; 260 #define PTD_LEN_MSK (0x3ff << 0) 261 #define PTD_DIR_MSK (3 << 10) 262 #define PTD_DIR_SETUP (0) 263 #define PTD_DIR_OUT (1) 264 #define PTD_DIR_IN (2) 265 u16 faddr; 266 #define PTD_FA_MSK (0x7f << 0) 267 /* PTD Byte 7: [StartingFrame (if ISO PTD) | StartingFrame[0..4], PollingRate[0..2] (if INT PTD)] */ 268 #define PTD_SF_ISO_MSK (0xff << 8) 269 #define PTD_SF_INT_MSK (0x1f << 8) 270 #define PTD_PR_MSK (0x07 << 13) 271 } __attribute__ ((packed, aligned(2))); 272 #define PTD_HEADER_SIZE sizeof(struct ptd) 273 274 /* ------------------------------------------------------------------------- */ 275 /* Copied from ohci.h: */ 276 /* 277 * Hardware transfer status codes -- CC from PTD 278 */ 279 #define PTD_CC_NOERROR 0x00 280 #define PTD_CC_CRC 0x01 281 #define PTD_CC_BITSTUFFING 0x02 282 #define PTD_CC_DATATOGGLEM 0x03 283 #define PTD_CC_STALL 0x04 284 #define PTD_DEVNOTRESP 0x05 285 #define PTD_PIDCHECKFAIL 0x06 286 #define PTD_UNEXPECTEDPID 0x07 287 #define PTD_DATAOVERRUN 0x08 288 #define PTD_DATAUNDERRUN 0x09 289 /* 0x0A, 0x0B reserved for hardware */ 290 #define PTD_BUFFEROVERRUN 0x0C 291 #define PTD_BUFFERUNDERRUN 0x0D 292 /* 0x0E, 0x0F reserved for HCD */ 293 #define PTD_NOTACCESSED 0x0F 294 295 296 /* map OHCI TD status codes (CC) to errno values */ 297 static const int cc_to_error[16] = { 298 /* No Error */ 0, 299 /* CRC Error */ -EILSEQ, 300 /* Bit Stuff */ -EPROTO, 301 /* Data Togg */ -EILSEQ, 302 /* Stall */ -EPIPE, 303 /* DevNotResp */ -ETIMEDOUT, 304 /* PIDCheck */ -EPROTO, 305 /* UnExpPID */ -EPROTO, 306 /* DataOver */ -EOVERFLOW, 307 /* DataUnder */ -EREMOTEIO, 308 /* (for hw) */ -EIO, 309 /* (for hw) */ -EIO, 310 /* BufferOver */ -ECOMM, 311 /* BuffUnder */ -ENOSR, 312 /* (for HCD) */ -EALREADY, 313 /* (for HCD) */ -EALREADY 314 }; 315 316 317 /* 318 * HcControl (control) register masks 319 */ 320 #define OHCI_CTRL_HCFS (3 << 6) /* host controller functional state */ 321 #define OHCI_CTRL_RWC (1 << 9) /* remote wakeup connected */ 322 #define OHCI_CTRL_RWE (1 << 10) /* remote wakeup enable */ 323 324 /* pre-shifted values for HCFS */ 325 # define OHCI_USB_RESET (0 << 6) 326 # define OHCI_USB_RESUME (1 << 6) 327 # define OHCI_USB_OPER (2 << 6) 328 # define OHCI_USB_SUSPEND (3 << 6) 329 330 /* 331 * HcCommandStatus (cmdstatus) register masks 332 */ 333 #define OHCI_HCR (1 << 0) /* host controller reset */ 334 #define OHCI_SOC (3 << 16) /* scheduling overrun count */ 335 336 /* 337 * masks used with interrupt registers: 338 * HcInterruptStatus (intrstatus) 339 * HcInterruptEnable (intrenable) 340 * HcInterruptDisable (intrdisable) 341 */ 342 #define OHCI_INTR_SO (1 << 0) /* scheduling overrun */ 343 #define OHCI_INTR_WDH (1 << 1) /* writeback of done_head */ 344 #define OHCI_INTR_SF (1 << 2) /* start frame */ 345 #define OHCI_INTR_RD (1 << 3) /* resume detect */ 346 #define OHCI_INTR_UE (1 << 4) /* unrecoverable error */ 347 #define OHCI_INTR_FNO (1 << 5) /* frame number overflow */ 348 #define OHCI_INTR_RHSC (1 << 6) /* root hub status change */ 349 #define OHCI_INTR_OC (1 << 30) /* ownership change */ 350 #define OHCI_INTR_MIE (1 << 31) /* master interrupt enable */ 351 352 /* roothub.portstatus [i] bits */ 353 #define RH_PS_CCS 0x00000001 /* current connect status */ 354 #define RH_PS_PES 0x00000002 /* port enable status*/ 355 #define RH_PS_PSS 0x00000004 /* port suspend status */ 356 #define RH_PS_POCI 0x00000008 /* port over current indicator */ 357 #define RH_PS_PRS 0x00000010 /* port reset status */ 358 #define RH_PS_PPS 0x00000100 /* port power status */ 359 #define RH_PS_LSDA 0x00000200 /* low speed device attached */ 360 #define RH_PS_CSC 0x00010000 /* connect status change */ 361 #define RH_PS_PESC 0x00020000 /* port enable status change */ 362 #define RH_PS_PSSC 0x00040000 /* port suspend status change */ 363 #define RH_PS_OCIC 0x00080000 /* over current indicator change */ 364 #define RH_PS_PRSC 0x00100000 /* port reset status change */ 365 366 /* roothub.status bits */ 367 #define RH_HS_LPS 0x00000001 /* local power status */ 368 #define RH_HS_OCI 0x00000002 /* over current indicator */ 369 #define RH_HS_DRWE 0x00008000 /* device remote wakeup enable */ 370 #define RH_HS_LPSC 0x00010000 /* local power status change */ 371 #define RH_HS_OCIC 0x00020000 /* over current indicator change */ 372 #define RH_HS_CRWE 0x80000000 /* clear remote wakeup enable */ 373 374 /* roothub.b masks */ 375 #define RH_B_DR 0x0000ffff /* device removable flags */ 376 #define RH_B_PPCM 0xffff0000 /* port power control mask */ 377 378 /* roothub.a masks */ 379 #define RH_A_NDP (0xff << 0) /* number of downstream ports */ 380 #define RH_A_PSM (1 << 8) /* power switching mode */ 381 #define RH_A_NPS (1 << 9) /* no power switching */ 382 #define RH_A_DT (1 << 10) /* device type (mbz) */ 383 #define RH_A_OCPM (1 << 11) /* over current protection mode */ 384 #define RH_A_NOCP (1 << 12) /* no over current protection */ 385 #define RH_A_POTPGT (0xff << 24) /* power on to power good time */ 386 387 #define FI 0x2edf /* 12000 bits per frame (-1) */ 388 #define FSMP(fi) (0x7fff & ((6 * ((fi) - 210)) / 7)) 389 #define LSTHRESH 0x628 /* lowspeed bit threshold */ 390 391 /* ------------------------------------------------------------------------- */ 392 393 /* PTD accessor macros. */ 394 #define PTD_GET_COUNT(p) (((p)->count & PTD_COUNT_MSK) >> 0) 395 #define PTD_COUNT(v) (((v) << 0) & PTD_COUNT_MSK) 396 #define PTD_GET_TOGGLE(p) (((p)->count & PTD_TOGGLE_MSK) >> 10) 397 #define PTD_TOGGLE(v) (((v) << 10) & PTD_TOGGLE_MSK) 398 #define PTD_GET_ACTIVE(p) (((p)->count & PTD_ACTIVE_MSK) >> 11) 399 #define PTD_ACTIVE(v) (((v) << 11) & PTD_ACTIVE_MSK) 400 #define PTD_GET_CC(p) (((p)->count & PTD_CC_MSK) >> 12) 401 #define PTD_CC(v) (((v) << 12) & PTD_CC_MSK) 402 #define PTD_GET_MPS(p) (((p)->mps & PTD_MPS_MSK) >> 0) 403 #define PTD_MPS(v) (((v) << 0) & PTD_MPS_MSK) 404 #define PTD_GET_SPD(p) (((p)->mps & PTD_SPD_MSK) >> 10) 405 #define PTD_SPD(v) (((v) << 10) & PTD_SPD_MSK) 406 #define PTD_GET_LAST(p) (((p)->mps & PTD_LAST_MSK) >> 11) 407 #define PTD_LAST(v) (((v) << 11) & PTD_LAST_MSK) 408 #define PTD_GET_EP(p) (((p)->mps & PTD_EP_MSK) >> 12) 409 #define PTD_EP(v) (((v) << 12) & PTD_EP_MSK) 410 #define PTD_GET_LEN(p) (((p)->len & PTD_LEN_MSK) >> 0) 411 #define PTD_LEN(v) (((v) << 0) & PTD_LEN_MSK) 412 #define PTD_GET_DIR(p) (((p)->len & PTD_DIR_MSK) >> 10) 413 #define PTD_DIR(v) (((v) << 10) & PTD_DIR_MSK) 414 #define PTD_GET_FA(p) (((p)->faddr & PTD_FA_MSK) >> 0) 415 #define PTD_FA(v) (((v) << 0) & PTD_FA_MSK) 416 #define PTD_GET_SF_INT(p) (((p)->faddr & PTD_SF_INT_MSK) >> 8) 417 #define PTD_SF_INT(v) (((v) << 8) & PTD_SF_INT_MSK) 418 #define PTD_GET_SF_ISO(p) (((p)->faddr & PTD_SF_ISO_MSK) >> 8) 419 #define PTD_SF_ISO(v) (((v) << 8) & PTD_SF_ISO_MSK) 420 #define PTD_GET_PR(p) (((p)->faddr & PTD_PR_MSK) >> 13) 421 #define PTD_PR(v) (((v) << 13) & PTD_PR_MSK) 422 423 #define LOG2_PERIODIC_SIZE 5 /* arbitrary; this matches OHCI */ 424 #define PERIODIC_SIZE (1 << LOG2_PERIODIC_SIZE) 425 426 struct isp1362_ep { 427 struct usb_host_endpoint *hep; 428 struct usb_device *udev; 429 430 /* philips transfer descriptor */ 431 struct ptd ptd; 432 433 u8 maxpacket; 434 u8 epnum; 435 u8 nextpid; 436 u16 error_count; 437 u16 length; /* of current packet */ 438 s16 ptd_offset; /* buffer offset in ISP1362 where 439 PTD has been stored 440 (for access thru HCDIRDATA) */ 441 int ptd_index; 442 int num_ptds; 443 void *data; /* to databuf */ 444 /* queue of active EPs (the ones transmitted to the chip) */ 445 struct list_head active; 446 447 /* periodic schedule */ 448 u8 branch; 449 u16 interval; 450 u16 load; 451 u16 last_iso; 452 453 /* async schedule */ 454 struct list_head schedule; /* list of all EPs that need processing */ 455 struct list_head remove_list; 456 int num_req; 457 }; 458 459 struct isp1362_ep_queue { 460 struct list_head active; /* list of PTDs currently processed by HC */ 461 atomic_t finishing; 462 unsigned long buf_map; 463 unsigned long skip_map; 464 int free_ptd; 465 u16 buf_start; 466 u16 buf_size; 467 u16 blk_size; /* PTD buffer block size for ATL and INTL */ 468 u8 buf_count; 469 u8 buf_avail; 470 char name[16]; 471 472 /* for statistical tracking */ 473 u8 stat_maxptds; /* Max # of ptds seen simultaneously in fifo */ 474 u8 ptd_count; /* number of ptds submitted to this queue */ 475 }; 476 477 struct isp1362_hcd { 478 spinlock_t lock; 479 void __iomem *addr_reg; 480 void __iomem *data_reg; 481 482 struct isp1362_platform_data *board; 483 484 struct dentry *debug_file; 485 unsigned long stat1, stat2, stat4, stat8, stat16; 486 487 /* HC registers */ 488 u32 intenb; /* "OHCI" interrupts */ 489 u16 irqenb; /* uP interrupts */ 490 491 /* Root hub registers */ 492 u32 rhdesca; 493 u32 rhdescb; 494 u32 rhstatus; 495 u32 rhport[MAX_ROOT_PORTS]; 496 unsigned long next_statechange; 497 498 /* HC control reg shadow copy */ 499 u32 hc_control; 500 501 /* async schedule: control, bulk */ 502 struct list_head async; 503 504 /* periodic schedule: int */ 505 u16 load[PERIODIC_SIZE]; 506 struct list_head periodic; 507 u16 fmindex; 508 509 /* periodic schedule: isochronous */ 510 struct list_head isoc; 511 unsigned int istl_flip:1; 512 unsigned int irq_active:1; 513 514 /* Schedules for the current frame */ 515 struct isp1362_ep_queue atl_queue; 516 struct isp1362_ep_queue intl_queue; 517 struct isp1362_ep_queue istl_queue[2]; 518 519 /* list of PTDs retrieved from HC */ 520 struct list_head remove_list; 521 enum { 522 ISP1362_INT_SOF, 523 ISP1362_INT_ISTL0, 524 ISP1362_INT_ISTL1, 525 ISP1362_INT_EOT, 526 ISP1362_INT_OPR, 527 ISP1362_INT_SUSP, 528 ISP1362_INT_CLKRDY, 529 ISP1362_INT_INTL, 530 ISP1362_INT_ATL, 531 ISP1362_INT_OTG, 532 NUM_ISP1362_IRQS 533 } IRQ_NAMES; 534 unsigned int irq_stat[NUM_ISP1362_IRQS]; 535 int req_serial; 536 }; 537 538 static inline const char *ISP1362_INT_NAME(int n) 539 { 540 switch (n) { 541 case ISP1362_INT_SOF: return "SOF"; 542 case ISP1362_INT_ISTL0: return "ISTL0"; 543 case ISP1362_INT_ISTL1: return "ISTL1"; 544 case ISP1362_INT_EOT: return "EOT"; 545 case ISP1362_INT_OPR: return "OPR"; 546 case ISP1362_INT_SUSP: return "SUSP"; 547 case ISP1362_INT_CLKRDY: return "CLKRDY"; 548 case ISP1362_INT_INTL: return "INTL"; 549 case ISP1362_INT_ATL: return "ATL"; 550 case ISP1362_INT_OTG: return "OTG"; 551 default: return "unknown"; 552 } 553 } 554 555 static inline void ALIGNSTAT(struct isp1362_hcd *isp1362_hcd, void *ptr) 556 { 557 unsigned long p = (unsigned long)ptr; 558 if (!(p & 0xf)) 559 isp1362_hcd->stat16++; 560 else if (!(p & 0x7)) 561 isp1362_hcd->stat8++; 562 else if (!(p & 0x3)) 563 isp1362_hcd->stat4++; 564 else if (!(p & 0x1)) 565 isp1362_hcd->stat2++; 566 else 567 isp1362_hcd->stat1++; 568 } 569 570 static inline struct isp1362_hcd *hcd_to_isp1362_hcd(struct usb_hcd *hcd) 571 { 572 return (struct isp1362_hcd *) (hcd->hcd_priv); 573 } 574 575 static inline struct usb_hcd *isp1362_hcd_to_hcd(struct isp1362_hcd *isp1362_hcd) 576 { 577 return container_of((void *)isp1362_hcd, struct usb_hcd, hcd_priv); 578 } 579 580 #define frame_before(f1, f2) ((s16)((u16)f1 - (u16)f2) < 0) 581 582 /* 583 * ISP1362 HW Interface 584 */ 585 586 #define DBG(level, fmt...) \ 587 do { \ 588 if (dbg_level > level) \ 589 pr_debug(fmt); \ 590 } while (0) 591 592 #ifdef VERBOSE 593 # define VDBG(fmt...) DBG(3, fmt) 594 #else 595 # define VDBG(fmt...) do {} while (0) 596 #endif 597 598 #ifdef REGISTERS 599 # define RDBG(fmt...) DBG(1, fmt) 600 #else 601 # define RDBG(fmt...) do {} while (0) 602 #endif 603 604 #ifdef URB_TRACE 605 #define URB_DBG(fmt...) DBG(0, fmt) 606 #else 607 #define URB_DBG(fmt...) do {} while (0) 608 #endif 609 610 611 #if USE_PLATFORM_DELAY 612 #if USE_NDELAY 613 #error USE_PLATFORM_DELAY and USE_NDELAY defined simultaneously. 614 #endif 615 #define isp1362_delay(h, d) (h)->board->delay(isp1362_hcd_to_hcd(h)->self.controller, d) 616 #elif USE_NDELAY 617 #define isp1362_delay(h, d) ndelay(d) 618 #else 619 #define isp1362_delay(h, d) do {} while (0) 620 #endif 621 622 #define get_urb(ep) ({ \ 623 BUG_ON(list_empty(&ep->hep->urb_list)); \ 624 container_of(ep->hep->urb_list.next, struct urb, urb_list); \ 625 }) 626 627 /* basic access functions for ISP1362 chip registers */ 628 /* NOTE: The contents of the address pointer register cannot be read back! The driver must ensure, 629 * that all register accesses are performed with interrupts disabled, since the interrupt 630 * handler has no way of restoring the previous state. 631 */ 632 static void isp1362_write_addr(struct isp1362_hcd *isp1362_hcd, isp1362_reg_t reg) 633 { 634 REG_ACCESS_TEST(reg); 635 DUMMY_DELAY_ACCESS; 636 writew(ISP1362_REG_NO(reg), isp1362_hcd->addr_reg); 637 DUMMY_DELAY_ACCESS; 638 isp1362_delay(isp1362_hcd, 1); 639 } 640 641 static void isp1362_write_data16(struct isp1362_hcd *isp1362_hcd, u16 val) 642 { 643 DUMMY_DELAY_ACCESS; 644 writew(val, isp1362_hcd->data_reg); 645 } 646 647 static u16 isp1362_read_data16(struct isp1362_hcd *isp1362_hcd) 648 { 649 u16 val; 650 651 DUMMY_DELAY_ACCESS; 652 val = readw(isp1362_hcd->data_reg); 653 654 return val; 655 } 656 657 static void isp1362_write_data32(struct isp1362_hcd *isp1362_hcd, u32 val) 658 { 659 #if USE_32BIT 660 DUMMY_DELAY_ACCESS; 661 writel(val, isp1362_hcd->data_reg); 662 #else 663 DUMMY_DELAY_ACCESS; 664 writew((u16)val, isp1362_hcd->data_reg); 665 DUMMY_DELAY_ACCESS; 666 writew(val >> 16, isp1362_hcd->data_reg); 667 #endif 668 } 669 670 static u32 isp1362_read_data32(struct isp1362_hcd *isp1362_hcd) 671 { 672 u32 val; 673 674 #if USE_32BIT 675 DUMMY_DELAY_ACCESS; 676 val = readl(isp1362_hcd->data_reg); 677 #else 678 DUMMY_DELAY_ACCESS; 679 val = (u32)readw(isp1362_hcd->data_reg); 680 DUMMY_DELAY_ACCESS; 681 val |= (u32)readw(isp1362_hcd->data_reg) << 16; 682 #endif 683 return val; 684 } 685 686 /* use readsw/writesw to access the fifo whenever possible */ 687 /* assume HCDIRDATA or XFERCTR & addr_reg have been set up */ 688 static void isp1362_read_fifo(struct isp1362_hcd *isp1362_hcd, void *buf, u16 len) 689 { 690 u8 *dp = buf; 691 u16 data; 692 693 if (!len) 694 return; 695 696 RDBG("%s: Reading %d byte from fifo to mem @ %p\n", __func__, len, buf); 697 #if USE_32BIT 698 if (len >= 4) { 699 RDBG("%s: Using readsl for %d dwords\n", __func__, len >> 2); 700 readsl(isp1362_hcd->data_reg, dp, len >> 2); 701 dp += len & ~3; 702 len &= 3; 703 } 704 #endif 705 if (len >= 2) { 706 RDBG("%s: Using readsw for %d words\n", __func__, len >> 1); 707 insw((unsigned long)isp1362_hcd->data_reg, dp, len >> 1); 708 dp += len & ~1; 709 len &= 1; 710 } 711 712 BUG_ON(len & ~1); 713 if (len > 0) { 714 data = isp1362_read_data16(isp1362_hcd); 715 RDBG("%s: Reading trailing byte %02x to mem @ %08x\n", __func__, 716 (u8)data, (u32)dp); 717 *dp = (u8)data; 718 } 719 } 720 721 static void isp1362_write_fifo(struct isp1362_hcd *isp1362_hcd, void *buf, u16 len) 722 { 723 u8 *dp = buf; 724 u16 data; 725 726 if (!len) 727 return; 728 729 if ((unsigned long)dp & 0x1) { 730 /* not aligned */ 731 for (; len > 1; len -= 2) { 732 data = *dp++; 733 data |= *dp++ << 8; 734 isp1362_write_data16(isp1362_hcd, data); 735 } 736 if (len) 737 isp1362_write_data16(isp1362_hcd, *dp); 738 return; 739 } 740 741 RDBG("%s: Writing %d byte to fifo from memory @%p\n", __func__, len, buf); 742 #if USE_32BIT 743 if (len >= 4) { 744 RDBG("%s: Using writesl for %d dwords\n", __func__, len >> 2); 745 writesl(isp1362_hcd->data_reg, dp, len >> 2); 746 dp += len & ~3; 747 len &= 3; 748 } 749 #endif 750 if (len >= 2) { 751 RDBG("%s: Using writesw for %d words\n", __func__, len >> 1); 752 outsw((unsigned long)isp1362_hcd->data_reg, dp, len >> 1); 753 dp += len & ~1; 754 len &= 1; 755 } 756 757 BUG_ON(len & ~1); 758 if (len > 0) { 759 /* finally write any trailing byte; we don't need to care 760 * about the high byte of the last word written 761 */ 762 data = (u16)*dp; 763 RDBG("%s: Sending trailing byte %02x from mem @ %08x\n", __func__, 764 data, (u32)dp); 765 isp1362_write_data16(isp1362_hcd, data); 766 } 767 } 768 769 #define isp1362_read_reg16(d, r) ({ \ 770 u16 __v; \ 771 REG_WIDTH_TEST(ISP1362_REG_##r, REG_WIDTH_16); \ 772 isp1362_write_addr(d, ISP1362_REG_##r); \ 773 __v = isp1362_read_data16(d); \ 774 RDBG("%s: Read %04x from %s[%02x]\n", __func__, __v, #r, \ 775 ISP1362_REG_NO(ISP1362_REG_##r)); \ 776 __v; \ 777 }) 778 779 #define isp1362_read_reg32(d, r) ({ \ 780 u32 __v; \ 781 REG_WIDTH_TEST(ISP1362_REG_##r, REG_WIDTH_32); \ 782 isp1362_write_addr(d, ISP1362_REG_##r); \ 783 __v = isp1362_read_data32(d); \ 784 RDBG("%s: Read %08x from %s[%02x]\n", __func__, __v, #r, \ 785 ISP1362_REG_NO(ISP1362_REG_##r)); \ 786 __v; \ 787 }) 788 789 #define isp1362_write_reg16(d, r, v) { \ 790 REG_WIDTH_TEST(ISP1362_REG_##r, REG_WIDTH_16); \ 791 isp1362_write_addr(d, (ISP1362_REG_##r) | ISP1362_REG_WRITE_OFFSET); \ 792 isp1362_write_data16(d, (u16)(v)); \ 793 RDBG("%s: Wrote %04x to %s[%02x]\n", __func__, (u16)(v), #r, \ 794 ISP1362_REG_NO(ISP1362_REG_##r)); \ 795 } 796 797 #define isp1362_write_reg32(d, r, v) { \ 798 REG_WIDTH_TEST(ISP1362_REG_##r, REG_WIDTH_32); \ 799 isp1362_write_addr(d, (ISP1362_REG_##r) | ISP1362_REG_WRITE_OFFSET); \ 800 isp1362_write_data32(d, (u32)(v)); \ 801 RDBG("%s: Wrote %08x to %s[%02x]\n", __func__, (u32)(v), #r, \ 802 ISP1362_REG_NO(ISP1362_REG_##r)); \ 803 } 804 805 #define isp1362_set_mask16(d, r, m) { \ 806 u16 __v; \ 807 __v = isp1362_read_reg16(d, r); \ 808 if ((__v | m) != __v) \ 809 isp1362_write_reg16(d, r, __v | m); \ 810 } 811 812 #define isp1362_clr_mask16(d, r, m) { \ 813 u16 __v; \ 814 __v = isp1362_read_reg16(d, r); \ 815 if ((__v & ~m) != __v) \ 816 isp1362_write_reg16(d, r, __v & ~m); \ 817 } 818 819 #define isp1362_set_mask32(d, r, m) { \ 820 u32 __v; \ 821 __v = isp1362_read_reg32(d, r); \ 822 if ((__v | m) != __v) \ 823 isp1362_write_reg32(d, r, __v | m); \ 824 } 825 826 #define isp1362_clr_mask32(d, r, m) { \ 827 u32 __v; \ 828 __v = isp1362_read_reg32(d, r); \ 829 if ((__v & ~m) != __v) \ 830 isp1362_write_reg32(d, r, __v & ~m); \ 831 } 832 833 #define isp1362_show_reg(d, r) { \ 834 if ((ISP1362_REG_##r & REG_WIDTH_MASK) == REG_WIDTH_32) \ 835 DBG(0, "%-12s[%02x]: %08x\n", #r, \ 836 ISP1362_REG_NO(ISP1362_REG_##r), isp1362_read_reg32(d, r)); \ 837 else \ 838 DBG(0, "%-12s[%02x]: %04x\n", #r, \ 839 ISP1362_REG_NO(ISP1362_REG_##r), isp1362_read_reg16(d, r)); \ 840 } 841 842 static void __attribute__((__unused__)) isp1362_show_regs(struct isp1362_hcd *isp1362_hcd) 843 { 844 isp1362_show_reg(isp1362_hcd, HCREVISION); 845 isp1362_show_reg(isp1362_hcd, HCCONTROL); 846 isp1362_show_reg(isp1362_hcd, HCCMDSTAT); 847 isp1362_show_reg(isp1362_hcd, HCINTSTAT); 848 isp1362_show_reg(isp1362_hcd, HCINTENB); 849 isp1362_show_reg(isp1362_hcd, HCFMINTVL); 850 isp1362_show_reg(isp1362_hcd, HCFMREM); 851 isp1362_show_reg(isp1362_hcd, HCFMNUM); 852 isp1362_show_reg(isp1362_hcd, HCLSTHRESH); 853 isp1362_show_reg(isp1362_hcd, HCRHDESCA); 854 isp1362_show_reg(isp1362_hcd, HCRHDESCB); 855 isp1362_show_reg(isp1362_hcd, HCRHSTATUS); 856 isp1362_show_reg(isp1362_hcd, HCRHPORT1); 857 isp1362_show_reg(isp1362_hcd, HCRHPORT2); 858 859 isp1362_show_reg(isp1362_hcd, HCHWCFG); 860 isp1362_show_reg(isp1362_hcd, HCDMACFG); 861 isp1362_show_reg(isp1362_hcd, HCXFERCTR); 862 isp1362_show_reg(isp1362_hcd, HCuPINT); 863 864 if (in_interrupt()) 865 DBG(0, "%-12s[%02x]: %04x\n", "HCuPINTENB", 866 ISP1362_REG_NO(ISP1362_REG_HCuPINTENB), isp1362_hcd->irqenb); 867 else 868 isp1362_show_reg(isp1362_hcd, HCuPINTENB); 869 isp1362_show_reg(isp1362_hcd, HCCHIPID); 870 isp1362_show_reg(isp1362_hcd, HCSCRATCH); 871 isp1362_show_reg(isp1362_hcd, HCBUFSTAT); 872 isp1362_show_reg(isp1362_hcd, HCDIRADDR); 873 /* Access would advance fifo 874 * isp1362_show_reg(isp1362_hcd, HCDIRDATA); 875 */ 876 isp1362_show_reg(isp1362_hcd, HCISTLBUFSZ); 877 isp1362_show_reg(isp1362_hcd, HCISTLRATE); 878 isp1362_show_reg(isp1362_hcd, HCINTLBUFSZ); 879 isp1362_show_reg(isp1362_hcd, HCINTLBLKSZ); 880 isp1362_show_reg(isp1362_hcd, HCINTLDONE); 881 isp1362_show_reg(isp1362_hcd, HCINTLSKIP); 882 isp1362_show_reg(isp1362_hcd, HCINTLLAST); 883 isp1362_show_reg(isp1362_hcd, HCINTLCURR); 884 isp1362_show_reg(isp1362_hcd, HCATLBUFSZ); 885 isp1362_show_reg(isp1362_hcd, HCATLBLKSZ); 886 /* only valid after ATL_DONE interrupt 887 * isp1362_show_reg(isp1362_hcd, HCATLDONE); 888 */ 889 isp1362_show_reg(isp1362_hcd, HCATLSKIP); 890 isp1362_show_reg(isp1362_hcd, HCATLLAST); 891 isp1362_show_reg(isp1362_hcd, HCATLCURR); 892 isp1362_show_reg(isp1362_hcd, HCATLDTC); 893 isp1362_show_reg(isp1362_hcd, HCATLDTCTO); 894 } 895 896 static void isp1362_write_diraddr(struct isp1362_hcd *isp1362_hcd, u16 offset, u16 len) 897 { 898 len = (len + 1) & ~1; 899 900 isp1362_clr_mask16(isp1362_hcd, HCDMACFG, HCDMACFG_CTR_ENABLE); 901 isp1362_write_reg32(isp1362_hcd, HCDIRADDR, 902 HCDIRADDR_ADDR(offset) | HCDIRADDR_COUNT(len)); 903 } 904 905 static void isp1362_read_buffer(struct isp1362_hcd *isp1362_hcd, void *buf, u16 offset, int len) 906 { 907 isp1362_write_diraddr(isp1362_hcd, offset, len); 908 909 DBG(3, "%s: Reading %d byte from buffer @%04x to memory @ %p\n", 910 __func__, len, offset, buf); 911 912 isp1362_write_reg16(isp1362_hcd, HCuPINT, HCuPINT_EOT); 913 914 isp1362_write_addr(isp1362_hcd, ISP1362_REG_HCDIRDATA); 915 916 isp1362_read_fifo(isp1362_hcd, buf, len); 917 isp1362_write_reg16(isp1362_hcd, HCuPINT, HCuPINT_EOT); 918 } 919 920 static void isp1362_write_buffer(struct isp1362_hcd *isp1362_hcd, void *buf, u16 offset, int len) 921 { 922 isp1362_write_diraddr(isp1362_hcd, offset, len); 923 924 DBG(3, "%s: Writing %d byte to buffer @%04x from memory @ %p\n", 925 __func__, len, offset, buf); 926 927 isp1362_write_reg16(isp1362_hcd, HCuPINT, HCuPINT_EOT); 928 929 isp1362_write_addr(isp1362_hcd, ISP1362_REG_HCDIRDATA | ISP1362_REG_WRITE_OFFSET); 930 isp1362_write_fifo(isp1362_hcd, buf, len); 931 932 isp1362_write_reg16(isp1362_hcd, HCuPINT, HCuPINT_EOT); 933 } 934 935 static void __attribute__((unused)) dump_data(char *buf, int len) 936 { 937 if (dbg_level > 0) { 938 int k; 939 int lf = 0; 940 941 for (k = 0; k < len; ++k) { 942 if (!lf) 943 DBG(0, "%04x:", k); 944 printk(" %02x", ((u8 *) buf)[k]); 945 lf = 1; 946 if (!k) 947 continue; 948 if (k % 16 == 15) { 949 printk("\n"); 950 lf = 0; 951 continue; 952 } 953 if (k % 8 == 7) 954 printk(" "); 955 if (k % 4 == 3) 956 printk(" "); 957 } 958 if (lf) 959 printk("\n"); 960 } 961 } 962 963 #if defined(PTD_TRACE) 964 965 static void dump_ptd(struct ptd *ptd) 966 { 967 DBG(0, "EP %p: CC=%x EP=%d DIR=%x CNT=%d LEN=%d MPS=%d TGL=%x ACT=%x FA=%d SPD=%x SF=%x PR=%x LST=%x\n", 968 container_of(ptd, struct isp1362_ep, ptd), 969 PTD_GET_CC(ptd), PTD_GET_EP(ptd), PTD_GET_DIR(ptd), 970 PTD_GET_COUNT(ptd), PTD_GET_LEN(ptd), PTD_GET_MPS(ptd), 971 PTD_GET_TOGGLE(ptd), PTD_GET_ACTIVE(ptd), PTD_GET_FA(ptd), 972 PTD_GET_SPD(ptd), PTD_GET_SF_INT(ptd), PTD_GET_PR(ptd), PTD_GET_LAST(ptd)); 973 DBG(0, " %04x %04x %04x %04x\n", ptd->count, ptd->mps, ptd->len, ptd->faddr); 974 } 975 976 static void dump_ptd_out_data(struct ptd *ptd, u8 *buf) 977 { 978 if (dbg_level > 0) { 979 if (PTD_GET_DIR(ptd) != PTD_DIR_IN && PTD_GET_LEN(ptd)) { 980 DBG(0, "--out->\n"); 981 dump_data(buf, PTD_GET_LEN(ptd)); 982 } 983 } 984 } 985 986 static void dump_ptd_in_data(struct ptd *ptd, u8 *buf) 987 { 988 if (dbg_level > 0) { 989 if (PTD_GET_DIR(ptd) == PTD_DIR_IN && PTD_GET_COUNT(ptd)) { 990 DBG(0, "<--in--\n"); 991 dump_data(buf, PTD_GET_COUNT(ptd)); 992 } 993 DBG(0, "-----\n"); 994 } 995 } 996 997 static void dump_ptd_queue(struct isp1362_ep_queue *epq) 998 { 999 struct isp1362_ep *ep; 1000 int dbg = dbg_level; 1001 1002 dbg_level = 1; 1003 list_for_each_entry(ep, &epq->active, active) { 1004 dump_ptd(&ep->ptd); 1005 dump_data(ep->data, ep->length); 1006 } 1007 dbg_level = dbg; 1008 } 1009 #else 1010 #define dump_ptd(ptd) do {} while (0) 1011 #define dump_ptd_in_data(ptd, buf) do {} while (0) 1012 #define dump_ptd_out_data(ptd, buf) do {} while (0) 1013 #define dump_ptd_data(ptd, buf) do {} while (0) 1014 #define dump_ptd_queue(epq) do {} while (0) 1015 #endif 1016