1 /* 2 * Copyright (c) 2001-2002 by David Brownell 3 * 4 * This program is free software; you can redistribute it and/or modify it 5 * under the terms of the GNU General Public License as published by the 6 * Free Software Foundation; either version 2 of the License, or (at your 7 * option) any later version. 8 * 9 * This program is distributed in the hope that it will be useful, but 10 * WITHOUT ANY WARRANTY; without even the implied warranty of MERCHANTABILITY 11 * or FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License 12 * for more details. 13 * 14 * You should have received a copy of the GNU General Public License 15 * along with this program; if not, write to the Free Software Foundation, 16 * Inc., 675 Mass Ave, Cambridge, MA 02139, USA. 17 */ 18 19 #ifndef __LINUX_EHCI_HCD_H 20 #define __LINUX_EHCI_HCD_H 21 22 /* definitions used for the EHCI driver */ 23 24 /* 25 * __hc32 and __hc16 are "Host Controller" types, they may be equivalent to 26 * __leXX (normally) or __beXX (given EHCI_BIG_ENDIAN_DESC), depending on 27 * the host controller implementation. 28 * 29 * To facilitate the strongest possible byte-order checking from "sparse" 30 * and so on, we use __leXX unless that's not practical. 31 */ 32 #ifdef CONFIG_USB_EHCI_BIG_ENDIAN_DESC 33 typedef __u32 __bitwise __hc32; 34 typedef __u16 __bitwise __hc16; 35 #else 36 #define __hc32 __le32 37 #define __hc16 __le16 38 #endif 39 40 /* statistics can be kept for tuning/monitoring */ 41 #if defined(DEBUG) || defined(CONFIG_DYNAMIC_DEBUG) 42 #define EHCI_STATS 43 #endif 44 45 struct ehci_stats { 46 /* irq usage */ 47 unsigned long normal; 48 unsigned long error; 49 unsigned long iaa; 50 unsigned long lost_iaa; 51 52 /* termination of urbs from core */ 53 unsigned long complete; 54 unsigned long unlink; 55 }; 56 57 /* ehci_hcd->lock guards shared data against other CPUs: 58 * ehci_hcd: async, unlink, periodic (and shadow), ... 59 * usb_host_endpoint: hcpriv 60 * ehci_qh: qh_next, qtd_list 61 * ehci_qtd: qtd_list 62 * 63 * Also, hold this lock when talking to HC registers or 64 * when updating hw_* fields in shared qh/qtd/... structures. 65 */ 66 67 #define EHCI_MAX_ROOT_PORTS 15 /* see HCS_N_PORTS */ 68 69 /* 70 * ehci_rh_state values of EHCI_RH_RUNNING or above mean that the 71 * controller may be doing DMA. Lower values mean there's no DMA. 72 */ 73 enum ehci_rh_state { 74 EHCI_RH_HALTED, 75 EHCI_RH_SUSPENDED, 76 EHCI_RH_RUNNING, 77 EHCI_RH_STOPPING 78 }; 79 80 /* 81 * Timer events, ordered by increasing delay length. 82 * Always update event_delays_ns[] and event_handlers[] (defined in 83 * ehci-timer.c) in parallel with this list. 84 */ 85 enum ehci_hrtimer_event { 86 EHCI_HRTIMER_POLL_ASS, /* Poll for async schedule off */ 87 EHCI_HRTIMER_POLL_PSS, /* Poll for periodic schedule off */ 88 EHCI_HRTIMER_POLL_DEAD, /* Wait for dead controller to stop */ 89 EHCI_HRTIMER_UNLINK_INTR, /* Wait for interrupt QH unlink */ 90 EHCI_HRTIMER_FREE_ITDS, /* Wait for unused iTDs and siTDs */ 91 EHCI_HRTIMER_START_UNLINK_INTR, /* Unlink empty interrupt QHs */ 92 EHCI_HRTIMER_ASYNC_UNLINKS, /* Unlink empty async QHs */ 93 EHCI_HRTIMER_IAA_WATCHDOG, /* Handle lost IAA interrupts */ 94 EHCI_HRTIMER_DISABLE_PERIODIC, /* Wait to disable periodic sched */ 95 EHCI_HRTIMER_DISABLE_ASYNC, /* Wait to disable async sched */ 96 EHCI_HRTIMER_IO_WATCHDOG, /* Check for missing IRQs */ 97 EHCI_HRTIMER_NUM_EVENTS /* Must come last */ 98 }; 99 #define EHCI_HRTIMER_NO_EVENT 99 100 101 struct ehci_hcd { /* one per controller */ 102 /* timing support */ 103 enum ehci_hrtimer_event next_hrtimer_event; 104 unsigned enabled_hrtimer_events; 105 ktime_t hr_timeouts[EHCI_HRTIMER_NUM_EVENTS]; 106 struct hrtimer hrtimer; 107 108 int PSS_poll_count; 109 int ASS_poll_count; 110 int died_poll_count; 111 112 /* glue to PCI and HCD framework */ 113 struct ehci_caps __iomem *caps; 114 struct ehci_regs __iomem *regs; 115 struct ehci_dbg_port __iomem *debug; 116 117 __u32 hcs_params; /* cached register copy */ 118 spinlock_t lock; 119 enum ehci_rh_state rh_state; 120 121 /* general schedule support */ 122 bool scanning:1; 123 bool need_rescan:1; 124 bool intr_unlinking:1; 125 bool iaa_in_progress:1; 126 bool async_unlinking:1; 127 bool shutdown:1; 128 struct ehci_qh *qh_scan_next; 129 130 /* async schedule support */ 131 struct ehci_qh *async; 132 struct ehci_qh *dummy; /* For AMD quirk use */ 133 struct list_head async_unlink; 134 struct list_head async_idle; 135 unsigned async_unlink_cycle; 136 unsigned async_count; /* async activity count */ 137 138 /* periodic schedule support */ 139 #define DEFAULT_I_TDPS 1024 /* some HCs can do less */ 140 unsigned periodic_size; 141 __hc32 *periodic; /* hw periodic table */ 142 dma_addr_t periodic_dma; 143 struct list_head intr_qh_list; 144 unsigned i_thresh; /* uframes HC might cache */ 145 146 union ehci_shadow *pshadow; /* mirror hw periodic table */ 147 struct list_head intr_unlink_wait; 148 struct list_head intr_unlink; 149 unsigned intr_unlink_wait_cycle; 150 unsigned intr_unlink_cycle; 151 unsigned now_frame; /* frame from HC hardware */ 152 unsigned last_iso_frame; /* last frame scanned for iso */ 153 unsigned intr_count; /* intr activity count */ 154 unsigned isoc_count; /* isoc activity count */ 155 unsigned periodic_count; /* periodic activity count */ 156 unsigned uframe_periodic_max; /* max periodic time per uframe */ 157 158 159 /* list of itds & sitds completed while now_frame was still active */ 160 struct list_head cached_itd_list; 161 struct ehci_itd *last_itd_to_free; 162 struct list_head cached_sitd_list; 163 struct ehci_sitd *last_sitd_to_free; 164 165 /* per root hub port */ 166 unsigned long reset_done [EHCI_MAX_ROOT_PORTS]; 167 168 /* bit vectors (one bit per port) */ 169 unsigned long bus_suspended; /* which ports were 170 already suspended at the start of a bus suspend */ 171 unsigned long companion_ports; /* which ports are 172 dedicated to the companion controller */ 173 unsigned long owned_ports; /* which ports are 174 owned by the companion during a bus suspend */ 175 unsigned long port_c_suspend; /* which ports have 176 the change-suspend feature turned on */ 177 unsigned long suspended_ports; /* which ports are 178 suspended */ 179 unsigned long resuming_ports; /* which ports have 180 started to resume */ 181 182 /* per-HC memory pools (could be per-bus, but ...) */ 183 struct dma_pool *qh_pool; /* qh per active urb */ 184 struct dma_pool *qtd_pool; /* one or more per qh */ 185 struct dma_pool *itd_pool; /* itd per iso urb */ 186 struct dma_pool *sitd_pool; /* sitd per split iso urb */ 187 188 unsigned random_frame; 189 unsigned long next_statechange; 190 ktime_t last_periodic_enable; 191 u32 command; 192 193 /* SILICON QUIRKS */ 194 unsigned no_selective_suspend:1; 195 unsigned has_fsl_port_bug:1; /* FreeScale */ 196 unsigned big_endian_mmio:1; 197 unsigned big_endian_desc:1; 198 unsigned big_endian_capbase:1; 199 unsigned has_amcc_usb23:1; 200 unsigned need_io_watchdog:1; 201 unsigned amd_pll_fix:1; 202 unsigned use_dummy_qh:1; /* AMD Frame List table quirk*/ 203 unsigned has_synopsys_hc_bug:1; /* Synopsys HC */ 204 unsigned frame_index_bug:1; /* MosChip (AKA NetMos) */ 205 unsigned need_oc_pp_cycle:1; /* MPC834X port power */ 206 207 /* required for usb32 quirk */ 208 #define OHCI_CTRL_HCFS (3 << 6) 209 #define OHCI_USB_OPER (2 << 6) 210 #define OHCI_USB_SUSPEND (3 << 6) 211 212 #define OHCI_HCCTRL_OFFSET 0x4 213 #define OHCI_HCCTRL_LEN 0x4 214 __hc32 *ohci_hcctrl_reg; 215 unsigned has_hostpc:1; 216 unsigned has_tdi_phy_lpm:1; 217 unsigned has_ppcd:1; /* support per-port change bits */ 218 u8 sbrn; /* packed release number */ 219 220 /* irq statistics */ 221 #ifdef EHCI_STATS 222 struct ehci_stats stats; 223 # define COUNT(x) do { (x)++; } while (0) 224 #else 225 # define COUNT(x) do {} while (0) 226 #endif 227 228 /* debug files */ 229 #if defined(DEBUG) || defined(CONFIG_DYNAMIC_DEBUG) 230 struct dentry *debug_dir; 231 #endif 232 233 /* platform-specific data -- must come last */ 234 unsigned long priv[0] __aligned(sizeof(s64)); 235 }; 236 237 /* convert between an HCD pointer and the corresponding EHCI_HCD */ 238 static inline struct ehci_hcd *hcd_to_ehci (struct usb_hcd *hcd) 239 { 240 return (struct ehci_hcd *) (hcd->hcd_priv); 241 } 242 static inline struct usb_hcd *ehci_to_hcd (struct ehci_hcd *ehci) 243 { 244 return container_of ((void *) ehci, struct usb_hcd, hcd_priv); 245 } 246 247 /*-------------------------------------------------------------------------*/ 248 249 #include <linux/usb/ehci_def.h> 250 251 /*-------------------------------------------------------------------------*/ 252 253 #define QTD_NEXT(ehci, dma) cpu_to_hc32(ehci, (u32)dma) 254 255 /* 256 * EHCI Specification 0.95 Section 3.5 257 * QTD: describe data transfer components (buffer, direction, ...) 258 * See Fig 3-6 "Queue Element Transfer Descriptor Block Diagram". 259 * 260 * These are associated only with "QH" (Queue Head) structures, 261 * used with control, bulk, and interrupt transfers. 262 */ 263 struct ehci_qtd { 264 /* first part defined by EHCI spec */ 265 __hc32 hw_next; /* see EHCI 3.5.1 */ 266 __hc32 hw_alt_next; /* see EHCI 3.5.2 */ 267 __hc32 hw_token; /* see EHCI 3.5.3 */ 268 #define QTD_TOGGLE (1 << 31) /* data toggle */ 269 #define QTD_LENGTH(tok) (((tok)>>16) & 0x7fff) 270 #define QTD_IOC (1 << 15) /* interrupt on complete */ 271 #define QTD_CERR(tok) (((tok)>>10) & 0x3) 272 #define QTD_PID(tok) (((tok)>>8) & 0x3) 273 #define QTD_STS_ACTIVE (1 << 7) /* HC may execute this */ 274 #define QTD_STS_HALT (1 << 6) /* halted on error */ 275 #define QTD_STS_DBE (1 << 5) /* data buffer error (in HC) */ 276 #define QTD_STS_BABBLE (1 << 4) /* device was babbling (qtd halted) */ 277 #define QTD_STS_XACT (1 << 3) /* device gave illegal response */ 278 #define QTD_STS_MMF (1 << 2) /* incomplete split transaction */ 279 #define QTD_STS_STS (1 << 1) /* split transaction state */ 280 #define QTD_STS_PING (1 << 0) /* issue PING? */ 281 282 #define ACTIVE_BIT(ehci) cpu_to_hc32(ehci, QTD_STS_ACTIVE) 283 #define HALT_BIT(ehci) cpu_to_hc32(ehci, QTD_STS_HALT) 284 #define STATUS_BIT(ehci) cpu_to_hc32(ehci, QTD_STS_STS) 285 286 __hc32 hw_buf [5]; /* see EHCI 3.5.4 */ 287 __hc32 hw_buf_hi [5]; /* Appendix B */ 288 289 /* the rest is HCD-private */ 290 dma_addr_t qtd_dma; /* qtd address */ 291 struct list_head qtd_list; /* sw qtd list */ 292 struct urb *urb; /* qtd's urb */ 293 size_t length; /* length of buffer */ 294 } __attribute__ ((aligned (32))); 295 296 /* mask NakCnt+T in qh->hw_alt_next */ 297 #define QTD_MASK(ehci) cpu_to_hc32 (ehci, ~0x1f) 298 299 #define IS_SHORT_READ(token) (QTD_LENGTH (token) != 0 && QTD_PID (token) == 1) 300 301 /*-------------------------------------------------------------------------*/ 302 303 /* type tag from {qh,itd,sitd,fstn}->hw_next */ 304 #define Q_NEXT_TYPE(ehci,dma) ((dma) & cpu_to_hc32(ehci, 3 << 1)) 305 306 /* 307 * Now the following defines are not converted using the 308 * cpu_to_le32() macro anymore, since we have to support 309 * "dynamic" switching between be and le support, so that the driver 310 * can be used on one system with SoC EHCI controller using big-endian 311 * descriptors as well as a normal little-endian PCI EHCI controller. 312 */ 313 /* values for that type tag */ 314 #define Q_TYPE_ITD (0 << 1) 315 #define Q_TYPE_QH (1 << 1) 316 #define Q_TYPE_SITD (2 << 1) 317 #define Q_TYPE_FSTN (3 << 1) 318 319 /* next async queue entry, or pointer to interrupt/periodic QH */ 320 #define QH_NEXT(ehci,dma) (cpu_to_hc32(ehci, (((u32)dma)&~0x01f)|Q_TYPE_QH)) 321 322 /* for periodic/async schedules and qtd lists, mark end of list */ 323 #define EHCI_LIST_END(ehci) cpu_to_hc32(ehci, 1) /* "null pointer" to hw */ 324 325 /* 326 * Entries in periodic shadow table are pointers to one of four kinds 327 * of data structure. That's dictated by the hardware; a type tag is 328 * encoded in the low bits of the hardware's periodic schedule. Use 329 * Q_NEXT_TYPE to get the tag. 330 * 331 * For entries in the async schedule, the type tag always says "qh". 332 */ 333 union ehci_shadow { 334 struct ehci_qh *qh; /* Q_TYPE_QH */ 335 struct ehci_itd *itd; /* Q_TYPE_ITD */ 336 struct ehci_sitd *sitd; /* Q_TYPE_SITD */ 337 struct ehci_fstn *fstn; /* Q_TYPE_FSTN */ 338 __hc32 *hw_next; /* (all types) */ 339 void *ptr; 340 }; 341 342 /*-------------------------------------------------------------------------*/ 343 344 /* 345 * EHCI Specification 0.95 Section 3.6 346 * QH: describes control/bulk/interrupt endpoints 347 * See Fig 3-7 "Queue Head Structure Layout". 348 * 349 * These appear in both the async and (for interrupt) periodic schedules. 350 */ 351 352 /* first part defined by EHCI spec */ 353 struct ehci_qh_hw { 354 __hc32 hw_next; /* see EHCI 3.6.1 */ 355 __hc32 hw_info1; /* see EHCI 3.6.2 */ 356 #define QH_CONTROL_EP (1 << 27) /* FS/LS control endpoint */ 357 #define QH_HEAD (1 << 15) /* Head of async reclamation list */ 358 #define QH_TOGGLE_CTL (1 << 14) /* Data toggle control */ 359 #define QH_HIGH_SPEED (2 << 12) /* Endpoint speed */ 360 #define QH_LOW_SPEED (1 << 12) 361 #define QH_FULL_SPEED (0 << 12) 362 #define QH_INACTIVATE (1 << 7) /* Inactivate on next transaction */ 363 __hc32 hw_info2; /* see EHCI 3.6.2 */ 364 #define QH_SMASK 0x000000ff 365 #define QH_CMASK 0x0000ff00 366 #define QH_HUBADDR 0x007f0000 367 #define QH_HUBPORT 0x3f800000 368 #define QH_MULT 0xc0000000 369 __hc32 hw_current; /* qtd list - see EHCI 3.6.4 */ 370 371 /* qtd overlay (hardware parts of a struct ehci_qtd) */ 372 __hc32 hw_qtd_next; 373 __hc32 hw_alt_next; 374 __hc32 hw_token; 375 __hc32 hw_buf [5]; 376 __hc32 hw_buf_hi [5]; 377 } __attribute__ ((aligned(32))); 378 379 struct ehci_qh { 380 struct ehci_qh_hw *hw; /* Must come first */ 381 /* the rest is HCD-private */ 382 dma_addr_t qh_dma; /* address of qh */ 383 union ehci_shadow qh_next; /* ptr to qh; or periodic */ 384 struct list_head qtd_list; /* sw qtd list */ 385 struct list_head intr_node; /* list of intr QHs */ 386 struct ehci_qtd *dummy; 387 struct list_head unlink_node; 388 389 unsigned unlink_cycle; 390 391 u8 qh_state; 392 #define QH_STATE_LINKED 1 /* HC sees this */ 393 #define QH_STATE_UNLINK 2 /* HC may still see this */ 394 #define QH_STATE_IDLE 3 /* HC doesn't see this */ 395 #define QH_STATE_UNLINK_WAIT 4 /* LINKED and on unlink q */ 396 #define QH_STATE_COMPLETING 5 /* don't touch token.HALT */ 397 398 u8 xacterrs; /* XactErr retry counter */ 399 #define QH_XACTERR_MAX 32 /* XactErr retry limit */ 400 401 /* periodic schedule info */ 402 u8 usecs; /* intr bandwidth */ 403 u8 gap_uf; /* uframes split/csplit gap */ 404 u8 c_usecs; /* ... split completion bw */ 405 u16 tt_usecs; /* tt downstream bandwidth */ 406 unsigned short period; /* polling interval */ 407 unsigned short start; /* where polling starts */ 408 #define NO_FRAME ((unsigned short)~0) /* pick new start */ 409 410 struct usb_device *dev; /* access to TT */ 411 unsigned is_out:1; /* bulk or intr OUT */ 412 unsigned clearing_tt:1; /* Clear-TT-Buf in progress */ 413 unsigned dequeue_during_giveback:1; 414 unsigned exception:1; /* got a fault, or an unlink 415 was requested */ 416 }; 417 418 /*-------------------------------------------------------------------------*/ 419 420 /* description of one iso transaction (up to 3 KB data if highspeed) */ 421 struct ehci_iso_packet { 422 /* These will be copied to iTD when scheduling */ 423 u64 bufp; /* itd->hw_bufp{,_hi}[pg] |= */ 424 __hc32 transaction; /* itd->hw_transaction[i] |= */ 425 u8 cross; /* buf crosses pages */ 426 /* for full speed OUT splits */ 427 u32 buf1; 428 }; 429 430 /* temporary schedule data for packets from iso urbs (both speeds) 431 * each packet is one logical usb transaction to the device (not TT), 432 * beginning at stream->next_uframe 433 */ 434 struct ehci_iso_sched { 435 struct list_head td_list; 436 unsigned span; 437 struct ehci_iso_packet packet [0]; 438 }; 439 440 /* 441 * ehci_iso_stream - groups all (s)itds for this endpoint. 442 * acts like a qh would, if EHCI had them for ISO. 443 */ 444 struct ehci_iso_stream { 445 /* first field matches ehci_hq, but is NULL */ 446 struct ehci_qh_hw *hw; 447 448 u8 bEndpointAddress; 449 u8 highspeed; 450 struct list_head td_list; /* queued itds/sitds */ 451 struct list_head free_list; /* list of unused itds/sitds */ 452 struct usb_device *udev; 453 struct usb_host_endpoint *ep; 454 455 /* output of (re)scheduling */ 456 int next_uframe; 457 __hc32 splits; 458 459 /* the rest is derived from the endpoint descriptor, 460 * trusting urb->interval == f(epdesc->bInterval) and 461 * including the extra info for hw_bufp[0..2] 462 */ 463 u8 usecs, c_usecs; 464 u16 interval; 465 u16 tt_usecs; 466 u16 maxp; 467 u16 raw_mask; 468 unsigned bandwidth; 469 470 /* This is used to initialize iTD's hw_bufp fields */ 471 __hc32 buf0; 472 __hc32 buf1; 473 __hc32 buf2; 474 475 /* this is used to initialize sITD's tt info */ 476 __hc32 address; 477 }; 478 479 /*-------------------------------------------------------------------------*/ 480 481 /* 482 * EHCI Specification 0.95 Section 3.3 483 * Fig 3-4 "Isochronous Transaction Descriptor (iTD)" 484 * 485 * Schedule records for high speed iso xfers 486 */ 487 struct ehci_itd { 488 /* first part defined by EHCI spec */ 489 __hc32 hw_next; /* see EHCI 3.3.1 */ 490 __hc32 hw_transaction [8]; /* see EHCI 3.3.2 */ 491 #define EHCI_ISOC_ACTIVE (1<<31) /* activate transfer this slot */ 492 #define EHCI_ISOC_BUF_ERR (1<<30) /* Data buffer error */ 493 #define EHCI_ISOC_BABBLE (1<<29) /* babble detected */ 494 #define EHCI_ISOC_XACTERR (1<<28) /* XactErr - transaction error */ 495 #define EHCI_ITD_LENGTH(tok) (((tok)>>16) & 0x0fff) 496 #define EHCI_ITD_IOC (1 << 15) /* interrupt on complete */ 497 498 #define ITD_ACTIVE(ehci) cpu_to_hc32(ehci, EHCI_ISOC_ACTIVE) 499 500 __hc32 hw_bufp [7]; /* see EHCI 3.3.3 */ 501 __hc32 hw_bufp_hi [7]; /* Appendix B */ 502 503 /* the rest is HCD-private */ 504 dma_addr_t itd_dma; /* for this itd */ 505 union ehci_shadow itd_next; /* ptr to periodic q entry */ 506 507 struct urb *urb; 508 struct ehci_iso_stream *stream; /* endpoint's queue */ 509 struct list_head itd_list; /* list of stream's itds */ 510 511 /* any/all hw_transactions here may be used by that urb */ 512 unsigned frame; /* where scheduled */ 513 unsigned pg; 514 unsigned index[8]; /* in urb->iso_frame_desc */ 515 } __attribute__ ((aligned (32))); 516 517 /*-------------------------------------------------------------------------*/ 518 519 /* 520 * EHCI Specification 0.95 Section 3.4 521 * siTD, aka split-transaction isochronous Transfer Descriptor 522 * ... describe full speed iso xfers through TT in hubs 523 * see Figure 3-5 "Split-transaction Isochronous Transaction Descriptor (siTD) 524 */ 525 struct ehci_sitd { 526 /* first part defined by EHCI spec */ 527 __hc32 hw_next; 528 /* uses bit field macros above - see EHCI 0.95 Table 3-8 */ 529 __hc32 hw_fullspeed_ep; /* EHCI table 3-9 */ 530 __hc32 hw_uframe; /* EHCI table 3-10 */ 531 __hc32 hw_results; /* EHCI table 3-11 */ 532 #define SITD_IOC (1 << 31) /* interrupt on completion */ 533 #define SITD_PAGE (1 << 30) /* buffer 0/1 */ 534 #define SITD_LENGTH(x) (0x3ff & ((x)>>16)) 535 #define SITD_STS_ACTIVE (1 << 7) /* HC may execute this */ 536 #define SITD_STS_ERR (1 << 6) /* error from TT */ 537 #define SITD_STS_DBE (1 << 5) /* data buffer error (in HC) */ 538 #define SITD_STS_BABBLE (1 << 4) /* device was babbling */ 539 #define SITD_STS_XACT (1 << 3) /* illegal IN response */ 540 #define SITD_STS_MMF (1 << 2) /* incomplete split transaction */ 541 #define SITD_STS_STS (1 << 1) /* split transaction state */ 542 543 #define SITD_ACTIVE(ehci) cpu_to_hc32(ehci, SITD_STS_ACTIVE) 544 545 __hc32 hw_buf [2]; /* EHCI table 3-12 */ 546 __hc32 hw_backpointer; /* EHCI table 3-13 */ 547 __hc32 hw_buf_hi [2]; /* Appendix B */ 548 549 /* the rest is HCD-private */ 550 dma_addr_t sitd_dma; 551 union ehci_shadow sitd_next; /* ptr to periodic q entry */ 552 553 struct urb *urb; 554 struct ehci_iso_stream *stream; /* endpoint's queue */ 555 struct list_head sitd_list; /* list of stream's sitds */ 556 unsigned frame; 557 unsigned index; 558 } __attribute__ ((aligned (32))); 559 560 /*-------------------------------------------------------------------------*/ 561 562 /* 563 * EHCI Specification 0.96 Section 3.7 564 * Periodic Frame Span Traversal Node (FSTN) 565 * 566 * Manages split interrupt transactions (using TT) that span frame boundaries 567 * into uframes 0/1; see 4.12.2.2. In those uframes, a "save place" FSTN 568 * makes the HC jump (back) to a QH to scan for fs/ls QH completions until 569 * it hits a "restore" FSTN; then it returns to finish other uframe 0/1 work. 570 */ 571 struct ehci_fstn { 572 __hc32 hw_next; /* any periodic q entry */ 573 __hc32 hw_prev; /* qh or EHCI_LIST_END */ 574 575 /* the rest is HCD-private */ 576 dma_addr_t fstn_dma; 577 union ehci_shadow fstn_next; /* ptr to periodic q entry */ 578 } __attribute__ ((aligned (32))); 579 580 /*-------------------------------------------------------------------------*/ 581 582 /* Prepare the PORTSC wakeup flags during controller suspend/resume */ 583 584 #define ehci_prepare_ports_for_controller_suspend(ehci, do_wakeup) \ 585 ehci_adjust_port_wakeup_flags(ehci, true, do_wakeup); 586 587 #define ehci_prepare_ports_for_controller_resume(ehci) \ 588 ehci_adjust_port_wakeup_flags(ehci, false, false); 589 590 /*-------------------------------------------------------------------------*/ 591 592 #ifdef CONFIG_USB_EHCI_ROOT_HUB_TT 593 594 /* 595 * Some EHCI controllers have a Transaction Translator built into the 596 * root hub. This is a non-standard feature. Each controller will need 597 * to add code to the following inline functions, and call them as 598 * needed (mostly in root hub code). 599 */ 600 601 #define ehci_is_TDI(e) (ehci_to_hcd(e)->has_tt) 602 603 /* Returns the speed of a device attached to a port on the root hub. */ 604 static inline unsigned int 605 ehci_port_speed(struct ehci_hcd *ehci, unsigned int portsc) 606 { 607 if (ehci_is_TDI(ehci)) { 608 switch ((portsc >> (ehci->has_hostpc ? 25 : 26)) & 3) { 609 case 0: 610 return 0; 611 case 1: 612 return USB_PORT_STAT_LOW_SPEED; 613 case 2: 614 default: 615 return USB_PORT_STAT_HIGH_SPEED; 616 } 617 } 618 return USB_PORT_STAT_HIGH_SPEED; 619 } 620 621 #else 622 623 #define ehci_is_TDI(e) (0) 624 625 #define ehci_port_speed(ehci, portsc) USB_PORT_STAT_HIGH_SPEED 626 #endif 627 628 /*-------------------------------------------------------------------------*/ 629 630 #ifdef CONFIG_PPC_83xx 631 /* Some Freescale processors have an erratum in which the TT 632 * port number in the queue head was 0..N-1 instead of 1..N. 633 */ 634 #define ehci_has_fsl_portno_bug(e) ((e)->has_fsl_port_bug) 635 #else 636 #define ehci_has_fsl_portno_bug(e) (0) 637 #endif 638 639 /* 640 * While most USB host controllers implement their registers in 641 * little-endian format, a minority (celleb companion chip) implement 642 * them in big endian format. 643 * 644 * This attempts to support either format at compile time without a 645 * runtime penalty, or both formats with the additional overhead 646 * of checking a flag bit. 647 * 648 * ehci_big_endian_capbase is a special quirk for controllers that 649 * implement the HC capability registers as separate registers and not 650 * as fields of a 32-bit register. 651 */ 652 653 #ifdef CONFIG_USB_EHCI_BIG_ENDIAN_MMIO 654 #define ehci_big_endian_mmio(e) ((e)->big_endian_mmio) 655 #define ehci_big_endian_capbase(e) ((e)->big_endian_capbase) 656 #else 657 #define ehci_big_endian_mmio(e) 0 658 #define ehci_big_endian_capbase(e) 0 659 #endif 660 661 /* 662 * Big-endian read/write functions are arch-specific. 663 * Other arches can be added if/when they're needed. 664 */ 665 #if defined(CONFIG_ARM) && defined(CONFIG_ARCH_IXP4XX) 666 #define readl_be(addr) __raw_readl((__force unsigned *)addr) 667 #define writel_be(val, addr) __raw_writel(val, (__force unsigned *)addr) 668 #endif 669 670 static inline unsigned int ehci_readl(const struct ehci_hcd *ehci, 671 __u32 __iomem * regs) 672 { 673 #ifdef CONFIG_USB_EHCI_BIG_ENDIAN_MMIO 674 return ehci_big_endian_mmio(ehci) ? 675 readl_be(regs) : 676 readl(regs); 677 #else 678 return readl(regs); 679 #endif 680 } 681 682 static inline void ehci_writel(const struct ehci_hcd *ehci, 683 const unsigned int val, __u32 __iomem *regs) 684 { 685 #ifdef CONFIG_USB_EHCI_BIG_ENDIAN_MMIO 686 ehci_big_endian_mmio(ehci) ? 687 writel_be(val, regs) : 688 writel(val, regs); 689 #else 690 writel(val, regs); 691 #endif 692 } 693 694 /* 695 * On certain ppc-44x SoC there is a HW issue, that could only worked around with 696 * explicit suspend/operate of OHCI. This function hereby makes sense only on that arch. 697 * Other common bits are dependent on has_amcc_usb23 quirk flag. 698 */ 699 #ifdef CONFIG_44x 700 static inline void set_ohci_hcfs(struct ehci_hcd *ehci, int operational) 701 { 702 u32 hc_control; 703 704 hc_control = (readl_be(ehci->ohci_hcctrl_reg) & ~OHCI_CTRL_HCFS); 705 if (operational) 706 hc_control |= OHCI_USB_OPER; 707 else 708 hc_control |= OHCI_USB_SUSPEND; 709 710 writel_be(hc_control, ehci->ohci_hcctrl_reg); 711 (void) readl_be(ehci->ohci_hcctrl_reg); 712 } 713 #else 714 static inline void set_ohci_hcfs(struct ehci_hcd *ehci, int operational) 715 { } 716 #endif 717 718 /*-------------------------------------------------------------------------*/ 719 720 /* 721 * The AMCC 440EPx not only implements its EHCI registers in big-endian 722 * format, but also its DMA data structures (descriptors). 723 * 724 * EHCI controllers accessed through PCI work normally (little-endian 725 * everywhere), so we won't bother supporting a BE-only mode for now. 726 */ 727 #ifdef CONFIG_USB_EHCI_BIG_ENDIAN_DESC 728 #define ehci_big_endian_desc(e) ((e)->big_endian_desc) 729 730 /* cpu to ehci */ 731 static inline __hc32 cpu_to_hc32 (const struct ehci_hcd *ehci, const u32 x) 732 { 733 return ehci_big_endian_desc(ehci) 734 ? (__force __hc32)cpu_to_be32(x) 735 : (__force __hc32)cpu_to_le32(x); 736 } 737 738 /* ehci to cpu */ 739 static inline u32 hc32_to_cpu (const struct ehci_hcd *ehci, const __hc32 x) 740 { 741 return ehci_big_endian_desc(ehci) 742 ? be32_to_cpu((__force __be32)x) 743 : le32_to_cpu((__force __le32)x); 744 } 745 746 static inline u32 hc32_to_cpup (const struct ehci_hcd *ehci, const __hc32 *x) 747 { 748 return ehci_big_endian_desc(ehci) 749 ? be32_to_cpup((__force __be32 *)x) 750 : le32_to_cpup((__force __le32 *)x); 751 } 752 753 #else 754 755 /* cpu to ehci */ 756 static inline __hc32 cpu_to_hc32 (const struct ehci_hcd *ehci, const u32 x) 757 { 758 return cpu_to_le32(x); 759 } 760 761 /* ehci to cpu */ 762 static inline u32 hc32_to_cpu (const struct ehci_hcd *ehci, const __hc32 x) 763 { 764 return le32_to_cpu(x); 765 } 766 767 static inline u32 hc32_to_cpup (const struct ehci_hcd *ehci, const __hc32 *x) 768 { 769 return le32_to_cpup(x); 770 } 771 772 #endif 773 774 /*-------------------------------------------------------------------------*/ 775 776 #define ehci_dbg(ehci, fmt, args...) \ 777 dev_dbg(ehci_to_hcd(ehci)->self.controller , fmt , ## args) 778 #define ehci_err(ehci, fmt, args...) \ 779 dev_err(ehci_to_hcd(ehci)->self.controller , fmt , ## args) 780 #define ehci_info(ehci, fmt, args...) \ 781 dev_info(ehci_to_hcd(ehci)->self.controller , fmt , ## args) 782 #define ehci_warn(ehci, fmt, args...) \ 783 dev_warn(ehci_to_hcd(ehci)->self.controller , fmt , ## args) 784 785 786 #if !defined(DEBUG) && !defined(CONFIG_DYNAMIC_DEBUG) 787 #define STUB_DEBUG_FILES 788 #endif /* !DEBUG && !CONFIG_DYNAMIC_DEBUG */ 789 790 /*-------------------------------------------------------------------------*/ 791 792 /* Declarations of things exported for use by ehci platform drivers */ 793 794 struct ehci_driver_overrides { 795 size_t extra_priv_size; 796 int (*reset)(struct usb_hcd *hcd); 797 }; 798 799 extern void ehci_init_driver(struct hc_driver *drv, 800 const struct ehci_driver_overrides *over); 801 extern int ehci_setup(struct usb_hcd *hcd); 802 extern int ehci_handshake(struct ehci_hcd *ehci, void __iomem *ptr, 803 u32 mask, u32 done, int usec); 804 805 #ifdef CONFIG_PM 806 extern int ehci_suspend(struct usb_hcd *hcd, bool do_wakeup); 807 extern int ehci_resume(struct usb_hcd *hcd, bool hibernated); 808 #endif /* CONFIG_PM */ 809 810 #endif /* __LINUX_EHCI_HCD_H */ 811