1 /* 2 * Copyright (c) 2001-2002 by David Brownell 3 * 4 * This program is free software; you can redistribute it and/or modify it 5 * under the terms of the GNU General Public License as published by the 6 * Free Software Foundation; either version 2 of the License, or (at your 7 * option) any later version. 8 * 9 * This program is distributed in the hope that it will be useful, but 10 * WITHOUT ANY WARRANTY; without even the implied warranty of MERCHANTABILITY 11 * or FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License 12 * for more details. 13 * 14 * You should have received a copy of the GNU General Public License 15 * along with this program; if not, write to the Free Software Foundation, 16 * Inc., 675 Mass Ave, Cambridge, MA 02139, USA. 17 */ 18 19 #ifndef __LINUX_EHCI_HCD_H 20 #define __LINUX_EHCI_HCD_H 21 22 /* definitions used for the EHCI driver */ 23 24 /* 25 * __hc32 and __hc16 are "Host Controller" types, they may be equivalent to 26 * __leXX (normally) or __beXX (given EHCI_BIG_ENDIAN_DESC), depending on 27 * the host controller implementation. 28 * 29 * To facilitate the strongest possible byte-order checking from "sparse" 30 * and so on, we use __leXX unless that's not practical. 31 */ 32 #ifdef CONFIG_USB_EHCI_BIG_ENDIAN_DESC 33 typedef __u32 __bitwise __hc32; 34 typedef __u16 __bitwise __hc16; 35 #else 36 #define __hc32 __le32 37 #define __hc16 __le16 38 #endif 39 40 /* statistics can be kept for tuning/monitoring */ 41 struct ehci_stats { 42 /* irq usage */ 43 unsigned long normal; 44 unsigned long error; 45 unsigned long reclaim; 46 unsigned long lost_iaa; 47 48 /* termination of urbs from core */ 49 unsigned long complete; 50 unsigned long unlink; 51 }; 52 53 /* ehci_hcd->lock guards shared data against other CPUs: 54 * ehci_hcd: async, reclaim, periodic (and shadow), ... 55 * usb_host_endpoint: hcpriv 56 * ehci_qh: qh_next, qtd_list 57 * ehci_qtd: qtd_list 58 * 59 * Also, hold this lock when talking to HC registers or 60 * when updating hw_* fields in shared qh/qtd/... structures. 61 */ 62 63 #define EHCI_MAX_ROOT_PORTS 15 /* see HCS_N_PORTS */ 64 65 struct ehci_hcd { /* one per controller */ 66 /* glue to PCI and HCD framework */ 67 struct ehci_caps __iomem *caps; 68 struct ehci_regs __iomem *regs; 69 struct ehci_dbg_port __iomem *debug; 70 71 __u32 hcs_params; /* cached register copy */ 72 spinlock_t lock; 73 74 /* async schedule support */ 75 struct ehci_qh *async; 76 struct ehci_qh *dummy; /* For AMD quirk use */ 77 struct ehci_qh *reclaim; 78 unsigned scanning : 1; 79 80 /* periodic schedule support */ 81 #define DEFAULT_I_TDPS 1024 /* some HCs can do less */ 82 unsigned periodic_size; 83 __hc32 *periodic; /* hw periodic table */ 84 dma_addr_t periodic_dma; 85 unsigned i_thresh; /* uframes HC might cache */ 86 87 union ehci_shadow *pshadow; /* mirror hw periodic table */ 88 int next_uframe; /* scan periodic, start here */ 89 unsigned periodic_sched; /* periodic activity count */ 90 91 /* list of itds & sitds completed while clock_frame was still active */ 92 struct list_head cached_itd_list; 93 struct list_head cached_sitd_list; 94 unsigned clock_frame; 95 96 /* per root hub port */ 97 unsigned long reset_done [EHCI_MAX_ROOT_PORTS]; 98 99 /* bit vectors (one bit per port) */ 100 unsigned long bus_suspended; /* which ports were 101 already suspended at the start of a bus suspend */ 102 unsigned long companion_ports; /* which ports are 103 dedicated to the companion controller */ 104 unsigned long owned_ports; /* which ports are 105 owned by the companion during a bus suspend */ 106 unsigned long port_c_suspend; /* which ports have 107 the change-suspend feature turned on */ 108 unsigned long suspended_ports; /* which ports are 109 suspended */ 110 111 /* per-HC memory pools (could be per-bus, but ...) */ 112 struct dma_pool *qh_pool; /* qh per active urb */ 113 struct dma_pool *qtd_pool; /* one or more per qh */ 114 struct dma_pool *itd_pool; /* itd per iso urb */ 115 struct dma_pool *sitd_pool; /* sitd per split iso urb */ 116 117 struct timer_list iaa_watchdog; 118 struct timer_list watchdog; 119 unsigned long actions; 120 unsigned stamp; 121 unsigned random_frame; 122 unsigned long next_statechange; 123 ktime_t last_periodic_enable; 124 u32 command; 125 126 /* SILICON QUIRKS */ 127 unsigned no_selective_suspend:1; 128 unsigned has_fsl_port_bug:1; /* FreeScale */ 129 unsigned big_endian_mmio:1; 130 unsigned big_endian_desc:1; 131 unsigned has_amcc_usb23:1; 132 unsigned need_io_watchdog:1; 133 unsigned broken_periodic:1; 134 unsigned fs_i_thresh:1; /* Intel iso scheduling */ 135 unsigned use_dummy_qh:1; /* AMD Frame List table quirk*/ 136 137 /* required for usb32 quirk */ 138 #define OHCI_CTRL_HCFS (3 << 6) 139 #define OHCI_USB_OPER (2 << 6) 140 #define OHCI_USB_SUSPEND (3 << 6) 141 142 #define OHCI_HCCTRL_OFFSET 0x4 143 #define OHCI_HCCTRL_LEN 0x4 144 __hc32 *ohci_hcctrl_reg; 145 unsigned has_hostpc:1; 146 unsigned has_lpm:1; /* support link power management */ 147 unsigned has_ppcd:1; /* support per-port change bits */ 148 u8 sbrn; /* packed release number */ 149 150 /* irq statistics */ 151 #ifdef EHCI_STATS 152 struct ehci_stats stats; 153 # define COUNT(x) do { (x)++; } while (0) 154 #else 155 # define COUNT(x) do {} while (0) 156 #endif 157 158 /* debug files */ 159 #ifdef DEBUG 160 struct dentry *debug_dir; 161 #endif 162 }; 163 164 /* convert between an HCD pointer and the corresponding EHCI_HCD */ 165 static inline struct ehci_hcd *hcd_to_ehci (struct usb_hcd *hcd) 166 { 167 return (struct ehci_hcd *) (hcd->hcd_priv); 168 } 169 static inline struct usb_hcd *ehci_to_hcd (struct ehci_hcd *ehci) 170 { 171 return container_of ((void *) ehci, struct usb_hcd, hcd_priv); 172 } 173 174 175 static inline void 176 iaa_watchdog_start(struct ehci_hcd *ehci) 177 { 178 WARN_ON(timer_pending(&ehci->iaa_watchdog)); 179 mod_timer(&ehci->iaa_watchdog, 180 jiffies + msecs_to_jiffies(EHCI_IAA_MSECS)); 181 } 182 183 static inline void iaa_watchdog_done(struct ehci_hcd *ehci) 184 { 185 del_timer(&ehci->iaa_watchdog); 186 } 187 188 enum ehci_timer_action { 189 TIMER_IO_WATCHDOG, 190 TIMER_ASYNC_SHRINK, 191 TIMER_ASYNC_OFF, 192 }; 193 194 static inline void 195 timer_action_done (struct ehci_hcd *ehci, enum ehci_timer_action action) 196 { 197 clear_bit (action, &ehci->actions); 198 } 199 200 static void free_cached_lists(struct ehci_hcd *ehci); 201 202 /*-------------------------------------------------------------------------*/ 203 204 #include <linux/usb/ehci_def.h> 205 206 /*-------------------------------------------------------------------------*/ 207 208 #define QTD_NEXT(ehci, dma) cpu_to_hc32(ehci, (u32)dma) 209 210 /* 211 * EHCI Specification 0.95 Section 3.5 212 * QTD: describe data transfer components (buffer, direction, ...) 213 * See Fig 3-6 "Queue Element Transfer Descriptor Block Diagram". 214 * 215 * These are associated only with "QH" (Queue Head) structures, 216 * used with control, bulk, and interrupt transfers. 217 */ 218 struct ehci_qtd { 219 /* first part defined by EHCI spec */ 220 __hc32 hw_next; /* see EHCI 3.5.1 */ 221 __hc32 hw_alt_next; /* see EHCI 3.5.2 */ 222 __hc32 hw_token; /* see EHCI 3.5.3 */ 223 #define QTD_TOGGLE (1 << 31) /* data toggle */ 224 #define QTD_LENGTH(tok) (((tok)>>16) & 0x7fff) 225 #define QTD_IOC (1 << 15) /* interrupt on complete */ 226 #define QTD_CERR(tok) (((tok)>>10) & 0x3) 227 #define QTD_PID(tok) (((tok)>>8) & 0x3) 228 #define QTD_STS_ACTIVE (1 << 7) /* HC may execute this */ 229 #define QTD_STS_HALT (1 << 6) /* halted on error */ 230 #define QTD_STS_DBE (1 << 5) /* data buffer error (in HC) */ 231 #define QTD_STS_BABBLE (1 << 4) /* device was babbling (qtd halted) */ 232 #define QTD_STS_XACT (1 << 3) /* device gave illegal response */ 233 #define QTD_STS_MMF (1 << 2) /* incomplete split transaction */ 234 #define QTD_STS_STS (1 << 1) /* split transaction state */ 235 #define QTD_STS_PING (1 << 0) /* issue PING? */ 236 237 #define ACTIVE_BIT(ehci) cpu_to_hc32(ehci, QTD_STS_ACTIVE) 238 #define HALT_BIT(ehci) cpu_to_hc32(ehci, QTD_STS_HALT) 239 #define STATUS_BIT(ehci) cpu_to_hc32(ehci, QTD_STS_STS) 240 241 __hc32 hw_buf [5]; /* see EHCI 3.5.4 */ 242 __hc32 hw_buf_hi [5]; /* Appendix B */ 243 244 /* the rest is HCD-private */ 245 dma_addr_t qtd_dma; /* qtd address */ 246 struct list_head qtd_list; /* sw qtd list */ 247 struct urb *urb; /* qtd's urb */ 248 size_t length; /* length of buffer */ 249 } __attribute__ ((aligned (32))); 250 251 /* mask NakCnt+T in qh->hw_alt_next */ 252 #define QTD_MASK(ehci) cpu_to_hc32 (ehci, ~0x1f) 253 254 #define IS_SHORT_READ(token) (QTD_LENGTH (token) != 0 && QTD_PID (token) == 1) 255 256 /*-------------------------------------------------------------------------*/ 257 258 /* type tag from {qh,itd,sitd,fstn}->hw_next */ 259 #define Q_NEXT_TYPE(ehci,dma) ((dma) & cpu_to_hc32(ehci, 3 << 1)) 260 261 /* 262 * Now the following defines are not converted using the 263 * cpu_to_le32() macro anymore, since we have to support 264 * "dynamic" switching between be and le support, so that the driver 265 * can be used on one system with SoC EHCI controller using big-endian 266 * descriptors as well as a normal little-endian PCI EHCI controller. 267 */ 268 /* values for that type tag */ 269 #define Q_TYPE_ITD (0 << 1) 270 #define Q_TYPE_QH (1 << 1) 271 #define Q_TYPE_SITD (2 << 1) 272 #define Q_TYPE_FSTN (3 << 1) 273 274 /* next async queue entry, or pointer to interrupt/periodic QH */ 275 #define QH_NEXT(ehci,dma) (cpu_to_hc32(ehci, (((u32)dma)&~0x01f)|Q_TYPE_QH)) 276 277 /* for periodic/async schedules and qtd lists, mark end of list */ 278 #define EHCI_LIST_END(ehci) cpu_to_hc32(ehci, 1) /* "null pointer" to hw */ 279 280 /* 281 * Entries in periodic shadow table are pointers to one of four kinds 282 * of data structure. That's dictated by the hardware; a type tag is 283 * encoded in the low bits of the hardware's periodic schedule. Use 284 * Q_NEXT_TYPE to get the tag. 285 * 286 * For entries in the async schedule, the type tag always says "qh". 287 */ 288 union ehci_shadow { 289 struct ehci_qh *qh; /* Q_TYPE_QH */ 290 struct ehci_itd *itd; /* Q_TYPE_ITD */ 291 struct ehci_sitd *sitd; /* Q_TYPE_SITD */ 292 struct ehci_fstn *fstn; /* Q_TYPE_FSTN */ 293 __hc32 *hw_next; /* (all types) */ 294 void *ptr; 295 }; 296 297 /*-------------------------------------------------------------------------*/ 298 299 /* 300 * EHCI Specification 0.95 Section 3.6 301 * QH: describes control/bulk/interrupt endpoints 302 * See Fig 3-7 "Queue Head Structure Layout". 303 * 304 * These appear in both the async and (for interrupt) periodic schedules. 305 */ 306 307 /* first part defined by EHCI spec */ 308 struct ehci_qh_hw { 309 __hc32 hw_next; /* see EHCI 3.6.1 */ 310 __hc32 hw_info1; /* see EHCI 3.6.2 */ 311 #define QH_HEAD 0x00008000 312 __hc32 hw_info2; /* see EHCI 3.6.2 */ 313 #define QH_SMASK 0x000000ff 314 #define QH_CMASK 0x0000ff00 315 #define QH_HUBADDR 0x007f0000 316 #define QH_HUBPORT 0x3f800000 317 #define QH_MULT 0xc0000000 318 __hc32 hw_current; /* qtd list - see EHCI 3.6.4 */ 319 320 /* qtd overlay (hardware parts of a struct ehci_qtd) */ 321 __hc32 hw_qtd_next; 322 __hc32 hw_alt_next; 323 __hc32 hw_token; 324 __hc32 hw_buf [5]; 325 __hc32 hw_buf_hi [5]; 326 } __attribute__ ((aligned(32))); 327 328 struct ehci_qh { 329 struct ehci_qh_hw *hw; 330 /* the rest is HCD-private */ 331 dma_addr_t qh_dma; /* address of qh */ 332 union ehci_shadow qh_next; /* ptr to qh; or periodic */ 333 struct list_head qtd_list; /* sw qtd list */ 334 struct ehci_qtd *dummy; 335 struct ehci_qh *reclaim; /* next to reclaim */ 336 337 struct ehci_hcd *ehci; 338 339 /* 340 * Do NOT use atomic operations for QH refcounting. On some CPUs 341 * (PPC7448 for example), atomic operations cannot be performed on 342 * memory that is cache-inhibited (i.e. being used for DMA). 343 * Spinlocks are used to protect all QH fields. 344 */ 345 u32 refcount; 346 unsigned stamp; 347 348 u8 needs_rescan; /* Dequeue during giveback */ 349 u8 qh_state; 350 #define QH_STATE_LINKED 1 /* HC sees this */ 351 #define QH_STATE_UNLINK 2 /* HC may still see this */ 352 #define QH_STATE_IDLE 3 /* HC doesn't see this */ 353 #define QH_STATE_UNLINK_WAIT 4 /* LINKED and on reclaim q */ 354 #define QH_STATE_COMPLETING 5 /* don't touch token.HALT */ 355 356 u8 xacterrs; /* XactErr retry counter */ 357 #define QH_XACTERR_MAX 32 /* XactErr retry limit */ 358 359 /* periodic schedule info */ 360 u8 usecs; /* intr bandwidth */ 361 u8 gap_uf; /* uframes split/csplit gap */ 362 u8 c_usecs; /* ... split completion bw */ 363 u16 tt_usecs; /* tt downstream bandwidth */ 364 unsigned short period; /* polling interval */ 365 unsigned short start; /* where polling starts */ 366 #define NO_FRAME ((unsigned short)~0) /* pick new start */ 367 368 struct usb_device *dev; /* access to TT */ 369 unsigned clearing_tt:1; /* Clear-TT-Buf in progress */ 370 }; 371 372 /*-------------------------------------------------------------------------*/ 373 374 /* description of one iso transaction (up to 3 KB data if highspeed) */ 375 struct ehci_iso_packet { 376 /* These will be copied to iTD when scheduling */ 377 u64 bufp; /* itd->hw_bufp{,_hi}[pg] |= */ 378 __hc32 transaction; /* itd->hw_transaction[i] |= */ 379 u8 cross; /* buf crosses pages */ 380 /* for full speed OUT splits */ 381 u32 buf1; 382 }; 383 384 /* temporary schedule data for packets from iso urbs (both speeds) 385 * each packet is one logical usb transaction to the device (not TT), 386 * beginning at stream->next_uframe 387 */ 388 struct ehci_iso_sched { 389 struct list_head td_list; 390 unsigned span; 391 struct ehci_iso_packet packet [0]; 392 }; 393 394 /* 395 * ehci_iso_stream - groups all (s)itds for this endpoint. 396 * acts like a qh would, if EHCI had them for ISO. 397 */ 398 struct ehci_iso_stream { 399 /* first field matches ehci_hq, but is NULL */ 400 struct ehci_qh_hw *hw; 401 402 u32 refcount; 403 u8 bEndpointAddress; 404 u8 highspeed; 405 struct list_head td_list; /* queued itds/sitds */ 406 struct list_head free_list; /* list of unused itds/sitds */ 407 struct usb_device *udev; 408 struct usb_host_endpoint *ep; 409 410 /* output of (re)scheduling */ 411 int next_uframe; 412 __hc32 splits; 413 414 /* the rest is derived from the endpoint descriptor, 415 * trusting urb->interval == f(epdesc->bInterval) and 416 * including the extra info for hw_bufp[0..2] 417 */ 418 u8 usecs, c_usecs; 419 u16 interval; 420 u16 tt_usecs; 421 u16 maxp; 422 u16 raw_mask; 423 unsigned bandwidth; 424 425 /* This is used to initialize iTD's hw_bufp fields */ 426 __hc32 buf0; 427 __hc32 buf1; 428 __hc32 buf2; 429 430 /* this is used to initialize sITD's tt info */ 431 __hc32 address; 432 }; 433 434 /*-------------------------------------------------------------------------*/ 435 436 /* 437 * EHCI Specification 0.95 Section 3.3 438 * Fig 3-4 "Isochronous Transaction Descriptor (iTD)" 439 * 440 * Schedule records for high speed iso xfers 441 */ 442 struct ehci_itd { 443 /* first part defined by EHCI spec */ 444 __hc32 hw_next; /* see EHCI 3.3.1 */ 445 __hc32 hw_transaction [8]; /* see EHCI 3.3.2 */ 446 #define EHCI_ISOC_ACTIVE (1<<31) /* activate transfer this slot */ 447 #define EHCI_ISOC_BUF_ERR (1<<30) /* Data buffer error */ 448 #define EHCI_ISOC_BABBLE (1<<29) /* babble detected */ 449 #define EHCI_ISOC_XACTERR (1<<28) /* XactErr - transaction error */ 450 #define EHCI_ITD_LENGTH(tok) (((tok)>>16) & 0x0fff) 451 #define EHCI_ITD_IOC (1 << 15) /* interrupt on complete */ 452 453 #define ITD_ACTIVE(ehci) cpu_to_hc32(ehci, EHCI_ISOC_ACTIVE) 454 455 __hc32 hw_bufp [7]; /* see EHCI 3.3.3 */ 456 __hc32 hw_bufp_hi [7]; /* Appendix B */ 457 458 /* the rest is HCD-private */ 459 dma_addr_t itd_dma; /* for this itd */ 460 union ehci_shadow itd_next; /* ptr to periodic q entry */ 461 462 struct urb *urb; 463 struct ehci_iso_stream *stream; /* endpoint's queue */ 464 struct list_head itd_list; /* list of stream's itds */ 465 466 /* any/all hw_transactions here may be used by that urb */ 467 unsigned frame; /* where scheduled */ 468 unsigned pg; 469 unsigned index[8]; /* in urb->iso_frame_desc */ 470 } __attribute__ ((aligned (32))); 471 472 /*-------------------------------------------------------------------------*/ 473 474 /* 475 * EHCI Specification 0.95 Section 3.4 476 * siTD, aka split-transaction isochronous Transfer Descriptor 477 * ... describe full speed iso xfers through TT in hubs 478 * see Figure 3-5 "Split-transaction Isochronous Transaction Descriptor (siTD) 479 */ 480 struct ehci_sitd { 481 /* first part defined by EHCI spec */ 482 __hc32 hw_next; 483 /* uses bit field macros above - see EHCI 0.95 Table 3-8 */ 484 __hc32 hw_fullspeed_ep; /* EHCI table 3-9 */ 485 __hc32 hw_uframe; /* EHCI table 3-10 */ 486 __hc32 hw_results; /* EHCI table 3-11 */ 487 #define SITD_IOC (1 << 31) /* interrupt on completion */ 488 #define SITD_PAGE (1 << 30) /* buffer 0/1 */ 489 #define SITD_LENGTH(x) (0x3ff & ((x)>>16)) 490 #define SITD_STS_ACTIVE (1 << 7) /* HC may execute this */ 491 #define SITD_STS_ERR (1 << 6) /* error from TT */ 492 #define SITD_STS_DBE (1 << 5) /* data buffer error (in HC) */ 493 #define SITD_STS_BABBLE (1 << 4) /* device was babbling */ 494 #define SITD_STS_XACT (1 << 3) /* illegal IN response */ 495 #define SITD_STS_MMF (1 << 2) /* incomplete split transaction */ 496 #define SITD_STS_STS (1 << 1) /* split transaction state */ 497 498 #define SITD_ACTIVE(ehci) cpu_to_hc32(ehci, SITD_STS_ACTIVE) 499 500 __hc32 hw_buf [2]; /* EHCI table 3-12 */ 501 __hc32 hw_backpointer; /* EHCI table 3-13 */ 502 __hc32 hw_buf_hi [2]; /* Appendix B */ 503 504 /* the rest is HCD-private */ 505 dma_addr_t sitd_dma; 506 union ehci_shadow sitd_next; /* ptr to periodic q entry */ 507 508 struct urb *urb; 509 struct ehci_iso_stream *stream; /* endpoint's queue */ 510 struct list_head sitd_list; /* list of stream's sitds */ 511 unsigned frame; 512 unsigned index; 513 } __attribute__ ((aligned (32))); 514 515 /*-------------------------------------------------------------------------*/ 516 517 /* 518 * EHCI Specification 0.96 Section 3.7 519 * Periodic Frame Span Traversal Node (FSTN) 520 * 521 * Manages split interrupt transactions (using TT) that span frame boundaries 522 * into uframes 0/1; see 4.12.2.2. In those uframes, a "save place" FSTN 523 * makes the HC jump (back) to a QH to scan for fs/ls QH completions until 524 * it hits a "restore" FSTN; then it returns to finish other uframe 0/1 work. 525 */ 526 struct ehci_fstn { 527 __hc32 hw_next; /* any periodic q entry */ 528 __hc32 hw_prev; /* qh or EHCI_LIST_END */ 529 530 /* the rest is HCD-private */ 531 dma_addr_t fstn_dma; 532 union ehci_shadow fstn_next; /* ptr to periodic q entry */ 533 } __attribute__ ((aligned (32))); 534 535 /*-------------------------------------------------------------------------*/ 536 537 /* Prepare the PORTSC wakeup flags during controller suspend/resume */ 538 539 #define ehci_prepare_ports_for_controller_suspend(ehci, do_wakeup) \ 540 ehci_adjust_port_wakeup_flags(ehci, true, do_wakeup); 541 542 #define ehci_prepare_ports_for_controller_resume(ehci) \ 543 ehci_adjust_port_wakeup_flags(ehci, false, false); 544 545 /*-------------------------------------------------------------------------*/ 546 547 #ifdef CONFIG_USB_EHCI_ROOT_HUB_TT 548 549 /* 550 * Some EHCI controllers have a Transaction Translator built into the 551 * root hub. This is a non-standard feature. Each controller will need 552 * to add code to the following inline functions, and call them as 553 * needed (mostly in root hub code). 554 */ 555 556 #define ehci_is_TDI(e) (ehci_to_hcd(e)->has_tt) 557 558 /* Returns the speed of a device attached to a port on the root hub. */ 559 static inline unsigned int 560 ehci_port_speed(struct ehci_hcd *ehci, unsigned int portsc) 561 { 562 if (ehci_is_TDI(ehci)) { 563 switch ((portsc >> (ehci->has_hostpc ? 25 : 26)) & 3) { 564 case 0: 565 return 0; 566 case 1: 567 return USB_PORT_STAT_LOW_SPEED; 568 case 2: 569 default: 570 return USB_PORT_STAT_HIGH_SPEED; 571 } 572 } 573 return USB_PORT_STAT_HIGH_SPEED; 574 } 575 576 #else 577 578 #define ehci_is_TDI(e) (0) 579 580 #define ehci_port_speed(ehci, portsc) USB_PORT_STAT_HIGH_SPEED 581 #endif 582 583 /*-------------------------------------------------------------------------*/ 584 585 #ifdef CONFIG_PPC_83xx 586 /* Some Freescale processors have an erratum in which the TT 587 * port number in the queue head was 0..N-1 instead of 1..N. 588 */ 589 #define ehci_has_fsl_portno_bug(e) ((e)->has_fsl_port_bug) 590 #else 591 #define ehci_has_fsl_portno_bug(e) (0) 592 #endif 593 594 /* 595 * While most USB host controllers implement their registers in 596 * little-endian format, a minority (celleb companion chip) implement 597 * them in big endian format. 598 * 599 * This attempts to support either format at compile time without a 600 * runtime penalty, or both formats with the additional overhead 601 * of checking a flag bit. 602 */ 603 604 #ifdef CONFIG_USB_EHCI_BIG_ENDIAN_MMIO 605 #define ehci_big_endian_mmio(e) ((e)->big_endian_mmio) 606 #else 607 #define ehci_big_endian_mmio(e) 0 608 #endif 609 610 /* 611 * Big-endian read/write functions are arch-specific. 612 * Other arches can be added if/when they're needed. 613 */ 614 #if defined(CONFIG_ARM) && defined(CONFIG_ARCH_IXP4XX) 615 #define readl_be(addr) __raw_readl((__force unsigned *)addr) 616 #define writel_be(val, addr) __raw_writel(val, (__force unsigned *)addr) 617 #endif 618 619 static inline unsigned int ehci_readl(const struct ehci_hcd *ehci, 620 __u32 __iomem * regs) 621 { 622 #ifdef CONFIG_USB_EHCI_BIG_ENDIAN_MMIO 623 return ehci_big_endian_mmio(ehci) ? 624 readl_be(regs) : 625 readl(regs); 626 #else 627 return readl(regs); 628 #endif 629 } 630 631 static inline void ehci_writel(const struct ehci_hcd *ehci, 632 const unsigned int val, __u32 __iomem *regs) 633 { 634 #ifdef CONFIG_USB_EHCI_BIG_ENDIAN_MMIO 635 ehci_big_endian_mmio(ehci) ? 636 writel_be(val, regs) : 637 writel(val, regs); 638 #else 639 writel(val, regs); 640 #endif 641 } 642 643 /* 644 * On certain ppc-44x SoC there is a HW issue, that could only worked around with 645 * explicit suspend/operate of OHCI. This function hereby makes sense only on that arch. 646 * Other common bits are dependant on has_amcc_usb23 quirk flag. 647 */ 648 #ifdef CONFIG_44x 649 static inline void set_ohci_hcfs(struct ehci_hcd *ehci, int operational) 650 { 651 u32 hc_control; 652 653 hc_control = (readl_be(ehci->ohci_hcctrl_reg) & ~OHCI_CTRL_HCFS); 654 if (operational) 655 hc_control |= OHCI_USB_OPER; 656 else 657 hc_control |= OHCI_USB_SUSPEND; 658 659 writel_be(hc_control, ehci->ohci_hcctrl_reg); 660 (void) readl_be(ehci->ohci_hcctrl_reg); 661 } 662 #else 663 static inline void set_ohci_hcfs(struct ehci_hcd *ehci, int operational) 664 { } 665 #endif 666 667 /*-------------------------------------------------------------------------*/ 668 669 /* 670 * The AMCC 440EPx not only implements its EHCI registers in big-endian 671 * format, but also its DMA data structures (descriptors). 672 * 673 * EHCI controllers accessed through PCI work normally (little-endian 674 * everywhere), so we won't bother supporting a BE-only mode for now. 675 */ 676 #ifdef CONFIG_USB_EHCI_BIG_ENDIAN_DESC 677 #define ehci_big_endian_desc(e) ((e)->big_endian_desc) 678 679 /* cpu to ehci */ 680 static inline __hc32 cpu_to_hc32 (const struct ehci_hcd *ehci, const u32 x) 681 { 682 return ehci_big_endian_desc(ehci) 683 ? (__force __hc32)cpu_to_be32(x) 684 : (__force __hc32)cpu_to_le32(x); 685 } 686 687 /* ehci to cpu */ 688 static inline u32 hc32_to_cpu (const struct ehci_hcd *ehci, const __hc32 x) 689 { 690 return ehci_big_endian_desc(ehci) 691 ? be32_to_cpu((__force __be32)x) 692 : le32_to_cpu((__force __le32)x); 693 } 694 695 static inline u32 hc32_to_cpup (const struct ehci_hcd *ehci, const __hc32 *x) 696 { 697 return ehci_big_endian_desc(ehci) 698 ? be32_to_cpup((__force __be32 *)x) 699 : le32_to_cpup((__force __le32 *)x); 700 } 701 702 #else 703 704 /* cpu to ehci */ 705 static inline __hc32 cpu_to_hc32 (const struct ehci_hcd *ehci, const u32 x) 706 { 707 return cpu_to_le32(x); 708 } 709 710 /* ehci to cpu */ 711 static inline u32 hc32_to_cpu (const struct ehci_hcd *ehci, const __hc32 x) 712 { 713 return le32_to_cpu(x); 714 } 715 716 static inline u32 hc32_to_cpup (const struct ehci_hcd *ehci, const __hc32 *x) 717 { 718 return le32_to_cpup(x); 719 } 720 721 #endif 722 723 /*-------------------------------------------------------------------------*/ 724 725 #ifndef DEBUG 726 #define STUB_DEBUG_FILES 727 #endif /* DEBUG */ 728 729 /*-------------------------------------------------------------------------*/ 730 731 #endif /* __LINUX_EHCI_HCD_H */ 732