xref: /openbmc/linux/drivers/usb/host/ehci.h (revision 9ac8d3fb)
1 /*
2  * Copyright (c) 2001-2002 by David Brownell
3  *
4  * This program is free software; you can redistribute it and/or modify it
5  * under the terms of the GNU General Public License as published by the
6  * Free Software Foundation; either version 2 of the License, or (at your
7  * option) any later version.
8  *
9  * This program is distributed in the hope that it will be useful, but
10  * WITHOUT ANY WARRANTY; without even the implied warranty of MERCHANTABILITY
11  * or FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License
12  * for more details.
13  *
14  * You should have received a copy of the GNU General Public License
15  * along with this program; if not, write to the Free Software Foundation,
16  * Inc., 675 Mass Ave, Cambridge, MA 02139, USA.
17  */
18 
19 #ifndef __LINUX_EHCI_HCD_H
20 #define __LINUX_EHCI_HCD_H
21 
22 /* definitions used for the EHCI driver */
23 
24 /*
25  * __hc32 and __hc16 are "Host Controller" types, they may be equivalent to
26  * __leXX (normally) or __beXX (given EHCI_BIG_ENDIAN_DESC), depending on
27  * the host controller implementation.
28  *
29  * To facilitate the strongest possible byte-order checking from "sparse"
30  * and so on, we use __leXX unless that's not practical.
31  */
32 #ifdef CONFIG_USB_EHCI_BIG_ENDIAN_DESC
33 typedef __u32 __bitwise __hc32;
34 typedef __u16 __bitwise __hc16;
35 #else
36 #define __hc32	__le32
37 #define __hc16	__le16
38 #endif
39 
40 /* statistics can be kept for for tuning/monitoring */
41 struct ehci_stats {
42 	/* irq usage */
43 	unsigned long		normal;
44 	unsigned long		error;
45 	unsigned long		reclaim;
46 	unsigned long		lost_iaa;
47 
48 	/* termination of urbs from core */
49 	unsigned long		complete;
50 	unsigned long		unlink;
51 };
52 
53 /* ehci_hcd->lock guards shared data against other CPUs:
54  *   ehci_hcd:	async, reclaim, periodic (and shadow), ...
55  *   usb_host_endpoint: hcpriv
56  *   ehci_qh:	qh_next, qtd_list
57  *   ehci_qtd:	qtd_list
58  *
59  * Also, hold this lock when talking to HC registers or
60  * when updating hw_* fields in shared qh/qtd/... structures.
61  */
62 
63 #define	EHCI_MAX_ROOT_PORTS	15		/* see HCS_N_PORTS */
64 
65 struct ehci_hcd {			/* one per controller */
66 	/* glue to PCI and HCD framework */
67 	struct ehci_caps __iomem *caps;
68 	struct ehci_regs __iomem *regs;
69 	struct ehci_dbg_port __iomem *debug;
70 
71 	__u32			hcs_params;	/* cached register copy */
72 	spinlock_t		lock;
73 
74 	/* async schedule support */
75 	struct ehci_qh		*async;
76 	struct ehci_qh		*reclaim;
77 	unsigned		scanning : 1;
78 
79 	/* periodic schedule support */
80 #define	DEFAULT_I_TDPS		1024		/* some HCs can do less */
81 	unsigned		periodic_size;
82 	__hc32			*periodic;	/* hw periodic table */
83 	dma_addr_t		periodic_dma;
84 	unsigned		i_thresh;	/* uframes HC might cache */
85 
86 	union ehci_shadow	*pshadow;	/* mirror hw periodic table */
87 	int			next_uframe;	/* scan periodic, start here */
88 	unsigned		periodic_sched;	/* periodic activity count */
89 
90 	/* per root hub port */
91 	unsigned long		reset_done [EHCI_MAX_ROOT_PORTS];
92 
93 	/* bit vectors (one bit per port) */
94 	unsigned long		bus_suspended;		/* which ports were
95 			already suspended at the start of a bus suspend */
96 	unsigned long		companion_ports;	/* which ports are
97 			dedicated to the companion controller */
98 	unsigned long		owned_ports;		/* which ports are
99 			owned by the companion during a bus suspend */
100 	unsigned long		port_c_suspend;		/* which ports have
101 			the change-suspend feature turned on */
102 	unsigned long		suspended_ports;	/* which ports are
103 			suspended */
104 
105 	/* per-HC memory pools (could be per-bus, but ...) */
106 	struct dma_pool		*qh_pool;	/* qh per active urb */
107 	struct dma_pool		*qtd_pool;	/* one or more per qh */
108 	struct dma_pool		*itd_pool;	/* itd per iso urb */
109 	struct dma_pool		*sitd_pool;	/* sitd per split iso urb */
110 
111 	struct timer_list	iaa_watchdog;
112 	struct timer_list	watchdog;
113 	unsigned long		actions;
114 	unsigned		stamp;
115 	unsigned long		next_statechange;
116 	u32			command;
117 
118 	/* SILICON QUIRKS */
119 	unsigned		no_selective_suspend:1;
120 	unsigned		has_fsl_port_bug:1; /* FreeScale */
121 	unsigned		big_endian_mmio:1;
122 	unsigned		big_endian_desc:1;
123 
124 	u8			sbrn;		/* packed release number */
125 
126 	/* irq statistics */
127 #ifdef EHCI_STATS
128 	struct ehci_stats	stats;
129 #	define COUNT(x) do { (x)++; } while (0)
130 #else
131 #	define COUNT(x) do {} while (0)
132 #endif
133 
134 	/* debug files */
135 #ifdef DEBUG
136 	struct dentry		*debug_dir;
137 	struct dentry		*debug_async;
138 	struct dentry		*debug_periodic;
139 	struct dentry		*debug_registers;
140 #endif
141 };
142 
143 /* convert between an HCD pointer and the corresponding EHCI_HCD */
144 static inline struct ehci_hcd *hcd_to_ehci (struct usb_hcd *hcd)
145 {
146 	return (struct ehci_hcd *) (hcd->hcd_priv);
147 }
148 static inline struct usb_hcd *ehci_to_hcd (struct ehci_hcd *ehci)
149 {
150 	return container_of ((void *) ehci, struct usb_hcd, hcd_priv);
151 }
152 
153 
154 static inline void
155 iaa_watchdog_start(struct ehci_hcd *ehci)
156 {
157 	WARN_ON(timer_pending(&ehci->iaa_watchdog));
158 	mod_timer(&ehci->iaa_watchdog,
159 			jiffies + msecs_to_jiffies(EHCI_IAA_MSECS));
160 }
161 
162 static inline void iaa_watchdog_done(struct ehci_hcd *ehci)
163 {
164 	del_timer(&ehci->iaa_watchdog);
165 }
166 
167 enum ehci_timer_action {
168 	TIMER_IO_WATCHDOG,
169 	TIMER_ASYNC_SHRINK,
170 	TIMER_ASYNC_OFF,
171 };
172 
173 static inline void
174 timer_action_done (struct ehci_hcd *ehci, enum ehci_timer_action action)
175 {
176 	clear_bit (action, &ehci->actions);
177 }
178 
179 static inline void
180 timer_action (struct ehci_hcd *ehci, enum ehci_timer_action action)
181 {
182 	/* Don't override timeouts which shrink or (later) disable
183 	 * the async ring; just the I/O watchdog.  Note that if a
184 	 * SHRINK were pending, OFF would never be requested.
185 	 */
186 	enum ehci_timer_action oldactions = ehci->actions;
187 
188 	if (!test_and_set_bit (action, &ehci->actions)) {
189 		unsigned long t;
190 
191 		if (timer_pending(&ehci->watchdog)
192 			&& ((BIT(TIMER_ASYNC_SHRINK) | BIT(TIMER_ASYNC_OFF))
193 				& oldactions))
194 			return;
195 
196 		switch (action) {
197 		case TIMER_IO_WATCHDOG:
198 			t = EHCI_IO_JIFFIES;
199 			break;
200 		case TIMER_ASYNC_OFF:
201 			t = EHCI_ASYNC_JIFFIES;
202 			break;
203 		// case TIMER_ASYNC_SHRINK:
204 		default:
205 			/* add a jiffie since we synch against the
206 			 * 8 KHz uframe counter.
207 			 */
208 			t = DIV_ROUND_UP(EHCI_SHRINK_FRAMES * HZ, 1000) + 1;
209 			break;
210 		}
211 		mod_timer(&ehci->watchdog, round_jiffies(t + jiffies));
212 	}
213 }
214 
215 /*-------------------------------------------------------------------------*/
216 
217 #include <linux/usb/ehci_def.h>
218 
219 /*-------------------------------------------------------------------------*/
220 
221 #define	QTD_NEXT(ehci, dma)	cpu_to_hc32(ehci, (u32)dma)
222 
223 /*
224  * EHCI Specification 0.95 Section 3.5
225  * QTD: describe data transfer components (buffer, direction, ...)
226  * See Fig 3-6 "Queue Element Transfer Descriptor Block Diagram".
227  *
228  * These are associated only with "QH" (Queue Head) structures,
229  * used with control, bulk, and interrupt transfers.
230  */
231 struct ehci_qtd {
232 	/* first part defined by EHCI spec */
233 	__hc32			hw_next;	/* see EHCI 3.5.1 */
234 	__hc32			hw_alt_next;    /* see EHCI 3.5.2 */
235 	__hc32			hw_token;       /* see EHCI 3.5.3 */
236 #define	QTD_TOGGLE	(1 << 31)	/* data toggle */
237 #define	QTD_LENGTH(tok)	(((tok)>>16) & 0x7fff)
238 #define	QTD_IOC		(1 << 15)	/* interrupt on complete */
239 #define	QTD_CERR(tok)	(((tok)>>10) & 0x3)
240 #define	QTD_PID(tok)	(((tok)>>8) & 0x3)
241 #define	QTD_STS_ACTIVE	(1 << 7)	/* HC may execute this */
242 #define	QTD_STS_HALT	(1 << 6)	/* halted on error */
243 #define	QTD_STS_DBE	(1 << 5)	/* data buffer error (in HC) */
244 #define	QTD_STS_BABBLE	(1 << 4)	/* device was babbling (qtd halted) */
245 #define	QTD_STS_XACT	(1 << 3)	/* device gave illegal response */
246 #define	QTD_STS_MMF	(1 << 2)	/* incomplete split transaction */
247 #define	QTD_STS_STS	(1 << 1)	/* split transaction state */
248 #define	QTD_STS_PING	(1 << 0)	/* issue PING? */
249 
250 #define ACTIVE_BIT(ehci)	cpu_to_hc32(ehci, QTD_STS_ACTIVE)
251 #define HALT_BIT(ehci)		cpu_to_hc32(ehci, QTD_STS_HALT)
252 #define STATUS_BIT(ehci)	cpu_to_hc32(ehci, QTD_STS_STS)
253 
254 	__hc32			hw_buf [5];        /* see EHCI 3.5.4 */
255 	__hc32			hw_buf_hi [5];        /* Appendix B */
256 
257 	/* the rest is HCD-private */
258 	dma_addr_t		qtd_dma;		/* qtd address */
259 	struct list_head	qtd_list;		/* sw qtd list */
260 	struct urb		*urb;			/* qtd's urb */
261 	size_t			length;			/* length of buffer */
262 } __attribute__ ((aligned (32)));
263 
264 /* mask NakCnt+T in qh->hw_alt_next */
265 #define QTD_MASK(ehci)	cpu_to_hc32 (ehci, ~0x1f)
266 
267 #define IS_SHORT_READ(token) (QTD_LENGTH (token) != 0 && QTD_PID (token) == 1)
268 
269 /*-------------------------------------------------------------------------*/
270 
271 /* type tag from {qh,itd,sitd,fstn}->hw_next */
272 #define Q_NEXT_TYPE(ehci,dma)	((dma) & cpu_to_hc32(ehci, 3 << 1))
273 
274 /*
275  * Now the following defines are not converted using the
276  * __constant_cpu_to_le32() macro anymore, since we have to support
277  * "dynamic" switching between be and le support, so that the driver
278  * can be used on one system with SoC EHCI controller using big-endian
279  * descriptors as well as a normal little-endian PCI EHCI controller.
280  */
281 /* values for that type tag */
282 #define Q_TYPE_ITD	(0 << 1)
283 #define Q_TYPE_QH	(1 << 1)
284 #define Q_TYPE_SITD	(2 << 1)
285 #define Q_TYPE_FSTN	(3 << 1)
286 
287 /* next async queue entry, or pointer to interrupt/periodic QH */
288 #define QH_NEXT(ehci,dma)	(cpu_to_hc32(ehci, (((u32)dma)&~0x01f)|Q_TYPE_QH))
289 
290 /* for periodic/async schedules and qtd lists, mark end of list */
291 #define EHCI_LIST_END(ehci)	cpu_to_hc32(ehci, 1) /* "null pointer" to hw */
292 
293 /*
294  * Entries in periodic shadow table are pointers to one of four kinds
295  * of data structure.  That's dictated by the hardware; a type tag is
296  * encoded in the low bits of the hardware's periodic schedule.  Use
297  * Q_NEXT_TYPE to get the tag.
298  *
299  * For entries in the async schedule, the type tag always says "qh".
300  */
301 union ehci_shadow {
302 	struct ehci_qh		*qh;		/* Q_TYPE_QH */
303 	struct ehci_itd		*itd;		/* Q_TYPE_ITD */
304 	struct ehci_sitd	*sitd;		/* Q_TYPE_SITD */
305 	struct ehci_fstn	*fstn;		/* Q_TYPE_FSTN */
306 	__hc32			*hw_next;	/* (all types) */
307 	void			*ptr;
308 };
309 
310 /*-------------------------------------------------------------------------*/
311 
312 /*
313  * EHCI Specification 0.95 Section 3.6
314  * QH: describes control/bulk/interrupt endpoints
315  * See Fig 3-7 "Queue Head Structure Layout".
316  *
317  * These appear in both the async and (for interrupt) periodic schedules.
318  */
319 
320 struct ehci_qh {
321 	/* first part defined by EHCI spec */
322 	__hc32			hw_next;	/* see EHCI 3.6.1 */
323 	__hc32			hw_info1;       /* see EHCI 3.6.2 */
324 #define	QH_HEAD		0x00008000
325 	__hc32			hw_info2;        /* see EHCI 3.6.2 */
326 #define	QH_SMASK	0x000000ff
327 #define	QH_CMASK	0x0000ff00
328 #define	QH_HUBADDR	0x007f0000
329 #define	QH_HUBPORT	0x3f800000
330 #define	QH_MULT		0xc0000000
331 	__hc32			hw_current;	/* qtd list - see EHCI 3.6.4 */
332 
333 	/* qtd overlay (hardware parts of a struct ehci_qtd) */
334 	__hc32			hw_qtd_next;
335 	__hc32			hw_alt_next;
336 	__hc32			hw_token;
337 	__hc32			hw_buf [5];
338 	__hc32			hw_buf_hi [5];
339 
340 	/* the rest is HCD-private */
341 	dma_addr_t		qh_dma;		/* address of qh */
342 	union ehci_shadow	qh_next;	/* ptr to qh; or periodic */
343 	struct list_head	qtd_list;	/* sw qtd list */
344 	struct ehci_qtd		*dummy;
345 	struct ehci_qh		*reclaim;	/* next to reclaim */
346 
347 	struct ehci_hcd		*ehci;
348 
349 	/*
350 	 * Do NOT use atomic operations for QH refcounting. On some CPUs
351 	 * (PPC7448 for example), atomic operations cannot be performed on
352 	 * memory that is cache-inhibited (i.e. being used for DMA).
353 	 * Spinlocks are used to protect all QH fields.
354 	 */
355 	u32			refcount;
356 	unsigned		stamp;
357 
358 	u8			qh_state;
359 #define	QH_STATE_LINKED		1		/* HC sees this */
360 #define	QH_STATE_UNLINK		2		/* HC may still see this */
361 #define	QH_STATE_IDLE		3		/* HC doesn't see this */
362 #define	QH_STATE_UNLINK_WAIT	4		/* LINKED and on reclaim q */
363 #define	QH_STATE_COMPLETING	5		/* don't touch token.HALT */
364 
365 	/* periodic schedule info */
366 	u8			usecs;		/* intr bandwidth */
367 	u8			gap_uf;		/* uframes split/csplit gap */
368 	u8			c_usecs;	/* ... split completion bw */
369 	u16			tt_usecs;	/* tt downstream bandwidth */
370 	unsigned short		period;		/* polling interval */
371 	unsigned short		start;		/* where polling starts */
372 #define NO_FRAME ((unsigned short)~0)			/* pick new start */
373 	struct usb_device	*dev;		/* access to TT */
374 } __attribute__ ((aligned (32)));
375 
376 /*-------------------------------------------------------------------------*/
377 
378 /* description of one iso transaction (up to 3 KB data if highspeed) */
379 struct ehci_iso_packet {
380 	/* These will be copied to iTD when scheduling */
381 	u64			bufp;		/* itd->hw_bufp{,_hi}[pg] |= */
382 	__hc32			transaction;	/* itd->hw_transaction[i] |= */
383 	u8			cross;		/* buf crosses pages */
384 	/* for full speed OUT splits */
385 	u32			buf1;
386 };
387 
388 /* temporary schedule data for packets from iso urbs (both speeds)
389  * each packet is one logical usb transaction to the device (not TT),
390  * beginning at stream->next_uframe
391  */
392 struct ehci_iso_sched {
393 	struct list_head	td_list;
394 	unsigned		span;
395 	struct ehci_iso_packet	packet [0];
396 };
397 
398 /*
399  * ehci_iso_stream - groups all (s)itds for this endpoint.
400  * acts like a qh would, if EHCI had them for ISO.
401  */
402 struct ehci_iso_stream {
403 	/* first two fields match QH, but info1 == 0 */
404 	__hc32			hw_next;
405 	__hc32			hw_info1;
406 
407 	u32			refcount;
408 	u8			bEndpointAddress;
409 	u8			highspeed;
410 	u16			depth;		/* depth in uframes */
411 	struct list_head	td_list;	/* queued itds/sitds */
412 	struct list_head	free_list;	/* list of unused itds/sitds */
413 	struct usb_device	*udev;
414 	struct usb_host_endpoint *ep;
415 
416 	/* output of (re)scheduling */
417 	unsigned long		start;		/* jiffies */
418 	unsigned long		rescheduled;
419 	int			next_uframe;
420 	__hc32			splits;
421 
422 	/* the rest is derived from the endpoint descriptor,
423 	 * trusting urb->interval == f(epdesc->bInterval) and
424 	 * including the extra info for hw_bufp[0..2]
425 	 */
426 	u8			usecs, c_usecs;
427 	u16			interval;
428 	u16			tt_usecs;
429 	u16			maxp;
430 	u16			raw_mask;
431 	unsigned		bandwidth;
432 
433 	/* This is used to initialize iTD's hw_bufp fields */
434 	__hc32			buf0;
435 	__hc32			buf1;
436 	__hc32			buf2;
437 
438 	/* this is used to initialize sITD's tt info */
439 	__hc32			address;
440 };
441 
442 /*-------------------------------------------------------------------------*/
443 
444 /*
445  * EHCI Specification 0.95 Section 3.3
446  * Fig 3-4 "Isochronous Transaction Descriptor (iTD)"
447  *
448  * Schedule records for high speed iso xfers
449  */
450 struct ehci_itd {
451 	/* first part defined by EHCI spec */
452 	__hc32			hw_next;           /* see EHCI 3.3.1 */
453 	__hc32			hw_transaction [8]; /* see EHCI 3.3.2 */
454 #define EHCI_ISOC_ACTIVE        (1<<31)        /* activate transfer this slot */
455 #define EHCI_ISOC_BUF_ERR       (1<<30)        /* Data buffer error */
456 #define EHCI_ISOC_BABBLE        (1<<29)        /* babble detected */
457 #define EHCI_ISOC_XACTERR       (1<<28)        /* XactErr - transaction error */
458 #define	EHCI_ITD_LENGTH(tok)	(((tok)>>16) & 0x0fff)
459 #define	EHCI_ITD_IOC		(1 << 15)	/* interrupt on complete */
460 
461 #define ITD_ACTIVE(ehci)	cpu_to_hc32(ehci, EHCI_ISOC_ACTIVE)
462 
463 	__hc32			hw_bufp [7];	/* see EHCI 3.3.3 */
464 	__hc32			hw_bufp_hi [7];	/* Appendix B */
465 
466 	/* the rest is HCD-private */
467 	dma_addr_t		itd_dma;	/* for this itd */
468 	union ehci_shadow	itd_next;	/* ptr to periodic q entry */
469 
470 	struct urb		*urb;
471 	struct ehci_iso_stream	*stream;	/* endpoint's queue */
472 	struct list_head	itd_list;	/* list of stream's itds */
473 
474 	/* any/all hw_transactions here may be used by that urb */
475 	unsigned		frame;		/* where scheduled */
476 	unsigned		pg;
477 	unsigned		index[8];	/* in urb->iso_frame_desc */
478 } __attribute__ ((aligned (32)));
479 
480 /*-------------------------------------------------------------------------*/
481 
482 /*
483  * EHCI Specification 0.95 Section 3.4
484  * siTD, aka split-transaction isochronous Transfer Descriptor
485  *       ... describe full speed iso xfers through TT in hubs
486  * see Figure 3-5 "Split-transaction Isochronous Transaction Descriptor (siTD)
487  */
488 struct ehci_sitd {
489 	/* first part defined by EHCI spec */
490 	__hc32			hw_next;
491 /* uses bit field macros above - see EHCI 0.95 Table 3-8 */
492 	__hc32			hw_fullspeed_ep;	/* EHCI table 3-9 */
493 	__hc32			hw_uframe;		/* EHCI table 3-10 */
494 	__hc32			hw_results;		/* EHCI table 3-11 */
495 #define	SITD_IOC	(1 << 31)	/* interrupt on completion */
496 #define	SITD_PAGE	(1 << 30)	/* buffer 0/1 */
497 #define	SITD_LENGTH(x)	(0x3ff & ((x)>>16))
498 #define	SITD_STS_ACTIVE	(1 << 7)	/* HC may execute this */
499 #define	SITD_STS_ERR	(1 << 6)	/* error from TT */
500 #define	SITD_STS_DBE	(1 << 5)	/* data buffer error (in HC) */
501 #define	SITD_STS_BABBLE	(1 << 4)	/* device was babbling */
502 #define	SITD_STS_XACT	(1 << 3)	/* illegal IN response */
503 #define	SITD_STS_MMF	(1 << 2)	/* incomplete split transaction */
504 #define	SITD_STS_STS	(1 << 1)	/* split transaction state */
505 
506 #define SITD_ACTIVE(ehci)	cpu_to_hc32(ehci, SITD_STS_ACTIVE)
507 
508 	__hc32			hw_buf [2];		/* EHCI table 3-12 */
509 	__hc32			hw_backpointer;		/* EHCI table 3-13 */
510 	__hc32			hw_buf_hi [2];		/* Appendix B */
511 
512 	/* the rest is HCD-private */
513 	dma_addr_t		sitd_dma;
514 	union ehci_shadow	sitd_next;	/* ptr to periodic q entry */
515 
516 	struct urb		*urb;
517 	struct ehci_iso_stream	*stream;	/* endpoint's queue */
518 	struct list_head	sitd_list;	/* list of stream's sitds */
519 	unsigned		frame;
520 	unsigned		index;
521 } __attribute__ ((aligned (32)));
522 
523 /*-------------------------------------------------------------------------*/
524 
525 /*
526  * EHCI Specification 0.96 Section 3.7
527  * Periodic Frame Span Traversal Node (FSTN)
528  *
529  * Manages split interrupt transactions (using TT) that span frame boundaries
530  * into uframes 0/1; see 4.12.2.2.  In those uframes, a "save place" FSTN
531  * makes the HC jump (back) to a QH to scan for fs/ls QH completions until
532  * it hits a "restore" FSTN; then it returns to finish other uframe 0/1 work.
533  */
534 struct ehci_fstn {
535 	__hc32			hw_next;	/* any periodic q entry */
536 	__hc32			hw_prev;	/* qh or EHCI_LIST_END */
537 
538 	/* the rest is HCD-private */
539 	dma_addr_t		fstn_dma;
540 	union ehci_shadow	fstn_next;	/* ptr to periodic q entry */
541 } __attribute__ ((aligned (32)));
542 
543 /*-------------------------------------------------------------------------*/
544 
545 #ifdef CONFIG_USB_EHCI_ROOT_HUB_TT
546 
547 /*
548  * Some EHCI controllers have a Transaction Translator built into the
549  * root hub. This is a non-standard feature.  Each controller will need
550  * to add code to the following inline functions, and call them as
551  * needed (mostly in root hub code).
552  */
553 
554 #define	ehci_is_TDI(e)			(ehci_to_hcd(e)->has_tt)
555 
556 /* Returns the speed of a device attached to a port on the root hub. */
557 static inline unsigned int
558 ehci_port_speed(struct ehci_hcd *ehci, unsigned int portsc)
559 {
560 	if (ehci_is_TDI(ehci)) {
561 		switch ((portsc>>26)&3) {
562 		case 0:
563 			return 0;
564 		case 1:
565 			return (1<<USB_PORT_FEAT_LOWSPEED);
566 		case 2:
567 		default:
568 			return (1<<USB_PORT_FEAT_HIGHSPEED);
569 		}
570 	}
571 	return (1<<USB_PORT_FEAT_HIGHSPEED);
572 }
573 
574 #else
575 
576 #define	ehci_is_TDI(e)			(0)
577 
578 #define	ehci_port_speed(ehci, portsc)	(1<<USB_PORT_FEAT_HIGHSPEED)
579 #endif
580 
581 /*-------------------------------------------------------------------------*/
582 
583 #ifdef CONFIG_PPC_83xx
584 /* Some Freescale processors have an erratum in which the TT
585  * port number in the queue head was 0..N-1 instead of 1..N.
586  */
587 #define	ehci_has_fsl_portno_bug(e)		((e)->has_fsl_port_bug)
588 #else
589 #define	ehci_has_fsl_portno_bug(e)		(0)
590 #endif
591 
592 /*
593  * While most USB host controllers implement their registers in
594  * little-endian format, a minority (celleb companion chip) implement
595  * them in big endian format.
596  *
597  * This attempts to support either format at compile time without a
598  * runtime penalty, or both formats with the additional overhead
599  * of checking a flag bit.
600  */
601 
602 #ifdef CONFIG_USB_EHCI_BIG_ENDIAN_MMIO
603 #define ehci_big_endian_mmio(e)		((e)->big_endian_mmio)
604 #else
605 #define ehci_big_endian_mmio(e)		0
606 #endif
607 
608 /*
609  * Big-endian read/write functions are arch-specific.
610  * Other arches can be added if/when they're needed.
611  */
612 #if defined(CONFIG_ARM) && defined(CONFIG_ARCH_IXP4XX)
613 #define readl_be(addr)		__raw_readl((__force unsigned *)addr)
614 #define writel_be(val, addr)	__raw_writel(val, (__force unsigned *)addr)
615 #endif
616 
617 static inline unsigned int ehci_readl(const struct ehci_hcd *ehci,
618 		__u32 __iomem * regs)
619 {
620 #ifdef CONFIG_USB_EHCI_BIG_ENDIAN_MMIO
621 	return ehci_big_endian_mmio(ehci) ?
622 		readl_be(regs) :
623 		readl(regs);
624 #else
625 	return readl(regs);
626 #endif
627 }
628 
629 static inline void ehci_writel(const struct ehci_hcd *ehci,
630 		const unsigned int val, __u32 __iomem *regs)
631 {
632 #ifdef CONFIG_USB_EHCI_BIG_ENDIAN_MMIO
633 	ehci_big_endian_mmio(ehci) ?
634 		writel_be(val, regs) :
635 		writel(val, regs);
636 #else
637 	writel(val, regs);
638 #endif
639 }
640 
641 /*-------------------------------------------------------------------------*/
642 
643 /*
644  * The AMCC 440EPx not only implements its EHCI registers in big-endian
645  * format, but also its DMA data structures (descriptors).
646  *
647  * EHCI controllers accessed through PCI work normally (little-endian
648  * everywhere), so we won't bother supporting a BE-only mode for now.
649  */
650 #ifdef CONFIG_USB_EHCI_BIG_ENDIAN_DESC
651 #define ehci_big_endian_desc(e)		((e)->big_endian_desc)
652 
653 /* cpu to ehci */
654 static inline __hc32 cpu_to_hc32 (const struct ehci_hcd *ehci, const u32 x)
655 {
656 	return ehci_big_endian_desc(ehci)
657 		? (__force __hc32)cpu_to_be32(x)
658 		: (__force __hc32)cpu_to_le32(x);
659 }
660 
661 /* ehci to cpu */
662 static inline u32 hc32_to_cpu (const struct ehci_hcd *ehci, const __hc32 x)
663 {
664 	return ehci_big_endian_desc(ehci)
665 		? be32_to_cpu((__force __be32)x)
666 		: le32_to_cpu((__force __le32)x);
667 }
668 
669 static inline u32 hc32_to_cpup (const struct ehci_hcd *ehci, const __hc32 *x)
670 {
671 	return ehci_big_endian_desc(ehci)
672 		? be32_to_cpup((__force __be32 *)x)
673 		: le32_to_cpup((__force __le32 *)x);
674 }
675 
676 #else
677 
678 /* cpu to ehci */
679 static inline __hc32 cpu_to_hc32 (const struct ehci_hcd *ehci, const u32 x)
680 {
681 	return cpu_to_le32(x);
682 }
683 
684 /* ehci to cpu */
685 static inline u32 hc32_to_cpu (const struct ehci_hcd *ehci, const __hc32 x)
686 {
687 	return le32_to_cpu(x);
688 }
689 
690 static inline u32 hc32_to_cpup (const struct ehci_hcd *ehci, const __hc32 *x)
691 {
692 	return le32_to_cpup(x);
693 }
694 
695 #endif
696 
697 /*-------------------------------------------------------------------------*/
698 
699 #ifndef DEBUG
700 #define STUB_DEBUG_FILES
701 #endif	/* DEBUG */
702 
703 /*-------------------------------------------------------------------------*/
704 
705 #endif /* __LINUX_EHCI_HCD_H */
706