1 /* 2 * Copyright (c) 2001-2002 by David Brownell 3 * 4 * This program is free software; you can redistribute it and/or modify it 5 * under the terms of the GNU General Public License as published by the 6 * Free Software Foundation; either version 2 of the License, or (at your 7 * option) any later version. 8 * 9 * This program is distributed in the hope that it will be useful, but 10 * WITHOUT ANY WARRANTY; without even the implied warranty of MERCHANTABILITY 11 * or FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License 12 * for more details. 13 * 14 * You should have received a copy of the GNU General Public License 15 * along with this program; if not, write to the Free Software Foundation, 16 * Inc., 675 Mass Ave, Cambridge, MA 02139, USA. 17 */ 18 19 #ifndef __LINUX_EHCI_HCD_H 20 #define __LINUX_EHCI_HCD_H 21 22 /* definitions used for the EHCI driver */ 23 24 /* 25 * __hc32 and __hc16 are "Host Controller" types, they may be equivalent to 26 * __leXX (normally) or __beXX (given EHCI_BIG_ENDIAN_DESC), depending on 27 * the host controller implementation. 28 * 29 * To facilitate the strongest possible byte-order checking from "sparse" 30 * and so on, we use __leXX unless that's not practical. 31 */ 32 #ifdef CONFIG_USB_EHCI_BIG_ENDIAN_DESC 33 typedef __u32 __bitwise __hc32; 34 typedef __u16 __bitwise __hc16; 35 #else 36 #define __hc32 __le32 37 #define __hc16 __le16 38 #endif 39 40 /* statistics can be kept for for tuning/monitoring */ 41 struct ehci_stats { 42 /* irq usage */ 43 unsigned long normal; 44 unsigned long error; 45 unsigned long reclaim; 46 unsigned long lost_iaa; 47 48 /* termination of urbs from core */ 49 unsigned long complete; 50 unsigned long unlink; 51 }; 52 53 /* ehci_hcd->lock guards shared data against other CPUs: 54 * ehci_hcd: async, reclaim, periodic (and shadow), ... 55 * usb_host_endpoint: hcpriv 56 * ehci_qh: qh_next, qtd_list 57 * ehci_qtd: qtd_list 58 * 59 * Also, hold this lock when talking to HC registers or 60 * when updating hw_* fields in shared qh/qtd/... structures. 61 */ 62 63 #define EHCI_MAX_ROOT_PORTS 15 /* see HCS_N_PORTS */ 64 65 struct ehci_hcd { /* one per controller */ 66 /* glue to PCI and HCD framework */ 67 struct ehci_caps __iomem *caps; 68 struct ehci_regs __iomem *regs; 69 struct ehci_dbg_port __iomem *debug; 70 71 __u32 hcs_params; /* cached register copy */ 72 spinlock_t lock; 73 74 /* async schedule support */ 75 struct ehci_qh *async; 76 struct ehci_qh *reclaim; 77 unsigned scanning : 1; 78 79 /* periodic schedule support */ 80 #define DEFAULT_I_TDPS 1024 /* some HCs can do less */ 81 unsigned periodic_size; 82 __hc32 *periodic; /* hw periodic table */ 83 dma_addr_t periodic_dma; 84 unsigned i_thresh; /* uframes HC might cache */ 85 86 union ehci_shadow *pshadow; /* mirror hw periodic table */ 87 int next_uframe; /* scan periodic, start here */ 88 unsigned periodic_sched; /* periodic activity count */ 89 90 /* per root hub port */ 91 unsigned long reset_done [EHCI_MAX_ROOT_PORTS]; 92 93 /* bit vectors (one bit per port) */ 94 unsigned long bus_suspended; /* which ports were 95 already suspended at the start of a bus suspend */ 96 unsigned long companion_ports; /* which ports are 97 dedicated to the companion controller */ 98 unsigned long owned_ports; /* which ports are 99 owned by the companion during a bus suspend */ 100 unsigned long port_c_suspend; /* which ports have 101 the change-suspend feature turned on */ 102 103 /* per-HC memory pools (could be per-bus, but ...) */ 104 struct dma_pool *qh_pool; /* qh per active urb */ 105 struct dma_pool *qtd_pool; /* one or more per qh */ 106 struct dma_pool *itd_pool; /* itd per iso urb */ 107 struct dma_pool *sitd_pool; /* sitd per split iso urb */ 108 109 struct timer_list iaa_watchdog; 110 struct timer_list watchdog; 111 unsigned long actions; 112 unsigned stamp; 113 unsigned long next_statechange; 114 u32 command; 115 116 /* SILICON QUIRKS */ 117 unsigned no_selective_suspend:1; 118 unsigned has_fsl_port_bug:1; /* FreeScale */ 119 unsigned big_endian_mmio:1; 120 unsigned big_endian_desc:1; 121 122 u8 sbrn; /* packed release number */ 123 124 /* irq statistics */ 125 #ifdef EHCI_STATS 126 struct ehci_stats stats; 127 # define COUNT(x) do { (x)++; } while (0) 128 #else 129 # define COUNT(x) do {} while (0) 130 #endif 131 132 /* debug files */ 133 #ifdef DEBUG 134 struct dentry *debug_dir; 135 struct dentry *debug_async; 136 struct dentry *debug_periodic; 137 struct dentry *debug_registers; 138 #endif 139 }; 140 141 /* convert between an HCD pointer and the corresponding EHCI_HCD */ 142 static inline struct ehci_hcd *hcd_to_ehci (struct usb_hcd *hcd) 143 { 144 return (struct ehci_hcd *) (hcd->hcd_priv); 145 } 146 static inline struct usb_hcd *ehci_to_hcd (struct ehci_hcd *ehci) 147 { 148 return container_of ((void *) ehci, struct usb_hcd, hcd_priv); 149 } 150 151 152 static inline void 153 iaa_watchdog_start(struct ehci_hcd *ehci) 154 { 155 WARN_ON(timer_pending(&ehci->iaa_watchdog)); 156 mod_timer(&ehci->iaa_watchdog, 157 jiffies + msecs_to_jiffies(EHCI_IAA_MSECS)); 158 } 159 160 static inline void iaa_watchdog_done(struct ehci_hcd *ehci) 161 { 162 del_timer(&ehci->iaa_watchdog); 163 } 164 165 enum ehci_timer_action { 166 TIMER_IO_WATCHDOG, 167 TIMER_ASYNC_SHRINK, 168 TIMER_ASYNC_OFF, 169 }; 170 171 static inline void 172 timer_action_done (struct ehci_hcd *ehci, enum ehci_timer_action action) 173 { 174 clear_bit (action, &ehci->actions); 175 } 176 177 static inline void 178 timer_action (struct ehci_hcd *ehci, enum ehci_timer_action action) 179 { 180 /* Don't override timeouts which shrink or (later) disable 181 * the async ring; just the I/O watchdog. Note that if a 182 * SHRINK were pending, OFF would never be requested. 183 */ 184 if (timer_pending(&ehci->watchdog) 185 && ((BIT(TIMER_ASYNC_SHRINK) | BIT(TIMER_ASYNC_OFF)) 186 & ehci->actions)) 187 return; 188 189 if (!test_and_set_bit (action, &ehci->actions)) { 190 unsigned long t; 191 192 switch (action) { 193 case TIMER_IO_WATCHDOG: 194 t = EHCI_IO_JIFFIES; 195 break; 196 case TIMER_ASYNC_OFF: 197 t = EHCI_ASYNC_JIFFIES; 198 break; 199 // case TIMER_ASYNC_SHRINK: 200 default: 201 /* add a jiffie since we synch against the 202 * 8 KHz uframe counter. 203 */ 204 t = DIV_ROUND_UP(EHCI_SHRINK_FRAMES * HZ, 1000) + 1; 205 break; 206 } 207 mod_timer(&ehci->watchdog, t + jiffies); 208 } 209 } 210 211 /*-------------------------------------------------------------------------*/ 212 213 /* EHCI register interface, corresponds to EHCI Revision 0.95 specification */ 214 215 /* Section 2.2 Host Controller Capability Registers */ 216 struct ehci_caps { 217 /* these fields are specified as 8 and 16 bit registers, 218 * but some hosts can't perform 8 or 16 bit PCI accesses. 219 */ 220 u32 hc_capbase; 221 #define HC_LENGTH(p) (((p)>>00)&0x00ff) /* bits 7:0 */ 222 #define HC_VERSION(p) (((p)>>16)&0xffff) /* bits 31:16 */ 223 u32 hcs_params; /* HCSPARAMS - offset 0x4 */ 224 #define HCS_DEBUG_PORT(p) (((p)>>20)&0xf) /* bits 23:20, debug port? */ 225 #define HCS_INDICATOR(p) ((p)&(1 << 16)) /* true: has port indicators */ 226 #define HCS_N_CC(p) (((p)>>12)&0xf) /* bits 15:12, #companion HCs */ 227 #define HCS_N_PCC(p) (((p)>>8)&0xf) /* bits 11:8, ports per CC */ 228 #define HCS_PORTROUTED(p) ((p)&(1 << 7)) /* true: port routing */ 229 #define HCS_PPC(p) ((p)&(1 << 4)) /* true: port power control */ 230 #define HCS_N_PORTS(p) (((p)>>0)&0xf) /* bits 3:0, ports on HC */ 231 232 u32 hcc_params; /* HCCPARAMS - offset 0x8 */ 233 #define HCC_EXT_CAPS(p) (((p)>>8)&0xff) /* for pci extended caps */ 234 #define HCC_ISOC_CACHE(p) ((p)&(1 << 7)) /* true: can cache isoc frame */ 235 #define HCC_ISOC_THRES(p) (((p)>>4)&0x7) /* bits 6:4, uframes cached */ 236 #define HCC_CANPARK(p) ((p)&(1 << 2)) /* true: can park on async qh */ 237 #define HCC_PGM_FRAMELISTLEN(p) ((p)&(1 << 1)) /* true: periodic_size changes*/ 238 #define HCC_64BIT_ADDR(p) ((p)&(1)) /* true: can use 64-bit addr */ 239 u8 portroute [8]; /* nibbles for routing - offset 0xC */ 240 } __attribute__ ((packed)); 241 242 243 /* Section 2.3 Host Controller Operational Registers */ 244 struct ehci_regs { 245 246 /* USBCMD: offset 0x00 */ 247 u32 command; 248 /* 23:16 is r/w intr rate, in microframes; default "8" == 1/msec */ 249 #define CMD_PARK (1<<11) /* enable "park" on async qh */ 250 #define CMD_PARK_CNT(c) (((c)>>8)&3) /* how many transfers to park for */ 251 #define CMD_LRESET (1<<7) /* partial reset (no ports, etc) */ 252 #define CMD_IAAD (1<<6) /* "doorbell" interrupt async advance */ 253 #define CMD_ASE (1<<5) /* async schedule enable */ 254 #define CMD_PSE (1<<4) /* periodic schedule enable */ 255 /* 3:2 is periodic frame list size */ 256 #define CMD_RESET (1<<1) /* reset HC not bus */ 257 #define CMD_RUN (1<<0) /* start/stop HC */ 258 259 /* USBSTS: offset 0x04 */ 260 u32 status; 261 #define STS_ASS (1<<15) /* Async Schedule Status */ 262 #define STS_PSS (1<<14) /* Periodic Schedule Status */ 263 #define STS_RECL (1<<13) /* Reclamation */ 264 #define STS_HALT (1<<12) /* Not running (any reason) */ 265 /* some bits reserved */ 266 /* these STS_* flags are also intr_enable bits (USBINTR) */ 267 #define STS_IAA (1<<5) /* Interrupted on async advance */ 268 #define STS_FATAL (1<<4) /* such as some PCI access errors */ 269 #define STS_FLR (1<<3) /* frame list rolled over */ 270 #define STS_PCD (1<<2) /* port change detect */ 271 #define STS_ERR (1<<1) /* "error" completion (overflow, ...) */ 272 #define STS_INT (1<<0) /* "normal" completion (short, ...) */ 273 274 /* USBINTR: offset 0x08 */ 275 u32 intr_enable; 276 277 /* FRINDEX: offset 0x0C */ 278 u32 frame_index; /* current microframe number */ 279 /* CTRLDSSEGMENT: offset 0x10 */ 280 u32 segment; /* address bits 63:32 if needed */ 281 /* PERIODICLISTBASE: offset 0x14 */ 282 u32 frame_list; /* points to periodic list */ 283 /* ASYNCLISTADDR: offset 0x18 */ 284 u32 async_next; /* address of next async queue head */ 285 286 u32 reserved [9]; 287 288 /* CONFIGFLAG: offset 0x40 */ 289 u32 configured_flag; 290 #define FLAG_CF (1<<0) /* true: we'll support "high speed" */ 291 292 /* PORTSC: offset 0x44 */ 293 u32 port_status [0]; /* up to N_PORTS */ 294 /* 31:23 reserved */ 295 #define PORT_WKOC_E (1<<22) /* wake on overcurrent (enable) */ 296 #define PORT_WKDISC_E (1<<21) /* wake on disconnect (enable) */ 297 #define PORT_WKCONN_E (1<<20) /* wake on connect (enable) */ 298 /* 19:16 for port testing */ 299 #define PORT_LED_OFF (0<<14) 300 #define PORT_LED_AMBER (1<<14) 301 #define PORT_LED_GREEN (2<<14) 302 #define PORT_LED_MASK (3<<14) 303 #define PORT_OWNER (1<<13) /* true: companion hc owns this port */ 304 #define PORT_POWER (1<<12) /* true: has power (see PPC) */ 305 #define PORT_USB11(x) (((x)&(3<<10))==(1<<10)) /* USB 1.1 device */ 306 /* 11:10 for detecting lowspeed devices (reset vs release ownership) */ 307 /* 9 reserved */ 308 #define PORT_RESET (1<<8) /* reset port */ 309 #define PORT_SUSPEND (1<<7) /* suspend port */ 310 #define PORT_RESUME (1<<6) /* resume it */ 311 #define PORT_OCC (1<<5) /* over current change */ 312 #define PORT_OC (1<<4) /* over current active */ 313 #define PORT_PEC (1<<3) /* port enable change */ 314 #define PORT_PE (1<<2) /* port enable */ 315 #define PORT_CSC (1<<1) /* connect status change */ 316 #define PORT_CONNECT (1<<0) /* device connected */ 317 #define PORT_RWC_BITS (PORT_CSC | PORT_PEC | PORT_OCC) 318 } __attribute__ ((packed)); 319 320 #define USBMODE 0x68 /* USB Device mode */ 321 #define USBMODE_SDIS (1<<3) /* Stream disable */ 322 #define USBMODE_BE (1<<2) /* BE/LE endianness select */ 323 #define USBMODE_CM_HC (3<<0) /* host controller mode */ 324 #define USBMODE_CM_IDLE (0<<0) /* idle state */ 325 326 /* Appendix C, Debug port ... intended for use with special "debug devices" 327 * that can help if there's no serial console. (nonstandard enumeration.) 328 */ 329 struct ehci_dbg_port { 330 u32 control; 331 #define DBGP_OWNER (1<<30) 332 #define DBGP_ENABLED (1<<28) 333 #define DBGP_DONE (1<<16) 334 #define DBGP_INUSE (1<<10) 335 #define DBGP_ERRCODE(x) (((x)>>7)&0x07) 336 # define DBGP_ERR_BAD 1 337 # define DBGP_ERR_SIGNAL 2 338 #define DBGP_ERROR (1<<6) 339 #define DBGP_GO (1<<5) 340 #define DBGP_OUT (1<<4) 341 #define DBGP_LEN(x) (((x)>>0)&0x0f) 342 u32 pids; 343 #define DBGP_PID_GET(x) (((x)>>16)&0xff) 344 #define DBGP_PID_SET(data,tok) (((data)<<8)|(tok)) 345 u32 data03; 346 u32 data47; 347 u32 address; 348 #define DBGP_EPADDR(dev,ep) (((dev)<<8)|(ep)) 349 } __attribute__ ((packed)); 350 351 /*-------------------------------------------------------------------------*/ 352 353 #define QTD_NEXT(ehci, dma) cpu_to_hc32(ehci, (u32)dma) 354 355 /* 356 * EHCI Specification 0.95 Section 3.5 357 * QTD: describe data transfer components (buffer, direction, ...) 358 * See Fig 3-6 "Queue Element Transfer Descriptor Block Diagram". 359 * 360 * These are associated only with "QH" (Queue Head) structures, 361 * used with control, bulk, and interrupt transfers. 362 */ 363 struct ehci_qtd { 364 /* first part defined by EHCI spec */ 365 __hc32 hw_next; /* see EHCI 3.5.1 */ 366 __hc32 hw_alt_next; /* see EHCI 3.5.2 */ 367 __hc32 hw_token; /* see EHCI 3.5.3 */ 368 #define QTD_TOGGLE (1 << 31) /* data toggle */ 369 #define QTD_LENGTH(tok) (((tok)>>16) & 0x7fff) 370 #define QTD_IOC (1 << 15) /* interrupt on complete */ 371 #define QTD_CERR(tok) (((tok)>>10) & 0x3) 372 #define QTD_PID(tok) (((tok)>>8) & 0x3) 373 #define QTD_STS_ACTIVE (1 << 7) /* HC may execute this */ 374 #define QTD_STS_HALT (1 << 6) /* halted on error */ 375 #define QTD_STS_DBE (1 << 5) /* data buffer error (in HC) */ 376 #define QTD_STS_BABBLE (1 << 4) /* device was babbling (qtd halted) */ 377 #define QTD_STS_XACT (1 << 3) /* device gave illegal response */ 378 #define QTD_STS_MMF (1 << 2) /* incomplete split transaction */ 379 #define QTD_STS_STS (1 << 1) /* split transaction state */ 380 #define QTD_STS_PING (1 << 0) /* issue PING? */ 381 382 #define ACTIVE_BIT(ehci) cpu_to_hc32(ehci, QTD_STS_ACTIVE) 383 #define HALT_BIT(ehci) cpu_to_hc32(ehci, QTD_STS_HALT) 384 #define STATUS_BIT(ehci) cpu_to_hc32(ehci, QTD_STS_STS) 385 386 __hc32 hw_buf [5]; /* see EHCI 3.5.4 */ 387 __hc32 hw_buf_hi [5]; /* Appendix B */ 388 389 /* the rest is HCD-private */ 390 dma_addr_t qtd_dma; /* qtd address */ 391 struct list_head qtd_list; /* sw qtd list */ 392 struct urb *urb; /* qtd's urb */ 393 size_t length; /* length of buffer */ 394 } __attribute__ ((aligned (32))); 395 396 /* mask NakCnt+T in qh->hw_alt_next */ 397 #define QTD_MASK(ehci) cpu_to_hc32 (ehci, ~0x1f) 398 399 #define IS_SHORT_READ(token) (QTD_LENGTH (token) != 0 && QTD_PID (token) == 1) 400 401 /*-------------------------------------------------------------------------*/ 402 403 /* type tag from {qh,itd,sitd,fstn}->hw_next */ 404 #define Q_NEXT_TYPE(ehci,dma) ((dma) & cpu_to_hc32(ehci, 3 << 1)) 405 406 /* 407 * Now the following defines are not converted using the 408 * __constant_cpu_to_le32() macro anymore, since we have to support 409 * "dynamic" switching between be and le support, so that the driver 410 * can be used on one system with SoC EHCI controller using big-endian 411 * descriptors as well as a normal little-endian PCI EHCI controller. 412 */ 413 /* values for that type tag */ 414 #define Q_TYPE_ITD (0 << 1) 415 #define Q_TYPE_QH (1 << 1) 416 #define Q_TYPE_SITD (2 << 1) 417 #define Q_TYPE_FSTN (3 << 1) 418 419 /* next async queue entry, or pointer to interrupt/periodic QH */ 420 #define QH_NEXT(ehci,dma) (cpu_to_hc32(ehci, (((u32)dma)&~0x01f)|Q_TYPE_QH)) 421 422 /* for periodic/async schedules and qtd lists, mark end of list */ 423 #define EHCI_LIST_END(ehci) cpu_to_hc32(ehci, 1) /* "null pointer" to hw */ 424 425 /* 426 * Entries in periodic shadow table are pointers to one of four kinds 427 * of data structure. That's dictated by the hardware; a type tag is 428 * encoded in the low bits of the hardware's periodic schedule. Use 429 * Q_NEXT_TYPE to get the tag. 430 * 431 * For entries in the async schedule, the type tag always says "qh". 432 */ 433 union ehci_shadow { 434 struct ehci_qh *qh; /* Q_TYPE_QH */ 435 struct ehci_itd *itd; /* Q_TYPE_ITD */ 436 struct ehci_sitd *sitd; /* Q_TYPE_SITD */ 437 struct ehci_fstn *fstn; /* Q_TYPE_FSTN */ 438 __hc32 *hw_next; /* (all types) */ 439 void *ptr; 440 }; 441 442 /*-------------------------------------------------------------------------*/ 443 444 /* 445 * EHCI Specification 0.95 Section 3.6 446 * QH: describes control/bulk/interrupt endpoints 447 * See Fig 3-7 "Queue Head Structure Layout". 448 * 449 * These appear in both the async and (for interrupt) periodic schedules. 450 */ 451 452 struct ehci_qh { 453 /* first part defined by EHCI spec */ 454 __hc32 hw_next; /* see EHCI 3.6.1 */ 455 __hc32 hw_info1; /* see EHCI 3.6.2 */ 456 #define QH_HEAD 0x00008000 457 __hc32 hw_info2; /* see EHCI 3.6.2 */ 458 #define QH_SMASK 0x000000ff 459 #define QH_CMASK 0x0000ff00 460 #define QH_HUBADDR 0x007f0000 461 #define QH_HUBPORT 0x3f800000 462 #define QH_MULT 0xc0000000 463 __hc32 hw_current; /* qtd list - see EHCI 3.6.4 */ 464 465 /* qtd overlay (hardware parts of a struct ehci_qtd) */ 466 __hc32 hw_qtd_next; 467 __hc32 hw_alt_next; 468 __hc32 hw_token; 469 __hc32 hw_buf [5]; 470 __hc32 hw_buf_hi [5]; 471 472 /* the rest is HCD-private */ 473 dma_addr_t qh_dma; /* address of qh */ 474 union ehci_shadow qh_next; /* ptr to qh; or periodic */ 475 struct list_head qtd_list; /* sw qtd list */ 476 struct ehci_qtd *dummy; 477 struct ehci_qh *reclaim; /* next to reclaim */ 478 479 struct ehci_hcd *ehci; 480 481 /* 482 * Do NOT use atomic operations for QH refcounting. On some CPUs 483 * (PPC7448 for example), atomic operations cannot be performed on 484 * memory that is cache-inhibited (i.e. being used for DMA). 485 * Spinlocks are used to protect all QH fields. 486 */ 487 u32 refcount; 488 unsigned stamp; 489 490 u8 qh_state; 491 #define QH_STATE_LINKED 1 /* HC sees this */ 492 #define QH_STATE_UNLINK 2 /* HC may still see this */ 493 #define QH_STATE_IDLE 3 /* HC doesn't see this */ 494 #define QH_STATE_UNLINK_WAIT 4 /* LINKED and on reclaim q */ 495 #define QH_STATE_COMPLETING 5 /* don't touch token.HALT */ 496 497 /* periodic schedule info */ 498 u8 usecs; /* intr bandwidth */ 499 u8 gap_uf; /* uframes split/csplit gap */ 500 u8 c_usecs; /* ... split completion bw */ 501 u16 tt_usecs; /* tt downstream bandwidth */ 502 unsigned short period; /* polling interval */ 503 unsigned short start; /* where polling starts */ 504 #define NO_FRAME ((unsigned short)~0) /* pick new start */ 505 struct usb_device *dev; /* access to TT */ 506 } __attribute__ ((aligned (32))); 507 508 /*-------------------------------------------------------------------------*/ 509 510 /* description of one iso transaction (up to 3 KB data if highspeed) */ 511 struct ehci_iso_packet { 512 /* These will be copied to iTD when scheduling */ 513 u64 bufp; /* itd->hw_bufp{,_hi}[pg] |= */ 514 __hc32 transaction; /* itd->hw_transaction[i] |= */ 515 u8 cross; /* buf crosses pages */ 516 /* for full speed OUT splits */ 517 u32 buf1; 518 }; 519 520 /* temporary schedule data for packets from iso urbs (both speeds) 521 * each packet is one logical usb transaction to the device (not TT), 522 * beginning at stream->next_uframe 523 */ 524 struct ehci_iso_sched { 525 struct list_head td_list; 526 unsigned span; 527 struct ehci_iso_packet packet [0]; 528 }; 529 530 /* 531 * ehci_iso_stream - groups all (s)itds for this endpoint. 532 * acts like a qh would, if EHCI had them for ISO. 533 */ 534 struct ehci_iso_stream { 535 /* first two fields match QH, but info1 == 0 */ 536 __hc32 hw_next; 537 __hc32 hw_info1; 538 539 u32 refcount; 540 u8 bEndpointAddress; 541 u8 highspeed; 542 u16 depth; /* depth in uframes */ 543 struct list_head td_list; /* queued itds/sitds */ 544 struct list_head free_list; /* list of unused itds/sitds */ 545 struct usb_device *udev; 546 struct usb_host_endpoint *ep; 547 548 /* output of (re)scheduling */ 549 unsigned long start; /* jiffies */ 550 unsigned long rescheduled; 551 int next_uframe; 552 __hc32 splits; 553 554 /* the rest is derived from the endpoint descriptor, 555 * trusting urb->interval == f(epdesc->bInterval) and 556 * including the extra info for hw_bufp[0..2] 557 */ 558 u8 usecs, c_usecs; 559 u16 interval; 560 u16 tt_usecs; 561 u16 maxp; 562 u16 raw_mask; 563 unsigned bandwidth; 564 565 /* This is used to initialize iTD's hw_bufp fields */ 566 __hc32 buf0; 567 __hc32 buf1; 568 __hc32 buf2; 569 570 /* this is used to initialize sITD's tt info */ 571 __hc32 address; 572 }; 573 574 /*-------------------------------------------------------------------------*/ 575 576 /* 577 * EHCI Specification 0.95 Section 3.3 578 * Fig 3-4 "Isochronous Transaction Descriptor (iTD)" 579 * 580 * Schedule records for high speed iso xfers 581 */ 582 struct ehci_itd { 583 /* first part defined by EHCI spec */ 584 __hc32 hw_next; /* see EHCI 3.3.1 */ 585 __hc32 hw_transaction [8]; /* see EHCI 3.3.2 */ 586 #define EHCI_ISOC_ACTIVE (1<<31) /* activate transfer this slot */ 587 #define EHCI_ISOC_BUF_ERR (1<<30) /* Data buffer error */ 588 #define EHCI_ISOC_BABBLE (1<<29) /* babble detected */ 589 #define EHCI_ISOC_XACTERR (1<<28) /* XactErr - transaction error */ 590 #define EHCI_ITD_LENGTH(tok) (((tok)>>16) & 0x0fff) 591 #define EHCI_ITD_IOC (1 << 15) /* interrupt on complete */ 592 593 #define ITD_ACTIVE(ehci) cpu_to_hc32(ehci, EHCI_ISOC_ACTIVE) 594 595 __hc32 hw_bufp [7]; /* see EHCI 3.3.3 */ 596 __hc32 hw_bufp_hi [7]; /* Appendix B */ 597 598 /* the rest is HCD-private */ 599 dma_addr_t itd_dma; /* for this itd */ 600 union ehci_shadow itd_next; /* ptr to periodic q entry */ 601 602 struct urb *urb; 603 struct ehci_iso_stream *stream; /* endpoint's queue */ 604 struct list_head itd_list; /* list of stream's itds */ 605 606 /* any/all hw_transactions here may be used by that urb */ 607 unsigned frame; /* where scheduled */ 608 unsigned pg; 609 unsigned index[8]; /* in urb->iso_frame_desc */ 610 } __attribute__ ((aligned (32))); 611 612 /*-------------------------------------------------------------------------*/ 613 614 /* 615 * EHCI Specification 0.95 Section 3.4 616 * siTD, aka split-transaction isochronous Transfer Descriptor 617 * ... describe full speed iso xfers through TT in hubs 618 * see Figure 3-5 "Split-transaction Isochronous Transaction Descriptor (siTD) 619 */ 620 struct ehci_sitd { 621 /* first part defined by EHCI spec */ 622 __hc32 hw_next; 623 /* uses bit field macros above - see EHCI 0.95 Table 3-8 */ 624 __hc32 hw_fullspeed_ep; /* EHCI table 3-9 */ 625 __hc32 hw_uframe; /* EHCI table 3-10 */ 626 __hc32 hw_results; /* EHCI table 3-11 */ 627 #define SITD_IOC (1 << 31) /* interrupt on completion */ 628 #define SITD_PAGE (1 << 30) /* buffer 0/1 */ 629 #define SITD_LENGTH(x) (0x3ff & ((x)>>16)) 630 #define SITD_STS_ACTIVE (1 << 7) /* HC may execute this */ 631 #define SITD_STS_ERR (1 << 6) /* error from TT */ 632 #define SITD_STS_DBE (1 << 5) /* data buffer error (in HC) */ 633 #define SITD_STS_BABBLE (1 << 4) /* device was babbling */ 634 #define SITD_STS_XACT (1 << 3) /* illegal IN response */ 635 #define SITD_STS_MMF (1 << 2) /* incomplete split transaction */ 636 #define SITD_STS_STS (1 << 1) /* split transaction state */ 637 638 #define SITD_ACTIVE(ehci) cpu_to_hc32(ehci, SITD_STS_ACTIVE) 639 640 __hc32 hw_buf [2]; /* EHCI table 3-12 */ 641 __hc32 hw_backpointer; /* EHCI table 3-13 */ 642 __hc32 hw_buf_hi [2]; /* Appendix B */ 643 644 /* the rest is HCD-private */ 645 dma_addr_t sitd_dma; 646 union ehci_shadow sitd_next; /* ptr to periodic q entry */ 647 648 struct urb *urb; 649 struct ehci_iso_stream *stream; /* endpoint's queue */ 650 struct list_head sitd_list; /* list of stream's sitds */ 651 unsigned frame; 652 unsigned index; 653 } __attribute__ ((aligned (32))); 654 655 /*-------------------------------------------------------------------------*/ 656 657 /* 658 * EHCI Specification 0.96 Section 3.7 659 * Periodic Frame Span Traversal Node (FSTN) 660 * 661 * Manages split interrupt transactions (using TT) that span frame boundaries 662 * into uframes 0/1; see 4.12.2.2. In those uframes, a "save place" FSTN 663 * makes the HC jump (back) to a QH to scan for fs/ls QH completions until 664 * it hits a "restore" FSTN; then it returns to finish other uframe 0/1 work. 665 */ 666 struct ehci_fstn { 667 __hc32 hw_next; /* any periodic q entry */ 668 __hc32 hw_prev; /* qh or EHCI_LIST_END */ 669 670 /* the rest is HCD-private */ 671 dma_addr_t fstn_dma; 672 union ehci_shadow fstn_next; /* ptr to periodic q entry */ 673 } __attribute__ ((aligned (32))); 674 675 /*-------------------------------------------------------------------------*/ 676 677 #ifdef CONFIG_USB_EHCI_ROOT_HUB_TT 678 679 /* 680 * Some EHCI controllers have a Transaction Translator built into the 681 * root hub. This is a non-standard feature. Each controller will need 682 * to add code to the following inline functions, and call them as 683 * needed (mostly in root hub code). 684 */ 685 686 #define ehci_is_TDI(e) (ehci_to_hcd(e)->has_tt) 687 688 /* Returns the speed of a device attached to a port on the root hub. */ 689 static inline unsigned int 690 ehci_port_speed(struct ehci_hcd *ehci, unsigned int portsc) 691 { 692 if (ehci_is_TDI(ehci)) { 693 switch ((portsc>>26)&3) { 694 case 0: 695 return 0; 696 case 1: 697 return (1<<USB_PORT_FEAT_LOWSPEED); 698 case 2: 699 default: 700 return (1<<USB_PORT_FEAT_HIGHSPEED); 701 } 702 } 703 return (1<<USB_PORT_FEAT_HIGHSPEED); 704 } 705 706 #else 707 708 #define ehci_is_TDI(e) (0) 709 710 #define ehci_port_speed(ehci, portsc) (1<<USB_PORT_FEAT_HIGHSPEED) 711 #endif 712 713 /*-------------------------------------------------------------------------*/ 714 715 #ifdef CONFIG_PPC_83xx 716 /* Some Freescale processors have an erratum in which the TT 717 * port number in the queue head was 0..N-1 instead of 1..N. 718 */ 719 #define ehci_has_fsl_portno_bug(e) ((e)->has_fsl_port_bug) 720 #else 721 #define ehci_has_fsl_portno_bug(e) (0) 722 #endif 723 724 /* 725 * While most USB host controllers implement their registers in 726 * little-endian format, a minority (celleb companion chip) implement 727 * them in big endian format. 728 * 729 * This attempts to support either format at compile time without a 730 * runtime penalty, or both formats with the additional overhead 731 * of checking a flag bit. 732 */ 733 734 #ifdef CONFIG_USB_EHCI_BIG_ENDIAN_MMIO 735 #define ehci_big_endian_mmio(e) ((e)->big_endian_mmio) 736 #else 737 #define ehci_big_endian_mmio(e) 0 738 #endif 739 740 /* 741 * Big-endian read/write functions are arch-specific. 742 * Other arches can be added if/when they're needed. 743 * 744 * REVISIT: arch/powerpc now has readl/writel_be, so the 745 * definition below can die once the 4xx support is 746 * finally ported over. 747 */ 748 #if defined(CONFIG_PPC) && !defined(CONFIG_PPC_MERGE) 749 #define readl_be(addr) in_be32((__force unsigned *)addr) 750 #define writel_be(val, addr) out_be32((__force unsigned *)addr, val) 751 #endif 752 753 #if defined(CONFIG_ARM) && defined(CONFIG_ARCH_IXP4XX) 754 #define readl_be(addr) __raw_readl((__force unsigned *)addr) 755 #define writel_be(val, addr) __raw_writel(val, (__force unsigned *)addr) 756 #endif 757 758 static inline unsigned int ehci_readl(const struct ehci_hcd *ehci, 759 __u32 __iomem * regs) 760 { 761 #ifdef CONFIG_USB_EHCI_BIG_ENDIAN_MMIO 762 return ehci_big_endian_mmio(ehci) ? 763 readl_be(regs) : 764 readl(regs); 765 #else 766 return readl(regs); 767 #endif 768 } 769 770 static inline void ehci_writel(const struct ehci_hcd *ehci, 771 const unsigned int val, __u32 __iomem *regs) 772 { 773 #ifdef CONFIG_USB_EHCI_BIG_ENDIAN_MMIO 774 ehci_big_endian_mmio(ehci) ? 775 writel_be(val, regs) : 776 writel(val, regs); 777 #else 778 writel(val, regs); 779 #endif 780 } 781 782 /*-------------------------------------------------------------------------*/ 783 784 /* 785 * The AMCC 440EPx not only implements its EHCI registers in big-endian 786 * format, but also its DMA data structures (descriptors). 787 * 788 * EHCI controllers accessed through PCI work normally (little-endian 789 * everywhere), so we won't bother supporting a BE-only mode for now. 790 */ 791 #ifdef CONFIG_USB_EHCI_BIG_ENDIAN_DESC 792 #define ehci_big_endian_desc(e) ((e)->big_endian_desc) 793 794 /* cpu to ehci */ 795 static inline __hc32 cpu_to_hc32 (const struct ehci_hcd *ehci, const u32 x) 796 { 797 return ehci_big_endian_desc(ehci) 798 ? (__force __hc32)cpu_to_be32(x) 799 : (__force __hc32)cpu_to_le32(x); 800 } 801 802 /* ehci to cpu */ 803 static inline u32 hc32_to_cpu (const struct ehci_hcd *ehci, const __hc32 x) 804 { 805 return ehci_big_endian_desc(ehci) 806 ? be32_to_cpu((__force __be32)x) 807 : le32_to_cpu((__force __le32)x); 808 } 809 810 static inline u32 hc32_to_cpup (const struct ehci_hcd *ehci, const __hc32 *x) 811 { 812 return ehci_big_endian_desc(ehci) 813 ? be32_to_cpup((__force __be32 *)x) 814 : le32_to_cpup((__force __le32 *)x); 815 } 816 817 #else 818 819 /* cpu to ehci */ 820 static inline __hc32 cpu_to_hc32 (const struct ehci_hcd *ehci, const u32 x) 821 { 822 return cpu_to_le32(x); 823 } 824 825 /* ehci to cpu */ 826 static inline u32 hc32_to_cpu (const struct ehci_hcd *ehci, const __hc32 x) 827 { 828 return le32_to_cpu(x); 829 } 830 831 static inline u32 hc32_to_cpup (const struct ehci_hcd *ehci, const __hc32 *x) 832 { 833 return le32_to_cpup(x); 834 } 835 836 #endif 837 838 /*-------------------------------------------------------------------------*/ 839 840 #ifndef DEBUG 841 #define STUB_DEBUG_FILES 842 #endif /* DEBUG */ 843 844 /*-------------------------------------------------------------------------*/ 845 846 #endif /* __LINUX_EHCI_HCD_H */ 847