1 /* 2 * Copyright (c) 2001-2002 by David Brownell 3 * 4 * This program is free software; you can redistribute it and/or modify it 5 * under the terms of the GNU General Public License as published by the 6 * Free Software Foundation; either version 2 of the License, or (at your 7 * option) any later version. 8 * 9 * This program is distributed in the hope that it will be useful, but 10 * WITHOUT ANY WARRANTY; without even the implied warranty of MERCHANTABILITY 11 * or FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License 12 * for more details. 13 * 14 * You should have received a copy of the GNU General Public License 15 * along with this program; if not, write to the Free Software Foundation, 16 * Inc., 675 Mass Ave, Cambridge, MA 02139, USA. 17 */ 18 19 #ifndef __LINUX_EHCI_HCD_H 20 #define __LINUX_EHCI_HCD_H 21 22 /* definitions used for the EHCI driver */ 23 24 /* 25 * __hc32 and __hc16 are "Host Controller" types, they may be equivalent to 26 * __leXX (normally) or __beXX (given EHCI_BIG_ENDIAN_DESC), depending on 27 * the host controller implementation. 28 * 29 * To facilitate the strongest possible byte-order checking from "sparse" 30 * and so on, we use __leXX unless that's not practical. 31 */ 32 #ifdef CONFIG_USB_EHCI_BIG_ENDIAN_DESC 33 typedef __u32 __bitwise __hc32; 34 typedef __u16 __bitwise __hc16; 35 #else 36 #define __hc32 __le32 37 #define __hc16 __le16 38 #endif 39 40 /* statistics can be kept for tuning/monitoring */ 41 #if defined(DEBUG) || defined(CONFIG_DYNAMIC_DEBUG) 42 #define EHCI_STATS 43 #endif 44 45 struct ehci_stats { 46 /* irq usage */ 47 unsigned long normal; 48 unsigned long error; 49 unsigned long iaa; 50 unsigned long lost_iaa; 51 52 /* termination of urbs from core */ 53 unsigned long complete; 54 unsigned long unlink; 55 }; 56 57 /* 58 * Scheduling and budgeting information for periodic transfers, for both 59 * high-speed devices and full/low-speed devices lying behind a TT. 60 */ 61 struct ehci_per_sched { 62 struct usb_device *udev; /* access to the TT */ 63 struct usb_host_endpoint *ep; 64 struct list_head ps_list; /* node on ehci_tt's ps_list */ 65 u16 tt_usecs; /* time on the FS/LS bus */ 66 u16 cs_mask; /* C-mask and S-mask bytes */ 67 u16 period; /* actual period in frames */ 68 u16 phase; /* actual phase, frame part */ 69 u8 bw_phase; /* same, for bandwidth 70 reservation */ 71 u8 phase_uf; /* uframe part of the phase */ 72 u8 usecs, c_usecs; /* times on the HS bus */ 73 u8 bw_uperiod; /* period in microframes, for 74 bandwidth reservation */ 75 u8 bw_period; /* same, in frames */ 76 }; 77 #define NO_FRAME 29999 /* frame not assigned yet */ 78 79 /* ehci_hcd->lock guards shared data against other CPUs: 80 * ehci_hcd: async, unlink, periodic (and shadow), ... 81 * usb_host_endpoint: hcpriv 82 * ehci_qh: qh_next, qtd_list 83 * ehci_qtd: qtd_list 84 * 85 * Also, hold this lock when talking to HC registers or 86 * when updating hw_* fields in shared qh/qtd/... structures. 87 */ 88 89 #define EHCI_MAX_ROOT_PORTS 15 /* see HCS_N_PORTS */ 90 91 /* 92 * ehci_rh_state values of EHCI_RH_RUNNING or above mean that the 93 * controller may be doing DMA. Lower values mean there's no DMA. 94 */ 95 enum ehci_rh_state { 96 EHCI_RH_HALTED, 97 EHCI_RH_SUSPENDED, 98 EHCI_RH_RUNNING, 99 EHCI_RH_STOPPING 100 }; 101 102 /* 103 * Timer events, ordered by increasing delay length. 104 * Always update event_delays_ns[] and event_handlers[] (defined in 105 * ehci-timer.c) in parallel with this list. 106 */ 107 enum ehci_hrtimer_event { 108 EHCI_HRTIMER_POLL_ASS, /* Poll for async schedule off */ 109 EHCI_HRTIMER_POLL_PSS, /* Poll for periodic schedule off */ 110 EHCI_HRTIMER_POLL_DEAD, /* Wait for dead controller to stop */ 111 EHCI_HRTIMER_UNLINK_INTR, /* Wait for interrupt QH unlink */ 112 EHCI_HRTIMER_FREE_ITDS, /* Wait for unused iTDs and siTDs */ 113 EHCI_HRTIMER_START_UNLINK_INTR, /* Unlink empty interrupt QHs */ 114 EHCI_HRTIMER_ASYNC_UNLINKS, /* Unlink empty async QHs */ 115 EHCI_HRTIMER_IAA_WATCHDOG, /* Handle lost IAA interrupts */ 116 EHCI_HRTIMER_DISABLE_PERIODIC, /* Wait to disable periodic sched */ 117 EHCI_HRTIMER_DISABLE_ASYNC, /* Wait to disable async sched */ 118 EHCI_HRTIMER_IO_WATCHDOG, /* Check for missing IRQs */ 119 EHCI_HRTIMER_NUM_EVENTS /* Must come last */ 120 }; 121 #define EHCI_HRTIMER_NO_EVENT 99 122 123 struct ehci_hcd { /* one per controller */ 124 /* timing support */ 125 enum ehci_hrtimer_event next_hrtimer_event; 126 unsigned enabled_hrtimer_events; 127 ktime_t hr_timeouts[EHCI_HRTIMER_NUM_EVENTS]; 128 struct hrtimer hrtimer; 129 130 int PSS_poll_count; 131 int ASS_poll_count; 132 int died_poll_count; 133 134 /* glue to PCI and HCD framework */ 135 struct ehci_caps __iomem *caps; 136 struct ehci_regs __iomem *regs; 137 struct ehci_dbg_port __iomem *debug; 138 139 __u32 hcs_params; /* cached register copy */ 140 spinlock_t lock; 141 enum ehci_rh_state rh_state; 142 143 /* general schedule support */ 144 bool scanning:1; 145 bool need_rescan:1; 146 bool intr_unlinking:1; 147 bool iaa_in_progress:1; 148 bool async_unlinking:1; 149 bool shutdown:1; 150 struct ehci_qh *qh_scan_next; 151 152 /* async schedule support */ 153 struct ehci_qh *async; 154 struct ehci_qh *dummy; /* For AMD quirk use */ 155 struct list_head async_unlink; 156 struct list_head async_idle; 157 unsigned async_unlink_cycle; 158 unsigned async_count; /* async activity count */ 159 160 /* periodic schedule support */ 161 #define DEFAULT_I_TDPS 1024 /* some HCs can do less */ 162 unsigned periodic_size; 163 __hc32 *periodic; /* hw periodic table */ 164 dma_addr_t periodic_dma; 165 struct list_head intr_qh_list; 166 unsigned i_thresh; /* uframes HC might cache */ 167 168 union ehci_shadow *pshadow; /* mirror hw periodic table */ 169 struct list_head intr_unlink_wait; 170 struct list_head intr_unlink; 171 unsigned intr_unlink_wait_cycle; 172 unsigned intr_unlink_cycle; 173 unsigned now_frame; /* frame from HC hardware */ 174 unsigned last_iso_frame; /* last frame scanned for iso */ 175 unsigned intr_count; /* intr activity count */ 176 unsigned isoc_count; /* isoc activity count */ 177 unsigned periodic_count; /* periodic activity count */ 178 unsigned uframe_periodic_max; /* max periodic time per uframe */ 179 180 181 /* list of itds & sitds completed while now_frame was still active */ 182 struct list_head cached_itd_list; 183 struct ehci_itd *last_itd_to_free; 184 struct list_head cached_sitd_list; 185 struct ehci_sitd *last_sitd_to_free; 186 187 /* per root hub port */ 188 unsigned long reset_done [EHCI_MAX_ROOT_PORTS]; 189 190 /* bit vectors (one bit per port) */ 191 unsigned long bus_suspended; /* which ports were 192 already suspended at the start of a bus suspend */ 193 unsigned long companion_ports; /* which ports are 194 dedicated to the companion controller */ 195 unsigned long owned_ports; /* which ports are 196 owned by the companion during a bus suspend */ 197 unsigned long port_c_suspend; /* which ports have 198 the change-suspend feature turned on */ 199 unsigned long suspended_ports; /* which ports are 200 suspended */ 201 unsigned long resuming_ports; /* which ports have 202 started to resume */ 203 204 /* per-HC memory pools (could be per-bus, but ...) */ 205 struct dma_pool *qh_pool; /* qh per active urb */ 206 struct dma_pool *qtd_pool; /* one or more per qh */ 207 struct dma_pool *itd_pool; /* itd per iso urb */ 208 struct dma_pool *sitd_pool; /* sitd per split iso urb */ 209 210 unsigned random_frame; 211 unsigned long next_statechange; 212 ktime_t last_periodic_enable; 213 u32 command; 214 215 /* SILICON QUIRKS */ 216 unsigned no_selective_suspend:1; 217 unsigned has_fsl_port_bug:1; /* FreeScale */ 218 unsigned big_endian_mmio:1; 219 unsigned big_endian_desc:1; 220 unsigned big_endian_capbase:1; 221 unsigned has_amcc_usb23:1; 222 unsigned need_io_watchdog:1; 223 unsigned amd_pll_fix:1; 224 unsigned use_dummy_qh:1; /* AMD Frame List table quirk*/ 225 unsigned has_synopsys_hc_bug:1; /* Synopsys HC */ 226 unsigned frame_index_bug:1; /* MosChip (AKA NetMos) */ 227 unsigned need_oc_pp_cycle:1; /* MPC834X port power */ 228 229 /* required for usb32 quirk */ 230 #define OHCI_CTRL_HCFS (3 << 6) 231 #define OHCI_USB_OPER (2 << 6) 232 #define OHCI_USB_SUSPEND (3 << 6) 233 234 #define OHCI_HCCTRL_OFFSET 0x4 235 #define OHCI_HCCTRL_LEN 0x4 236 __hc32 *ohci_hcctrl_reg; 237 unsigned has_hostpc:1; 238 unsigned has_tdi_phy_lpm:1; 239 unsigned has_ppcd:1; /* support per-port change bits */ 240 u8 sbrn; /* packed release number */ 241 242 /* irq statistics */ 243 #ifdef EHCI_STATS 244 struct ehci_stats stats; 245 # define COUNT(x) do { (x)++; } while (0) 246 #else 247 # define COUNT(x) do {} while (0) 248 #endif 249 250 /* debug files */ 251 #if defined(DEBUG) || defined(CONFIG_DYNAMIC_DEBUG) 252 struct dentry *debug_dir; 253 #endif 254 255 /* bandwidth usage */ 256 #define EHCI_BANDWIDTH_SIZE 64 257 #define EHCI_BANDWIDTH_FRAMES (EHCI_BANDWIDTH_SIZE >> 3) 258 u8 bandwidth[EHCI_BANDWIDTH_SIZE]; 259 /* us allocated per uframe */ 260 u8 tt_budget[EHCI_BANDWIDTH_SIZE]; 261 /* us budgeted per uframe */ 262 struct list_head tt_list; 263 264 /* platform-specific data -- must come last */ 265 unsigned long priv[0] __aligned(sizeof(s64)); 266 }; 267 268 /* convert between an HCD pointer and the corresponding EHCI_HCD */ 269 static inline struct ehci_hcd *hcd_to_ehci (struct usb_hcd *hcd) 270 { 271 return (struct ehci_hcd *) (hcd->hcd_priv); 272 } 273 static inline struct usb_hcd *ehci_to_hcd (struct ehci_hcd *ehci) 274 { 275 return container_of ((void *) ehci, struct usb_hcd, hcd_priv); 276 } 277 278 /*-------------------------------------------------------------------------*/ 279 280 #include <linux/usb/ehci_def.h> 281 282 /*-------------------------------------------------------------------------*/ 283 284 #define QTD_NEXT(ehci, dma) cpu_to_hc32(ehci, (u32)dma) 285 286 /* 287 * EHCI Specification 0.95 Section 3.5 288 * QTD: describe data transfer components (buffer, direction, ...) 289 * See Fig 3-6 "Queue Element Transfer Descriptor Block Diagram". 290 * 291 * These are associated only with "QH" (Queue Head) structures, 292 * used with control, bulk, and interrupt transfers. 293 */ 294 struct ehci_qtd { 295 /* first part defined by EHCI spec */ 296 __hc32 hw_next; /* see EHCI 3.5.1 */ 297 __hc32 hw_alt_next; /* see EHCI 3.5.2 */ 298 __hc32 hw_token; /* see EHCI 3.5.3 */ 299 #define QTD_TOGGLE (1 << 31) /* data toggle */ 300 #define QTD_LENGTH(tok) (((tok)>>16) & 0x7fff) 301 #define QTD_IOC (1 << 15) /* interrupt on complete */ 302 #define QTD_CERR(tok) (((tok)>>10) & 0x3) 303 #define QTD_PID(tok) (((tok)>>8) & 0x3) 304 #define QTD_STS_ACTIVE (1 << 7) /* HC may execute this */ 305 #define QTD_STS_HALT (1 << 6) /* halted on error */ 306 #define QTD_STS_DBE (1 << 5) /* data buffer error (in HC) */ 307 #define QTD_STS_BABBLE (1 << 4) /* device was babbling (qtd halted) */ 308 #define QTD_STS_XACT (1 << 3) /* device gave illegal response */ 309 #define QTD_STS_MMF (1 << 2) /* incomplete split transaction */ 310 #define QTD_STS_STS (1 << 1) /* split transaction state */ 311 #define QTD_STS_PING (1 << 0) /* issue PING? */ 312 313 #define ACTIVE_BIT(ehci) cpu_to_hc32(ehci, QTD_STS_ACTIVE) 314 #define HALT_BIT(ehci) cpu_to_hc32(ehci, QTD_STS_HALT) 315 #define STATUS_BIT(ehci) cpu_to_hc32(ehci, QTD_STS_STS) 316 317 __hc32 hw_buf [5]; /* see EHCI 3.5.4 */ 318 __hc32 hw_buf_hi [5]; /* Appendix B */ 319 320 /* the rest is HCD-private */ 321 dma_addr_t qtd_dma; /* qtd address */ 322 struct list_head qtd_list; /* sw qtd list */ 323 struct urb *urb; /* qtd's urb */ 324 size_t length; /* length of buffer */ 325 } __attribute__ ((aligned (32))); 326 327 /* mask NakCnt+T in qh->hw_alt_next */ 328 #define QTD_MASK(ehci) cpu_to_hc32 (ehci, ~0x1f) 329 330 #define IS_SHORT_READ(token) (QTD_LENGTH (token) != 0 && QTD_PID (token) == 1) 331 332 /*-------------------------------------------------------------------------*/ 333 334 /* type tag from {qh,itd,sitd,fstn}->hw_next */ 335 #define Q_NEXT_TYPE(ehci,dma) ((dma) & cpu_to_hc32(ehci, 3 << 1)) 336 337 /* 338 * Now the following defines are not converted using the 339 * cpu_to_le32() macro anymore, since we have to support 340 * "dynamic" switching between be and le support, so that the driver 341 * can be used on one system with SoC EHCI controller using big-endian 342 * descriptors as well as a normal little-endian PCI EHCI controller. 343 */ 344 /* values for that type tag */ 345 #define Q_TYPE_ITD (0 << 1) 346 #define Q_TYPE_QH (1 << 1) 347 #define Q_TYPE_SITD (2 << 1) 348 #define Q_TYPE_FSTN (3 << 1) 349 350 /* next async queue entry, or pointer to interrupt/periodic QH */ 351 #define QH_NEXT(ehci,dma) (cpu_to_hc32(ehci, (((u32)dma)&~0x01f)|Q_TYPE_QH)) 352 353 /* for periodic/async schedules and qtd lists, mark end of list */ 354 #define EHCI_LIST_END(ehci) cpu_to_hc32(ehci, 1) /* "null pointer" to hw */ 355 356 /* 357 * Entries in periodic shadow table are pointers to one of four kinds 358 * of data structure. That's dictated by the hardware; a type tag is 359 * encoded in the low bits of the hardware's periodic schedule. Use 360 * Q_NEXT_TYPE to get the tag. 361 * 362 * For entries in the async schedule, the type tag always says "qh". 363 */ 364 union ehci_shadow { 365 struct ehci_qh *qh; /* Q_TYPE_QH */ 366 struct ehci_itd *itd; /* Q_TYPE_ITD */ 367 struct ehci_sitd *sitd; /* Q_TYPE_SITD */ 368 struct ehci_fstn *fstn; /* Q_TYPE_FSTN */ 369 __hc32 *hw_next; /* (all types) */ 370 void *ptr; 371 }; 372 373 /*-------------------------------------------------------------------------*/ 374 375 /* 376 * EHCI Specification 0.95 Section 3.6 377 * QH: describes control/bulk/interrupt endpoints 378 * See Fig 3-7 "Queue Head Structure Layout". 379 * 380 * These appear in both the async and (for interrupt) periodic schedules. 381 */ 382 383 /* first part defined by EHCI spec */ 384 struct ehci_qh_hw { 385 __hc32 hw_next; /* see EHCI 3.6.1 */ 386 __hc32 hw_info1; /* see EHCI 3.6.2 */ 387 #define QH_CONTROL_EP (1 << 27) /* FS/LS control endpoint */ 388 #define QH_HEAD (1 << 15) /* Head of async reclamation list */ 389 #define QH_TOGGLE_CTL (1 << 14) /* Data toggle control */ 390 #define QH_HIGH_SPEED (2 << 12) /* Endpoint speed */ 391 #define QH_LOW_SPEED (1 << 12) 392 #define QH_FULL_SPEED (0 << 12) 393 #define QH_INACTIVATE (1 << 7) /* Inactivate on next transaction */ 394 __hc32 hw_info2; /* see EHCI 3.6.2 */ 395 #define QH_SMASK 0x000000ff 396 #define QH_CMASK 0x0000ff00 397 #define QH_HUBADDR 0x007f0000 398 #define QH_HUBPORT 0x3f800000 399 #define QH_MULT 0xc0000000 400 __hc32 hw_current; /* qtd list - see EHCI 3.6.4 */ 401 402 /* qtd overlay (hardware parts of a struct ehci_qtd) */ 403 __hc32 hw_qtd_next; 404 __hc32 hw_alt_next; 405 __hc32 hw_token; 406 __hc32 hw_buf [5]; 407 __hc32 hw_buf_hi [5]; 408 } __attribute__ ((aligned(32))); 409 410 struct ehci_qh { 411 struct ehci_qh_hw *hw; /* Must come first */ 412 /* the rest is HCD-private */ 413 dma_addr_t qh_dma; /* address of qh */ 414 union ehci_shadow qh_next; /* ptr to qh; or periodic */ 415 struct list_head qtd_list; /* sw qtd list */ 416 struct list_head intr_node; /* list of intr QHs */ 417 struct ehci_qtd *dummy; 418 struct list_head unlink_node; 419 struct ehci_per_sched ps; /* scheduling info */ 420 421 unsigned unlink_cycle; 422 423 u8 qh_state; 424 #define QH_STATE_LINKED 1 /* HC sees this */ 425 #define QH_STATE_UNLINK 2 /* HC may still see this */ 426 #define QH_STATE_IDLE 3 /* HC doesn't see this */ 427 #define QH_STATE_UNLINK_WAIT 4 /* LINKED and on unlink q */ 428 #define QH_STATE_COMPLETING 5 /* don't touch token.HALT */ 429 430 u8 xacterrs; /* XactErr retry counter */ 431 #define QH_XACTERR_MAX 32 /* XactErr retry limit */ 432 433 u8 gap_uf; /* uframes split/csplit gap */ 434 435 unsigned is_out:1; /* bulk or intr OUT */ 436 unsigned clearing_tt:1; /* Clear-TT-Buf in progress */ 437 unsigned dequeue_during_giveback:1; 438 unsigned exception:1; /* got a fault, or an unlink 439 was requested */ 440 }; 441 442 /*-------------------------------------------------------------------------*/ 443 444 /* description of one iso transaction (up to 3 KB data if highspeed) */ 445 struct ehci_iso_packet { 446 /* These will be copied to iTD when scheduling */ 447 u64 bufp; /* itd->hw_bufp{,_hi}[pg] |= */ 448 __hc32 transaction; /* itd->hw_transaction[i] |= */ 449 u8 cross; /* buf crosses pages */ 450 /* for full speed OUT splits */ 451 u32 buf1; 452 }; 453 454 /* temporary schedule data for packets from iso urbs (both speeds) 455 * each packet is one logical usb transaction to the device (not TT), 456 * beginning at stream->next_uframe 457 */ 458 struct ehci_iso_sched { 459 struct list_head td_list; 460 unsigned span; 461 unsigned first_packet; 462 struct ehci_iso_packet packet [0]; 463 }; 464 465 /* 466 * ehci_iso_stream - groups all (s)itds for this endpoint. 467 * acts like a qh would, if EHCI had them for ISO. 468 */ 469 struct ehci_iso_stream { 470 /* first field matches ehci_hq, but is NULL */ 471 struct ehci_qh_hw *hw; 472 473 u8 bEndpointAddress; 474 u8 highspeed; 475 struct list_head td_list; /* queued itds/sitds */ 476 struct list_head free_list; /* list of unused itds/sitds */ 477 478 /* output of (re)scheduling */ 479 struct ehci_per_sched ps; /* scheduling info */ 480 unsigned next_uframe; 481 __hc32 splits; 482 483 /* the rest is derived from the endpoint descriptor, 484 * including the extra info for hw_bufp[0..2] 485 */ 486 u16 uperiod; /* period in uframes */ 487 u16 maxp; 488 unsigned bandwidth; 489 490 /* This is used to initialize iTD's hw_bufp fields */ 491 __hc32 buf0; 492 __hc32 buf1; 493 __hc32 buf2; 494 495 /* this is used to initialize sITD's tt info */ 496 __hc32 address; 497 }; 498 499 /*-------------------------------------------------------------------------*/ 500 501 /* 502 * EHCI Specification 0.95 Section 3.3 503 * Fig 3-4 "Isochronous Transaction Descriptor (iTD)" 504 * 505 * Schedule records for high speed iso xfers 506 */ 507 struct ehci_itd { 508 /* first part defined by EHCI spec */ 509 __hc32 hw_next; /* see EHCI 3.3.1 */ 510 __hc32 hw_transaction [8]; /* see EHCI 3.3.2 */ 511 #define EHCI_ISOC_ACTIVE (1<<31) /* activate transfer this slot */ 512 #define EHCI_ISOC_BUF_ERR (1<<30) /* Data buffer error */ 513 #define EHCI_ISOC_BABBLE (1<<29) /* babble detected */ 514 #define EHCI_ISOC_XACTERR (1<<28) /* XactErr - transaction error */ 515 #define EHCI_ITD_LENGTH(tok) (((tok)>>16) & 0x0fff) 516 #define EHCI_ITD_IOC (1 << 15) /* interrupt on complete */ 517 518 #define ITD_ACTIVE(ehci) cpu_to_hc32(ehci, EHCI_ISOC_ACTIVE) 519 520 __hc32 hw_bufp [7]; /* see EHCI 3.3.3 */ 521 __hc32 hw_bufp_hi [7]; /* Appendix B */ 522 523 /* the rest is HCD-private */ 524 dma_addr_t itd_dma; /* for this itd */ 525 union ehci_shadow itd_next; /* ptr to periodic q entry */ 526 527 struct urb *urb; 528 struct ehci_iso_stream *stream; /* endpoint's queue */ 529 struct list_head itd_list; /* list of stream's itds */ 530 531 /* any/all hw_transactions here may be used by that urb */ 532 unsigned frame; /* where scheduled */ 533 unsigned pg; 534 unsigned index[8]; /* in urb->iso_frame_desc */ 535 } __attribute__ ((aligned (32))); 536 537 /*-------------------------------------------------------------------------*/ 538 539 /* 540 * EHCI Specification 0.95 Section 3.4 541 * siTD, aka split-transaction isochronous Transfer Descriptor 542 * ... describe full speed iso xfers through TT in hubs 543 * see Figure 3-5 "Split-transaction Isochronous Transaction Descriptor (siTD) 544 */ 545 struct ehci_sitd { 546 /* first part defined by EHCI spec */ 547 __hc32 hw_next; 548 /* uses bit field macros above - see EHCI 0.95 Table 3-8 */ 549 __hc32 hw_fullspeed_ep; /* EHCI table 3-9 */ 550 __hc32 hw_uframe; /* EHCI table 3-10 */ 551 __hc32 hw_results; /* EHCI table 3-11 */ 552 #define SITD_IOC (1 << 31) /* interrupt on completion */ 553 #define SITD_PAGE (1 << 30) /* buffer 0/1 */ 554 #define SITD_LENGTH(x) (0x3ff & ((x)>>16)) 555 #define SITD_STS_ACTIVE (1 << 7) /* HC may execute this */ 556 #define SITD_STS_ERR (1 << 6) /* error from TT */ 557 #define SITD_STS_DBE (1 << 5) /* data buffer error (in HC) */ 558 #define SITD_STS_BABBLE (1 << 4) /* device was babbling */ 559 #define SITD_STS_XACT (1 << 3) /* illegal IN response */ 560 #define SITD_STS_MMF (1 << 2) /* incomplete split transaction */ 561 #define SITD_STS_STS (1 << 1) /* split transaction state */ 562 563 #define SITD_ACTIVE(ehci) cpu_to_hc32(ehci, SITD_STS_ACTIVE) 564 565 __hc32 hw_buf [2]; /* EHCI table 3-12 */ 566 __hc32 hw_backpointer; /* EHCI table 3-13 */ 567 __hc32 hw_buf_hi [2]; /* Appendix B */ 568 569 /* the rest is HCD-private */ 570 dma_addr_t sitd_dma; 571 union ehci_shadow sitd_next; /* ptr to periodic q entry */ 572 573 struct urb *urb; 574 struct ehci_iso_stream *stream; /* endpoint's queue */ 575 struct list_head sitd_list; /* list of stream's sitds */ 576 unsigned frame; 577 unsigned index; 578 } __attribute__ ((aligned (32))); 579 580 /*-------------------------------------------------------------------------*/ 581 582 /* 583 * EHCI Specification 0.96 Section 3.7 584 * Periodic Frame Span Traversal Node (FSTN) 585 * 586 * Manages split interrupt transactions (using TT) that span frame boundaries 587 * into uframes 0/1; see 4.12.2.2. In those uframes, a "save place" FSTN 588 * makes the HC jump (back) to a QH to scan for fs/ls QH completions until 589 * it hits a "restore" FSTN; then it returns to finish other uframe 0/1 work. 590 */ 591 struct ehci_fstn { 592 __hc32 hw_next; /* any periodic q entry */ 593 __hc32 hw_prev; /* qh or EHCI_LIST_END */ 594 595 /* the rest is HCD-private */ 596 dma_addr_t fstn_dma; 597 union ehci_shadow fstn_next; /* ptr to periodic q entry */ 598 } __attribute__ ((aligned (32))); 599 600 /*-------------------------------------------------------------------------*/ 601 602 /* 603 * USB-2.0 Specification Sections 11.14 and 11.18 604 * Scheduling and budgeting split transactions using TTs 605 * 606 * A hub can have a single TT for all its ports, or multiple TTs (one for each 607 * port). The bandwidth and budgeting information for the full/low-speed bus 608 * below each TT is self-contained and independent of the other TTs or the 609 * high-speed bus. 610 * 611 * "Bandwidth" refers to the number of microseconds on the FS/LS bus allocated 612 * to an interrupt or isochronous endpoint for each frame. "Budget" refers to 613 * the best-case estimate of the number of full-speed bytes allocated to an 614 * endpoint for each microframe within an allocated frame. 615 * 616 * Removal of an endpoint invalidates a TT's budget. Instead of trying to 617 * keep an up-to-date record, we recompute the budget when it is needed. 618 */ 619 620 struct ehci_tt { 621 u16 bandwidth[EHCI_BANDWIDTH_FRAMES]; 622 623 struct list_head tt_list; /* List of all ehci_tt's */ 624 struct list_head ps_list; /* Items using this TT */ 625 struct usb_tt *usb_tt; 626 int tt_port; /* TT port number */ 627 }; 628 629 /*-------------------------------------------------------------------------*/ 630 631 /* Prepare the PORTSC wakeup flags during controller suspend/resume */ 632 633 #define ehci_prepare_ports_for_controller_suspend(ehci, do_wakeup) \ 634 ehci_adjust_port_wakeup_flags(ehci, true, do_wakeup); 635 636 #define ehci_prepare_ports_for_controller_resume(ehci) \ 637 ehci_adjust_port_wakeup_flags(ehci, false, false); 638 639 /*-------------------------------------------------------------------------*/ 640 641 #ifdef CONFIG_USB_EHCI_ROOT_HUB_TT 642 643 /* 644 * Some EHCI controllers have a Transaction Translator built into the 645 * root hub. This is a non-standard feature. Each controller will need 646 * to add code to the following inline functions, and call them as 647 * needed (mostly in root hub code). 648 */ 649 650 #define ehci_is_TDI(e) (ehci_to_hcd(e)->has_tt) 651 652 /* Returns the speed of a device attached to a port on the root hub. */ 653 static inline unsigned int 654 ehci_port_speed(struct ehci_hcd *ehci, unsigned int portsc) 655 { 656 if (ehci_is_TDI(ehci)) { 657 switch ((portsc >> (ehci->has_hostpc ? 25 : 26)) & 3) { 658 case 0: 659 return 0; 660 case 1: 661 return USB_PORT_STAT_LOW_SPEED; 662 case 2: 663 default: 664 return USB_PORT_STAT_HIGH_SPEED; 665 } 666 } 667 return USB_PORT_STAT_HIGH_SPEED; 668 } 669 670 #else 671 672 #define ehci_is_TDI(e) (0) 673 674 #define ehci_port_speed(ehci, portsc) USB_PORT_STAT_HIGH_SPEED 675 #endif 676 677 /*-------------------------------------------------------------------------*/ 678 679 #ifdef CONFIG_PPC_83xx 680 /* Some Freescale processors have an erratum in which the TT 681 * port number in the queue head was 0..N-1 instead of 1..N. 682 */ 683 #define ehci_has_fsl_portno_bug(e) ((e)->has_fsl_port_bug) 684 #else 685 #define ehci_has_fsl_portno_bug(e) (0) 686 #endif 687 688 /* 689 * While most USB host controllers implement their registers in 690 * little-endian format, a minority (celleb companion chip) implement 691 * them in big endian format. 692 * 693 * This attempts to support either format at compile time without a 694 * runtime penalty, or both formats with the additional overhead 695 * of checking a flag bit. 696 * 697 * ehci_big_endian_capbase is a special quirk for controllers that 698 * implement the HC capability registers as separate registers and not 699 * as fields of a 32-bit register. 700 */ 701 702 #ifdef CONFIG_USB_EHCI_BIG_ENDIAN_MMIO 703 #define ehci_big_endian_mmio(e) ((e)->big_endian_mmio) 704 #define ehci_big_endian_capbase(e) ((e)->big_endian_capbase) 705 #else 706 #define ehci_big_endian_mmio(e) 0 707 #define ehci_big_endian_capbase(e) 0 708 #endif 709 710 /* 711 * Big-endian read/write functions are arch-specific. 712 * Other arches can be added if/when they're needed. 713 */ 714 #if defined(CONFIG_ARM) && defined(CONFIG_ARCH_IXP4XX) 715 #define readl_be(addr) __raw_readl((__force unsigned *)addr) 716 #define writel_be(val, addr) __raw_writel(val, (__force unsigned *)addr) 717 #endif 718 719 static inline unsigned int ehci_readl(const struct ehci_hcd *ehci, 720 __u32 __iomem * regs) 721 { 722 #ifdef CONFIG_USB_EHCI_BIG_ENDIAN_MMIO 723 return ehci_big_endian_mmio(ehci) ? 724 readl_be(regs) : 725 readl(regs); 726 #else 727 return readl(regs); 728 #endif 729 } 730 731 static inline void ehci_writel(const struct ehci_hcd *ehci, 732 const unsigned int val, __u32 __iomem *regs) 733 { 734 #ifdef CONFIG_USB_EHCI_BIG_ENDIAN_MMIO 735 ehci_big_endian_mmio(ehci) ? 736 writel_be(val, regs) : 737 writel(val, regs); 738 #else 739 writel(val, regs); 740 #endif 741 } 742 743 /* 744 * On certain ppc-44x SoC there is a HW issue, that could only worked around with 745 * explicit suspend/operate of OHCI. This function hereby makes sense only on that arch. 746 * Other common bits are dependent on has_amcc_usb23 quirk flag. 747 */ 748 #ifdef CONFIG_44x 749 static inline void set_ohci_hcfs(struct ehci_hcd *ehci, int operational) 750 { 751 u32 hc_control; 752 753 hc_control = (readl_be(ehci->ohci_hcctrl_reg) & ~OHCI_CTRL_HCFS); 754 if (operational) 755 hc_control |= OHCI_USB_OPER; 756 else 757 hc_control |= OHCI_USB_SUSPEND; 758 759 writel_be(hc_control, ehci->ohci_hcctrl_reg); 760 (void) readl_be(ehci->ohci_hcctrl_reg); 761 } 762 #else 763 static inline void set_ohci_hcfs(struct ehci_hcd *ehci, int operational) 764 { } 765 #endif 766 767 /*-------------------------------------------------------------------------*/ 768 769 /* 770 * The AMCC 440EPx not only implements its EHCI registers in big-endian 771 * format, but also its DMA data structures (descriptors). 772 * 773 * EHCI controllers accessed through PCI work normally (little-endian 774 * everywhere), so we won't bother supporting a BE-only mode for now. 775 */ 776 #ifdef CONFIG_USB_EHCI_BIG_ENDIAN_DESC 777 #define ehci_big_endian_desc(e) ((e)->big_endian_desc) 778 779 /* cpu to ehci */ 780 static inline __hc32 cpu_to_hc32 (const struct ehci_hcd *ehci, const u32 x) 781 { 782 return ehci_big_endian_desc(ehci) 783 ? (__force __hc32)cpu_to_be32(x) 784 : (__force __hc32)cpu_to_le32(x); 785 } 786 787 /* ehci to cpu */ 788 static inline u32 hc32_to_cpu (const struct ehci_hcd *ehci, const __hc32 x) 789 { 790 return ehci_big_endian_desc(ehci) 791 ? be32_to_cpu((__force __be32)x) 792 : le32_to_cpu((__force __le32)x); 793 } 794 795 static inline u32 hc32_to_cpup (const struct ehci_hcd *ehci, const __hc32 *x) 796 { 797 return ehci_big_endian_desc(ehci) 798 ? be32_to_cpup((__force __be32 *)x) 799 : le32_to_cpup((__force __le32 *)x); 800 } 801 802 #else 803 804 /* cpu to ehci */ 805 static inline __hc32 cpu_to_hc32 (const struct ehci_hcd *ehci, const u32 x) 806 { 807 return cpu_to_le32(x); 808 } 809 810 /* ehci to cpu */ 811 static inline u32 hc32_to_cpu (const struct ehci_hcd *ehci, const __hc32 x) 812 { 813 return le32_to_cpu(x); 814 } 815 816 static inline u32 hc32_to_cpup (const struct ehci_hcd *ehci, const __hc32 *x) 817 { 818 return le32_to_cpup(x); 819 } 820 821 #endif 822 823 /*-------------------------------------------------------------------------*/ 824 825 #define ehci_dbg(ehci, fmt, args...) \ 826 dev_dbg(ehci_to_hcd(ehci)->self.controller , fmt , ## args) 827 #define ehci_err(ehci, fmt, args...) \ 828 dev_err(ehci_to_hcd(ehci)->self.controller , fmt , ## args) 829 #define ehci_info(ehci, fmt, args...) \ 830 dev_info(ehci_to_hcd(ehci)->self.controller , fmt , ## args) 831 #define ehci_warn(ehci, fmt, args...) \ 832 dev_warn(ehci_to_hcd(ehci)->self.controller , fmt , ## args) 833 834 835 #if !defined(DEBUG) && !defined(CONFIG_DYNAMIC_DEBUG) 836 #define STUB_DEBUG_FILES 837 #endif /* !DEBUG && !CONFIG_DYNAMIC_DEBUG */ 838 839 /*-------------------------------------------------------------------------*/ 840 841 /* Declarations of things exported for use by ehci platform drivers */ 842 843 struct ehci_driver_overrides { 844 size_t extra_priv_size; 845 int (*reset)(struct usb_hcd *hcd); 846 }; 847 848 extern void ehci_init_driver(struct hc_driver *drv, 849 const struct ehci_driver_overrides *over); 850 extern int ehci_setup(struct usb_hcd *hcd); 851 extern int ehci_handshake(struct ehci_hcd *ehci, void __iomem *ptr, 852 u32 mask, u32 done, int usec); 853 854 #ifdef CONFIG_PM 855 extern int ehci_suspend(struct usb_hcd *hcd, bool do_wakeup); 856 extern int ehci_resume(struct usb_hcd *hcd, bool hibernated); 857 #endif /* CONFIG_PM */ 858 859 #endif /* __LINUX_EHCI_HCD_H */ 860