1 /* 2 * Copyright (c) 2001-2004 by David Brownell 3 * Copyright (c) 2003 Michal Sojka, for high-speed iso transfers 4 * 5 * This program is free software; you can redistribute it and/or modify it 6 * under the terms of the GNU General Public License as published by the 7 * Free Software Foundation; either version 2 of the License, or (at your 8 * option) any later version. 9 * 10 * This program is distributed in the hope that it will be useful, but 11 * WITHOUT ANY WARRANTY; without even the implied warranty of MERCHANTABILITY 12 * or FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License 13 * for more details. 14 * 15 * You should have received a copy of the GNU General Public License 16 * along with this program; if not, write to the Free Software Foundation, 17 * Inc., 675 Mass Ave, Cambridge, MA 02139, USA. 18 */ 19 20 /* this file is part of ehci-hcd.c */ 21 22 /*-------------------------------------------------------------------------*/ 23 24 /* 25 * EHCI scheduled transaction support: interrupt, iso, split iso 26 * These are called "periodic" transactions in the EHCI spec. 27 * 28 * Note that for interrupt transfers, the QH/QTD manipulation is shared 29 * with the "asynchronous" transaction support (control/bulk transfers). 30 * The only real difference is in how interrupt transfers are scheduled. 31 * 32 * For ISO, we make an "iso_stream" head to serve the same role as a QH. 33 * It keeps track of every ITD (or SITD) that's linked, and holds enough 34 * pre-calculated schedule data to make appending to the queue be quick. 35 */ 36 37 static int ehci_get_frame(struct usb_hcd *hcd); 38 39 /* 40 * periodic_next_shadow - return "next" pointer on shadow list 41 * @periodic: host pointer to qh/itd/sitd 42 * @tag: hardware tag for type of this record 43 */ 44 static union ehci_shadow * 45 periodic_next_shadow(struct ehci_hcd *ehci, union ehci_shadow *periodic, 46 __hc32 tag) 47 { 48 switch (hc32_to_cpu(ehci, tag)) { 49 case Q_TYPE_QH: 50 return &periodic->qh->qh_next; 51 case Q_TYPE_FSTN: 52 return &periodic->fstn->fstn_next; 53 case Q_TYPE_ITD: 54 return &periodic->itd->itd_next; 55 // case Q_TYPE_SITD: 56 default: 57 return &periodic->sitd->sitd_next; 58 } 59 } 60 61 static __hc32 * 62 shadow_next_periodic(struct ehci_hcd *ehci, union ehci_shadow *periodic, 63 __hc32 tag) 64 { 65 switch (hc32_to_cpu(ehci, tag)) { 66 /* our ehci_shadow.qh is actually software part */ 67 case Q_TYPE_QH: 68 return &periodic->qh->hw->hw_next; 69 /* others are hw parts */ 70 default: 71 return periodic->hw_next; 72 } 73 } 74 75 /* caller must hold ehci->lock */ 76 static void periodic_unlink(struct ehci_hcd *ehci, unsigned frame, void *ptr) 77 { 78 union ehci_shadow *prev_p = &ehci->pshadow[frame]; 79 __hc32 *hw_p = &ehci->periodic[frame]; 80 union ehci_shadow here = *prev_p; 81 82 /* find predecessor of "ptr"; hw and shadow lists are in sync */ 83 while (here.ptr && here.ptr != ptr) { 84 prev_p = periodic_next_shadow(ehci, prev_p, 85 Q_NEXT_TYPE(ehci, *hw_p)); 86 hw_p = shadow_next_periodic(ehci, &here, 87 Q_NEXT_TYPE(ehci, *hw_p)); 88 here = *prev_p; 89 } 90 /* an interrupt entry (at list end) could have been shared */ 91 if (!here.ptr) 92 return; 93 94 /* update shadow and hardware lists ... the old "next" pointers 95 * from ptr may still be in use, the caller updates them. 96 */ 97 *prev_p = *periodic_next_shadow(ehci, &here, 98 Q_NEXT_TYPE(ehci, *hw_p)); 99 100 if (!ehci->use_dummy_qh || 101 *shadow_next_periodic(ehci, &here, Q_NEXT_TYPE(ehci, *hw_p)) 102 != EHCI_LIST_END(ehci)) 103 *hw_p = *shadow_next_periodic(ehci, &here, 104 Q_NEXT_TYPE(ehci, *hw_p)); 105 else 106 *hw_p = cpu_to_hc32(ehci, ehci->dummy->qh_dma); 107 } 108 109 /*-------------------------------------------------------------------------*/ 110 111 /* Bandwidth and TT management */ 112 113 /* Find the TT data structure for this device; create it if necessary */ 114 static struct ehci_tt *find_tt(struct usb_device *udev) 115 { 116 struct usb_tt *utt = udev->tt; 117 struct ehci_tt *tt, **tt_index, **ptt; 118 unsigned port; 119 bool allocated_index = false; 120 121 if (!utt) 122 return NULL; /* Not below a TT */ 123 124 /* 125 * Find/create our data structure. 126 * For hubs with a single TT, we get it directly. 127 * For hubs with multiple TTs, there's an extra level of pointers. 128 */ 129 tt_index = NULL; 130 if (utt->multi) { 131 tt_index = utt->hcpriv; 132 if (!tt_index) { /* Create the index array */ 133 tt_index = kzalloc(utt->hub->maxchild * 134 sizeof(*tt_index), GFP_ATOMIC); 135 if (!tt_index) 136 return ERR_PTR(-ENOMEM); 137 utt->hcpriv = tt_index; 138 allocated_index = true; 139 } 140 port = udev->ttport - 1; 141 ptt = &tt_index[port]; 142 } else { 143 port = 0; 144 ptt = (struct ehci_tt **) &utt->hcpriv; 145 } 146 147 tt = *ptt; 148 if (!tt) { /* Create the ehci_tt */ 149 struct ehci_hcd *ehci = 150 hcd_to_ehci(bus_to_hcd(udev->bus)); 151 152 tt = kzalloc(sizeof(*tt), GFP_ATOMIC); 153 if (!tt) { 154 if (allocated_index) { 155 utt->hcpriv = NULL; 156 kfree(tt_index); 157 } 158 return ERR_PTR(-ENOMEM); 159 } 160 list_add_tail(&tt->tt_list, &ehci->tt_list); 161 INIT_LIST_HEAD(&tt->ps_list); 162 tt->usb_tt = utt; 163 tt->tt_port = port; 164 *ptt = tt; 165 } 166 167 return tt; 168 } 169 170 /* Release the TT above udev, if it's not in use */ 171 static void drop_tt(struct usb_device *udev) 172 { 173 struct usb_tt *utt = udev->tt; 174 struct ehci_tt *tt, **tt_index, **ptt; 175 int cnt, i; 176 177 if (!utt || !utt->hcpriv) 178 return; /* Not below a TT, or never allocated */ 179 180 cnt = 0; 181 if (utt->multi) { 182 tt_index = utt->hcpriv; 183 ptt = &tt_index[udev->ttport - 1]; 184 185 /* How many entries are left in tt_index? */ 186 for (i = 0; i < utt->hub->maxchild; ++i) 187 cnt += !!tt_index[i]; 188 } else { 189 tt_index = NULL; 190 ptt = (struct ehci_tt **) &utt->hcpriv; 191 } 192 193 tt = *ptt; 194 if (!tt || !list_empty(&tt->ps_list)) 195 return; /* never allocated, or still in use */ 196 197 list_del(&tt->tt_list); 198 *ptt = NULL; 199 kfree(tt); 200 if (cnt == 1) { 201 utt->hcpriv = NULL; 202 kfree(tt_index); 203 } 204 } 205 206 static void bandwidth_dbg(struct ehci_hcd *ehci, int sign, char *type, 207 struct ehci_per_sched *ps) 208 { 209 dev_dbg(&ps->udev->dev, 210 "ep %02x: %s %s @ %u+%u (%u.%u+%u) [%u/%u us] mask %04x\n", 211 ps->ep->desc.bEndpointAddress, 212 (sign >= 0 ? "reserve" : "release"), type, 213 (ps->bw_phase << 3) + ps->phase_uf, ps->bw_uperiod, 214 ps->phase, ps->phase_uf, ps->period, 215 ps->usecs, ps->c_usecs, ps->cs_mask); 216 } 217 218 static void reserve_release_intr_bandwidth(struct ehci_hcd *ehci, 219 struct ehci_qh *qh, int sign) 220 { 221 unsigned start_uf; 222 unsigned i, j, m; 223 int usecs = qh->ps.usecs; 224 int c_usecs = qh->ps.c_usecs; 225 int tt_usecs = qh->ps.tt_usecs; 226 struct ehci_tt *tt; 227 228 if (qh->ps.phase == NO_FRAME) /* Bandwidth wasn't reserved */ 229 return; 230 start_uf = qh->ps.bw_phase << 3; 231 232 bandwidth_dbg(ehci, sign, "intr", &qh->ps); 233 234 if (sign < 0) { /* Release bandwidth */ 235 usecs = -usecs; 236 c_usecs = -c_usecs; 237 tt_usecs = -tt_usecs; 238 } 239 240 /* Entire transaction (high speed) or start-split (full/low speed) */ 241 for (i = start_uf + qh->ps.phase_uf; i < EHCI_BANDWIDTH_SIZE; 242 i += qh->ps.bw_uperiod) 243 ehci->bandwidth[i] += usecs; 244 245 /* Complete-split (full/low speed) */ 246 if (qh->ps.c_usecs) { 247 /* NOTE: adjustments needed for FSTN */ 248 for (i = start_uf; i < EHCI_BANDWIDTH_SIZE; 249 i += qh->ps.bw_uperiod) { 250 for ((j = 2, m = 1 << (j+8)); j < 8; (++j, m <<= 1)) { 251 if (qh->ps.cs_mask & m) 252 ehci->bandwidth[i+j] += c_usecs; 253 } 254 } 255 } 256 257 /* FS/LS bus bandwidth */ 258 if (tt_usecs) { 259 tt = find_tt(qh->ps.udev); 260 if (sign > 0) 261 list_add_tail(&qh->ps.ps_list, &tt->ps_list); 262 else 263 list_del(&qh->ps.ps_list); 264 265 for (i = start_uf >> 3; i < EHCI_BANDWIDTH_FRAMES; 266 i += qh->ps.bw_period) 267 tt->bandwidth[i] += tt_usecs; 268 } 269 } 270 271 /*-------------------------------------------------------------------------*/ 272 273 static void compute_tt_budget(u8 budget_table[EHCI_BANDWIDTH_SIZE], 274 struct ehci_tt *tt) 275 { 276 struct ehci_per_sched *ps; 277 unsigned uframe, uf, x; 278 u8 *budget_line; 279 280 if (!tt) 281 return; 282 memset(budget_table, 0, EHCI_BANDWIDTH_SIZE); 283 284 /* Add up the contributions from all the endpoints using this TT */ 285 list_for_each_entry(ps, &tt->ps_list, ps_list) { 286 for (uframe = ps->bw_phase << 3; uframe < EHCI_BANDWIDTH_SIZE; 287 uframe += ps->bw_uperiod) { 288 budget_line = &budget_table[uframe]; 289 x = ps->tt_usecs; 290 291 /* propagate the time forward */ 292 for (uf = ps->phase_uf; uf < 8; ++uf) { 293 x += budget_line[uf]; 294 295 /* Each microframe lasts 125 us */ 296 if (x <= 125) { 297 budget_line[uf] = x; 298 break; 299 } else { 300 budget_line[uf] = 125; 301 x -= 125; 302 } 303 } 304 } 305 } 306 } 307 308 static int __maybe_unused same_tt(struct usb_device *dev1, 309 struct usb_device *dev2) 310 { 311 if (!dev1->tt || !dev2->tt) 312 return 0; 313 if (dev1->tt != dev2->tt) 314 return 0; 315 if (dev1->tt->multi) 316 return dev1->ttport == dev2->ttport; 317 else 318 return 1; 319 } 320 321 #ifdef CONFIG_USB_EHCI_TT_NEWSCHED 322 323 /* Which uframe does the low/fullspeed transfer start in? 324 * 325 * The parameter is the mask of ssplits in "H-frame" terms 326 * and this returns the transfer start uframe in "B-frame" terms, 327 * which allows both to match, e.g. a ssplit in "H-frame" uframe 0 328 * will cause a transfer in "B-frame" uframe 0. "B-frames" lag 329 * "H-frames" by 1 uframe. See the EHCI spec sec 4.5 and figure 4.7. 330 */ 331 static inline unsigned char tt_start_uframe(struct ehci_hcd *ehci, __hc32 mask) 332 { 333 unsigned char smask = hc32_to_cpu(ehci, mask) & QH_SMASK; 334 if (!smask) { 335 ehci_err(ehci, "invalid empty smask!\n"); 336 /* uframe 7 can't have bw so this will indicate failure */ 337 return 7; 338 } 339 return ffs(smask) - 1; 340 } 341 342 static const unsigned char 343 max_tt_usecs[] = { 125, 125, 125, 125, 125, 125, 30, 0 }; 344 345 /* carryover low/fullspeed bandwidth that crosses uframe boundries */ 346 static inline void carryover_tt_bandwidth(unsigned short tt_usecs[8]) 347 { 348 int i; 349 for (i = 0; i < 7; i++) { 350 if (max_tt_usecs[i] < tt_usecs[i]) { 351 tt_usecs[i+1] += tt_usecs[i] - max_tt_usecs[i]; 352 tt_usecs[i] = max_tt_usecs[i]; 353 } 354 } 355 } 356 357 /* 358 * Return true if the device's tt's downstream bus is available for a 359 * periodic transfer of the specified length (usecs), starting at the 360 * specified frame/uframe. Note that (as summarized in section 11.19 361 * of the usb 2.0 spec) TTs can buffer multiple transactions for each 362 * uframe. 363 * 364 * The uframe parameter is when the fullspeed/lowspeed transfer 365 * should be executed in "B-frame" terms, which is the same as the 366 * highspeed ssplit's uframe (which is in "H-frame" terms). For example 367 * a ssplit in "H-frame" 0 causes a transfer in "B-frame" 0. 368 * See the EHCI spec sec 4.5 and fig 4.7. 369 * 370 * This checks if the full/lowspeed bus, at the specified starting uframe, 371 * has the specified bandwidth available, according to rules listed 372 * in USB 2.0 spec section 11.18.1 fig 11-60. 373 * 374 * This does not check if the transfer would exceed the max ssplit 375 * limit of 16, specified in USB 2.0 spec section 11.18.4 requirement #4, 376 * since proper scheduling limits ssplits to less than 16 per uframe. 377 */ 378 static int tt_available( 379 struct ehci_hcd *ehci, 380 struct ehci_per_sched *ps, 381 struct ehci_tt *tt, 382 unsigned frame, 383 unsigned uframe 384 ) 385 { 386 unsigned period = ps->bw_period; 387 unsigned usecs = ps->tt_usecs; 388 389 if ((period == 0) || (uframe >= 7)) /* error */ 390 return 0; 391 392 for (frame &= period - 1; frame < EHCI_BANDWIDTH_FRAMES; 393 frame += period) { 394 unsigned i, uf; 395 unsigned short tt_usecs[8]; 396 397 if (tt->bandwidth[frame] + usecs > 900) 398 return 0; 399 400 uf = frame << 3; 401 for (i = 0; i < 8; (++i, ++uf)) 402 tt_usecs[i] = ehci->tt_budget[uf]; 403 404 if (max_tt_usecs[uframe] <= tt_usecs[uframe]) 405 return 0; 406 407 /* special case for isoc transfers larger than 125us: 408 * the first and each subsequent fully used uframe 409 * must be empty, so as to not illegally delay 410 * already scheduled transactions 411 */ 412 if (usecs > 125) { 413 int ufs = (usecs / 125); 414 415 for (i = uframe; i < (uframe + ufs) && i < 8; i++) 416 if (tt_usecs[i] > 0) 417 return 0; 418 } 419 420 tt_usecs[uframe] += usecs; 421 422 carryover_tt_bandwidth(tt_usecs); 423 424 /* fail if the carryover pushed bw past the last uframe's limit */ 425 if (max_tt_usecs[7] < tt_usecs[7]) 426 return 0; 427 } 428 429 return 1; 430 } 431 432 #else 433 434 /* return true iff the device's transaction translator is available 435 * for a periodic transfer starting at the specified frame, using 436 * all the uframes in the mask. 437 */ 438 static int tt_no_collision( 439 struct ehci_hcd *ehci, 440 unsigned period, 441 struct usb_device *dev, 442 unsigned frame, 443 u32 uf_mask 444 ) 445 { 446 if (period == 0) /* error */ 447 return 0; 448 449 /* note bandwidth wastage: split never follows csplit 450 * (different dev or endpoint) until the next uframe. 451 * calling convention doesn't make that distinction. 452 */ 453 for (; frame < ehci->periodic_size; frame += period) { 454 union ehci_shadow here; 455 __hc32 type; 456 struct ehci_qh_hw *hw; 457 458 here = ehci->pshadow[frame]; 459 type = Q_NEXT_TYPE(ehci, ehci->periodic[frame]); 460 while (here.ptr) { 461 switch (hc32_to_cpu(ehci, type)) { 462 case Q_TYPE_ITD: 463 type = Q_NEXT_TYPE(ehci, here.itd->hw_next); 464 here = here.itd->itd_next; 465 continue; 466 case Q_TYPE_QH: 467 hw = here.qh->hw; 468 if (same_tt(dev, here.qh->ps.udev)) { 469 u32 mask; 470 471 mask = hc32_to_cpu(ehci, 472 hw->hw_info2); 473 /* "knows" no gap is needed */ 474 mask |= mask >> 8; 475 if (mask & uf_mask) 476 break; 477 } 478 type = Q_NEXT_TYPE(ehci, hw->hw_next); 479 here = here.qh->qh_next; 480 continue; 481 case Q_TYPE_SITD: 482 if (same_tt(dev, here.sitd->urb->dev)) { 483 u16 mask; 484 485 mask = hc32_to_cpu(ehci, here.sitd 486 ->hw_uframe); 487 /* FIXME assumes no gap for IN! */ 488 mask |= mask >> 8; 489 if (mask & uf_mask) 490 break; 491 } 492 type = Q_NEXT_TYPE(ehci, here.sitd->hw_next); 493 here = here.sitd->sitd_next; 494 continue; 495 // case Q_TYPE_FSTN: 496 default: 497 ehci_dbg(ehci, 498 "periodic frame %d bogus type %d\n", 499 frame, type); 500 } 501 502 /* collision or error */ 503 return 0; 504 } 505 } 506 507 /* no collision */ 508 return 1; 509 } 510 511 #endif /* CONFIG_USB_EHCI_TT_NEWSCHED */ 512 513 /*-------------------------------------------------------------------------*/ 514 515 static void enable_periodic(struct ehci_hcd *ehci) 516 { 517 if (ehci->periodic_count++) 518 return; 519 520 /* Stop waiting to turn off the periodic schedule */ 521 ehci->enabled_hrtimer_events &= ~BIT(EHCI_HRTIMER_DISABLE_PERIODIC); 522 523 /* Don't start the schedule until PSS is 0 */ 524 ehci_poll_PSS(ehci); 525 turn_on_io_watchdog(ehci); 526 } 527 528 static void disable_periodic(struct ehci_hcd *ehci) 529 { 530 if (--ehci->periodic_count) 531 return; 532 533 /* Don't turn off the schedule until PSS is 1 */ 534 ehci_poll_PSS(ehci); 535 } 536 537 /*-------------------------------------------------------------------------*/ 538 539 /* periodic schedule slots have iso tds (normal or split) first, then a 540 * sparse tree for active interrupt transfers. 541 * 542 * this just links in a qh; caller guarantees uframe masks are set right. 543 * no FSTN support (yet; ehci 0.96+) 544 */ 545 static void qh_link_periodic(struct ehci_hcd *ehci, struct ehci_qh *qh) 546 { 547 unsigned i; 548 unsigned period = qh->ps.period; 549 550 dev_dbg(&qh->ps.udev->dev, 551 "link qh%d-%04x/%p start %d [%d/%d us]\n", 552 period, hc32_to_cpup(ehci, &qh->hw->hw_info2) 553 & (QH_CMASK | QH_SMASK), 554 qh, qh->ps.phase, qh->ps.usecs, qh->ps.c_usecs); 555 556 /* high bandwidth, or otherwise every microframe */ 557 if (period == 0) 558 period = 1; 559 560 for (i = qh->ps.phase; i < ehci->periodic_size; i += period) { 561 union ehci_shadow *prev = &ehci->pshadow[i]; 562 __hc32 *hw_p = &ehci->periodic[i]; 563 union ehci_shadow here = *prev; 564 __hc32 type = 0; 565 566 /* skip the iso nodes at list head */ 567 while (here.ptr) { 568 type = Q_NEXT_TYPE(ehci, *hw_p); 569 if (type == cpu_to_hc32(ehci, Q_TYPE_QH)) 570 break; 571 prev = periodic_next_shadow(ehci, prev, type); 572 hw_p = shadow_next_periodic(ehci, &here, type); 573 here = *prev; 574 } 575 576 /* sorting each branch by period (slow-->fast) 577 * enables sharing interior tree nodes 578 */ 579 while (here.ptr && qh != here.qh) { 580 if (qh->ps.period > here.qh->ps.period) 581 break; 582 prev = &here.qh->qh_next; 583 hw_p = &here.qh->hw->hw_next; 584 here = *prev; 585 } 586 /* link in this qh, unless some earlier pass did that */ 587 if (qh != here.qh) { 588 qh->qh_next = here; 589 if (here.qh) 590 qh->hw->hw_next = *hw_p; 591 wmb(); 592 prev->qh = qh; 593 *hw_p = QH_NEXT(ehci, qh->qh_dma); 594 } 595 } 596 qh->qh_state = QH_STATE_LINKED; 597 qh->xacterrs = 0; 598 qh->unlink_reason = 0; 599 600 /* update per-qh bandwidth for debugfs */ 601 ehci_to_hcd(ehci)->self.bandwidth_allocated += qh->ps.bw_period 602 ? ((qh->ps.usecs + qh->ps.c_usecs) / qh->ps.bw_period) 603 : (qh->ps.usecs * 8); 604 605 list_add(&qh->intr_node, &ehci->intr_qh_list); 606 607 /* maybe enable periodic schedule processing */ 608 ++ehci->intr_count; 609 enable_periodic(ehci); 610 } 611 612 static void qh_unlink_periodic(struct ehci_hcd *ehci, struct ehci_qh *qh) 613 { 614 unsigned i; 615 unsigned period; 616 617 /* 618 * If qh is for a low/full-speed device, simply unlinking it 619 * could interfere with an ongoing split transaction. To unlink 620 * it safely would require setting the QH_INACTIVATE bit and 621 * waiting at least one frame, as described in EHCI 4.12.2.5. 622 * 623 * We won't bother with any of this. Instead, we assume that the 624 * only reason for unlinking an interrupt QH while the current URB 625 * is still active is to dequeue all the URBs (flush the whole 626 * endpoint queue). 627 * 628 * If rebalancing the periodic schedule is ever implemented, this 629 * approach will no longer be valid. 630 */ 631 632 /* high bandwidth, or otherwise part of every microframe */ 633 period = qh->ps.period ? : 1; 634 635 for (i = qh->ps.phase; i < ehci->periodic_size; i += period) 636 periodic_unlink(ehci, i, qh); 637 638 /* update per-qh bandwidth for debugfs */ 639 ehci_to_hcd(ehci)->self.bandwidth_allocated -= qh->ps.bw_period 640 ? ((qh->ps.usecs + qh->ps.c_usecs) / qh->ps.bw_period) 641 : (qh->ps.usecs * 8); 642 643 dev_dbg(&qh->ps.udev->dev, 644 "unlink qh%d-%04x/%p start %d [%d/%d us]\n", 645 qh->ps.period, 646 hc32_to_cpup(ehci, &qh->hw->hw_info2) & (QH_CMASK | QH_SMASK), 647 qh, qh->ps.phase, qh->ps.usecs, qh->ps.c_usecs); 648 649 /* qh->qh_next still "live" to HC */ 650 qh->qh_state = QH_STATE_UNLINK; 651 qh->qh_next.ptr = NULL; 652 653 if (ehci->qh_scan_next == qh) 654 ehci->qh_scan_next = list_entry(qh->intr_node.next, 655 struct ehci_qh, intr_node); 656 list_del(&qh->intr_node); 657 } 658 659 static void cancel_unlink_wait_intr(struct ehci_hcd *ehci, struct ehci_qh *qh) 660 { 661 if (qh->qh_state != QH_STATE_LINKED || 662 list_empty(&qh->unlink_node)) 663 return; 664 665 list_del_init(&qh->unlink_node); 666 667 /* 668 * TODO: disable the event of EHCI_HRTIMER_START_UNLINK_INTR for 669 * avoiding unnecessary CPU wakeup 670 */ 671 } 672 673 static void start_unlink_intr(struct ehci_hcd *ehci, struct ehci_qh *qh) 674 { 675 /* If the QH isn't linked then there's nothing we can do. */ 676 if (qh->qh_state != QH_STATE_LINKED) 677 return; 678 679 /* if the qh is waiting for unlink, cancel it now */ 680 cancel_unlink_wait_intr(ehci, qh); 681 682 qh_unlink_periodic(ehci, qh); 683 684 /* Make sure the unlinks are visible before starting the timer */ 685 wmb(); 686 687 /* 688 * The EHCI spec doesn't say how long it takes the controller to 689 * stop accessing an unlinked interrupt QH. The timer delay is 690 * 9 uframes; presumably that will be long enough. 691 */ 692 qh->unlink_cycle = ehci->intr_unlink_cycle; 693 694 /* New entries go at the end of the intr_unlink list */ 695 list_add_tail(&qh->unlink_node, &ehci->intr_unlink); 696 697 if (ehci->intr_unlinking) 698 ; /* Avoid recursive calls */ 699 else if (ehci->rh_state < EHCI_RH_RUNNING) 700 ehci_handle_intr_unlinks(ehci); 701 else if (ehci->intr_unlink.next == &qh->unlink_node) { 702 ehci_enable_event(ehci, EHCI_HRTIMER_UNLINK_INTR, true); 703 ++ehci->intr_unlink_cycle; 704 } 705 } 706 707 /* 708 * It is common only one intr URB is scheduled on one qh, and 709 * given complete() is run in tasklet context, introduce a bit 710 * delay to avoid unlink qh too early. 711 */ 712 static void start_unlink_intr_wait(struct ehci_hcd *ehci, 713 struct ehci_qh *qh) 714 { 715 qh->unlink_cycle = ehci->intr_unlink_wait_cycle; 716 717 /* New entries go at the end of the intr_unlink_wait list */ 718 list_add_tail(&qh->unlink_node, &ehci->intr_unlink_wait); 719 720 if (ehci->rh_state < EHCI_RH_RUNNING) 721 ehci_handle_start_intr_unlinks(ehci); 722 else if (ehci->intr_unlink_wait.next == &qh->unlink_node) { 723 ehci_enable_event(ehci, EHCI_HRTIMER_START_UNLINK_INTR, true); 724 ++ehci->intr_unlink_wait_cycle; 725 } 726 } 727 728 static void end_unlink_intr(struct ehci_hcd *ehci, struct ehci_qh *qh) 729 { 730 struct ehci_qh_hw *hw = qh->hw; 731 int rc; 732 733 qh->qh_state = QH_STATE_IDLE; 734 hw->hw_next = EHCI_LIST_END(ehci); 735 736 if (!list_empty(&qh->qtd_list)) 737 qh_completions(ehci, qh); 738 739 /* reschedule QH iff another request is queued */ 740 if (!list_empty(&qh->qtd_list) && ehci->rh_state == EHCI_RH_RUNNING) { 741 rc = qh_schedule(ehci, qh); 742 if (rc == 0) { 743 qh_refresh(ehci, qh); 744 qh_link_periodic(ehci, qh); 745 } 746 747 /* An error here likely indicates handshake failure 748 * or no space left in the schedule. Neither fault 749 * should happen often ... 750 * 751 * FIXME kill the now-dysfunctional queued urbs 752 */ 753 else { 754 ehci_err(ehci, "can't reschedule qh %p, err %d\n", 755 qh, rc); 756 } 757 } 758 759 /* maybe turn off periodic schedule */ 760 --ehci->intr_count; 761 disable_periodic(ehci); 762 } 763 764 /*-------------------------------------------------------------------------*/ 765 766 static int check_period( 767 struct ehci_hcd *ehci, 768 unsigned frame, 769 unsigned uframe, 770 unsigned uperiod, 771 unsigned usecs 772 ) { 773 /* complete split running into next frame? 774 * given FSTN support, we could sometimes check... 775 */ 776 if (uframe >= 8) 777 return 0; 778 779 /* convert "usecs we need" to "max already claimed" */ 780 usecs = ehci->uframe_periodic_max - usecs; 781 782 for (uframe += frame << 3; uframe < EHCI_BANDWIDTH_SIZE; 783 uframe += uperiod) { 784 if (ehci->bandwidth[uframe] > usecs) 785 return 0; 786 } 787 788 // success! 789 return 1; 790 } 791 792 static int check_intr_schedule( 793 struct ehci_hcd *ehci, 794 unsigned frame, 795 unsigned uframe, 796 struct ehci_qh *qh, 797 unsigned *c_maskp, 798 struct ehci_tt *tt 799 ) 800 { 801 int retval = -ENOSPC; 802 u8 mask = 0; 803 804 if (qh->ps.c_usecs && uframe >= 6) /* FSTN territory? */ 805 goto done; 806 807 if (!check_period(ehci, frame, uframe, qh->ps.bw_uperiod, qh->ps.usecs)) 808 goto done; 809 if (!qh->ps.c_usecs) { 810 retval = 0; 811 *c_maskp = 0; 812 goto done; 813 } 814 815 #ifdef CONFIG_USB_EHCI_TT_NEWSCHED 816 if (tt_available(ehci, &qh->ps, tt, frame, uframe)) { 817 unsigned i; 818 819 /* TODO : this may need FSTN for SSPLIT in uframe 5. */ 820 for (i = uframe+2; i < 8 && i <= uframe+4; i++) 821 if (!check_period(ehci, frame, i, 822 qh->ps.bw_uperiod, qh->ps.c_usecs)) 823 goto done; 824 else 825 mask |= 1 << i; 826 827 retval = 0; 828 829 *c_maskp = mask; 830 } 831 #else 832 /* Make sure this tt's buffer is also available for CSPLITs. 833 * We pessimize a bit; probably the typical full speed case 834 * doesn't need the second CSPLIT. 835 * 836 * NOTE: both SPLIT and CSPLIT could be checked in just 837 * one smart pass... 838 */ 839 mask = 0x03 << (uframe + qh->gap_uf); 840 *c_maskp = mask; 841 842 mask |= 1 << uframe; 843 if (tt_no_collision(ehci, qh->ps.bw_period, qh->ps.udev, frame, mask)) { 844 if (!check_period(ehci, frame, uframe + qh->gap_uf + 1, 845 qh->ps.bw_uperiod, qh->ps.c_usecs)) 846 goto done; 847 if (!check_period(ehci, frame, uframe + qh->gap_uf, 848 qh->ps.bw_uperiod, qh->ps.c_usecs)) 849 goto done; 850 retval = 0; 851 } 852 #endif 853 done: 854 return retval; 855 } 856 857 /* "first fit" scheduling policy used the first time through, 858 * or when the previous schedule slot can't be re-used. 859 */ 860 static int qh_schedule(struct ehci_hcd *ehci, struct ehci_qh *qh) 861 { 862 int status = 0; 863 unsigned uframe; 864 unsigned c_mask; 865 struct ehci_qh_hw *hw = qh->hw; 866 struct ehci_tt *tt; 867 868 hw->hw_next = EHCI_LIST_END(ehci); 869 870 /* reuse the previous schedule slots, if we can */ 871 if (qh->ps.phase != NO_FRAME) { 872 ehci_dbg(ehci, "reused qh %p schedule\n", qh); 873 return 0; 874 } 875 876 uframe = 0; 877 c_mask = 0; 878 tt = find_tt(qh->ps.udev); 879 if (IS_ERR(tt)) { 880 status = PTR_ERR(tt); 881 goto done; 882 } 883 compute_tt_budget(ehci->tt_budget, tt); 884 885 /* else scan the schedule to find a group of slots such that all 886 * uframes have enough periodic bandwidth available. 887 */ 888 /* "normal" case, uframing flexible except with splits */ 889 if (qh->ps.bw_period) { 890 int i; 891 unsigned frame; 892 893 for (i = qh->ps.bw_period; i > 0; --i) { 894 frame = ++ehci->random_frame & (qh->ps.bw_period - 1); 895 for (uframe = 0; uframe < 8; uframe++) { 896 status = check_intr_schedule(ehci, 897 frame, uframe, qh, &c_mask, tt); 898 if (status == 0) 899 goto got_it; 900 } 901 } 902 903 /* qh->ps.bw_period == 0 means every uframe */ 904 } else { 905 status = check_intr_schedule(ehci, 0, 0, qh, &c_mask, tt); 906 } 907 if (status) 908 goto done; 909 910 got_it: 911 qh->ps.phase = (qh->ps.period ? ehci->random_frame & 912 (qh->ps.period - 1) : 0); 913 qh->ps.bw_phase = qh->ps.phase & (qh->ps.bw_period - 1); 914 qh->ps.phase_uf = uframe; 915 qh->ps.cs_mask = qh->ps.period ? 916 (c_mask << 8) | (1 << uframe) : 917 QH_SMASK; 918 919 /* reset S-frame and (maybe) C-frame masks */ 920 hw->hw_info2 &= cpu_to_hc32(ehci, ~(QH_CMASK | QH_SMASK)); 921 hw->hw_info2 |= cpu_to_hc32(ehci, qh->ps.cs_mask); 922 reserve_release_intr_bandwidth(ehci, qh, 1); 923 924 done: 925 return status; 926 } 927 928 static int intr_submit( 929 struct ehci_hcd *ehci, 930 struct urb *urb, 931 struct list_head *qtd_list, 932 gfp_t mem_flags 933 ) { 934 unsigned epnum; 935 unsigned long flags; 936 struct ehci_qh *qh; 937 int status; 938 struct list_head empty; 939 940 /* get endpoint and transfer/schedule data */ 941 epnum = urb->ep->desc.bEndpointAddress; 942 943 spin_lock_irqsave(&ehci->lock, flags); 944 945 if (unlikely(!HCD_HW_ACCESSIBLE(ehci_to_hcd(ehci)))) { 946 status = -ESHUTDOWN; 947 goto done_not_linked; 948 } 949 status = usb_hcd_link_urb_to_ep(ehci_to_hcd(ehci), urb); 950 if (unlikely(status)) 951 goto done_not_linked; 952 953 /* get qh and force any scheduling errors */ 954 INIT_LIST_HEAD(&empty); 955 qh = qh_append_tds(ehci, urb, &empty, epnum, &urb->ep->hcpriv); 956 if (qh == NULL) { 957 status = -ENOMEM; 958 goto done; 959 } 960 if (qh->qh_state == QH_STATE_IDLE) { 961 status = qh_schedule(ehci, qh); 962 if (status) 963 goto done; 964 } 965 966 /* then queue the urb's tds to the qh */ 967 qh = qh_append_tds(ehci, urb, qtd_list, epnum, &urb->ep->hcpriv); 968 BUG_ON(qh == NULL); 969 970 /* stuff into the periodic schedule */ 971 if (qh->qh_state == QH_STATE_IDLE) { 972 qh_refresh(ehci, qh); 973 qh_link_periodic(ehci, qh); 974 } else { 975 /* cancel unlink wait for the qh */ 976 cancel_unlink_wait_intr(ehci, qh); 977 } 978 979 /* ... update usbfs periodic stats */ 980 ehci_to_hcd(ehci)->self.bandwidth_int_reqs++; 981 982 done: 983 if (unlikely(status)) 984 usb_hcd_unlink_urb_from_ep(ehci_to_hcd(ehci), urb); 985 done_not_linked: 986 spin_unlock_irqrestore(&ehci->lock, flags); 987 if (status) 988 qtd_list_free(ehci, urb, qtd_list); 989 990 return status; 991 } 992 993 static void scan_intr(struct ehci_hcd *ehci) 994 { 995 struct ehci_qh *qh; 996 997 list_for_each_entry_safe(qh, ehci->qh_scan_next, &ehci->intr_qh_list, 998 intr_node) { 999 1000 /* clean any finished work for this qh */ 1001 if (!list_empty(&qh->qtd_list)) { 1002 int temp; 1003 1004 /* 1005 * Unlinks could happen here; completion reporting 1006 * drops the lock. That's why ehci->qh_scan_next 1007 * always holds the next qh to scan; if the next qh 1008 * gets unlinked then ehci->qh_scan_next is adjusted 1009 * in qh_unlink_periodic(). 1010 */ 1011 temp = qh_completions(ehci, qh); 1012 if (unlikely(temp)) 1013 start_unlink_intr(ehci, qh); 1014 else if (unlikely(list_empty(&qh->qtd_list) && 1015 qh->qh_state == QH_STATE_LINKED)) 1016 start_unlink_intr_wait(ehci, qh); 1017 } 1018 } 1019 } 1020 1021 /*-------------------------------------------------------------------------*/ 1022 1023 /* ehci_iso_stream ops work with both ITD and SITD */ 1024 1025 static struct ehci_iso_stream * 1026 iso_stream_alloc(gfp_t mem_flags) 1027 { 1028 struct ehci_iso_stream *stream; 1029 1030 stream = kzalloc(sizeof *stream, mem_flags); 1031 if (likely(stream != NULL)) { 1032 INIT_LIST_HEAD(&stream->td_list); 1033 INIT_LIST_HEAD(&stream->free_list); 1034 stream->next_uframe = NO_FRAME; 1035 stream->ps.phase = NO_FRAME; 1036 } 1037 return stream; 1038 } 1039 1040 static void 1041 iso_stream_init( 1042 struct ehci_hcd *ehci, 1043 struct ehci_iso_stream *stream, 1044 struct urb *urb 1045 ) 1046 { 1047 static const u8 smask_out[] = { 0x01, 0x03, 0x07, 0x0f, 0x1f, 0x3f }; 1048 1049 struct usb_device *dev = urb->dev; 1050 u32 buf1; 1051 unsigned epnum, maxp; 1052 int is_input; 1053 unsigned tmp; 1054 1055 /* 1056 * this might be a "high bandwidth" highspeed endpoint, 1057 * as encoded in the ep descriptor's wMaxPacket field 1058 */ 1059 epnum = usb_pipeendpoint(urb->pipe); 1060 is_input = usb_pipein(urb->pipe) ? USB_DIR_IN : 0; 1061 maxp = usb_endpoint_maxp(&urb->ep->desc); 1062 if (is_input) { 1063 buf1 = (1 << 11); 1064 } else { 1065 buf1 = 0; 1066 } 1067 1068 /* knows about ITD vs SITD */ 1069 if (dev->speed == USB_SPEED_HIGH) { 1070 unsigned multi = hb_mult(maxp); 1071 1072 stream->highspeed = 1; 1073 1074 maxp = max_packet(maxp); 1075 buf1 |= maxp; 1076 maxp *= multi; 1077 1078 stream->buf0 = cpu_to_hc32(ehci, (epnum << 8) | dev->devnum); 1079 stream->buf1 = cpu_to_hc32(ehci, buf1); 1080 stream->buf2 = cpu_to_hc32(ehci, multi); 1081 1082 /* usbfs wants to report the average usecs per frame tied up 1083 * when transfers on this endpoint are scheduled ... 1084 */ 1085 stream->ps.usecs = HS_USECS_ISO(maxp); 1086 1087 /* period for bandwidth allocation */ 1088 tmp = min_t(unsigned, EHCI_BANDWIDTH_SIZE, 1089 1 << (urb->ep->desc.bInterval - 1)); 1090 1091 /* Allow urb->interval to override */ 1092 stream->ps.bw_uperiod = min_t(unsigned, tmp, urb->interval); 1093 1094 stream->uperiod = urb->interval; 1095 stream->ps.period = urb->interval >> 3; 1096 stream->bandwidth = stream->ps.usecs * 8 / 1097 stream->ps.bw_uperiod; 1098 1099 } else { 1100 u32 addr; 1101 int think_time; 1102 int hs_transfers; 1103 1104 addr = dev->ttport << 24; 1105 if (!ehci_is_TDI(ehci) 1106 || (dev->tt->hub != 1107 ehci_to_hcd(ehci)->self.root_hub)) 1108 addr |= dev->tt->hub->devnum << 16; 1109 addr |= epnum << 8; 1110 addr |= dev->devnum; 1111 stream->ps.usecs = HS_USECS_ISO(maxp); 1112 think_time = dev->tt ? dev->tt->think_time : 0; 1113 stream->ps.tt_usecs = NS_TO_US(think_time + usb_calc_bus_time( 1114 dev->speed, is_input, 1, maxp)); 1115 hs_transfers = max(1u, (maxp + 187) / 188); 1116 if (is_input) { 1117 u32 tmp; 1118 1119 addr |= 1 << 31; 1120 stream->ps.c_usecs = stream->ps.usecs; 1121 stream->ps.usecs = HS_USECS_ISO(1); 1122 stream->ps.cs_mask = 1; 1123 1124 /* c-mask as specified in USB 2.0 11.18.4 3.c */ 1125 tmp = (1 << (hs_transfers + 2)) - 1; 1126 stream->ps.cs_mask |= tmp << (8 + 2); 1127 } else 1128 stream->ps.cs_mask = smask_out[hs_transfers - 1]; 1129 1130 /* period for bandwidth allocation */ 1131 tmp = min_t(unsigned, EHCI_BANDWIDTH_FRAMES, 1132 1 << (urb->ep->desc.bInterval - 1)); 1133 1134 /* Allow urb->interval to override */ 1135 stream->ps.bw_period = min_t(unsigned, tmp, urb->interval); 1136 stream->ps.bw_uperiod = stream->ps.bw_period << 3; 1137 1138 stream->ps.period = urb->interval; 1139 stream->uperiod = urb->interval << 3; 1140 stream->bandwidth = (stream->ps.usecs + stream->ps.c_usecs) / 1141 stream->ps.bw_period; 1142 1143 /* stream->splits gets created from cs_mask later */ 1144 stream->address = cpu_to_hc32(ehci, addr); 1145 } 1146 1147 stream->ps.udev = dev; 1148 stream->ps.ep = urb->ep; 1149 1150 stream->bEndpointAddress = is_input | epnum; 1151 stream->maxp = maxp; 1152 } 1153 1154 static struct ehci_iso_stream * 1155 iso_stream_find(struct ehci_hcd *ehci, struct urb *urb) 1156 { 1157 unsigned epnum; 1158 struct ehci_iso_stream *stream; 1159 struct usb_host_endpoint *ep; 1160 unsigned long flags; 1161 1162 epnum = usb_pipeendpoint (urb->pipe); 1163 if (usb_pipein(urb->pipe)) 1164 ep = urb->dev->ep_in[epnum]; 1165 else 1166 ep = urb->dev->ep_out[epnum]; 1167 1168 spin_lock_irqsave(&ehci->lock, flags); 1169 stream = ep->hcpriv; 1170 1171 if (unlikely(stream == NULL)) { 1172 stream = iso_stream_alloc(GFP_ATOMIC); 1173 if (likely(stream != NULL)) { 1174 ep->hcpriv = stream; 1175 iso_stream_init(ehci, stream, urb); 1176 } 1177 1178 /* if dev->ep [epnum] is a QH, hw is set */ 1179 } else if (unlikely(stream->hw != NULL)) { 1180 ehci_dbg(ehci, "dev %s ep%d%s, not iso??\n", 1181 urb->dev->devpath, epnum, 1182 usb_pipein(urb->pipe) ? "in" : "out"); 1183 stream = NULL; 1184 } 1185 1186 spin_unlock_irqrestore(&ehci->lock, flags); 1187 return stream; 1188 } 1189 1190 /*-------------------------------------------------------------------------*/ 1191 1192 /* ehci_iso_sched ops can be ITD-only or SITD-only */ 1193 1194 static struct ehci_iso_sched * 1195 iso_sched_alloc(unsigned packets, gfp_t mem_flags) 1196 { 1197 struct ehci_iso_sched *iso_sched; 1198 int size = sizeof *iso_sched; 1199 1200 size += packets * sizeof(struct ehci_iso_packet); 1201 iso_sched = kzalloc(size, mem_flags); 1202 if (likely(iso_sched != NULL)) 1203 INIT_LIST_HEAD(&iso_sched->td_list); 1204 1205 return iso_sched; 1206 } 1207 1208 static inline void 1209 itd_sched_init( 1210 struct ehci_hcd *ehci, 1211 struct ehci_iso_sched *iso_sched, 1212 struct ehci_iso_stream *stream, 1213 struct urb *urb 1214 ) 1215 { 1216 unsigned i; 1217 dma_addr_t dma = urb->transfer_dma; 1218 1219 /* how many uframes are needed for these transfers */ 1220 iso_sched->span = urb->number_of_packets * stream->uperiod; 1221 1222 /* figure out per-uframe itd fields that we'll need later 1223 * when we fit new itds into the schedule. 1224 */ 1225 for (i = 0; i < urb->number_of_packets; i++) { 1226 struct ehci_iso_packet *uframe = &iso_sched->packet[i]; 1227 unsigned length; 1228 dma_addr_t buf; 1229 u32 trans; 1230 1231 length = urb->iso_frame_desc[i].length; 1232 buf = dma + urb->iso_frame_desc[i].offset; 1233 1234 trans = EHCI_ISOC_ACTIVE; 1235 trans |= buf & 0x0fff; 1236 if (unlikely(((i + 1) == urb->number_of_packets)) 1237 && !(urb->transfer_flags & URB_NO_INTERRUPT)) 1238 trans |= EHCI_ITD_IOC; 1239 trans |= length << 16; 1240 uframe->transaction = cpu_to_hc32(ehci, trans); 1241 1242 /* might need to cross a buffer page within a uframe */ 1243 uframe->bufp = (buf & ~(u64)0x0fff); 1244 buf += length; 1245 if (unlikely((uframe->bufp != (buf & ~(u64)0x0fff)))) 1246 uframe->cross = 1; 1247 } 1248 } 1249 1250 static void 1251 iso_sched_free( 1252 struct ehci_iso_stream *stream, 1253 struct ehci_iso_sched *iso_sched 1254 ) 1255 { 1256 if (!iso_sched) 1257 return; 1258 // caller must hold ehci->lock! 1259 list_splice(&iso_sched->td_list, &stream->free_list); 1260 kfree(iso_sched); 1261 } 1262 1263 static int 1264 itd_urb_transaction( 1265 struct ehci_iso_stream *stream, 1266 struct ehci_hcd *ehci, 1267 struct urb *urb, 1268 gfp_t mem_flags 1269 ) 1270 { 1271 struct ehci_itd *itd; 1272 dma_addr_t itd_dma; 1273 int i; 1274 unsigned num_itds; 1275 struct ehci_iso_sched *sched; 1276 unsigned long flags; 1277 1278 sched = iso_sched_alloc(urb->number_of_packets, mem_flags); 1279 if (unlikely(sched == NULL)) 1280 return -ENOMEM; 1281 1282 itd_sched_init(ehci, sched, stream, urb); 1283 1284 if (urb->interval < 8) 1285 num_itds = 1 + (sched->span + 7) / 8; 1286 else 1287 num_itds = urb->number_of_packets; 1288 1289 /* allocate/init ITDs */ 1290 spin_lock_irqsave(&ehci->lock, flags); 1291 for (i = 0; i < num_itds; i++) { 1292 1293 /* 1294 * Use iTDs from the free list, but not iTDs that may 1295 * still be in use by the hardware. 1296 */ 1297 if (likely(!list_empty(&stream->free_list))) { 1298 itd = list_first_entry(&stream->free_list, 1299 struct ehci_itd, itd_list); 1300 if (itd->frame == ehci->now_frame) 1301 goto alloc_itd; 1302 list_del(&itd->itd_list); 1303 itd_dma = itd->itd_dma; 1304 } else { 1305 alloc_itd: 1306 spin_unlock_irqrestore(&ehci->lock, flags); 1307 itd = dma_pool_alloc(ehci->itd_pool, mem_flags, 1308 &itd_dma); 1309 spin_lock_irqsave(&ehci->lock, flags); 1310 if (!itd) { 1311 iso_sched_free(stream, sched); 1312 spin_unlock_irqrestore(&ehci->lock, flags); 1313 return -ENOMEM; 1314 } 1315 } 1316 1317 memset(itd, 0, sizeof *itd); 1318 itd->itd_dma = itd_dma; 1319 itd->frame = NO_FRAME; 1320 list_add(&itd->itd_list, &sched->td_list); 1321 } 1322 spin_unlock_irqrestore(&ehci->lock, flags); 1323 1324 /* temporarily store schedule info in hcpriv */ 1325 urb->hcpriv = sched; 1326 urb->error_count = 0; 1327 return 0; 1328 } 1329 1330 /*-------------------------------------------------------------------------*/ 1331 1332 static void reserve_release_iso_bandwidth(struct ehci_hcd *ehci, 1333 struct ehci_iso_stream *stream, int sign) 1334 { 1335 unsigned uframe; 1336 unsigned i, j; 1337 unsigned s_mask, c_mask, m; 1338 int usecs = stream->ps.usecs; 1339 int c_usecs = stream->ps.c_usecs; 1340 int tt_usecs = stream->ps.tt_usecs; 1341 struct ehci_tt *tt; 1342 1343 if (stream->ps.phase == NO_FRAME) /* Bandwidth wasn't reserved */ 1344 return; 1345 uframe = stream->ps.bw_phase << 3; 1346 1347 bandwidth_dbg(ehci, sign, "iso", &stream->ps); 1348 1349 if (sign < 0) { /* Release bandwidth */ 1350 usecs = -usecs; 1351 c_usecs = -c_usecs; 1352 tt_usecs = -tt_usecs; 1353 } 1354 1355 if (!stream->splits) { /* High speed */ 1356 for (i = uframe + stream->ps.phase_uf; i < EHCI_BANDWIDTH_SIZE; 1357 i += stream->ps.bw_uperiod) 1358 ehci->bandwidth[i] += usecs; 1359 1360 } else { /* Full speed */ 1361 s_mask = stream->ps.cs_mask; 1362 c_mask = s_mask >> 8; 1363 1364 /* NOTE: adjustment needed for frame overflow */ 1365 for (i = uframe; i < EHCI_BANDWIDTH_SIZE; 1366 i += stream->ps.bw_uperiod) { 1367 for ((j = stream->ps.phase_uf, m = 1 << j); j < 8; 1368 (++j, m <<= 1)) { 1369 if (s_mask & m) 1370 ehci->bandwidth[i+j] += usecs; 1371 else if (c_mask & m) 1372 ehci->bandwidth[i+j] += c_usecs; 1373 } 1374 } 1375 1376 tt = find_tt(stream->ps.udev); 1377 if (sign > 0) 1378 list_add_tail(&stream->ps.ps_list, &tt->ps_list); 1379 else 1380 list_del(&stream->ps.ps_list); 1381 1382 for (i = uframe >> 3; i < EHCI_BANDWIDTH_FRAMES; 1383 i += stream->ps.bw_period) 1384 tt->bandwidth[i] += tt_usecs; 1385 } 1386 } 1387 1388 static inline int 1389 itd_slot_ok( 1390 struct ehci_hcd *ehci, 1391 struct ehci_iso_stream *stream, 1392 unsigned uframe 1393 ) 1394 { 1395 unsigned usecs; 1396 1397 /* convert "usecs we need" to "max already claimed" */ 1398 usecs = ehci->uframe_periodic_max - stream->ps.usecs; 1399 1400 for (uframe &= stream->ps.bw_uperiod - 1; uframe < EHCI_BANDWIDTH_SIZE; 1401 uframe += stream->ps.bw_uperiod) { 1402 if (ehci->bandwidth[uframe] > usecs) 1403 return 0; 1404 } 1405 return 1; 1406 } 1407 1408 static inline int 1409 sitd_slot_ok( 1410 struct ehci_hcd *ehci, 1411 struct ehci_iso_stream *stream, 1412 unsigned uframe, 1413 struct ehci_iso_sched *sched, 1414 struct ehci_tt *tt 1415 ) 1416 { 1417 unsigned mask, tmp; 1418 unsigned frame, uf; 1419 1420 mask = stream->ps.cs_mask << (uframe & 7); 1421 1422 /* for OUT, don't wrap SSPLIT into H-microframe 7 */ 1423 if (((stream->ps.cs_mask & 0xff) << (uframe & 7)) >= (1 << 7)) 1424 return 0; 1425 1426 /* for IN, don't wrap CSPLIT into the next frame */ 1427 if (mask & ~0xffff) 1428 return 0; 1429 1430 /* check bandwidth */ 1431 uframe &= stream->ps.bw_uperiod - 1; 1432 frame = uframe >> 3; 1433 1434 #ifdef CONFIG_USB_EHCI_TT_NEWSCHED 1435 /* The tt's fullspeed bus bandwidth must be available. 1436 * tt_available scheduling guarantees 10+% for control/bulk. 1437 */ 1438 uf = uframe & 7; 1439 if (!tt_available(ehci, &stream->ps, tt, frame, uf)) 1440 return 0; 1441 #else 1442 /* tt must be idle for start(s), any gap, and csplit. 1443 * assume scheduling slop leaves 10+% for control/bulk. 1444 */ 1445 if (!tt_no_collision(ehci, stream->ps.bw_period, 1446 stream->ps.udev, frame, mask)) 1447 return 0; 1448 #endif 1449 1450 do { 1451 unsigned max_used; 1452 unsigned i; 1453 1454 /* check starts (OUT uses more than one) */ 1455 uf = uframe; 1456 max_used = ehci->uframe_periodic_max - stream->ps.usecs; 1457 for (tmp = stream->ps.cs_mask & 0xff; tmp; tmp >>= 1, uf++) { 1458 if (ehci->bandwidth[uf] > max_used) 1459 return 0; 1460 } 1461 1462 /* for IN, check CSPLIT */ 1463 if (stream->ps.c_usecs) { 1464 max_used = ehci->uframe_periodic_max - 1465 stream->ps.c_usecs; 1466 uf = uframe & ~7; 1467 tmp = 1 << (2+8); 1468 for (i = (uframe & 7) + 2; i < 8; (++i, tmp <<= 1)) { 1469 if ((stream->ps.cs_mask & tmp) == 0) 1470 continue; 1471 if (ehci->bandwidth[uf+i] > max_used) 1472 return 0; 1473 } 1474 } 1475 1476 uframe += stream->ps.bw_uperiod; 1477 } while (uframe < EHCI_BANDWIDTH_SIZE); 1478 1479 stream->ps.cs_mask <<= uframe & 7; 1480 stream->splits = cpu_to_hc32(ehci, stream->ps.cs_mask); 1481 return 1; 1482 } 1483 1484 /* 1485 * This scheduler plans almost as far into the future as it has actual 1486 * periodic schedule slots. (Affected by TUNE_FLS, which defaults to 1487 * "as small as possible" to be cache-friendlier.) That limits the size 1488 * transfers you can stream reliably; avoid more than 64 msec per urb. 1489 * Also avoid queue depths of less than ehci's worst irq latency (affected 1490 * by the per-urb URB_NO_INTERRUPT hint, the log2_irq_thresh module parameter, 1491 * and other factors); or more than about 230 msec total (for portability, 1492 * given EHCI_TUNE_FLS and the slop). Or, write a smarter scheduler! 1493 */ 1494 1495 static int 1496 iso_stream_schedule( 1497 struct ehci_hcd *ehci, 1498 struct urb *urb, 1499 struct ehci_iso_stream *stream 1500 ) 1501 { 1502 u32 now, base, next, start, period, span, now2; 1503 u32 wrap = 0, skip = 0; 1504 int status = 0; 1505 unsigned mod = ehci->periodic_size << 3; 1506 struct ehci_iso_sched *sched = urb->hcpriv; 1507 bool empty = list_empty(&stream->td_list); 1508 bool new_stream = false; 1509 1510 period = stream->uperiod; 1511 span = sched->span; 1512 if (!stream->highspeed) 1513 span <<= 3; 1514 1515 /* Start a new isochronous stream? */ 1516 if (unlikely(empty && !hcd_periodic_completion_in_progress( 1517 ehci_to_hcd(ehci), urb->ep))) { 1518 1519 /* Schedule the endpoint */ 1520 if (stream->ps.phase == NO_FRAME) { 1521 int done = 0; 1522 struct ehci_tt *tt = find_tt(stream->ps.udev); 1523 1524 if (IS_ERR(tt)) { 1525 status = PTR_ERR(tt); 1526 goto fail; 1527 } 1528 compute_tt_budget(ehci->tt_budget, tt); 1529 1530 start = ((-(++ehci->random_frame)) << 3) & (period - 1); 1531 1532 /* find a uframe slot with enough bandwidth. 1533 * Early uframes are more precious because full-speed 1534 * iso IN transfers can't use late uframes, 1535 * and therefore they should be allocated last. 1536 */ 1537 next = start; 1538 start += period; 1539 do { 1540 start--; 1541 /* check schedule: enough space? */ 1542 if (stream->highspeed) { 1543 if (itd_slot_ok(ehci, stream, start)) 1544 done = 1; 1545 } else { 1546 if ((start % 8) >= 6) 1547 continue; 1548 if (sitd_slot_ok(ehci, stream, start, 1549 sched, tt)) 1550 done = 1; 1551 } 1552 } while (start > next && !done); 1553 1554 /* no room in the schedule */ 1555 if (!done) { 1556 ehci_dbg(ehci, "iso sched full %p", urb); 1557 status = -ENOSPC; 1558 goto fail; 1559 } 1560 stream->ps.phase = (start >> 3) & 1561 (stream->ps.period - 1); 1562 stream->ps.bw_phase = stream->ps.phase & 1563 (stream->ps.bw_period - 1); 1564 stream->ps.phase_uf = start & 7; 1565 reserve_release_iso_bandwidth(ehci, stream, 1); 1566 } 1567 1568 /* New stream is already scheduled; use the upcoming slot */ 1569 else { 1570 start = (stream->ps.phase << 3) + stream->ps.phase_uf; 1571 } 1572 1573 stream->next_uframe = start; 1574 new_stream = true; 1575 } 1576 1577 now = ehci_read_frame_index(ehci) & (mod - 1); 1578 1579 /* Take the isochronous scheduling threshold into account */ 1580 if (ehci->i_thresh) 1581 next = now + ehci->i_thresh; /* uframe cache */ 1582 else 1583 next = (now + 2 + 7) & ~0x07; /* full frame cache */ 1584 1585 /* If needed, initialize last_iso_frame so that this URB will be seen */ 1586 if (ehci->isoc_count == 0) 1587 ehci->last_iso_frame = now >> 3; 1588 1589 /* 1590 * Use ehci->last_iso_frame as the base. There can't be any 1591 * TDs scheduled for earlier than that. 1592 */ 1593 base = ehci->last_iso_frame << 3; 1594 next = (next - base) & (mod - 1); 1595 start = (stream->next_uframe - base) & (mod - 1); 1596 1597 if (unlikely(new_stream)) 1598 goto do_ASAP; 1599 1600 /* 1601 * Typical case: reuse current schedule, stream may still be active. 1602 * Hopefully there are no gaps from the host falling behind 1603 * (irq delays etc). If there are, the behavior depends on 1604 * whether URB_ISO_ASAP is set. 1605 */ 1606 now2 = (now - base) & (mod - 1); 1607 1608 /* Is the schedule about to wrap around? */ 1609 if (unlikely(!empty && start < period)) { 1610 ehci_dbg(ehci, "request %p would overflow (%u-%u < %u mod %u)\n", 1611 urb, stream->next_uframe, base, period, mod); 1612 status = -EFBIG; 1613 goto fail; 1614 } 1615 1616 /* Is the next packet scheduled after the base time? */ 1617 if (likely(!empty || start <= now2 + period)) { 1618 1619 /* URB_ISO_ASAP: make sure that start >= next */ 1620 if (unlikely(start < next && 1621 (urb->transfer_flags & URB_ISO_ASAP))) 1622 goto do_ASAP; 1623 1624 /* Otherwise use start, if it's not in the past */ 1625 if (likely(start >= now2)) 1626 goto use_start; 1627 1628 /* Otherwise we got an underrun while the queue was empty */ 1629 } else { 1630 if (urb->transfer_flags & URB_ISO_ASAP) 1631 goto do_ASAP; 1632 wrap = mod; 1633 now2 += mod; 1634 } 1635 1636 /* How many uframes and packets do we need to skip? */ 1637 skip = (now2 - start + period - 1) & -period; 1638 if (skip >= span) { /* Entirely in the past? */ 1639 ehci_dbg(ehci, "iso underrun %p (%u+%u < %u) [%u]\n", 1640 urb, start + base, span - period, now2 + base, 1641 base); 1642 1643 /* Try to keep the last TD intact for scanning later */ 1644 skip = span - period; 1645 1646 /* Will it come before the current scan position? */ 1647 if (empty) { 1648 skip = span; /* Skip the entire URB */ 1649 status = 1; /* and give it back immediately */ 1650 iso_sched_free(stream, sched); 1651 sched = NULL; 1652 } 1653 } 1654 urb->error_count = skip / period; 1655 if (sched) 1656 sched->first_packet = urb->error_count; 1657 goto use_start; 1658 1659 do_ASAP: 1660 /* Use the first slot after "next" */ 1661 start = next + ((start - next) & (period - 1)); 1662 1663 use_start: 1664 /* Tried to schedule too far into the future? */ 1665 if (unlikely(start + span - period >= mod + wrap)) { 1666 ehci_dbg(ehci, "request %p would overflow (%u+%u >= %u)\n", 1667 urb, start, span - period, mod + wrap); 1668 status = -EFBIG; 1669 goto fail; 1670 } 1671 1672 start += base; 1673 stream->next_uframe = (start + skip) & (mod - 1); 1674 1675 /* report high speed start in uframes; full speed, in frames */ 1676 urb->start_frame = start & (mod - 1); 1677 if (!stream->highspeed) 1678 urb->start_frame >>= 3; 1679 return status; 1680 1681 fail: 1682 iso_sched_free(stream, sched); 1683 urb->hcpriv = NULL; 1684 return status; 1685 } 1686 1687 /*-------------------------------------------------------------------------*/ 1688 1689 static inline void 1690 itd_init(struct ehci_hcd *ehci, struct ehci_iso_stream *stream, 1691 struct ehci_itd *itd) 1692 { 1693 int i; 1694 1695 /* it's been recently zeroed */ 1696 itd->hw_next = EHCI_LIST_END(ehci); 1697 itd->hw_bufp[0] = stream->buf0; 1698 itd->hw_bufp[1] = stream->buf1; 1699 itd->hw_bufp[2] = stream->buf2; 1700 1701 for (i = 0; i < 8; i++) 1702 itd->index[i] = -1; 1703 1704 /* All other fields are filled when scheduling */ 1705 } 1706 1707 static inline void 1708 itd_patch( 1709 struct ehci_hcd *ehci, 1710 struct ehci_itd *itd, 1711 struct ehci_iso_sched *iso_sched, 1712 unsigned index, 1713 u16 uframe 1714 ) 1715 { 1716 struct ehci_iso_packet *uf = &iso_sched->packet[index]; 1717 unsigned pg = itd->pg; 1718 1719 // BUG_ON (pg == 6 && uf->cross); 1720 1721 uframe &= 0x07; 1722 itd->index[uframe] = index; 1723 1724 itd->hw_transaction[uframe] = uf->transaction; 1725 itd->hw_transaction[uframe] |= cpu_to_hc32(ehci, pg << 12); 1726 itd->hw_bufp[pg] |= cpu_to_hc32(ehci, uf->bufp & ~(u32)0); 1727 itd->hw_bufp_hi[pg] |= cpu_to_hc32(ehci, (u32)(uf->bufp >> 32)); 1728 1729 /* iso_frame_desc[].offset must be strictly increasing */ 1730 if (unlikely(uf->cross)) { 1731 u64 bufp = uf->bufp + 4096; 1732 1733 itd->pg = ++pg; 1734 itd->hw_bufp[pg] |= cpu_to_hc32(ehci, bufp & ~(u32)0); 1735 itd->hw_bufp_hi[pg] |= cpu_to_hc32(ehci, (u32)(bufp >> 32)); 1736 } 1737 } 1738 1739 static inline void 1740 itd_link(struct ehci_hcd *ehci, unsigned frame, struct ehci_itd *itd) 1741 { 1742 union ehci_shadow *prev = &ehci->pshadow[frame]; 1743 __hc32 *hw_p = &ehci->periodic[frame]; 1744 union ehci_shadow here = *prev; 1745 __hc32 type = 0; 1746 1747 /* skip any iso nodes which might belong to previous microframes */ 1748 while (here.ptr) { 1749 type = Q_NEXT_TYPE(ehci, *hw_p); 1750 if (type == cpu_to_hc32(ehci, Q_TYPE_QH)) 1751 break; 1752 prev = periodic_next_shadow(ehci, prev, type); 1753 hw_p = shadow_next_periodic(ehci, &here, type); 1754 here = *prev; 1755 } 1756 1757 itd->itd_next = here; 1758 itd->hw_next = *hw_p; 1759 prev->itd = itd; 1760 itd->frame = frame; 1761 wmb(); 1762 *hw_p = cpu_to_hc32(ehci, itd->itd_dma | Q_TYPE_ITD); 1763 } 1764 1765 /* fit urb's itds into the selected schedule slot; activate as needed */ 1766 static void itd_link_urb( 1767 struct ehci_hcd *ehci, 1768 struct urb *urb, 1769 unsigned mod, 1770 struct ehci_iso_stream *stream 1771 ) 1772 { 1773 int packet; 1774 unsigned next_uframe, uframe, frame; 1775 struct ehci_iso_sched *iso_sched = urb->hcpriv; 1776 struct ehci_itd *itd; 1777 1778 next_uframe = stream->next_uframe & (mod - 1); 1779 1780 if (unlikely(list_empty(&stream->td_list))) 1781 ehci_to_hcd(ehci)->self.bandwidth_allocated 1782 += stream->bandwidth; 1783 1784 if (ehci_to_hcd(ehci)->self.bandwidth_isoc_reqs == 0) { 1785 if (ehci->amd_pll_fix == 1) 1786 usb_amd_quirk_pll_disable(); 1787 } 1788 1789 ehci_to_hcd(ehci)->self.bandwidth_isoc_reqs++; 1790 1791 /* fill iTDs uframe by uframe */ 1792 for (packet = iso_sched->first_packet, itd = NULL; 1793 packet < urb->number_of_packets;) { 1794 if (itd == NULL) { 1795 /* ASSERT: we have all necessary itds */ 1796 // BUG_ON (list_empty (&iso_sched->td_list)); 1797 1798 /* ASSERT: no itds for this endpoint in this uframe */ 1799 1800 itd = list_entry(iso_sched->td_list.next, 1801 struct ehci_itd, itd_list); 1802 list_move_tail(&itd->itd_list, &stream->td_list); 1803 itd->stream = stream; 1804 itd->urb = urb; 1805 itd_init(ehci, stream, itd); 1806 } 1807 1808 uframe = next_uframe & 0x07; 1809 frame = next_uframe >> 3; 1810 1811 itd_patch(ehci, itd, iso_sched, packet, uframe); 1812 1813 next_uframe += stream->uperiod; 1814 next_uframe &= mod - 1; 1815 packet++; 1816 1817 /* link completed itds into the schedule */ 1818 if (((next_uframe >> 3) != frame) 1819 || packet == urb->number_of_packets) { 1820 itd_link(ehci, frame & (ehci->periodic_size - 1), itd); 1821 itd = NULL; 1822 } 1823 } 1824 stream->next_uframe = next_uframe; 1825 1826 /* don't need that schedule data any more */ 1827 iso_sched_free(stream, iso_sched); 1828 urb->hcpriv = stream; 1829 1830 ++ehci->isoc_count; 1831 enable_periodic(ehci); 1832 } 1833 1834 #define ISO_ERRS (EHCI_ISOC_BUF_ERR | EHCI_ISOC_BABBLE | EHCI_ISOC_XACTERR) 1835 1836 /* Process and recycle a completed ITD. Return true iff its urb completed, 1837 * and hence its completion callback probably added things to the hardware 1838 * schedule. 1839 * 1840 * Note that we carefully avoid recycling this descriptor until after any 1841 * completion callback runs, so that it won't be reused quickly. That is, 1842 * assuming (a) no more than two urbs per frame on this endpoint, and also 1843 * (b) only this endpoint's completions submit URBs. It seems some silicon 1844 * corrupts things if you reuse completed descriptors very quickly... 1845 */ 1846 static bool itd_complete(struct ehci_hcd *ehci, struct ehci_itd *itd) 1847 { 1848 struct urb *urb = itd->urb; 1849 struct usb_iso_packet_descriptor *desc; 1850 u32 t; 1851 unsigned uframe; 1852 int urb_index = -1; 1853 struct ehci_iso_stream *stream = itd->stream; 1854 struct usb_device *dev; 1855 bool retval = false; 1856 1857 /* for each uframe with a packet */ 1858 for (uframe = 0; uframe < 8; uframe++) { 1859 if (likely(itd->index[uframe] == -1)) 1860 continue; 1861 urb_index = itd->index[uframe]; 1862 desc = &urb->iso_frame_desc[urb_index]; 1863 1864 t = hc32_to_cpup(ehci, &itd->hw_transaction[uframe]); 1865 itd->hw_transaction[uframe] = 0; 1866 1867 /* report transfer status */ 1868 if (unlikely(t & ISO_ERRS)) { 1869 urb->error_count++; 1870 if (t & EHCI_ISOC_BUF_ERR) 1871 desc->status = usb_pipein(urb->pipe) 1872 ? -ENOSR /* hc couldn't read */ 1873 : -ECOMM; /* hc couldn't write */ 1874 else if (t & EHCI_ISOC_BABBLE) 1875 desc->status = -EOVERFLOW; 1876 else /* (t & EHCI_ISOC_XACTERR) */ 1877 desc->status = -EPROTO; 1878 1879 /* HC need not update length with this error */ 1880 if (!(t & EHCI_ISOC_BABBLE)) { 1881 desc->actual_length = EHCI_ITD_LENGTH(t); 1882 urb->actual_length += desc->actual_length; 1883 } 1884 } else if (likely((t & EHCI_ISOC_ACTIVE) == 0)) { 1885 desc->status = 0; 1886 desc->actual_length = EHCI_ITD_LENGTH(t); 1887 urb->actual_length += desc->actual_length; 1888 } else { 1889 /* URB was too late */ 1890 urb->error_count++; 1891 } 1892 } 1893 1894 /* handle completion now? */ 1895 if (likely((urb_index + 1) != urb->number_of_packets)) 1896 goto done; 1897 1898 /* ASSERT: it's really the last itd for this urb 1899 list_for_each_entry (itd, &stream->td_list, itd_list) 1900 BUG_ON (itd->urb == urb); 1901 */ 1902 1903 /* give urb back to the driver; completion often (re)submits */ 1904 dev = urb->dev; 1905 ehci_urb_done(ehci, urb, 0); 1906 retval = true; 1907 urb = NULL; 1908 1909 --ehci->isoc_count; 1910 disable_periodic(ehci); 1911 1912 ehci_to_hcd(ehci)->self.bandwidth_isoc_reqs--; 1913 if (ehci_to_hcd(ehci)->self.bandwidth_isoc_reqs == 0) { 1914 if (ehci->amd_pll_fix == 1) 1915 usb_amd_quirk_pll_enable(); 1916 } 1917 1918 if (unlikely(list_is_singular(&stream->td_list))) 1919 ehci_to_hcd(ehci)->self.bandwidth_allocated 1920 -= stream->bandwidth; 1921 1922 done: 1923 itd->urb = NULL; 1924 1925 /* Add to the end of the free list for later reuse */ 1926 list_move_tail(&itd->itd_list, &stream->free_list); 1927 1928 /* Recycle the iTDs when the pipeline is empty (ep no longer in use) */ 1929 if (list_empty(&stream->td_list)) { 1930 list_splice_tail_init(&stream->free_list, 1931 &ehci->cached_itd_list); 1932 start_free_itds(ehci); 1933 } 1934 1935 return retval; 1936 } 1937 1938 /*-------------------------------------------------------------------------*/ 1939 1940 static int itd_submit(struct ehci_hcd *ehci, struct urb *urb, 1941 gfp_t mem_flags) 1942 { 1943 int status = -EINVAL; 1944 unsigned long flags; 1945 struct ehci_iso_stream *stream; 1946 1947 /* Get iso_stream head */ 1948 stream = iso_stream_find(ehci, urb); 1949 if (unlikely(stream == NULL)) { 1950 ehci_dbg(ehci, "can't get iso stream\n"); 1951 return -ENOMEM; 1952 } 1953 if (unlikely(urb->interval != stream->uperiod)) { 1954 ehci_dbg(ehci, "can't change iso interval %d --> %d\n", 1955 stream->uperiod, urb->interval); 1956 goto done; 1957 } 1958 1959 #ifdef EHCI_URB_TRACE 1960 ehci_dbg(ehci, 1961 "%s %s urb %p ep%d%s len %d, %d pkts %d uframes [%p]\n", 1962 __func__, urb->dev->devpath, urb, 1963 usb_pipeendpoint(urb->pipe), 1964 usb_pipein(urb->pipe) ? "in" : "out", 1965 urb->transfer_buffer_length, 1966 urb->number_of_packets, urb->interval, 1967 stream); 1968 #endif 1969 1970 /* allocate ITDs w/o locking anything */ 1971 status = itd_urb_transaction(stream, ehci, urb, mem_flags); 1972 if (unlikely(status < 0)) { 1973 ehci_dbg(ehci, "can't init itds\n"); 1974 goto done; 1975 } 1976 1977 /* schedule ... need to lock */ 1978 spin_lock_irqsave(&ehci->lock, flags); 1979 if (unlikely(!HCD_HW_ACCESSIBLE(ehci_to_hcd(ehci)))) { 1980 status = -ESHUTDOWN; 1981 goto done_not_linked; 1982 } 1983 status = usb_hcd_link_urb_to_ep(ehci_to_hcd(ehci), urb); 1984 if (unlikely(status)) 1985 goto done_not_linked; 1986 status = iso_stream_schedule(ehci, urb, stream); 1987 if (likely(status == 0)) { 1988 itd_link_urb(ehci, urb, ehci->periodic_size << 3, stream); 1989 } else if (status > 0) { 1990 status = 0; 1991 ehci_urb_done(ehci, urb, 0); 1992 } else { 1993 usb_hcd_unlink_urb_from_ep(ehci_to_hcd(ehci), urb); 1994 } 1995 done_not_linked: 1996 spin_unlock_irqrestore(&ehci->lock, flags); 1997 done: 1998 return status; 1999 } 2000 2001 /*-------------------------------------------------------------------------*/ 2002 2003 /* 2004 * "Split ISO TDs" ... used for USB 1.1 devices going through the 2005 * TTs in USB 2.0 hubs. These need microframe scheduling. 2006 */ 2007 2008 static inline void 2009 sitd_sched_init( 2010 struct ehci_hcd *ehci, 2011 struct ehci_iso_sched *iso_sched, 2012 struct ehci_iso_stream *stream, 2013 struct urb *urb 2014 ) 2015 { 2016 unsigned i; 2017 dma_addr_t dma = urb->transfer_dma; 2018 2019 /* how many frames are needed for these transfers */ 2020 iso_sched->span = urb->number_of_packets * stream->ps.period; 2021 2022 /* figure out per-frame sitd fields that we'll need later 2023 * when we fit new sitds into the schedule. 2024 */ 2025 for (i = 0; i < urb->number_of_packets; i++) { 2026 struct ehci_iso_packet *packet = &iso_sched->packet[i]; 2027 unsigned length; 2028 dma_addr_t buf; 2029 u32 trans; 2030 2031 length = urb->iso_frame_desc[i].length & 0x03ff; 2032 buf = dma + urb->iso_frame_desc[i].offset; 2033 2034 trans = SITD_STS_ACTIVE; 2035 if (((i + 1) == urb->number_of_packets) 2036 && !(urb->transfer_flags & URB_NO_INTERRUPT)) 2037 trans |= SITD_IOC; 2038 trans |= length << 16; 2039 packet->transaction = cpu_to_hc32(ehci, trans); 2040 2041 /* might need to cross a buffer page within a td */ 2042 packet->bufp = buf; 2043 packet->buf1 = (buf + length) & ~0x0fff; 2044 if (packet->buf1 != (buf & ~(u64)0x0fff)) 2045 packet->cross = 1; 2046 2047 /* OUT uses multiple start-splits */ 2048 if (stream->bEndpointAddress & USB_DIR_IN) 2049 continue; 2050 length = (length + 187) / 188; 2051 if (length > 1) /* BEGIN vs ALL */ 2052 length |= 1 << 3; 2053 packet->buf1 |= length; 2054 } 2055 } 2056 2057 static int 2058 sitd_urb_transaction( 2059 struct ehci_iso_stream *stream, 2060 struct ehci_hcd *ehci, 2061 struct urb *urb, 2062 gfp_t mem_flags 2063 ) 2064 { 2065 struct ehci_sitd *sitd; 2066 dma_addr_t sitd_dma; 2067 int i; 2068 struct ehci_iso_sched *iso_sched; 2069 unsigned long flags; 2070 2071 iso_sched = iso_sched_alloc(urb->number_of_packets, mem_flags); 2072 if (iso_sched == NULL) 2073 return -ENOMEM; 2074 2075 sitd_sched_init(ehci, iso_sched, stream, urb); 2076 2077 /* allocate/init sITDs */ 2078 spin_lock_irqsave(&ehci->lock, flags); 2079 for (i = 0; i < urb->number_of_packets; i++) { 2080 2081 /* NOTE: for now, we don't try to handle wraparound cases 2082 * for IN (using sitd->hw_backpointer, like a FSTN), which 2083 * means we never need two sitds for full speed packets. 2084 */ 2085 2086 /* 2087 * Use siTDs from the free list, but not siTDs that may 2088 * still be in use by the hardware. 2089 */ 2090 if (likely(!list_empty(&stream->free_list))) { 2091 sitd = list_first_entry(&stream->free_list, 2092 struct ehci_sitd, sitd_list); 2093 if (sitd->frame == ehci->now_frame) 2094 goto alloc_sitd; 2095 list_del(&sitd->sitd_list); 2096 sitd_dma = sitd->sitd_dma; 2097 } else { 2098 alloc_sitd: 2099 spin_unlock_irqrestore(&ehci->lock, flags); 2100 sitd = dma_pool_alloc(ehci->sitd_pool, mem_flags, 2101 &sitd_dma); 2102 spin_lock_irqsave(&ehci->lock, flags); 2103 if (!sitd) { 2104 iso_sched_free(stream, iso_sched); 2105 spin_unlock_irqrestore(&ehci->lock, flags); 2106 return -ENOMEM; 2107 } 2108 } 2109 2110 memset(sitd, 0, sizeof *sitd); 2111 sitd->sitd_dma = sitd_dma; 2112 sitd->frame = NO_FRAME; 2113 list_add(&sitd->sitd_list, &iso_sched->td_list); 2114 } 2115 2116 /* temporarily store schedule info in hcpriv */ 2117 urb->hcpriv = iso_sched; 2118 urb->error_count = 0; 2119 2120 spin_unlock_irqrestore(&ehci->lock, flags); 2121 return 0; 2122 } 2123 2124 /*-------------------------------------------------------------------------*/ 2125 2126 static inline void 2127 sitd_patch( 2128 struct ehci_hcd *ehci, 2129 struct ehci_iso_stream *stream, 2130 struct ehci_sitd *sitd, 2131 struct ehci_iso_sched *iso_sched, 2132 unsigned index 2133 ) 2134 { 2135 struct ehci_iso_packet *uf = &iso_sched->packet[index]; 2136 u64 bufp; 2137 2138 sitd->hw_next = EHCI_LIST_END(ehci); 2139 sitd->hw_fullspeed_ep = stream->address; 2140 sitd->hw_uframe = stream->splits; 2141 sitd->hw_results = uf->transaction; 2142 sitd->hw_backpointer = EHCI_LIST_END(ehci); 2143 2144 bufp = uf->bufp; 2145 sitd->hw_buf[0] = cpu_to_hc32(ehci, bufp); 2146 sitd->hw_buf_hi[0] = cpu_to_hc32(ehci, bufp >> 32); 2147 2148 sitd->hw_buf[1] = cpu_to_hc32(ehci, uf->buf1); 2149 if (uf->cross) 2150 bufp += 4096; 2151 sitd->hw_buf_hi[1] = cpu_to_hc32(ehci, bufp >> 32); 2152 sitd->index = index; 2153 } 2154 2155 static inline void 2156 sitd_link(struct ehci_hcd *ehci, unsigned frame, struct ehci_sitd *sitd) 2157 { 2158 /* note: sitd ordering could matter (CSPLIT then SSPLIT) */ 2159 sitd->sitd_next = ehci->pshadow[frame]; 2160 sitd->hw_next = ehci->periodic[frame]; 2161 ehci->pshadow[frame].sitd = sitd; 2162 sitd->frame = frame; 2163 wmb(); 2164 ehci->periodic[frame] = cpu_to_hc32(ehci, sitd->sitd_dma | Q_TYPE_SITD); 2165 } 2166 2167 /* fit urb's sitds into the selected schedule slot; activate as needed */ 2168 static void sitd_link_urb( 2169 struct ehci_hcd *ehci, 2170 struct urb *urb, 2171 unsigned mod, 2172 struct ehci_iso_stream *stream 2173 ) 2174 { 2175 int packet; 2176 unsigned next_uframe; 2177 struct ehci_iso_sched *sched = urb->hcpriv; 2178 struct ehci_sitd *sitd; 2179 2180 next_uframe = stream->next_uframe; 2181 2182 if (list_empty(&stream->td_list)) 2183 /* usbfs ignores TT bandwidth */ 2184 ehci_to_hcd(ehci)->self.bandwidth_allocated 2185 += stream->bandwidth; 2186 2187 if (ehci_to_hcd(ehci)->self.bandwidth_isoc_reqs == 0) { 2188 if (ehci->amd_pll_fix == 1) 2189 usb_amd_quirk_pll_disable(); 2190 } 2191 2192 ehci_to_hcd(ehci)->self.bandwidth_isoc_reqs++; 2193 2194 /* fill sITDs frame by frame */ 2195 for (packet = sched->first_packet, sitd = NULL; 2196 packet < urb->number_of_packets; 2197 packet++) { 2198 2199 /* ASSERT: we have all necessary sitds */ 2200 BUG_ON(list_empty(&sched->td_list)); 2201 2202 /* ASSERT: no itds for this endpoint in this frame */ 2203 2204 sitd = list_entry(sched->td_list.next, 2205 struct ehci_sitd, sitd_list); 2206 list_move_tail(&sitd->sitd_list, &stream->td_list); 2207 sitd->stream = stream; 2208 sitd->urb = urb; 2209 2210 sitd_patch(ehci, stream, sitd, sched, packet); 2211 sitd_link(ehci, (next_uframe >> 3) & (ehci->periodic_size - 1), 2212 sitd); 2213 2214 next_uframe += stream->uperiod; 2215 } 2216 stream->next_uframe = next_uframe & (mod - 1); 2217 2218 /* don't need that schedule data any more */ 2219 iso_sched_free(stream, sched); 2220 urb->hcpriv = stream; 2221 2222 ++ehci->isoc_count; 2223 enable_periodic(ehci); 2224 } 2225 2226 /*-------------------------------------------------------------------------*/ 2227 2228 #define SITD_ERRS (SITD_STS_ERR | SITD_STS_DBE | SITD_STS_BABBLE \ 2229 | SITD_STS_XACT | SITD_STS_MMF) 2230 2231 /* Process and recycle a completed SITD. Return true iff its urb completed, 2232 * and hence its completion callback probably added things to the hardware 2233 * schedule. 2234 * 2235 * Note that we carefully avoid recycling this descriptor until after any 2236 * completion callback runs, so that it won't be reused quickly. That is, 2237 * assuming (a) no more than two urbs per frame on this endpoint, and also 2238 * (b) only this endpoint's completions submit URBs. It seems some silicon 2239 * corrupts things if you reuse completed descriptors very quickly... 2240 */ 2241 static bool sitd_complete(struct ehci_hcd *ehci, struct ehci_sitd *sitd) 2242 { 2243 struct urb *urb = sitd->urb; 2244 struct usb_iso_packet_descriptor *desc; 2245 u32 t; 2246 int urb_index; 2247 struct ehci_iso_stream *stream = sitd->stream; 2248 struct usb_device *dev; 2249 bool retval = false; 2250 2251 urb_index = sitd->index; 2252 desc = &urb->iso_frame_desc[urb_index]; 2253 t = hc32_to_cpup(ehci, &sitd->hw_results); 2254 2255 /* report transfer status */ 2256 if (unlikely(t & SITD_ERRS)) { 2257 urb->error_count++; 2258 if (t & SITD_STS_DBE) 2259 desc->status = usb_pipein(urb->pipe) 2260 ? -ENOSR /* hc couldn't read */ 2261 : -ECOMM; /* hc couldn't write */ 2262 else if (t & SITD_STS_BABBLE) 2263 desc->status = -EOVERFLOW; 2264 else /* XACT, MMF, etc */ 2265 desc->status = -EPROTO; 2266 } else if (unlikely(t & SITD_STS_ACTIVE)) { 2267 /* URB was too late */ 2268 urb->error_count++; 2269 } else { 2270 desc->status = 0; 2271 desc->actual_length = desc->length - SITD_LENGTH(t); 2272 urb->actual_length += desc->actual_length; 2273 } 2274 2275 /* handle completion now? */ 2276 if ((urb_index + 1) != urb->number_of_packets) 2277 goto done; 2278 2279 /* ASSERT: it's really the last sitd for this urb 2280 list_for_each_entry (sitd, &stream->td_list, sitd_list) 2281 BUG_ON (sitd->urb == urb); 2282 */ 2283 2284 /* give urb back to the driver; completion often (re)submits */ 2285 dev = urb->dev; 2286 ehci_urb_done(ehci, urb, 0); 2287 retval = true; 2288 urb = NULL; 2289 2290 --ehci->isoc_count; 2291 disable_periodic(ehci); 2292 2293 ehci_to_hcd(ehci)->self.bandwidth_isoc_reqs--; 2294 if (ehci_to_hcd(ehci)->self.bandwidth_isoc_reqs == 0) { 2295 if (ehci->amd_pll_fix == 1) 2296 usb_amd_quirk_pll_enable(); 2297 } 2298 2299 if (list_is_singular(&stream->td_list)) 2300 ehci_to_hcd(ehci)->self.bandwidth_allocated 2301 -= stream->bandwidth; 2302 2303 done: 2304 sitd->urb = NULL; 2305 2306 /* Add to the end of the free list for later reuse */ 2307 list_move_tail(&sitd->sitd_list, &stream->free_list); 2308 2309 /* Recycle the siTDs when the pipeline is empty (ep no longer in use) */ 2310 if (list_empty(&stream->td_list)) { 2311 list_splice_tail_init(&stream->free_list, 2312 &ehci->cached_sitd_list); 2313 start_free_itds(ehci); 2314 } 2315 2316 return retval; 2317 } 2318 2319 2320 static int sitd_submit(struct ehci_hcd *ehci, struct urb *urb, 2321 gfp_t mem_flags) 2322 { 2323 int status = -EINVAL; 2324 unsigned long flags; 2325 struct ehci_iso_stream *stream; 2326 2327 /* Get iso_stream head */ 2328 stream = iso_stream_find(ehci, urb); 2329 if (stream == NULL) { 2330 ehci_dbg(ehci, "can't get iso stream\n"); 2331 return -ENOMEM; 2332 } 2333 if (urb->interval != stream->ps.period) { 2334 ehci_dbg(ehci, "can't change iso interval %d --> %d\n", 2335 stream->ps.period, urb->interval); 2336 goto done; 2337 } 2338 2339 #ifdef EHCI_URB_TRACE 2340 ehci_dbg(ehci, 2341 "submit %p dev%s ep%d%s-iso len %d\n", 2342 urb, urb->dev->devpath, 2343 usb_pipeendpoint(urb->pipe), 2344 usb_pipein(urb->pipe) ? "in" : "out", 2345 urb->transfer_buffer_length); 2346 #endif 2347 2348 /* allocate SITDs */ 2349 status = sitd_urb_transaction(stream, ehci, urb, mem_flags); 2350 if (status < 0) { 2351 ehci_dbg(ehci, "can't init sitds\n"); 2352 goto done; 2353 } 2354 2355 /* schedule ... need to lock */ 2356 spin_lock_irqsave(&ehci->lock, flags); 2357 if (unlikely(!HCD_HW_ACCESSIBLE(ehci_to_hcd(ehci)))) { 2358 status = -ESHUTDOWN; 2359 goto done_not_linked; 2360 } 2361 status = usb_hcd_link_urb_to_ep(ehci_to_hcd(ehci), urb); 2362 if (unlikely(status)) 2363 goto done_not_linked; 2364 status = iso_stream_schedule(ehci, urb, stream); 2365 if (likely(status == 0)) { 2366 sitd_link_urb(ehci, urb, ehci->periodic_size << 3, stream); 2367 } else if (status > 0) { 2368 status = 0; 2369 ehci_urb_done(ehci, urb, 0); 2370 } else { 2371 usb_hcd_unlink_urb_from_ep(ehci_to_hcd(ehci), urb); 2372 } 2373 done_not_linked: 2374 spin_unlock_irqrestore(&ehci->lock, flags); 2375 done: 2376 return status; 2377 } 2378 2379 /*-------------------------------------------------------------------------*/ 2380 2381 static void scan_isoc(struct ehci_hcd *ehci) 2382 { 2383 unsigned uf, now_frame, frame; 2384 unsigned fmask = ehci->periodic_size - 1; 2385 bool modified, live; 2386 union ehci_shadow q, *q_p; 2387 __hc32 type, *hw_p; 2388 2389 /* 2390 * When running, scan from last scan point up to "now" 2391 * else clean up by scanning everything that's left. 2392 * Touches as few pages as possible: cache-friendly. 2393 */ 2394 if (ehci->rh_state >= EHCI_RH_RUNNING) { 2395 uf = ehci_read_frame_index(ehci); 2396 now_frame = (uf >> 3) & fmask; 2397 live = true; 2398 } else { 2399 now_frame = (ehci->last_iso_frame - 1) & fmask; 2400 live = false; 2401 } 2402 ehci->now_frame = now_frame; 2403 2404 frame = ehci->last_iso_frame; 2405 2406 restart: 2407 /* Scan each element in frame's queue for completions */ 2408 q_p = &ehci->pshadow[frame]; 2409 hw_p = &ehci->periodic[frame]; 2410 q.ptr = q_p->ptr; 2411 type = Q_NEXT_TYPE(ehci, *hw_p); 2412 modified = false; 2413 2414 while (q.ptr != NULL) { 2415 switch (hc32_to_cpu(ehci, type)) { 2416 case Q_TYPE_ITD: 2417 /* 2418 * If this ITD is still active, leave it for 2419 * later processing ... check the next entry. 2420 * No need to check for activity unless the 2421 * frame is current. 2422 */ 2423 if (frame == now_frame && live) { 2424 rmb(); 2425 for (uf = 0; uf < 8; uf++) { 2426 if (q.itd->hw_transaction[uf] & 2427 ITD_ACTIVE(ehci)) 2428 break; 2429 } 2430 if (uf < 8) { 2431 q_p = &q.itd->itd_next; 2432 hw_p = &q.itd->hw_next; 2433 type = Q_NEXT_TYPE(ehci, 2434 q.itd->hw_next); 2435 q = *q_p; 2436 break; 2437 } 2438 } 2439 2440 /* 2441 * Take finished ITDs out of the schedule 2442 * and process them: recycle, maybe report 2443 * URB completion. HC won't cache the 2444 * pointer for much longer, if at all. 2445 */ 2446 *q_p = q.itd->itd_next; 2447 if (!ehci->use_dummy_qh || 2448 q.itd->hw_next != EHCI_LIST_END(ehci)) 2449 *hw_p = q.itd->hw_next; 2450 else 2451 *hw_p = cpu_to_hc32(ehci, ehci->dummy->qh_dma); 2452 type = Q_NEXT_TYPE(ehci, q.itd->hw_next); 2453 wmb(); 2454 modified = itd_complete(ehci, q.itd); 2455 q = *q_p; 2456 break; 2457 case Q_TYPE_SITD: 2458 /* 2459 * If this SITD is still active, leave it for 2460 * later processing ... check the next entry. 2461 * No need to check for activity unless the 2462 * frame is current. 2463 */ 2464 if (((frame == now_frame) || 2465 (((frame + 1) & fmask) == now_frame)) 2466 && live 2467 && (q.sitd->hw_results & SITD_ACTIVE(ehci))) { 2468 2469 q_p = &q.sitd->sitd_next; 2470 hw_p = &q.sitd->hw_next; 2471 type = Q_NEXT_TYPE(ehci, q.sitd->hw_next); 2472 q = *q_p; 2473 break; 2474 } 2475 2476 /* 2477 * Take finished SITDs out of the schedule 2478 * and process them: recycle, maybe report 2479 * URB completion. 2480 */ 2481 *q_p = q.sitd->sitd_next; 2482 if (!ehci->use_dummy_qh || 2483 q.sitd->hw_next != EHCI_LIST_END(ehci)) 2484 *hw_p = q.sitd->hw_next; 2485 else 2486 *hw_p = cpu_to_hc32(ehci, ehci->dummy->qh_dma); 2487 type = Q_NEXT_TYPE(ehci, q.sitd->hw_next); 2488 wmb(); 2489 modified = sitd_complete(ehci, q.sitd); 2490 q = *q_p; 2491 break; 2492 default: 2493 ehci_dbg(ehci, "corrupt type %d frame %d shadow %p\n", 2494 type, frame, q.ptr); 2495 /* BUG(); */ 2496 /* FALL THROUGH */ 2497 case Q_TYPE_QH: 2498 case Q_TYPE_FSTN: 2499 /* End of the iTDs and siTDs */ 2500 q.ptr = NULL; 2501 break; 2502 } 2503 2504 /* Assume completion callbacks modify the queue */ 2505 if (unlikely(modified && ehci->isoc_count > 0)) 2506 goto restart; 2507 } 2508 2509 /* Stop when we have reached the current frame */ 2510 if (frame == now_frame) 2511 return; 2512 2513 /* The last frame may still have active siTDs */ 2514 ehci->last_iso_frame = frame; 2515 frame = (frame + 1) & fmask; 2516 2517 goto restart; 2518 } 2519