1 /* 2 * EHCI HCD (Host Controller Driver) PCI Bus Glue. 3 * 4 * Copyright (c) 2000-2004 by David Brownell 5 * 6 * This program is free software; you can redistribute it and/or modify it 7 * under the terms of the GNU General Public License as published by the 8 * Free Software Foundation; either version 2 of the License, or (at your 9 * option) any later version. 10 * 11 * This program is distributed in the hope that it will be useful, but 12 * WITHOUT ANY WARRANTY; without even the implied warranty of MERCHANTABILITY 13 * or FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License 14 * for more details. 15 * 16 * You should have received a copy of the GNU General Public License 17 * along with this program; if not, write to the Free Software Foundation, 18 * Inc., 675 Mass Ave, Cambridge, MA 02139, USA. 19 */ 20 21 #ifndef CONFIG_PCI 22 #error "This file is PCI bus glue. CONFIG_PCI must be defined." 23 #endif 24 25 /* defined here to avoid adding to pci_ids.h for single instance use */ 26 #define PCI_DEVICE_ID_INTEL_CE4100_USB 0x2e70 27 28 /*-------------------------------------------------------------------------*/ 29 30 /* called after powerup, by probe or system-pm "wakeup" */ 31 static int ehci_pci_reinit(struct ehci_hcd *ehci, struct pci_dev *pdev) 32 { 33 int retval; 34 35 /* we expect static quirk code to handle the "extended capabilities" 36 * (currently just BIOS handoff) allowed starting with EHCI 0.96 37 */ 38 39 /* PCI Memory-Write-Invalidate cycle support is optional (uncommon) */ 40 retval = pci_set_mwi(pdev); 41 if (!retval) 42 ehci_dbg(ehci, "MWI active\n"); 43 44 return 0; 45 } 46 47 /* called during probe() after chip reset completes */ 48 static int ehci_pci_setup(struct usb_hcd *hcd) 49 { 50 struct ehci_hcd *ehci = hcd_to_ehci(hcd); 51 struct pci_dev *pdev = to_pci_dev(hcd->self.controller); 52 struct pci_dev *p_smbus; 53 u8 rev; 54 u32 temp; 55 int retval; 56 57 switch (pdev->vendor) { 58 case PCI_VENDOR_ID_TOSHIBA_2: 59 /* celleb's companion chip */ 60 if (pdev->device == 0x01b5) { 61 #ifdef CONFIG_USB_EHCI_BIG_ENDIAN_MMIO 62 ehci->big_endian_mmio = 1; 63 #else 64 ehci_warn(ehci, 65 "unsupported big endian Toshiba quirk\n"); 66 #endif 67 } 68 break; 69 } 70 71 ehci->caps = hcd->regs; 72 ehci->regs = hcd->regs + 73 HC_LENGTH(ehci, ehci_readl(ehci, &ehci->caps->hc_capbase)); 74 75 dbg_hcs_params(ehci, "reset"); 76 dbg_hcc_params(ehci, "reset"); 77 78 /* ehci_init() causes memory for DMA transfers to be 79 * allocated. Thus, any vendor-specific workarounds based on 80 * limiting the type of memory used for DMA transfers must 81 * happen before ehci_init() is called. */ 82 switch (pdev->vendor) { 83 case PCI_VENDOR_ID_NVIDIA: 84 /* NVidia reports that certain chips don't handle 85 * QH, ITD, or SITD addresses above 2GB. (But TD, 86 * data buffer, and periodic schedule are normal.) 87 */ 88 switch (pdev->device) { 89 case 0x003c: /* MCP04 */ 90 case 0x005b: /* CK804 */ 91 case 0x00d8: /* CK8 */ 92 case 0x00e8: /* CK8S */ 93 if (pci_set_consistent_dma_mask(pdev, 94 DMA_BIT_MASK(31)) < 0) 95 ehci_warn(ehci, "can't enable NVidia " 96 "workaround for >2GB RAM\n"); 97 break; 98 } 99 break; 100 } 101 102 /* cache this readonly data; minimize chip reads */ 103 ehci->hcs_params = ehci_readl(ehci, &ehci->caps->hcs_params); 104 105 retval = ehci_halt(ehci); 106 if (retval) 107 return retval; 108 109 if ((pdev->vendor == PCI_VENDOR_ID_AMD && pdev->device == 0x7808) || 110 (pdev->vendor == PCI_VENDOR_ID_ATI && pdev->device == 0x4396)) { 111 /* EHCI controller on AMD SB700/SB800/Hudson-2/3 platforms may 112 * read/write memory space which does not belong to it when 113 * there is NULL pointer with T-bit set to 1 in the frame list 114 * table. To avoid the issue, the frame list link pointer 115 * should always contain a valid pointer to a inactive qh. 116 */ 117 ehci->use_dummy_qh = 1; 118 ehci_info(ehci, "applying AMD SB700/SB800/Hudson-2/3 EHCI " 119 "dummy qh workaround\n"); 120 } 121 122 /* data structure init */ 123 retval = ehci_init(hcd); 124 if (retval) 125 return retval; 126 127 switch (pdev->vendor) { 128 case PCI_VENDOR_ID_NEC: 129 ehci->need_io_watchdog = 0; 130 break; 131 case PCI_VENDOR_ID_INTEL: 132 ehci->need_io_watchdog = 0; 133 ehci->fs_i_thresh = 1; 134 if (pdev->device == 0x27cc) { 135 ehci->broken_periodic = 1; 136 ehci_info(ehci, "using broken periodic workaround\n"); 137 } 138 if (pdev->device == 0x0806 || pdev->device == 0x0811 139 || pdev->device == 0x0829) { 140 ehci_info(ehci, "disable lpm for langwell/penwell\n"); 141 ehci->has_lpm = 0; 142 } 143 if (pdev->device == PCI_DEVICE_ID_INTEL_CE4100_USB) { 144 hcd->has_tt = 1; 145 tdi_reset(ehci); 146 } 147 break; 148 case PCI_VENDOR_ID_TDI: 149 if (pdev->device == PCI_DEVICE_ID_TDI_EHCI) { 150 hcd->has_tt = 1; 151 tdi_reset(ehci); 152 } 153 break; 154 case PCI_VENDOR_ID_AMD: 155 /* AMD PLL quirk */ 156 if (usb_amd_find_chipset_info()) 157 ehci->amd_pll_fix = 1; 158 /* AMD8111 EHCI doesn't work, according to AMD errata */ 159 if (pdev->device == 0x7463) { 160 ehci_info(ehci, "ignoring AMD8111 (errata)\n"); 161 retval = -EIO; 162 goto done; 163 } 164 break; 165 case PCI_VENDOR_ID_NVIDIA: 166 switch (pdev->device) { 167 /* Some NForce2 chips have problems with selective suspend; 168 * fixed in newer silicon. 169 */ 170 case 0x0068: 171 if (pdev->revision < 0xa4) 172 ehci->no_selective_suspend = 1; 173 break; 174 175 /* MCP89 chips on the MacBookAir3,1 give EPROTO when 176 * fetching device descriptors unless LPM is disabled. 177 * There are also intermittent problems enumerating 178 * devices with PPCD enabled. 179 */ 180 case 0x0d9d: 181 ehci_info(ehci, "disable lpm/ppcd for nvidia mcp89"); 182 ehci->has_lpm = 0; 183 ehci->has_ppcd = 0; 184 ehci->command &= ~CMD_PPCEE; 185 break; 186 } 187 break; 188 case PCI_VENDOR_ID_VIA: 189 if (pdev->device == 0x3104 && (pdev->revision & 0xf0) == 0x60) { 190 u8 tmp; 191 192 /* The VT6212 defaults to a 1 usec EHCI sleep time which 193 * hogs the PCI bus *badly*. Setting bit 5 of 0x4B makes 194 * that sleep time use the conventional 10 usec. 195 */ 196 pci_read_config_byte(pdev, 0x4b, &tmp); 197 if (tmp & 0x20) 198 break; 199 pci_write_config_byte(pdev, 0x4b, tmp | 0x20); 200 } 201 break; 202 case PCI_VENDOR_ID_ATI: 203 /* AMD PLL quirk */ 204 if (usb_amd_find_chipset_info()) 205 ehci->amd_pll_fix = 1; 206 /* SB600 and old version of SB700 have a bug in EHCI controller, 207 * which causes usb devices lose response in some cases. 208 */ 209 if ((pdev->device == 0x4386) || (pdev->device == 0x4396)) { 210 p_smbus = pci_get_device(PCI_VENDOR_ID_ATI, 211 PCI_DEVICE_ID_ATI_SBX00_SMBUS, 212 NULL); 213 if (!p_smbus) 214 break; 215 rev = p_smbus->revision; 216 if ((pdev->device == 0x4386) || (rev == 0x3a) 217 || (rev == 0x3b)) { 218 u8 tmp; 219 ehci_info(ehci, "applying AMD SB600/SB700 USB " 220 "freeze workaround\n"); 221 pci_read_config_byte(pdev, 0x53, &tmp); 222 pci_write_config_byte(pdev, 0x53, tmp | (1<<3)); 223 } 224 pci_dev_put(p_smbus); 225 } 226 break; 227 } 228 229 /* optional debug port, normally in the first BAR */ 230 temp = pci_find_capability(pdev, 0x0a); 231 if (temp) { 232 pci_read_config_dword(pdev, temp, &temp); 233 temp >>= 16; 234 if ((temp & (3 << 13)) == (1 << 13)) { 235 temp &= 0x1fff; 236 ehci->debug = ehci_to_hcd(ehci)->regs + temp; 237 temp = ehci_readl(ehci, &ehci->debug->control); 238 ehci_info(ehci, "debug port %d%s\n", 239 HCS_DEBUG_PORT(ehci->hcs_params), 240 (temp & DBGP_ENABLED) 241 ? " IN USE" 242 : ""); 243 if (!(temp & DBGP_ENABLED)) 244 ehci->debug = NULL; 245 } 246 } 247 248 ehci_reset(ehci); 249 250 /* at least the Genesys GL880S needs fixup here */ 251 temp = HCS_N_CC(ehci->hcs_params) * HCS_N_PCC(ehci->hcs_params); 252 temp &= 0x0f; 253 if (temp && HCS_N_PORTS(ehci->hcs_params) > temp) { 254 ehci_dbg(ehci, "bogus port configuration: " 255 "cc=%d x pcc=%d < ports=%d\n", 256 HCS_N_CC(ehci->hcs_params), 257 HCS_N_PCC(ehci->hcs_params), 258 HCS_N_PORTS(ehci->hcs_params)); 259 260 switch (pdev->vendor) { 261 case 0x17a0: /* GENESYS */ 262 /* GL880S: should be PORTS=2 */ 263 temp |= (ehci->hcs_params & ~0xf); 264 ehci->hcs_params = temp; 265 break; 266 case PCI_VENDOR_ID_NVIDIA: 267 /* NF4: should be PCC=10 */ 268 break; 269 } 270 } 271 272 /* Serial Bus Release Number is at PCI 0x60 offset */ 273 pci_read_config_byte(pdev, 0x60, &ehci->sbrn); 274 275 /* Keep this around for a while just in case some EHCI 276 * implementation uses legacy PCI PM support. This test 277 * can be removed on 17 Dec 2009 if the dev_warn() hasn't 278 * been triggered by then. 279 */ 280 if (!device_can_wakeup(&pdev->dev)) { 281 u16 port_wake; 282 283 pci_read_config_word(pdev, 0x62, &port_wake); 284 if (port_wake & 0x0001) { 285 dev_warn(&pdev->dev, "Enabling legacy PCI PM\n"); 286 device_set_wakeup_capable(&pdev->dev, 1); 287 } 288 } 289 290 #ifdef CONFIG_USB_SUSPEND 291 /* REVISIT: the controller works fine for wakeup iff the root hub 292 * itself is "globally" suspended, but usbcore currently doesn't 293 * understand such things. 294 * 295 * System suspend currently expects to be able to suspend the entire 296 * device tree, device-at-a-time. If we failed selective suspend 297 * reports, system suspend would fail; so the root hub code must claim 298 * success. That's lying to usbcore, and it matters for runtime 299 * PM scenarios with selective suspend and remote wakeup... 300 */ 301 if (ehci->no_selective_suspend && device_can_wakeup(&pdev->dev)) 302 ehci_warn(ehci, "selective suspend/wakeup unavailable\n"); 303 #endif 304 305 ehci_port_power(ehci, 1); 306 retval = ehci_pci_reinit(ehci, pdev); 307 done: 308 return retval; 309 } 310 311 /*-------------------------------------------------------------------------*/ 312 313 #ifdef CONFIG_PM 314 315 /* suspend/resume, section 4.3 */ 316 317 /* These routines rely on the PCI bus glue 318 * to handle powerdown and wakeup, and currently also on 319 * transceivers that don't need any software attention to set up 320 * the right sort of wakeup. 321 * Also they depend on separate root hub suspend/resume. 322 */ 323 324 static int ehci_pci_suspend(struct usb_hcd *hcd, bool do_wakeup) 325 { 326 struct ehci_hcd *ehci = hcd_to_ehci(hcd); 327 unsigned long flags; 328 int rc = 0; 329 330 if (time_before(jiffies, ehci->next_statechange)) 331 msleep(10); 332 333 /* Root hub was already suspended. Disable irq emission and 334 * mark HW unaccessible. The PM and USB cores make sure that 335 * the root hub is either suspended or stopped. 336 */ 337 ehci_prepare_ports_for_controller_suspend(ehci, do_wakeup); 338 spin_lock_irqsave (&ehci->lock, flags); 339 ehci_writel(ehci, 0, &ehci->regs->intr_enable); 340 (void)ehci_readl(ehci, &ehci->regs->intr_enable); 341 342 clear_bit(HCD_FLAG_HW_ACCESSIBLE, &hcd->flags); 343 spin_unlock_irqrestore (&ehci->lock, flags); 344 345 // could save FLADJ in case of Vaux power loss 346 // ... we'd only use it to handle clock skew 347 348 return rc; 349 } 350 351 static bool usb_is_intel_switchable_ehci(struct pci_dev *pdev) 352 { 353 return pdev->class == PCI_CLASS_SERIAL_USB_EHCI && 354 pdev->vendor == PCI_VENDOR_ID_INTEL && 355 pdev->device == 0x1E26; 356 } 357 358 static void ehci_enable_xhci_companion(void) 359 { 360 struct pci_dev *companion = NULL; 361 362 /* The xHCI and EHCI controllers are not on the same PCI slot */ 363 for_each_pci_dev(companion) { 364 if (!usb_is_intel_switchable_xhci(companion)) 365 continue; 366 usb_enable_xhci_ports(companion); 367 return; 368 } 369 } 370 371 static int ehci_pci_resume(struct usb_hcd *hcd, bool hibernated) 372 { 373 struct ehci_hcd *ehci = hcd_to_ehci(hcd); 374 struct pci_dev *pdev = to_pci_dev(hcd->self.controller); 375 376 /* The BIOS on systems with the Intel Panther Point chipset may or may 377 * not support xHCI natively. That means that during system resume, it 378 * may switch the ports back to EHCI so that users can use their 379 * keyboard to select a kernel from GRUB after resume from hibernate. 380 * 381 * The BIOS is supposed to remember whether the OS had xHCI ports 382 * enabled before resume, and switch the ports back to xHCI when the 383 * BIOS/OS semaphore is written, but we all know we can't trust BIOS 384 * writers. 385 * 386 * Unconditionally switch the ports back to xHCI after a system resume. 387 * We can't tell whether the EHCI or xHCI controller will be resumed 388 * first, so we have to do the port switchover in both drivers. Writing 389 * a '1' to the port switchover registers should have no effect if the 390 * port was already switched over. 391 */ 392 if (usb_is_intel_switchable_ehci(pdev)) 393 ehci_enable_xhci_companion(); 394 395 // maybe restore FLADJ 396 397 if (time_before(jiffies, ehci->next_statechange)) 398 msleep(100); 399 400 /* Mark hardware accessible again as we are out of D3 state by now */ 401 set_bit(HCD_FLAG_HW_ACCESSIBLE, &hcd->flags); 402 403 /* If CF is still set and we aren't resuming from hibernation 404 * then we maintained PCI Vaux power. 405 * Just undo the effect of ehci_pci_suspend(). 406 */ 407 if (ehci_readl(ehci, &ehci->regs->configured_flag) == FLAG_CF && 408 !hibernated) { 409 int mask = INTR_MASK; 410 411 ehci_prepare_ports_for_controller_resume(ehci); 412 if (!hcd->self.root_hub->do_remote_wakeup) 413 mask &= ~STS_PCD; 414 ehci_writel(ehci, mask, &ehci->regs->intr_enable); 415 ehci_readl(ehci, &ehci->regs->intr_enable); 416 return 0; 417 } 418 419 usb_root_hub_lost_power(hcd->self.root_hub); 420 421 /* Else reset, to cope with power loss or flush-to-storage 422 * style "resume" having let BIOS kick in during reboot. 423 */ 424 (void) ehci_halt(ehci); 425 (void) ehci_reset(ehci); 426 (void) ehci_pci_reinit(ehci, pdev); 427 428 /* emptying the schedule aborts any urbs */ 429 spin_lock_irq(&ehci->lock); 430 if (ehci->reclaim) 431 end_unlink_async(ehci); 432 ehci_work(ehci); 433 spin_unlock_irq(&ehci->lock); 434 435 ehci_writel(ehci, ehci->command, &ehci->regs->command); 436 ehci_writel(ehci, FLAG_CF, &ehci->regs->configured_flag); 437 ehci_readl(ehci, &ehci->regs->command); /* unblock posted writes */ 438 439 /* here we "know" root ports should always stay powered */ 440 ehci_port_power(ehci, 1); 441 442 hcd->state = HC_STATE_SUSPENDED; 443 return 0; 444 } 445 #endif 446 447 static int ehci_update_device(struct usb_hcd *hcd, struct usb_device *udev) 448 { 449 struct ehci_hcd *ehci = hcd_to_ehci(hcd); 450 int rc = 0; 451 452 if (!udev->parent) /* udev is root hub itself, impossible */ 453 rc = -1; 454 /* we only support lpm device connected to root hub yet */ 455 if (ehci->has_lpm && !udev->parent->parent) { 456 rc = ehci_lpm_set_da(ehci, udev->devnum, udev->portnum); 457 if (!rc) 458 rc = ehci_lpm_check(ehci, udev->portnum); 459 } 460 return rc; 461 } 462 463 static const struct hc_driver ehci_pci_hc_driver = { 464 .description = hcd_name, 465 .product_desc = "EHCI Host Controller", 466 .hcd_priv_size = sizeof(struct ehci_hcd), 467 468 /* 469 * generic hardware linkage 470 */ 471 .irq = ehci_irq, 472 .flags = HCD_MEMORY | HCD_USB2, 473 474 /* 475 * basic lifecycle operations 476 */ 477 .reset = ehci_pci_setup, 478 .start = ehci_run, 479 #ifdef CONFIG_PM 480 .pci_suspend = ehci_pci_suspend, 481 .pci_resume = ehci_pci_resume, 482 #endif 483 .stop = ehci_stop, 484 .shutdown = ehci_shutdown, 485 486 /* 487 * managing i/o requests and associated device resources 488 */ 489 .urb_enqueue = ehci_urb_enqueue, 490 .urb_dequeue = ehci_urb_dequeue, 491 .endpoint_disable = ehci_endpoint_disable, 492 .endpoint_reset = ehci_endpoint_reset, 493 494 /* 495 * scheduling support 496 */ 497 .get_frame_number = ehci_get_frame, 498 499 /* 500 * root hub support 501 */ 502 .hub_status_data = ehci_hub_status_data, 503 .hub_control = ehci_hub_control, 504 .bus_suspend = ehci_bus_suspend, 505 .bus_resume = ehci_bus_resume, 506 .relinquish_port = ehci_relinquish_port, 507 .port_handed_over = ehci_port_handed_over, 508 509 /* 510 * call back when device connected and addressed 511 */ 512 .update_device = ehci_update_device, 513 514 .clear_tt_buffer_complete = ehci_clear_tt_buffer_complete, 515 }; 516 517 /*-------------------------------------------------------------------------*/ 518 519 /* PCI driver selection metadata; PCI hotplugging uses this */ 520 static const struct pci_device_id pci_ids [] = { { 521 /* handle any USB 2.0 EHCI controller */ 522 PCI_DEVICE_CLASS(PCI_CLASS_SERIAL_USB_EHCI, ~0), 523 .driver_data = (unsigned long) &ehci_pci_hc_driver, 524 }, 525 { /* end: all zeroes */ } 526 }; 527 MODULE_DEVICE_TABLE(pci, pci_ids); 528 529 /* pci driver glue; this is a "new style" PCI driver module */ 530 static struct pci_driver ehci_pci_driver = { 531 .name = (char *) hcd_name, 532 .id_table = pci_ids, 533 534 .probe = usb_hcd_pci_probe, 535 .remove = usb_hcd_pci_remove, 536 .shutdown = usb_hcd_pci_shutdown, 537 538 #ifdef CONFIG_PM_SLEEP 539 .driver = { 540 .pm = &usb_hcd_pci_pm_ops 541 }, 542 #endif 543 }; 544