1 /* 2 * EHCI HCD (Host Controller Driver) PCI Bus Glue. 3 * 4 * Copyright (c) 2000-2004 by David Brownell 5 * 6 * This program is free software; you can redistribute it and/or modify it 7 * under the terms of the GNU General Public License as published by the 8 * Free Software Foundation; either version 2 of the License, or (at your 9 * option) any later version. 10 * 11 * This program is distributed in the hope that it will be useful, but 12 * WITHOUT ANY WARRANTY; without even the implied warranty of MERCHANTABILITY 13 * or FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License 14 * for more details. 15 * 16 * You should have received a copy of the GNU General Public License 17 * along with this program; if not, write to the Free Software Foundation, 18 * Inc., 675 Mass Ave, Cambridge, MA 02139, USA. 19 */ 20 21 #ifndef CONFIG_PCI 22 #error "This file is PCI bus glue. CONFIG_PCI must be defined." 23 #endif 24 25 /*-------------------------------------------------------------------------*/ 26 27 /* called after powerup, by probe or system-pm "wakeup" */ 28 static int ehci_pci_reinit(struct ehci_hcd *ehci, struct pci_dev *pdev) 29 { 30 u32 temp; 31 int retval; 32 33 /* optional debug port, normally in the first BAR */ 34 temp = pci_find_capability(pdev, 0x0a); 35 if (temp) { 36 pci_read_config_dword(pdev, temp, &temp); 37 temp >>= 16; 38 if ((temp & (3 << 13)) == (1 << 13)) { 39 temp &= 0x1fff; 40 ehci->debug = ehci_to_hcd(ehci)->regs + temp; 41 temp = ehci_readl(ehci, &ehci->debug->control); 42 ehci_info(ehci, "debug port %d%s\n", 43 HCS_DEBUG_PORT(ehci->hcs_params), 44 (temp & DBGP_ENABLED) 45 ? " IN USE" 46 : ""); 47 if (!(temp & DBGP_ENABLED)) 48 ehci->debug = NULL; 49 } 50 } 51 52 /* we expect static quirk code to handle the "extended capabilities" 53 * (currently just BIOS handoff) allowed starting with EHCI 0.96 54 */ 55 56 /* PCI Memory-Write-Invalidate cycle support is optional (uncommon) */ 57 retval = pci_set_mwi(pdev); 58 if (!retval) 59 ehci_dbg(ehci, "MWI active\n"); 60 61 return 0; 62 } 63 64 /* called during probe() after chip reset completes */ 65 static int ehci_pci_setup(struct usb_hcd *hcd) 66 { 67 struct ehci_hcd *ehci = hcd_to_ehci(hcd); 68 struct pci_dev *pdev = to_pci_dev(hcd->self.controller); 69 u32 temp; 70 int retval; 71 72 switch (pdev->vendor) { 73 case PCI_VENDOR_ID_TOSHIBA_2: 74 /* celleb's companion chip */ 75 if (pdev->device == 0x01b5) { 76 #ifdef CONFIG_USB_EHCI_BIG_ENDIAN_MMIO 77 ehci->big_endian_mmio = 1; 78 #else 79 ehci_warn(ehci, 80 "unsupported big endian Toshiba quirk\n"); 81 #endif 82 } 83 break; 84 } 85 86 ehci->caps = hcd->regs; 87 ehci->regs = hcd->regs + 88 HC_LENGTH(ehci_readl(ehci, &ehci->caps->hc_capbase)); 89 90 dbg_hcs_params(ehci, "reset"); 91 dbg_hcc_params(ehci, "reset"); 92 93 /* ehci_init() causes memory for DMA transfers to be 94 * allocated. Thus, any vendor-specific workarounds based on 95 * limiting the type of memory used for DMA transfers must 96 * happen before ehci_init() is called. */ 97 switch (pdev->vendor) { 98 case PCI_VENDOR_ID_NVIDIA: 99 /* NVidia reports that certain chips don't handle 100 * QH, ITD, or SITD addresses above 2GB. (But TD, 101 * data buffer, and periodic schedule are normal.) 102 */ 103 switch (pdev->device) { 104 case 0x003c: /* MCP04 */ 105 case 0x005b: /* CK804 */ 106 case 0x00d8: /* CK8 */ 107 case 0x00e8: /* CK8S */ 108 if (pci_set_consistent_dma_mask(pdev, 109 DMA_31BIT_MASK) < 0) 110 ehci_warn(ehci, "can't enable NVidia " 111 "workaround for >2GB RAM\n"); 112 break; 113 } 114 break; 115 } 116 117 /* cache this readonly data; minimize chip reads */ 118 ehci->hcs_params = ehci_readl(ehci, &ehci->caps->hcs_params); 119 120 retval = ehci_halt(ehci); 121 if (retval) 122 return retval; 123 124 /* data structure init */ 125 retval = ehci_init(hcd); 126 if (retval) 127 return retval; 128 129 switch (pdev->vendor) { 130 case PCI_VENDOR_ID_TDI: 131 if (pdev->device == PCI_DEVICE_ID_TDI_EHCI) { 132 hcd->has_tt = 1; 133 tdi_reset(ehci); 134 } 135 break; 136 case PCI_VENDOR_ID_AMD: 137 /* AMD8111 EHCI doesn't work, according to AMD errata */ 138 if (pdev->device == 0x7463) { 139 ehci_info(ehci, "ignoring AMD8111 (errata)\n"); 140 retval = -EIO; 141 goto done; 142 } 143 break; 144 case PCI_VENDOR_ID_NVIDIA: 145 switch (pdev->device) { 146 /* Some NForce2 chips have problems with selective suspend; 147 * fixed in newer silicon. 148 */ 149 case 0x0068: 150 if (pdev->revision < 0xa4) 151 ehci->no_selective_suspend = 1; 152 break; 153 } 154 break; 155 case PCI_VENDOR_ID_VIA: 156 if (pdev->device == 0x3104 && (pdev->revision & 0xf0) == 0x60) { 157 u8 tmp; 158 159 /* The VT6212 defaults to a 1 usec EHCI sleep time which 160 * hogs the PCI bus *badly*. Setting bit 5 of 0x4B makes 161 * that sleep time use the conventional 10 usec. 162 */ 163 pci_read_config_byte(pdev, 0x4b, &tmp); 164 if (tmp & 0x20) 165 break; 166 pci_write_config_byte(pdev, 0x4b, tmp | 0x20); 167 } 168 break; 169 } 170 171 ehci_reset(ehci); 172 173 /* at least the Genesys GL880S needs fixup here */ 174 temp = HCS_N_CC(ehci->hcs_params) * HCS_N_PCC(ehci->hcs_params); 175 temp &= 0x0f; 176 if (temp && HCS_N_PORTS(ehci->hcs_params) > temp) { 177 ehci_dbg(ehci, "bogus port configuration: " 178 "cc=%d x pcc=%d < ports=%d\n", 179 HCS_N_CC(ehci->hcs_params), 180 HCS_N_PCC(ehci->hcs_params), 181 HCS_N_PORTS(ehci->hcs_params)); 182 183 switch (pdev->vendor) { 184 case 0x17a0: /* GENESYS */ 185 /* GL880S: should be PORTS=2 */ 186 temp |= (ehci->hcs_params & ~0xf); 187 ehci->hcs_params = temp; 188 break; 189 case PCI_VENDOR_ID_NVIDIA: 190 /* NF4: should be PCC=10 */ 191 break; 192 } 193 } 194 195 /* Serial Bus Release Number is at PCI 0x60 offset */ 196 pci_read_config_byte(pdev, 0x60, &ehci->sbrn); 197 198 /* Workaround current PCI init glitch: wakeup bits aren't 199 * being set from PCI PM capability. 200 */ 201 if (!device_can_wakeup(&pdev->dev)) { 202 u16 port_wake; 203 204 pci_read_config_word(pdev, 0x62, &port_wake); 205 if (port_wake & 0x0001) 206 device_init_wakeup(&pdev->dev, 1); 207 } 208 209 #ifdef CONFIG_USB_SUSPEND 210 /* REVISIT: the controller works fine for wakeup iff the root hub 211 * itself is "globally" suspended, but usbcore currently doesn't 212 * understand such things. 213 * 214 * System suspend currently expects to be able to suspend the entire 215 * device tree, device-at-a-time. If we failed selective suspend 216 * reports, system suspend would fail; so the root hub code must claim 217 * success. That's lying to usbcore, and it matters for for runtime 218 * PM scenarios with selective suspend and remote wakeup... 219 */ 220 if (ehci->no_selective_suspend && device_can_wakeup(&pdev->dev)) 221 ehci_warn(ehci, "selective suspend/wakeup unavailable\n"); 222 #endif 223 224 ehci_port_power(ehci, 1); 225 retval = ehci_pci_reinit(ehci, pdev); 226 done: 227 return retval; 228 } 229 230 /*-------------------------------------------------------------------------*/ 231 232 #ifdef CONFIG_PM 233 234 /* suspend/resume, section 4.3 */ 235 236 /* These routines rely on the PCI bus glue 237 * to handle powerdown and wakeup, and currently also on 238 * transceivers that don't need any software attention to set up 239 * the right sort of wakeup. 240 * Also they depend on separate root hub suspend/resume. 241 */ 242 243 static int ehci_pci_suspend(struct usb_hcd *hcd, pm_message_t message) 244 { 245 struct ehci_hcd *ehci = hcd_to_ehci(hcd); 246 unsigned long flags; 247 int rc = 0; 248 249 if (time_before(jiffies, ehci->next_statechange)) 250 msleep(10); 251 252 /* Root hub was already suspended. Disable irq emission and 253 * mark HW unaccessible, bail out if RH has been resumed. Use 254 * the spinlock to properly synchronize with possible pending 255 * RH suspend or resume activity. 256 * 257 * This is still racy as hcd->state is manipulated outside of 258 * any locks =P But that will be a different fix. 259 */ 260 spin_lock_irqsave (&ehci->lock, flags); 261 if (hcd->state != HC_STATE_SUSPENDED) { 262 rc = -EINVAL; 263 goto bail; 264 } 265 ehci_writel(ehci, 0, &ehci->regs->intr_enable); 266 (void)ehci_readl(ehci, &ehci->regs->intr_enable); 267 268 /* make sure snapshot being resumed re-enumerates everything */ 269 if (message.event == PM_EVENT_PRETHAW) { 270 ehci_halt(ehci); 271 ehci_reset(ehci); 272 } 273 274 clear_bit(HCD_FLAG_HW_ACCESSIBLE, &hcd->flags); 275 bail: 276 spin_unlock_irqrestore (&ehci->lock, flags); 277 278 // could save FLADJ in case of Vaux power loss 279 // ... we'd only use it to handle clock skew 280 281 return rc; 282 } 283 284 static int ehci_pci_resume(struct usb_hcd *hcd) 285 { 286 struct ehci_hcd *ehci = hcd_to_ehci(hcd); 287 struct pci_dev *pdev = to_pci_dev(hcd->self.controller); 288 289 // maybe restore FLADJ 290 291 if (time_before(jiffies, ehci->next_statechange)) 292 msleep(100); 293 294 /* Mark hardware accessible again as we are out of D3 state by now */ 295 set_bit(HCD_FLAG_HW_ACCESSIBLE, &hcd->flags); 296 297 /* If CF is still set, we maintained PCI Vaux power. 298 * Just undo the effect of ehci_pci_suspend(). 299 */ 300 if (ehci_readl(ehci, &ehci->regs->configured_flag) == FLAG_CF) { 301 int mask = INTR_MASK; 302 303 if (!hcd->self.root_hub->do_remote_wakeup) 304 mask &= ~STS_PCD; 305 ehci_writel(ehci, mask, &ehci->regs->intr_enable); 306 ehci_readl(ehci, &ehci->regs->intr_enable); 307 return 0; 308 } 309 310 ehci_dbg(ehci, "lost power, restarting\n"); 311 usb_root_hub_lost_power(hcd->self.root_hub); 312 313 /* Else reset, to cope with power loss or flush-to-storage 314 * style "resume" having let BIOS kick in during reboot. 315 */ 316 (void) ehci_halt(ehci); 317 (void) ehci_reset(ehci); 318 (void) ehci_pci_reinit(ehci, pdev); 319 320 /* emptying the schedule aborts any urbs */ 321 spin_lock_irq(&ehci->lock); 322 if (ehci->reclaim) 323 end_unlink_async(ehci); 324 ehci_work(ehci); 325 spin_unlock_irq(&ehci->lock); 326 327 ehci_writel(ehci, ehci->command, &ehci->regs->command); 328 ehci_writel(ehci, FLAG_CF, &ehci->regs->configured_flag); 329 ehci_readl(ehci, &ehci->regs->command); /* unblock posted writes */ 330 331 /* here we "know" root ports should always stay powered */ 332 ehci_port_power(ehci, 1); 333 334 hcd->state = HC_STATE_SUSPENDED; 335 return 0; 336 } 337 #endif 338 339 static const struct hc_driver ehci_pci_hc_driver = { 340 .description = hcd_name, 341 .product_desc = "EHCI Host Controller", 342 .hcd_priv_size = sizeof(struct ehci_hcd), 343 344 /* 345 * generic hardware linkage 346 */ 347 .irq = ehci_irq, 348 .flags = HCD_MEMORY | HCD_USB2, 349 350 /* 351 * basic lifecycle operations 352 */ 353 .reset = ehci_pci_setup, 354 .start = ehci_run, 355 #ifdef CONFIG_PM 356 .pci_suspend = ehci_pci_suspend, 357 .pci_resume = ehci_pci_resume, 358 #endif 359 .stop = ehci_stop, 360 .shutdown = ehci_shutdown, 361 362 /* 363 * managing i/o requests and associated device resources 364 */ 365 .urb_enqueue = ehci_urb_enqueue, 366 .urb_dequeue = ehci_urb_dequeue, 367 .endpoint_disable = ehci_endpoint_disable, 368 369 /* 370 * scheduling support 371 */ 372 .get_frame_number = ehci_get_frame, 373 374 /* 375 * root hub support 376 */ 377 .hub_status_data = ehci_hub_status_data, 378 .hub_control = ehci_hub_control, 379 .bus_suspend = ehci_bus_suspend, 380 .bus_resume = ehci_bus_resume, 381 .relinquish_port = ehci_relinquish_port, 382 .port_handed_over = ehci_port_handed_over, 383 }; 384 385 /*-------------------------------------------------------------------------*/ 386 387 /* PCI driver selection metadata; PCI hotplugging uses this */ 388 static const struct pci_device_id pci_ids [] = { { 389 /* handle any USB 2.0 EHCI controller */ 390 PCI_DEVICE_CLASS(PCI_CLASS_SERIAL_USB_EHCI, ~0), 391 .driver_data = (unsigned long) &ehci_pci_hc_driver, 392 }, 393 { /* end: all zeroes */ } 394 }; 395 MODULE_DEVICE_TABLE(pci, pci_ids); 396 397 /* pci driver glue; this is a "new style" PCI driver module */ 398 static struct pci_driver ehci_pci_driver = { 399 .name = (char *) hcd_name, 400 .id_table = pci_ids, 401 402 .probe = usb_hcd_pci_probe, 403 .remove = usb_hcd_pci_remove, 404 405 #ifdef CONFIG_PM 406 .suspend = usb_hcd_pci_suspend, 407 .resume = usb_hcd_pci_resume, 408 #endif 409 .shutdown = usb_hcd_pci_shutdown, 410 }; 411