1 /* 2 * EHCI HCD (Host Controller Driver) PCI Bus Glue. 3 * 4 * Copyright (c) 2000-2004 by David Brownell 5 * 6 * This program is free software; you can redistribute it and/or modify it 7 * under the terms of the GNU General Public License as published by the 8 * Free Software Foundation; either version 2 of the License, or (at your 9 * option) any later version. 10 * 11 * This program is distributed in the hope that it will be useful, but 12 * WITHOUT ANY WARRANTY; without even the implied warranty of MERCHANTABILITY 13 * or FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License 14 * for more details. 15 * 16 * You should have received a copy of the GNU General Public License 17 * along with this program; if not, write to the Free Software Foundation, 18 * Inc., 675 Mass Ave, Cambridge, MA 02139, USA. 19 */ 20 21 #ifndef CONFIG_PCI 22 #error "This file is PCI bus glue. CONFIG_PCI must be defined." 23 #endif 24 25 /* defined here to avoid adding to pci_ids.h for single instance use */ 26 #define PCI_DEVICE_ID_INTEL_CE4100_USB 0x2e70 27 28 /*-------------------------------------------------------------------------*/ 29 30 /* called after powerup, by probe or system-pm "wakeup" */ 31 static int ehci_pci_reinit(struct ehci_hcd *ehci, struct pci_dev *pdev) 32 { 33 int retval; 34 35 /* we expect static quirk code to handle the "extended capabilities" 36 * (currently just BIOS handoff) allowed starting with EHCI 0.96 37 */ 38 39 /* PCI Memory-Write-Invalidate cycle support is optional (uncommon) */ 40 retval = pci_set_mwi(pdev); 41 if (!retval) 42 ehci_dbg(ehci, "MWI active\n"); 43 44 return 0; 45 } 46 47 static int ehci_quirk_amd_hudson(struct ehci_hcd *ehci) 48 { 49 struct pci_dev *amd_smbus_dev; 50 u8 rev = 0; 51 52 amd_smbus_dev = pci_get_device(PCI_VENDOR_ID_ATI, 0x4385, NULL); 53 if (amd_smbus_dev) { 54 pci_read_config_byte(amd_smbus_dev, PCI_REVISION_ID, &rev); 55 if (rev < 0x40) { 56 pci_dev_put(amd_smbus_dev); 57 amd_smbus_dev = NULL; 58 return 0; 59 } 60 } else { 61 amd_smbus_dev = pci_get_device(PCI_VENDOR_ID_AMD, 0x780b, NULL); 62 if (!amd_smbus_dev) 63 return 0; 64 pci_read_config_byte(amd_smbus_dev, PCI_REVISION_ID, &rev); 65 if (rev < 0x11 || rev > 0x18) { 66 pci_dev_put(amd_smbus_dev); 67 amd_smbus_dev = NULL; 68 return 0; 69 } 70 } 71 72 if (!amd_nb_dev) 73 amd_nb_dev = pci_get_device(PCI_VENDOR_ID_AMD, 0x1510, NULL); 74 75 ehci_info(ehci, "QUIRK: Enable exception for AMD Hudson ASPM\n"); 76 77 pci_dev_put(amd_smbus_dev); 78 amd_smbus_dev = NULL; 79 80 return 1; 81 } 82 83 /* called during probe() after chip reset completes */ 84 static int ehci_pci_setup(struct usb_hcd *hcd) 85 { 86 struct ehci_hcd *ehci = hcd_to_ehci(hcd); 87 struct pci_dev *pdev = to_pci_dev(hcd->self.controller); 88 struct pci_dev *p_smbus; 89 u8 rev; 90 u32 temp; 91 int retval; 92 93 switch (pdev->vendor) { 94 case PCI_VENDOR_ID_TOSHIBA_2: 95 /* celleb's companion chip */ 96 if (pdev->device == 0x01b5) { 97 #ifdef CONFIG_USB_EHCI_BIG_ENDIAN_MMIO 98 ehci->big_endian_mmio = 1; 99 #else 100 ehci_warn(ehci, 101 "unsupported big endian Toshiba quirk\n"); 102 #endif 103 } 104 break; 105 } 106 107 ehci->caps = hcd->regs; 108 ehci->regs = hcd->regs + 109 HC_LENGTH(ehci_readl(ehci, &ehci->caps->hc_capbase)); 110 111 dbg_hcs_params(ehci, "reset"); 112 dbg_hcc_params(ehci, "reset"); 113 114 /* ehci_init() causes memory for DMA transfers to be 115 * allocated. Thus, any vendor-specific workarounds based on 116 * limiting the type of memory used for DMA transfers must 117 * happen before ehci_init() is called. */ 118 switch (pdev->vendor) { 119 case PCI_VENDOR_ID_NVIDIA: 120 /* NVidia reports that certain chips don't handle 121 * QH, ITD, or SITD addresses above 2GB. (But TD, 122 * data buffer, and periodic schedule are normal.) 123 */ 124 switch (pdev->device) { 125 case 0x003c: /* MCP04 */ 126 case 0x005b: /* CK804 */ 127 case 0x00d8: /* CK8 */ 128 case 0x00e8: /* CK8S */ 129 if (pci_set_consistent_dma_mask(pdev, 130 DMA_BIT_MASK(31)) < 0) 131 ehci_warn(ehci, "can't enable NVidia " 132 "workaround for >2GB RAM\n"); 133 break; 134 } 135 break; 136 } 137 138 /* cache this readonly data; minimize chip reads */ 139 ehci->hcs_params = ehci_readl(ehci, &ehci->caps->hcs_params); 140 141 if (ehci_quirk_amd_hudson(ehci)) 142 ehci->amd_l1_fix = 1; 143 144 retval = ehci_halt(ehci); 145 if (retval) 146 return retval; 147 148 if ((pdev->vendor == PCI_VENDOR_ID_AMD && pdev->device == 0x7808) || 149 (pdev->vendor == PCI_VENDOR_ID_ATI && pdev->device == 0x4396)) { 150 /* EHCI controller on AMD SB700/SB800/Hudson-2/3 platforms may 151 * read/write memory space which does not belong to it when 152 * there is NULL pointer with T-bit set to 1 in the frame list 153 * table. To avoid the issue, the frame list link pointer 154 * should always contain a valid pointer to a inactive qh. 155 */ 156 ehci->use_dummy_qh = 1; 157 ehci_info(ehci, "applying AMD SB700/SB800/Hudson-2/3 EHCI " 158 "dummy qh workaround\n"); 159 } 160 161 /* data structure init */ 162 retval = ehci_init(hcd); 163 if (retval) 164 return retval; 165 166 switch (pdev->vendor) { 167 case PCI_VENDOR_ID_NEC: 168 ehci->need_io_watchdog = 0; 169 break; 170 case PCI_VENDOR_ID_INTEL: 171 ehci->need_io_watchdog = 0; 172 ehci->fs_i_thresh = 1; 173 if (pdev->device == 0x27cc) { 174 ehci->broken_periodic = 1; 175 ehci_info(ehci, "using broken periodic workaround\n"); 176 } 177 if (pdev->device == 0x0806 || pdev->device == 0x0811 178 || pdev->device == 0x0829) { 179 ehci_info(ehci, "disable lpm for langwell/penwell\n"); 180 ehci->has_lpm = 0; 181 } 182 if (pdev->device == PCI_DEVICE_ID_INTEL_CE4100_USB) { 183 hcd->has_tt = 1; 184 tdi_reset(ehci); 185 } 186 break; 187 case PCI_VENDOR_ID_TDI: 188 if (pdev->device == PCI_DEVICE_ID_TDI_EHCI) { 189 hcd->has_tt = 1; 190 tdi_reset(ehci); 191 } 192 break; 193 case PCI_VENDOR_ID_AMD: 194 /* AMD8111 EHCI doesn't work, according to AMD errata */ 195 if (pdev->device == 0x7463) { 196 ehci_info(ehci, "ignoring AMD8111 (errata)\n"); 197 retval = -EIO; 198 goto done; 199 } 200 break; 201 case PCI_VENDOR_ID_NVIDIA: 202 switch (pdev->device) { 203 /* Some NForce2 chips have problems with selective suspend; 204 * fixed in newer silicon. 205 */ 206 case 0x0068: 207 if (pdev->revision < 0xa4) 208 ehci->no_selective_suspend = 1; 209 break; 210 211 /* MCP89 chips on the MacBookAir3,1 give EPROTO when 212 * fetching device descriptors unless LPM is disabled. 213 * There are also intermittent problems enumerating 214 * devices with PPCD enabled. 215 */ 216 case 0x0d9d: 217 ehci_info(ehci, "disable lpm/ppcd for nvidia mcp89"); 218 ehci->has_lpm = 0; 219 ehci->has_ppcd = 0; 220 ehci->command &= ~CMD_PPCEE; 221 break; 222 } 223 break; 224 case PCI_VENDOR_ID_VIA: 225 if (pdev->device == 0x3104 && (pdev->revision & 0xf0) == 0x60) { 226 u8 tmp; 227 228 /* The VT6212 defaults to a 1 usec EHCI sleep time which 229 * hogs the PCI bus *badly*. Setting bit 5 of 0x4B makes 230 * that sleep time use the conventional 10 usec. 231 */ 232 pci_read_config_byte(pdev, 0x4b, &tmp); 233 if (tmp & 0x20) 234 break; 235 pci_write_config_byte(pdev, 0x4b, tmp | 0x20); 236 } 237 break; 238 case PCI_VENDOR_ID_ATI: 239 /* SB600 and old version of SB700 have a bug in EHCI controller, 240 * which causes usb devices lose response in some cases. 241 */ 242 if ((pdev->device == 0x4386) || (pdev->device == 0x4396)) { 243 p_smbus = pci_get_device(PCI_VENDOR_ID_ATI, 244 PCI_DEVICE_ID_ATI_SBX00_SMBUS, 245 NULL); 246 if (!p_smbus) 247 break; 248 rev = p_smbus->revision; 249 if ((pdev->device == 0x4386) || (rev == 0x3a) 250 || (rev == 0x3b)) { 251 u8 tmp; 252 ehci_info(ehci, "applying AMD SB600/SB700 USB " 253 "freeze workaround\n"); 254 pci_read_config_byte(pdev, 0x53, &tmp); 255 pci_write_config_byte(pdev, 0x53, tmp | (1<<3)); 256 } 257 pci_dev_put(p_smbus); 258 } 259 break; 260 } 261 262 /* optional debug port, normally in the first BAR */ 263 temp = pci_find_capability(pdev, 0x0a); 264 if (temp) { 265 pci_read_config_dword(pdev, temp, &temp); 266 temp >>= 16; 267 if ((temp & (3 << 13)) == (1 << 13)) { 268 temp &= 0x1fff; 269 ehci->debug = ehci_to_hcd(ehci)->regs + temp; 270 temp = ehci_readl(ehci, &ehci->debug->control); 271 ehci_info(ehci, "debug port %d%s\n", 272 HCS_DEBUG_PORT(ehci->hcs_params), 273 (temp & DBGP_ENABLED) 274 ? " IN USE" 275 : ""); 276 if (!(temp & DBGP_ENABLED)) 277 ehci->debug = NULL; 278 } 279 } 280 281 ehci_reset(ehci); 282 283 /* at least the Genesys GL880S needs fixup here */ 284 temp = HCS_N_CC(ehci->hcs_params) * HCS_N_PCC(ehci->hcs_params); 285 temp &= 0x0f; 286 if (temp && HCS_N_PORTS(ehci->hcs_params) > temp) { 287 ehci_dbg(ehci, "bogus port configuration: " 288 "cc=%d x pcc=%d < ports=%d\n", 289 HCS_N_CC(ehci->hcs_params), 290 HCS_N_PCC(ehci->hcs_params), 291 HCS_N_PORTS(ehci->hcs_params)); 292 293 switch (pdev->vendor) { 294 case 0x17a0: /* GENESYS */ 295 /* GL880S: should be PORTS=2 */ 296 temp |= (ehci->hcs_params & ~0xf); 297 ehci->hcs_params = temp; 298 break; 299 case PCI_VENDOR_ID_NVIDIA: 300 /* NF4: should be PCC=10 */ 301 break; 302 } 303 } 304 305 /* Serial Bus Release Number is at PCI 0x60 offset */ 306 pci_read_config_byte(pdev, 0x60, &ehci->sbrn); 307 308 /* Keep this around for a while just in case some EHCI 309 * implementation uses legacy PCI PM support. This test 310 * can be removed on 17 Dec 2009 if the dev_warn() hasn't 311 * been triggered by then. 312 */ 313 if (!device_can_wakeup(&pdev->dev)) { 314 u16 port_wake; 315 316 pci_read_config_word(pdev, 0x62, &port_wake); 317 if (port_wake & 0x0001) { 318 dev_warn(&pdev->dev, "Enabling legacy PCI PM\n"); 319 device_set_wakeup_capable(&pdev->dev, 1); 320 } 321 } 322 323 #ifdef CONFIG_USB_SUSPEND 324 /* REVISIT: the controller works fine for wakeup iff the root hub 325 * itself is "globally" suspended, but usbcore currently doesn't 326 * understand such things. 327 * 328 * System suspend currently expects to be able to suspend the entire 329 * device tree, device-at-a-time. If we failed selective suspend 330 * reports, system suspend would fail; so the root hub code must claim 331 * success. That's lying to usbcore, and it matters for runtime 332 * PM scenarios with selective suspend and remote wakeup... 333 */ 334 if (ehci->no_selective_suspend && device_can_wakeup(&pdev->dev)) 335 ehci_warn(ehci, "selective suspend/wakeup unavailable\n"); 336 #endif 337 338 ehci_port_power(ehci, 1); 339 retval = ehci_pci_reinit(ehci, pdev); 340 done: 341 return retval; 342 } 343 344 /*-------------------------------------------------------------------------*/ 345 346 #ifdef CONFIG_PM 347 348 /* suspend/resume, section 4.3 */ 349 350 /* These routines rely on the PCI bus glue 351 * to handle powerdown and wakeup, and currently also on 352 * transceivers that don't need any software attention to set up 353 * the right sort of wakeup. 354 * Also they depend on separate root hub suspend/resume. 355 */ 356 357 static int ehci_pci_suspend(struct usb_hcd *hcd, bool do_wakeup) 358 { 359 struct ehci_hcd *ehci = hcd_to_ehci(hcd); 360 unsigned long flags; 361 int rc = 0; 362 363 if (time_before(jiffies, ehci->next_statechange)) 364 msleep(10); 365 366 /* Root hub was already suspended. Disable irq emission and 367 * mark HW unaccessible. The PM and USB cores make sure that 368 * the root hub is either suspended or stopped. 369 */ 370 ehci_prepare_ports_for_controller_suspend(ehci, do_wakeup); 371 spin_lock_irqsave (&ehci->lock, flags); 372 ehci_writel(ehci, 0, &ehci->regs->intr_enable); 373 (void)ehci_readl(ehci, &ehci->regs->intr_enable); 374 375 clear_bit(HCD_FLAG_HW_ACCESSIBLE, &hcd->flags); 376 spin_unlock_irqrestore (&ehci->lock, flags); 377 378 // could save FLADJ in case of Vaux power loss 379 // ... we'd only use it to handle clock skew 380 381 return rc; 382 } 383 384 static int ehci_pci_resume(struct usb_hcd *hcd, bool hibernated) 385 { 386 struct ehci_hcd *ehci = hcd_to_ehci(hcd); 387 struct pci_dev *pdev = to_pci_dev(hcd->self.controller); 388 389 // maybe restore FLADJ 390 391 if (time_before(jiffies, ehci->next_statechange)) 392 msleep(100); 393 394 /* Mark hardware accessible again as we are out of D3 state by now */ 395 set_bit(HCD_FLAG_HW_ACCESSIBLE, &hcd->flags); 396 397 /* If CF is still set and we aren't resuming from hibernation 398 * then we maintained PCI Vaux power. 399 * Just undo the effect of ehci_pci_suspend(). 400 */ 401 if (ehci_readl(ehci, &ehci->regs->configured_flag) == FLAG_CF && 402 !hibernated) { 403 int mask = INTR_MASK; 404 405 ehci_prepare_ports_for_controller_resume(ehci); 406 if (!hcd->self.root_hub->do_remote_wakeup) 407 mask &= ~STS_PCD; 408 ehci_writel(ehci, mask, &ehci->regs->intr_enable); 409 ehci_readl(ehci, &ehci->regs->intr_enable); 410 return 0; 411 } 412 413 usb_root_hub_lost_power(hcd->self.root_hub); 414 415 /* Else reset, to cope with power loss or flush-to-storage 416 * style "resume" having let BIOS kick in during reboot. 417 */ 418 (void) ehci_halt(ehci); 419 (void) ehci_reset(ehci); 420 (void) ehci_pci_reinit(ehci, pdev); 421 422 /* emptying the schedule aborts any urbs */ 423 spin_lock_irq(&ehci->lock); 424 if (ehci->reclaim) 425 end_unlink_async(ehci); 426 ehci_work(ehci); 427 spin_unlock_irq(&ehci->lock); 428 429 ehci_writel(ehci, ehci->command, &ehci->regs->command); 430 ehci_writel(ehci, FLAG_CF, &ehci->regs->configured_flag); 431 ehci_readl(ehci, &ehci->regs->command); /* unblock posted writes */ 432 433 /* here we "know" root ports should always stay powered */ 434 ehci_port_power(ehci, 1); 435 436 hcd->state = HC_STATE_SUSPENDED; 437 return 0; 438 } 439 #endif 440 441 static int ehci_update_device(struct usb_hcd *hcd, struct usb_device *udev) 442 { 443 struct ehci_hcd *ehci = hcd_to_ehci(hcd); 444 int rc = 0; 445 446 if (!udev->parent) /* udev is root hub itself, impossible */ 447 rc = -1; 448 /* we only support lpm device connected to root hub yet */ 449 if (ehci->has_lpm && !udev->parent->parent) { 450 rc = ehci_lpm_set_da(ehci, udev->devnum, udev->portnum); 451 if (!rc) 452 rc = ehci_lpm_check(ehci, udev->portnum); 453 } 454 return rc; 455 } 456 457 static const struct hc_driver ehci_pci_hc_driver = { 458 .description = hcd_name, 459 .product_desc = "EHCI Host Controller", 460 .hcd_priv_size = sizeof(struct ehci_hcd), 461 462 /* 463 * generic hardware linkage 464 */ 465 .irq = ehci_irq, 466 .flags = HCD_MEMORY | HCD_USB2, 467 468 /* 469 * basic lifecycle operations 470 */ 471 .reset = ehci_pci_setup, 472 .start = ehci_run, 473 #ifdef CONFIG_PM 474 .pci_suspend = ehci_pci_suspend, 475 .pci_resume = ehci_pci_resume, 476 #endif 477 .stop = ehci_stop, 478 .shutdown = ehci_shutdown, 479 480 /* 481 * managing i/o requests and associated device resources 482 */ 483 .urb_enqueue = ehci_urb_enqueue, 484 .urb_dequeue = ehci_urb_dequeue, 485 .endpoint_disable = ehci_endpoint_disable, 486 .endpoint_reset = ehci_endpoint_reset, 487 488 /* 489 * scheduling support 490 */ 491 .get_frame_number = ehci_get_frame, 492 493 /* 494 * root hub support 495 */ 496 .hub_status_data = ehci_hub_status_data, 497 .hub_control = ehci_hub_control, 498 .bus_suspend = ehci_bus_suspend, 499 .bus_resume = ehci_bus_resume, 500 .relinquish_port = ehci_relinquish_port, 501 .port_handed_over = ehci_port_handed_over, 502 503 /* 504 * call back when device connected and addressed 505 */ 506 .update_device = ehci_update_device, 507 508 .clear_tt_buffer_complete = ehci_clear_tt_buffer_complete, 509 }; 510 511 /*-------------------------------------------------------------------------*/ 512 513 /* PCI driver selection metadata; PCI hotplugging uses this */ 514 static const struct pci_device_id pci_ids [] = { { 515 /* handle any USB 2.0 EHCI controller */ 516 PCI_DEVICE_CLASS(PCI_CLASS_SERIAL_USB_EHCI, ~0), 517 .driver_data = (unsigned long) &ehci_pci_hc_driver, 518 }, 519 { /* end: all zeroes */ } 520 }; 521 MODULE_DEVICE_TABLE(pci, pci_ids); 522 523 /* pci driver glue; this is a "new style" PCI driver module */ 524 static struct pci_driver ehci_pci_driver = { 525 .name = (char *) hcd_name, 526 .id_table = pci_ids, 527 528 .probe = usb_hcd_pci_probe, 529 .remove = usb_hcd_pci_remove, 530 .shutdown = usb_hcd_pci_shutdown, 531 532 #ifdef CONFIG_PM_SLEEP 533 .driver = { 534 .pm = &usb_hcd_pci_pm_ops 535 }, 536 #endif 537 }; 538