1 /* 2 * Copyright (c) 2001 by David Brownell 3 * 4 * This program is free software; you can redistribute it and/or modify it 5 * under the terms of the GNU General Public License as published by the 6 * Free Software Foundation; either version 2 of the License, or (at your 7 * option) any later version. 8 * 9 * This program is distributed in the hope that it will be useful, but 10 * WITHOUT ANY WARRANTY; without even the implied warranty of MERCHANTABILITY 11 * or FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License 12 * for more details. 13 * 14 * You should have received a copy of the GNU General Public License 15 * along with this program; if not, write to the Free Software Foundation, 16 * Inc., 675 Mass Ave, Cambridge, MA 02139, USA. 17 */ 18 19 /* this file is part of ehci-hcd.c */ 20 21 /*-------------------------------------------------------------------------*/ 22 23 /* 24 * There's basically three types of memory: 25 * - data used only by the HCD ... kmalloc is fine 26 * - async and periodic schedules, shared by HC and HCD ... these 27 * need to use dma_pool or dma_alloc_coherent 28 * - driver buffers, read/written by HC ... single shot DMA mapped 29 * 30 * There's also "register" data (e.g. PCI or SOC), which is memory mapped. 31 * No memory seen by this driver is pageable. 32 */ 33 34 /*-------------------------------------------------------------------------*/ 35 36 /* Allocate the key transfer structures from the previously allocated pool */ 37 38 static inline void ehci_qtd_init(struct ehci_hcd *ehci, struct ehci_qtd *qtd, 39 dma_addr_t dma) 40 { 41 memset (qtd, 0, sizeof *qtd); 42 qtd->qtd_dma = dma; 43 qtd->hw_token = cpu_to_hc32(ehci, QTD_STS_HALT); 44 qtd->hw_next = EHCI_LIST_END(ehci); 45 qtd->hw_alt_next = EHCI_LIST_END(ehci); 46 INIT_LIST_HEAD (&qtd->qtd_list); 47 } 48 49 static struct ehci_qtd *ehci_qtd_alloc (struct ehci_hcd *ehci, gfp_t flags) 50 { 51 struct ehci_qtd *qtd; 52 dma_addr_t dma; 53 54 qtd = dma_pool_alloc (ehci->qtd_pool, flags, &dma); 55 if (qtd != NULL) { 56 ehci_qtd_init(ehci, qtd, dma); 57 } 58 return qtd; 59 } 60 61 static inline void ehci_qtd_free (struct ehci_hcd *ehci, struct ehci_qtd *qtd) 62 { 63 dma_pool_free (ehci->qtd_pool, qtd, qtd->qtd_dma); 64 } 65 66 67 static void qh_destroy(struct ehci_hcd *ehci, struct ehci_qh *qh) 68 { 69 /* clean qtds first, and know this is not linked */ 70 if (!list_empty (&qh->qtd_list) || qh->qh_next.ptr) { 71 ehci_dbg (ehci, "unused qh not empty!\n"); 72 BUG (); 73 } 74 if (qh->dummy) 75 ehci_qtd_free (ehci, qh->dummy); 76 dma_pool_free(ehci->qh_pool, qh->hw, qh->qh_dma); 77 kfree(qh); 78 } 79 80 static struct ehci_qh *ehci_qh_alloc (struct ehci_hcd *ehci, gfp_t flags) 81 { 82 struct ehci_qh *qh; 83 dma_addr_t dma; 84 85 qh = kzalloc(sizeof *qh, GFP_ATOMIC); 86 if (!qh) 87 goto done; 88 qh->hw = (struct ehci_qh_hw *) 89 dma_pool_alloc(ehci->qh_pool, flags, &dma); 90 if (!qh->hw) 91 goto fail; 92 memset(qh->hw, 0, sizeof *qh->hw); 93 qh->qh_dma = dma; 94 // INIT_LIST_HEAD (&qh->qh_list); 95 INIT_LIST_HEAD (&qh->qtd_list); 96 INIT_LIST_HEAD(&qh->unlink_node); 97 98 /* dummy td enables safe urb queuing */ 99 qh->dummy = ehci_qtd_alloc (ehci, flags); 100 if (qh->dummy == NULL) { 101 ehci_dbg (ehci, "no dummy td\n"); 102 goto fail1; 103 } 104 done: 105 return qh; 106 fail1: 107 dma_pool_free(ehci->qh_pool, qh->hw, qh->qh_dma); 108 fail: 109 kfree(qh); 110 return NULL; 111 } 112 113 /*-------------------------------------------------------------------------*/ 114 115 /* The queue heads and transfer descriptors are managed from pools tied 116 * to each of the "per device" structures. 117 * This is the initialisation and cleanup code. 118 */ 119 120 static void ehci_mem_cleanup (struct ehci_hcd *ehci) 121 { 122 if (ehci->async) 123 qh_destroy(ehci, ehci->async); 124 ehci->async = NULL; 125 126 if (ehci->dummy) 127 qh_destroy(ehci, ehci->dummy); 128 ehci->dummy = NULL; 129 130 /* DMA consistent memory and pools */ 131 if (ehci->qtd_pool) 132 dma_pool_destroy (ehci->qtd_pool); 133 ehci->qtd_pool = NULL; 134 135 if (ehci->qh_pool) { 136 dma_pool_destroy (ehci->qh_pool); 137 ehci->qh_pool = NULL; 138 } 139 140 if (ehci->itd_pool) 141 dma_pool_destroy (ehci->itd_pool); 142 ehci->itd_pool = NULL; 143 144 if (ehci->sitd_pool) 145 dma_pool_destroy (ehci->sitd_pool); 146 ehci->sitd_pool = NULL; 147 148 if (ehci->periodic) 149 dma_free_coherent (ehci_to_hcd(ehci)->self.controller, 150 ehci->periodic_size * sizeof (u32), 151 ehci->periodic, ehci->periodic_dma); 152 ehci->periodic = NULL; 153 154 /* shadow periodic table */ 155 kfree(ehci->pshadow); 156 ehci->pshadow = NULL; 157 } 158 159 /* remember to add cleanup code (above) if you add anything here */ 160 static int ehci_mem_init (struct ehci_hcd *ehci, gfp_t flags) 161 { 162 int i; 163 164 /* QTDs for control/bulk/intr transfers */ 165 ehci->qtd_pool = dma_pool_create ("ehci_qtd", 166 ehci_to_hcd(ehci)->self.controller, 167 sizeof (struct ehci_qtd), 168 32 /* byte alignment (for hw parts) */, 169 4096 /* can't cross 4K */); 170 if (!ehci->qtd_pool) { 171 goto fail; 172 } 173 174 /* QHs for control/bulk/intr transfers */ 175 ehci->qh_pool = dma_pool_create ("ehci_qh", 176 ehci_to_hcd(ehci)->self.controller, 177 sizeof(struct ehci_qh_hw), 178 32 /* byte alignment (for hw parts) */, 179 4096 /* can't cross 4K */); 180 if (!ehci->qh_pool) { 181 goto fail; 182 } 183 ehci->async = ehci_qh_alloc (ehci, flags); 184 if (!ehci->async) { 185 goto fail; 186 } 187 188 /* ITD for high speed ISO transfers */ 189 ehci->itd_pool = dma_pool_create ("ehci_itd", 190 ehci_to_hcd(ehci)->self.controller, 191 sizeof (struct ehci_itd), 192 32 /* byte alignment (for hw parts) */, 193 4096 /* can't cross 4K */); 194 if (!ehci->itd_pool) { 195 goto fail; 196 } 197 198 /* SITD for full/low speed split ISO transfers */ 199 ehci->sitd_pool = dma_pool_create ("ehci_sitd", 200 ehci_to_hcd(ehci)->self.controller, 201 sizeof (struct ehci_sitd), 202 32 /* byte alignment (for hw parts) */, 203 4096 /* can't cross 4K */); 204 if (!ehci->sitd_pool) { 205 goto fail; 206 } 207 208 /* Hardware periodic table */ 209 ehci->periodic = (__le32 *) 210 dma_alloc_coherent (ehci_to_hcd(ehci)->self.controller, 211 ehci->periodic_size * sizeof(__le32), 212 &ehci->periodic_dma, 0); 213 if (ehci->periodic == NULL) { 214 goto fail; 215 } 216 217 if (ehci->use_dummy_qh) { 218 struct ehci_qh_hw *hw; 219 ehci->dummy = ehci_qh_alloc(ehci, flags); 220 if (!ehci->dummy) 221 goto fail; 222 223 hw = ehci->dummy->hw; 224 hw->hw_next = EHCI_LIST_END(ehci); 225 hw->hw_qtd_next = EHCI_LIST_END(ehci); 226 hw->hw_alt_next = EHCI_LIST_END(ehci); 227 ehci->dummy->hw = hw; 228 229 for (i = 0; i < ehci->periodic_size; i++) 230 ehci->periodic[i] = cpu_to_hc32(ehci, 231 ehci->dummy->qh_dma); 232 } else { 233 for (i = 0; i < ehci->periodic_size; i++) 234 ehci->periodic[i] = EHCI_LIST_END(ehci); 235 } 236 237 /* software shadow of hardware table */ 238 ehci->pshadow = kcalloc(ehci->periodic_size, sizeof(void *), flags); 239 if (ehci->pshadow != NULL) 240 return 0; 241 242 fail: 243 ehci_dbg (ehci, "couldn't init memory\n"); 244 ehci_mem_cleanup (ehci); 245 return -ENOMEM; 246 } 247