1 /* 2 * Enhanced Host Controller Interface (EHCI) driver for USB. 3 * 4 * Maintainer: Alan Stern <stern@rowland.harvard.edu> 5 * 6 * Copyright (c) 2000-2004 by David Brownell 7 * 8 * This program is free software; you can redistribute it and/or modify it 9 * under the terms of the GNU General Public License as published by the 10 * Free Software Foundation; either version 2 of the License, or (at your 11 * option) any later version. 12 * 13 * This program is distributed in the hope that it will be useful, but 14 * WITHOUT ANY WARRANTY; without even the implied warranty of MERCHANTABILITY 15 * or FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License 16 * for more details. 17 * 18 * You should have received a copy of the GNU General Public License 19 * along with this program; if not, write to the Free Software Foundation, 20 * Inc., 675 Mass Ave, Cambridge, MA 02139, USA. 21 */ 22 23 #include <linux/module.h> 24 #include <linux/pci.h> 25 #include <linux/dmapool.h> 26 #include <linux/kernel.h> 27 #include <linux/delay.h> 28 #include <linux/ioport.h> 29 #include <linux/sched.h> 30 #include <linux/vmalloc.h> 31 #include <linux/errno.h> 32 #include <linux/init.h> 33 #include <linux/timer.h> 34 #include <linux/ktime.h> 35 #include <linux/list.h> 36 #include <linux/interrupt.h> 37 #include <linux/usb.h> 38 #include <linux/usb/hcd.h> 39 #include <linux/moduleparam.h> 40 #include <linux/dma-mapping.h> 41 #include <linux/debugfs.h> 42 #include <linux/slab.h> 43 #include <linux/uaccess.h> 44 45 #include <asm/byteorder.h> 46 #include <asm/io.h> 47 #include <asm/irq.h> 48 #include <asm/unaligned.h> 49 50 #if defined(CONFIG_PPC_PS3) 51 #include <asm/firmware.h> 52 #endif 53 54 /*-------------------------------------------------------------------------*/ 55 56 /* 57 * EHCI hc_driver implementation ... experimental, incomplete. 58 * Based on the final 1.0 register interface specification. 59 * 60 * USB 2.0 shows up in upcoming www.pcmcia.org technology. 61 * First was PCMCIA, like ISA; then CardBus, which is PCI. 62 * Next comes "CardBay", using USB 2.0 signals. 63 * 64 * Contains additional contributions by Brad Hards, Rory Bolt, and others. 65 * Special thanks to Intel and VIA for providing host controllers to 66 * test this driver on, and Cypress (including In-System Design) for 67 * providing early devices for those host controllers to talk to! 68 */ 69 70 #define DRIVER_AUTHOR "David Brownell" 71 #define DRIVER_DESC "USB 2.0 'Enhanced' Host Controller (EHCI) Driver" 72 73 static const char hcd_name [] = "ehci_hcd"; 74 75 76 #undef VERBOSE_DEBUG 77 #undef EHCI_URB_TRACE 78 79 #ifdef DEBUG 80 #define EHCI_STATS 81 #endif 82 83 /* magic numbers that can affect system performance */ 84 #define EHCI_TUNE_CERR 3 /* 0-3 qtd retries; 0 == don't stop */ 85 #define EHCI_TUNE_RL_HS 4 /* nak throttle; see 4.9 */ 86 #define EHCI_TUNE_RL_TT 0 87 #define EHCI_TUNE_MULT_HS 1 /* 1-3 transactions/uframe; 4.10.3 */ 88 #define EHCI_TUNE_MULT_TT 1 89 /* 90 * Some drivers think it's safe to schedule isochronous transfers more than 91 * 256 ms into the future (partly as a result of an old bug in the scheduling 92 * code). In an attempt to avoid trouble, we will use a minimum scheduling 93 * length of 512 frames instead of 256. 94 */ 95 #define EHCI_TUNE_FLS 1 /* (medium) 512-frame schedule */ 96 97 #define EHCI_IAA_MSECS 10 /* arbitrary */ 98 #define EHCI_IO_JIFFIES (HZ/10) /* io watchdog > irq_thresh */ 99 #define EHCI_ASYNC_JIFFIES (HZ/20) /* async idle timeout */ 100 #define EHCI_SHRINK_JIFFIES (DIV_ROUND_UP(HZ, 200) + 1) 101 /* 5-ms async qh unlink delay */ 102 103 /* Initial IRQ latency: faster than hw default */ 104 static int log2_irq_thresh = 0; // 0 to 6 105 module_param (log2_irq_thresh, int, S_IRUGO); 106 MODULE_PARM_DESC (log2_irq_thresh, "log2 IRQ latency, 1-64 microframes"); 107 108 /* initial park setting: slower than hw default */ 109 static unsigned park = 0; 110 module_param (park, uint, S_IRUGO); 111 MODULE_PARM_DESC (park, "park setting; 1-3 back-to-back async packets"); 112 113 /* for flakey hardware, ignore overcurrent indicators */ 114 static bool ignore_oc = 0; 115 module_param (ignore_oc, bool, S_IRUGO); 116 MODULE_PARM_DESC (ignore_oc, "ignore bogus hardware overcurrent indications"); 117 118 /* for link power management(LPM) feature */ 119 static unsigned int hird; 120 module_param(hird, int, S_IRUGO); 121 MODULE_PARM_DESC(hird, "host initiated resume duration, +1 for each 75us"); 122 123 #define INTR_MASK (STS_IAA | STS_FATAL | STS_PCD | STS_ERR | STS_INT) 124 125 /*-------------------------------------------------------------------------*/ 126 127 #include "ehci.h" 128 #include "ehci-dbg.c" 129 #include "pci-quirks.h" 130 131 /*-------------------------------------------------------------------------*/ 132 133 static void 134 timer_action(struct ehci_hcd *ehci, enum ehci_timer_action action) 135 { 136 /* Don't override timeouts which shrink or (later) disable 137 * the async ring; just the I/O watchdog. Note that if a 138 * SHRINK were pending, OFF would never be requested. 139 */ 140 if (timer_pending(&ehci->watchdog) 141 && ((BIT(TIMER_ASYNC_SHRINK) | BIT(TIMER_ASYNC_OFF)) 142 & ehci->actions)) 143 return; 144 145 if (!test_and_set_bit(action, &ehci->actions)) { 146 unsigned long t; 147 148 switch (action) { 149 case TIMER_IO_WATCHDOG: 150 if (!ehci->need_io_watchdog) 151 return; 152 t = EHCI_IO_JIFFIES; 153 break; 154 case TIMER_ASYNC_OFF: 155 t = EHCI_ASYNC_JIFFIES; 156 break; 157 /* case TIMER_ASYNC_SHRINK: */ 158 default: 159 t = EHCI_SHRINK_JIFFIES; 160 break; 161 } 162 mod_timer(&ehci->watchdog, t + jiffies); 163 } 164 } 165 166 /*-------------------------------------------------------------------------*/ 167 168 /* 169 * handshake - spin reading hc until handshake completes or fails 170 * @ptr: address of hc register to be read 171 * @mask: bits to look at in result of read 172 * @done: value of those bits when handshake succeeds 173 * @usec: timeout in microseconds 174 * 175 * Returns negative errno, or zero on success 176 * 177 * Success happens when the "mask" bits have the specified value (hardware 178 * handshake done). There are two failure modes: "usec" have passed (major 179 * hardware flakeout), or the register reads as all-ones (hardware removed). 180 * 181 * That last failure should_only happen in cases like physical cardbus eject 182 * before driver shutdown. But it also seems to be caused by bugs in cardbus 183 * bridge shutdown: shutting down the bridge before the devices using it. 184 */ 185 static int handshake (struct ehci_hcd *ehci, void __iomem *ptr, 186 u32 mask, u32 done, int usec) 187 { 188 u32 result; 189 190 do { 191 result = ehci_readl(ehci, ptr); 192 if (result == ~(u32)0) /* card removed */ 193 return -ENODEV; 194 result &= mask; 195 if (result == done) 196 return 0; 197 udelay (1); 198 usec--; 199 } while (usec > 0); 200 return -ETIMEDOUT; 201 } 202 203 /* check TDI/ARC silicon is in host mode */ 204 static int tdi_in_host_mode (struct ehci_hcd *ehci) 205 { 206 u32 __iomem *reg_ptr; 207 u32 tmp; 208 209 reg_ptr = (u32 __iomem *)(((u8 __iomem *)ehci->regs) + USBMODE); 210 tmp = ehci_readl(ehci, reg_ptr); 211 return (tmp & 3) == USBMODE_CM_HC; 212 } 213 214 /* force HC to halt state from unknown (EHCI spec section 2.3) */ 215 static int ehci_halt (struct ehci_hcd *ehci) 216 { 217 u32 temp = ehci_readl(ehci, &ehci->regs->status); 218 219 /* disable any irqs left enabled by previous code */ 220 ehci_writel(ehci, 0, &ehci->regs->intr_enable); 221 222 if (ehci_is_TDI(ehci) && tdi_in_host_mode(ehci) == 0) { 223 return 0; 224 } 225 226 if ((temp & STS_HALT) != 0) 227 return 0; 228 229 temp = ehci_readl(ehci, &ehci->regs->command); 230 temp &= ~CMD_RUN; 231 ehci_writel(ehci, temp, &ehci->regs->command); 232 return handshake (ehci, &ehci->regs->status, 233 STS_HALT, STS_HALT, 16 * 125); 234 } 235 236 #if defined(CONFIG_USB_SUSPEND) && defined(CONFIG_PPC_PS3) 237 238 /* 239 * The EHCI controller of the Cell Super Companion Chip used in the 240 * PS3 will stop the root hub after all root hub ports are suspended. 241 * When in this condition handshake will return -ETIMEDOUT. The 242 * STS_HLT bit will not be set, so inspection of the frame index is 243 * used here to test for the condition. If the condition is found 244 * return success to allow the USB suspend to complete. 245 */ 246 247 static int handshake_for_broken_root_hub(struct ehci_hcd *ehci, 248 void __iomem *ptr, u32 mask, u32 done, 249 int usec) 250 { 251 unsigned int old_index; 252 int error; 253 254 if (!firmware_has_feature(FW_FEATURE_PS3_LV1)) 255 return -ETIMEDOUT; 256 257 old_index = ehci_read_frame_index(ehci); 258 259 error = handshake(ehci, ptr, mask, done, usec); 260 261 if (error == -ETIMEDOUT && ehci_read_frame_index(ehci) == old_index) 262 return 0; 263 264 return error; 265 } 266 267 #else 268 269 static int handshake_for_broken_root_hub(struct ehci_hcd *ehci, 270 void __iomem *ptr, u32 mask, u32 done, 271 int usec) 272 { 273 return -ETIMEDOUT; 274 } 275 276 #endif 277 278 static int handshake_on_error_set_halt(struct ehci_hcd *ehci, void __iomem *ptr, 279 u32 mask, u32 done, int usec) 280 { 281 int error; 282 283 error = handshake(ehci, ptr, mask, done, usec); 284 if (error == -ETIMEDOUT) 285 error = handshake_for_broken_root_hub(ehci, ptr, mask, done, 286 usec); 287 288 if (error) { 289 ehci_halt(ehci); 290 ehci->rh_state = EHCI_RH_HALTED; 291 ehci_err(ehci, "force halt; handshake %p %08x %08x -> %d\n", 292 ptr, mask, done, error); 293 } 294 295 return error; 296 } 297 298 /* put TDI/ARC silicon into EHCI mode */ 299 static void tdi_reset (struct ehci_hcd *ehci) 300 { 301 u32 __iomem *reg_ptr; 302 u32 tmp; 303 304 reg_ptr = (u32 __iomem *)(((u8 __iomem *)ehci->regs) + USBMODE); 305 tmp = ehci_readl(ehci, reg_ptr); 306 tmp |= USBMODE_CM_HC; 307 /* The default byte access to MMR space is LE after 308 * controller reset. Set the required endian mode 309 * for transfer buffers to match the host microprocessor 310 */ 311 if (ehci_big_endian_mmio(ehci)) 312 tmp |= USBMODE_BE; 313 ehci_writel(ehci, tmp, reg_ptr); 314 } 315 316 /* reset a non-running (STS_HALT == 1) controller */ 317 static int ehci_reset (struct ehci_hcd *ehci) 318 { 319 int retval; 320 u32 command = ehci_readl(ehci, &ehci->regs->command); 321 322 /* If the EHCI debug controller is active, special care must be 323 * taken before and after a host controller reset */ 324 if (ehci->debug && !dbgp_reset_prep()) 325 ehci->debug = NULL; 326 327 command |= CMD_RESET; 328 dbg_cmd (ehci, "reset", command); 329 ehci_writel(ehci, command, &ehci->regs->command); 330 ehci->rh_state = EHCI_RH_HALTED; 331 ehci->next_statechange = jiffies; 332 retval = handshake (ehci, &ehci->regs->command, 333 CMD_RESET, 0, 250 * 1000); 334 335 if (ehci->has_hostpc) { 336 ehci_writel(ehci, USBMODE_EX_HC | USBMODE_EX_VBPS, 337 (u32 __iomem *)(((u8 *)ehci->regs) + USBMODE_EX)); 338 ehci_writel(ehci, TXFIFO_DEFAULT, 339 (u32 __iomem *)(((u8 *)ehci->regs) + TXFILLTUNING)); 340 } 341 if (retval) 342 return retval; 343 344 if (ehci_is_TDI(ehci)) 345 tdi_reset (ehci); 346 347 if (ehci->debug) 348 dbgp_external_startup(); 349 350 ehci->port_c_suspend = ehci->suspended_ports = 351 ehci->resuming_ports = 0; 352 return retval; 353 } 354 355 /* idle the controller (from running) */ 356 static void ehci_quiesce (struct ehci_hcd *ehci) 357 { 358 u32 temp; 359 360 #ifdef DEBUG 361 if (ehci->rh_state != EHCI_RH_RUNNING) 362 BUG (); 363 #endif 364 365 /* wait for any schedule enables/disables to take effect */ 366 temp = ehci_readl(ehci, &ehci->regs->command) << 10; 367 temp &= STS_ASS | STS_PSS; 368 if (handshake_on_error_set_halt(ehci, &ehci->regs->status, 369 STS_ASS | STS_PSS, temp, 16 * 125)) 370 return; 371 372 /* then disable anything that's still active */ 373 temp = ehci_readl(ehci, &ehci->regs->command); 374 temp &= ~(CMD_ASE | CMD_IAAD | CMD_PSE); 375 ehci_writel(ehci, temp, &ehci->regs->command); 376 377 /* hardware can take 16 microframes to turn off ... */ 378 handshake_on_error_set_halt(ehci, &ehci->regs->status, 379 STS_ASS | STS_PSS, 0, 16 * 125); 380 } 381 382 /*-------------------------------------------------------------------------*/ 383 384 static void end_unlink_async(struct ehci_hcd *ehci); 385 static void ehci_work(struct ehci_hcd *ehci); 386 387 #include "ehci-hub.c" 388 #include "ehci-lpm.c" 389 #include "ehci-mem.c" 390 #include "ehci-q.c" 391 #include "ehci-sched.c" 392 #include "ehci-sysfs.c" 393 394 /*-------------------------------------------------------------------------*/ 395 396 static void ehci_iaa_watchdog(unsigned long param) 397 { 398 struct ehci_hcd *ehci = (struct ehci_hcd *) param; 399 unsigned long flags; 400 401 spin_lock_irqsave (&ehci->lock, flags); 402 403 /* Lost IAA irqs wedge things badly; seen first with a vt8235. 404 * So we need this watchdog, but must protect it against both 405 * (a) SMP races against real IAA firing and retriggering, and 406 * (b) clean HC shutdown, when IAA watchdog was pending. 407 */ 408 if (ehci->reclaim 409 && !timer_pending(&ehci->iaa_watchdog) 410 && ehci->rh_state == EHCI_RH_RUNNING) { 411 u32 cmd, status; 412 413 /* If we get here, IAA is *REALLY* late. It's barely 414 * conceivable that the system is so busy that CMD_IAAD 415 * is still legitimately set, so let's be sure it's 416 * clear before we read STS_IAA. (The HC should clear 417 * CMD_IAAD when it sets STS_IAA.) 418 */ 419 cmd = ehci_readl(ehci, &ehci->regs->command); 420 if (cmd & CMD_IAAD) 421 ehci_writel(ehci, cmd & ~CMD_IAAD, 422 &ehci->regs->command); 423 424 /* If IAA is set here it either legitimately triggered 425 * before we cleared IAAD above (but _way_ late, so we'll 426 * still count it as lost) ... or a silicon erratum: 427 * - VIA seems to set IAA without triggering the IRQ; 428 * - IAAD potentially cleared without setting IAA. 429 */ 430 status = ehci_readl(ehci, &ehci->regs->status); 431 if ((status & STS_IAA) || !(cmd & CMD_IAAD)) { 432 COUNT (ehci->stats.lost_iaa); 433 ehci_writel(ehci, STS_IAA, &ehci->regs->status); 434 } 435 436 ehci_vdbg(ehci, "IAA watchdog: status %x cmd %x\n", 437 status, cmd); 438 end_unlink_async(ehci); 439 } 440 441 spin_unlock_irqrestore(&ehci->lock, flags); 442 } 443 444 static void ehci_watchdog(unsigned long param) 445 { 446 struct ehci_hcd *ehci = (struct ehci_hcd *) param; 447 unsigned long flags; 448 449 spin_lock_irqsave(&ehci->lock, flags); 450 451 /* stop async processing after it's idled a bit */ 452 if (test_bit (TIMER_ASYNC_OFF, &ehci->actions)) 453 start_unlink_async (ehci, ehci->async); 454 455 /* ehci could run by timer, without IRQs ... */ 456 ehci_work (ehci); 457 458 spin_unlock_irqrestore (&ehci->lock, flags); 459 } 460 461 /* On some systems, leaving remote wakeup enabled prevents system shutdown. 462 * The firmware seems to think that powering off is a wakeup event! 463 * This routine turns off remote wakeup and everything else, on all ports. 464 */ 465 static void ehci_turn_off_all_ports(struct ehci_hcd *ehci) 466 { 467 int port = HCS_N_PORTS(ehci->hcs_params); 468 469 while (port--) 470 ehci_writel(ehci, PORT_RWC_BITS, 471 &ehci->regs->port_status[port]); 472 } 473 474 /* 475 * Halt HC, turn off all ports, and let the BIOS use the companion controllers. 476 * Should be called with ehci->lock held. 477 */ 478 static void ehci_silence_controller(struct ehci_hcd *ehci) 479 { 480 ehci_halt(ehci); 481 ehci_turn_off_all_ports(ehci); 482 483 /* make BIOS/etc use companion controller during reboot */ 484 ehci_writel(ehci, 0, &ehci->regs->configured_flag); 485 486 /* unblock posted writes */ 487 ehci_readl(ehci, &ehci->regs->configured_flag); 488 } 489 490 /* ehci_shutdown kick in for silicon on any bus (not just pci, etc). 491 * This forcibly disables dma and IRQs, helping kexec and other cases 492 * where the next system software may expect clean state. 493 */ 494 static void ehci_shutdown(struct usb_hcd *hcd) 495 { 496 struct ehci_hcd *ehci = hcd_to_ehci(hcd); 497 498 del_timer_sync(&ehci->watchdog); 499 del_timer_sync(&ehci->iaa_watchdog); 500 501 spin_lock_irq(&ehci->lock); 502 ehci_silence_controller(ehci); 503 spin_unlock_irq(&ehci->lock); 504 } 505 506 static void ehci_port_power (struct ehci_hcd *ehci, int is_on) 507 { 508 unsigned port; 509 510 if (!HCS_PPC (ehci->hcs_params)) 511 return; 512 513 ehci_dbg (ehci, "...power%s ports...\n", is_on ? "up" : "down"); 514 for (port = HCS_N_PORTS (ehci->hcs_params); port > 0; ) 515 (void) ehci_hub_control(ehci_to_hcd(ehci), 516 is_on ? SetPortFeature : ClearPortFeature, 517 USB_PORT_FEAT_POWER, 518 port--, NULL, 0); 519 /* Flush those writes */ 520 ehci_readl(ehci, &ehci->regs->command); 521 msleep(20); 522 } 523 524 /*-------------------------------------------------------------------------*/ 525 526 /* 527 * ehci_work is called from some interrupts, timers, and so on. 528 * it calls driver completion functions, after dropping ehci->lock. 529 */ 530 static void ehci_work (struct ehci_hcd *ehci) 531 { 532 timer_action_done (ehci, TIMER_IO_WATCHDOG); 533 534 /* another CPU may drop ehci->lock during a schedule scan while 535 * it reports urb completions. this flag guards against bogus 536 * attempts at re-entrant schedule scanning. 537 */ 538 if (ehci->scanning) 539 return; 540 ehci->scanning = 1; 541 scan_async (ehci); 542 if (ehci->next_uframe != -1) 543 scan_periodic (ehci); 544 ehci->scanning = 0; 545 546 /* the IO watchdog guards against hardware or driver bugs that 547 * misplace IRQs, and should let us run completely without IRQs. 548 * such lossage has been observed on both VT6202 and VT8235. 549 */ 550 if (ehci->rh_state == EHCI_RH_RUNNING && 551 (ehci->async->qh_next.ptr != NULL || 552 ehci->periodic_sched != 0)) 553 timer_action (ehci, TIMER_IO_WATCHDOG); 554 } 555 556 /* 557 * Called when the ehci_hcd module is removed. 558 */ 559 static void ehci_stop (struct usb_hcd *hcd) 560 { 561 struct ehci_hcd *ehci = hcd_to_ehci (hcd); 562 563 ehci_dbg (ehci, "stop\n"); 564 565 /* no more interrupts ... */ 566 del_timer_sync (&ehci->watchdog); 567 del_timer_sync(&ehci->iaa_watchdog); 568 569 spin_lock_irq(&ehci->lock); 570 if (ehci->rh_state == EHCI_RH_RUNNING) 571 ehci_quiesce (ehci); 572 573 ehci_silence_controller(ehci); 574 ehci_reset (ehci); 575 spin_unlock_irq(&ehci->lock); 576 577 remove_sysfs_files(ehci); 578 remove_debug_files (ehci); 579 580 /* root hub is shut down separately (first, when possible) */ 581 spin_lock_irq (&ehci->lock); 582 if (ehci->async) 583 ehci_work (ehci); 584 spin_unlock_irq (&ehci->lock); 585 ehci_mem_cleanup (ehci); 586 587 if (ehci->amd_pll_fix == 1) 588 usb_amd_dev_put(); 589 590 #ifdef EHCI_STATS 591 ehci_dbg (ehci, "irq normal %ld err %ld reclaim %ld (lost %ld)\n", 592 ehci->stats.normal, ehci->stats.error, ehci->stats.reclaim, 593 ehci->stats.lost_iaa); 594 ehci_dbg (ehci, "complete %ld unlink %ld\n", 595 ehci->stats.complete, ehci->stats.unlink); 596 #endif 597 598 dbg_status (ehci, "ehci_stop completed", 599 ehci_readl(ehci, &ehci->regs->status)); 600 } 601 602 /* one-time init, only for memory state */ 603 static int ehci_init(struct usb_hcd *hcd) 604 { 605 struct ehci_hcd *ehci = hcd_to_ehci(hcd); 606 u32 temp; 607 int retval; 608 u32 hcc_params; 609 struct ehci_qh_hw *hw; 610 611 spin_lock_init(&ehci->lock); 612 613 /* 614 * keep io watchdog by default, those good HCDs could turn off it later 615 */ 616 ehci->need_io_watchdog = 1; 617 init_timer(&ehci->watchdog); 618 ehci->watchdog.function = ehci_watchdog; 619 ehci->watchdog.data = (unsigned long) ehci; 620 621 init_timer(&ehci->iaa_watchdog); 622 ehci->iaa_watchdog.function = ehci_iaa_watchdog; 623 ehci->iaa_watchdog.data = (unsigned long) ehci; 624 625 hcc_params = ehci_readl(ehci, &ehci->caps->hcc_params); 626 627 /* 628 * by default set standard 80% (== 100 usec/uframe) max periodic 629 * bandwidth as required by USB 2.0 630 */ 631 ehci->uframe_periodic_max = 100; 632 633 /* 634 * hw default: 1K periodic list heads, one per frame. 635 * periodic_size can shrink by USBCMD update if hcc_params allows. 636 */ 637 ehci->periodic_size = DEFAULT_I_TDPS; 638 INIT_LIST_HEAD(&ehci->cached_itd_list); 639 INIT_LIST_HEAD(&ehci->cached_sitd_list); 640 641 if (HCC_PGM_FRAMELISTLEN(hcc_params)) { 642 /* periodic schedule size can be smaller than default */ 643 switch (EHCI_TUNE_FLS) { 644 case 0: ehci->periodic_size = 1024; break; 645 case 1: ehci->periodic_size = 512; break; 646 case 2: ehci->periodic_size = 256; break; 647 default: BUG(); 648 } 649 } 650 if ((retval = ehci_mem_init(ehci, GFP_KERNEL)) < 0) 651 return retval; 652 653 /* controllers may cache some of the periodic schedule ... */ 654 if (HCC_ISOC_CACHE(hcc_params)) // full frame cache 655 ehci->i_thresh = 2 + 8; 656 else // N microframes cached 657 ehci->i_thresh = 2 + HCC_ISOC_THRES(hcc_params); 658 659 ehci->reclaim = NULL; 660 ehci->next_uframe = -1; 661 ehci->clock_frame = -1; 662 663 /* 664 * dedicate a qh for the async ring head, since we couldn't unlink 665 * a 'real' qh without stopping the async schedule [4.8]. use it 666 * as the 'reclamation list head' too. 667 * its dummy is used in hw_alt_next of many tds, to prevent the qh 668 * from automatically advancing to the next td after short reads. 669 */ 670 ehci->async->qh_next.qh = NULL; 671 hw = ehci->async->hw; 672 hw->hw_next = QH_NEXT(ehci, ehci->async->qh_dma); 673 hw->hw_info1 = cpu_to_hc32(ehci, QH_HEAD); 674 hw->hw_info1 |= cpu_to_hc32(ehci, (1 << 7)); /* I = 1 */ 675 hw->hw_token = cpu_to_hc32(ehci, QTD_STS_HALT); 676 hw->hw_qtd_next = EHCI_LIST_END(ehci); 677 ehci->async->qh_state = QH_STATE_LINKED; 678 hw->hw_alt_next = QTD_NEXT(ehci, ehci->async->dummy->qtd_dma); 679 680 /* clear interrupt enables, set irq latency */ 681 if (log2_irq_thresh < 0 || log2_irq_thresh > 6) 682 log2_irq_thresh = 0; 683 temp = 1 << (16 + log2_irq_thresh); 684 if (HCC_PER_PORT_CHANGE_EVENT(hcc_params)) { 685 ehci->has_ppcd = 1; 686 ehci_dbg(ehci, "enable per-port change event\n"); 687 temp |= CMD_PPCEE; 688 } 689 if (HCC_CANPARK(hcc_params)) { 690 /* HW default park == 3, on hardware that supports it (like 691 * NVidia and ALI silicon), maximizes throughput on the async 692 * schedule by avoiding QH fetches between transfers. 693 * 694 * With fast usb storage devices and NForce2, "park" seems to 695 * make problems: throughput reduction (!), data errors... 696 */ 697 if (park) { 698 park = min(park, (unsigned) 3); 699 temp |= CMD_PARK; 700 temp |= park << 8; 701 } 702 ehci_dbg(ehci, "park %d\n", park); 703 } 704 if (HCC_PGM_FRAMELISTLEN(hcc_params)) { 705 /* periodic schedule size can be smaller than default */ 706 temp &= ~(3 << 2); 707 temp |= (EHCI_TUNE_FLS << 2); 708 } 709 if (HCC_LPM(hcc_params)) { 710 /* support link power management EHCI 1.1 addendum */ 711 ehci_dbg(ehci, "support lpm\n"); 712 ehci->has_lpm = 1; 713 if (hird > 0xf) { 714 ehci_dbg(ehci, "hird %d invalid, use default 0", 715 hird); 716 hird = 0; 717 } 718 temp |= hird << 24; 719 } 720 ehci->command = temp; 721 722 /* Accept arbitrarily long scatter-gather lists */ 723 if (!(hcd->driver->flags & HCD_LOCAL_MEM)) 724 hcd->self.sg_tablesize = ~0; 725 return 0; 726 } 727 728 /* start HC running; it's halted, ehci_init() has been run (once) */ 729 static int ehci_run (struct usb_hcd *hcd) 730 { 731 struct ehci_hcd *ehci = hcd_to_ehci (hcd); 732 u32 temp; 733 u32 hcc_params; 734 735 hcd->uses_new_polling = 1; 736 737 /* EHCI spec section 4.1 */ 738 739 ehci_writel(ehci, ehci->periodic_dma, &ehci->regs->frame_list); 740 ehci_writel(ehci, (u32)ehci->async->qh_dma, &ehci->regs->async_next); 741 742 /* 743 * hcc_params controls whether ehci->regs->segment must (!!!) 744 * be used; it constrains QH/ITD/SITD and QTD locations. 745 * pci_pool consistent memory always uses segment zero. 746 * streaming mappings for I/O buffers, like pci_map_single(), 747 * can return segments above 4GB, if the device allows. 748 * 749 * NOTE: the dma mask is visible through dma_supported(), so 750 * drivers can pass this info along ... like NETIF_F_HIGHDMA, 751 * Scsi_Host.highmem_io, and so forth. It's readonly to all 752 * host side drivers though. 753 */ 754 hcc_params = ehci_readl(ehci, &ehci->caps->hcc_params); 755 if (HCC_64BIT_ADDR(hcc_params)) { 756 ehci_writel(ehci, 0, &ehci->regs->segment); 757 #if 0 758 // this is deeply broken on almost all architectures 759 if (!dma_set_mask(hcd->self.controller, DMA_BIT_MASK(64))) 760 ehci_info(ehci, "enabled 64bit DMA\n"); 761 #endif 762 } 763 764 765 // Philips, Intel, and maybe others need CMD_RUN before the 766 // root hub will detect new devices (why?); NEC doesn't 767 ehci->command &= ~(CMD_LRESET|CMD_IAAD|CMD_PSE|CMD_ASE|CMD_RESET); 768 ehci->command |= CMD_RUN; 769 ehci_writel(ehci, ehci->command, &ehci->regs->command); 770 dbg_cmd (ehci, "init", ehci->command); 771 772 /* 773 * Start, enabling full USB 2.0 functionality ... usb 1.1 devices 774 * are explicitly handed to companion controller(s), so no TT is 775 * involved with the root hub. (Except where one is integrated, 776 * and there's no companion controller unless maybe for USB OTG.) 777 * 778 * Turning on the CF flag will transfer ownership of all ports 779 * from the companions to the EHCI controller. If any of the 780 * companions are in the middle of a port reset at the time, it 781 * could cause trouble. Write-locking ehci_cf_port_reset_rwsem 782 * guarantees that no resets are in progress. After we set CF, 783 * a short delay lets the hardware catch up; new resets shouldn't 784 * be started before the port switching actions could complete. 785 */ 786 down_write(&ehci_cf_port_reset_rwsem); 787 ehci->rh_state = EHCI_RH_RUNNING; 788 ehci_writel(ehci, FLAG_CF, &ehci->regs->configured_flag); 789 ehci_readl(ehci, &ehci->regs->command); /* unblock posted writes */ 790 msleep(5); 791 up_write(&ehci_cf_port_reset_rwsem); 792 ehci->last_periodic_enable = ktime_get_real(); 793 794 temp = HC_VERSION(ehci, ehci_readl(ehci, &ehci->caps->hc_capbase)); 795 ehci_info (ehci, 796 "USB %x.%x started, EHCI %x.%02x%s\n", 797 ((ehci->sbrn & 0xf0)>>4), (ehci->sbrn & 0x0f), 798 temp >> 8, temp & 0xff, 799 ignore_oc ? ", overcurrent ignored" : ""); 800 801 ehci_writel(ehci, INTR_MASK, 802 &ehci->regs->intr_enable); /* Turn On Interrupts */ 803 804 /* GRR this is run-once init(), being done every time the HC starts. 805 * So long as they're part of class devices, we can't do it init() 806 * since the class device isn't created that early. 807 */ 808 create_debug_files(ehci); 809 create_sysfs_files(ehci); 810 811 return 0; 812 } 813 814 static int __maybe_unused ehci_setup (struct usb_hcd *hcd) 815 { 816 struct ehci_hcd *ehci = hcd_to_ehci(hcd); 817 int retval; 818 819 ehci->regs = (void __iomem *)ehci->caps + 820 HC_LENGTH(ehci, ehci_readl(ehci, &ehci->caps->hc_capbase)); 821 dbg_hcs_params(ehci, "reset"); 822 dbg_hcc_params(ehci, "reset"); 823 824 /* cache this readonly data; minimize chip reads */ 825 ehci->hcs_params = ehci_readl(ehci, &ehci->caps->hcs_params); 826 827 ehci->sbrn = HCD_USB2; 828 829 retval = ehci_halt(ehci); 830 if (retval) 831 return retval; 832 833 /* data structure init */ 834 retval = ehci_init(hcd); 835 if (retval) 836 return retval; 837 838 ehci_reset(ehci); 839 840 return 0; 841 } 842 843 /*-------------------------------------------------------------------------*/ 844 845 static irqreturn_t ehci_irq (struct usb_hcd *hcd) 846 { 847 struct ehci_hcd *ehci = hcd_to_ehci (hcd); 848 u32 status, masked_status, pcd_status = 0, cmd; 849 int bh; 850 851 spin_lock (&ehci->lock); 852 853 status = ehci_readl(ehci, &ehci->regs->status); 854 855 /* e.g. cardbus physical eject */ 856 if (status == ~(u32) 0) { 857 ehci_dbg (ehci, "device removed\n"); 858 goto dead; 859 } 860 861 /* 862 * We don't use STS_FLR, but some controllers don't like it to 863 * remain on, so mask it out along with the other status bits. 864 */ 865 masked_status = status & (INTR_MASK | STS_FLR); 866 867 /* Shared IRQ? */ 868 if (!masked_status || unlikely(ehci->rh_state == EHCI_RH_HALTED)) { 869 spin_unlock(&ehci->lock); 870 return IRQ_NONE; 871 } 872 873 /* clear (just) interrupts */ 874 ehci_writel(ehci, masked_status, &ehci->regs->status); 875 cmd = ehci_readl(ehci, &ehci->regs->command); 876 bh = 0; 877 878 #ifdef VERBOSE_DEBUG 879 /* unrequested/ignored: Frame List Rollover */ 880 dbg_status (ehci, "irq", status); 881 #endif 882 883 /* INT, ERR, and IAA interrupt rates can be throttled */ 884 885 /* normal [4.15.1.2] or error [4.15.1.1] completion */ 886 if (likely ((status & (STS_INT|STS_ERR)) != 0)) { 887 if (likely ((status & STS_ERR) == 0)) 888 COUNT (ehci->stats.normal); 889 else 890 COUNT (ehci->stats.error); 891 bh = 1; 892 } 893 894 /* complete the unlinking of some qh [4.15.2.3] */ 895 if (status & STS_IAA) { 896 /* guard against (alleged) silicon errata */ 897 if (cmd & CMD_IAAD) { 898 ehci_writel(ehci, cmd & ~CMD_IAAD, 899 &ehci->regs->command); 900 ehci_dbg(ehci, "IAA with IAAD still set?\n"); 901 } 902 if (ehci->reclaim) { 903 COUNT(ehci->stats.reclaim); 904 end_unlink_async(ehci); 905 } else 906 ehci_dbg(ehci, "IAA with nothing to reclaim?\n"); 907 } 908 909 /* remote wakeup [4.3.1] */ 910 if (status & STS_PCD) { 911 unsigned i = HCS_N_PORTS (ehci->hcs_params); 912 u32 ppcd = 0; 913 914 /* kick root hub later */ 915 pcd_status = status; 916 917 /* resume root hub? */ 918 if (ehci->rh_state == EHCI_RH_SUSPENDED) 919 usb_hcd_resume_root_hub(hcd); 920 921 /* get per-port change detect bits */ 922 if (ehci->has_ppcd) 923 ppcd = status >> 16; 924 925 while (i--) { 926 int pstatus; 927 928 /* leverage per-port change bits feature */ 929 if (ehci->has_ppcd && !(ppcd & (1 << i))) 930 continue; 931 pstatus = ehci_readl(ehci, 932 &ehci->regs->port_status[i]); 933 934 if (pstatus & PORT_OWNER) 935 continue; 936 if (!(test_bit(i, &ehci->suspended_ports) && 937 ((pstatus & PORT_RESUME) || 938 !(pstatus & PORT_SUSPEND)) && 939 (pstatus & PORT_PE) && 940 ehci->reset_done[i] == 0)) 941 continue; 942 943 /* start 20 msec resume signaling from this port, 944 * and make khubd collect PORT_STAT_C_SUSPEND to 945 * stop that signaling. Use 5 ms extra for safety, 946 * like usb_port_resume() does. 947 */ 948 ehci->reset_done[i] = jiffies + msecs_to_jiffies(25); 949 set_bit(i, &ehci->resuming_ports); 950 ehci_dbg (ehci, "port %d remote wakeup\n", i + 1); 951 mod_timer(&hcd->rh_timer, ehci->reset_done[i]); 952 } 953 } 954 955 /* PCI errors [4.15.2.4] */ 956 if (unlikely ((status & STS_FATAL) != 0)) { 957 ehci_err(ehci, "fatal error\n"); 958 dbg_cmd(ehci, "fatal", cmd); 959 dbg_status(ehci, "fatal", status); 960 ehci_halt(ehci); 961 dead: 962 ehci_reset(ehci); 963 ehci_writel(ehci, 0, &ehci->regs->configured_flag); 964 usb_hc_died(hcd); 965 /* generic layer kills/unlinks all urbs, then 966 * uses ehci_stop to clean up the rest 967 */ 968 bh = 1; 969 } 970 971 if (bh) 972 ehci_work (ehci); 973 spin_unlock (&ehci->lock); 974 if (pcd_status) 975 usb_hcd_poll_rh_status(hcd); 976 return IRQ_HANDLED; 977 } 978 979 /*-------------------------------------------------------------------------*/ 980 981 /* 982 * non-error returns are a promise to giveback() the urb later 983 * we drop ownership so next owner (or urb unlink) can get it 984 * 985 * urb + dev is in hcd.self.controller.urb_list 986 * we're queueing TDs onto software and hardware lists 987 * 988 * hcd-specific init for hcpriv hasn't been done yet 989 * 990 * NOTE: control, bulk, and interrupt share the same code to append TDs 991 * to a (possibly active) QH, and the same QH scanning code. 992 */ 993 static int ehci_urb_enqueue ( 994 struct usb_hcd *hcd, 995 struct urb *urb, 996 gfp_t mem_flags 997 ) { 998 struct ehci_hcd *ehci = hcd_to_ehci (hcd); 999 struct list_head qtd_list; 1000 1001 INIT_LIST_HEAD (&qtd_list); 1002 1003 switch (usb_pipetype (urb->pipe)) { 1004 case PIPE_CONTROL: 1005 /* qh_completions() code doesn't handle all the fault cases 1006 * in multi-TD control transfers. Even 1KB is rare anyway. 1007 */ 1008 if (urb->transfer_buffer_length > (16 * 1024)) 1009 return -EMSGSIZE; 1010 /* FALLTHROUGH */ 1011 /* case PIPE_BULK: */ 1012 default: 1013 if (!qh_urb_transaction (ehci, urb, &qtd_list, mem_flags)) 1014 return -ENOMEM; 1015 return submit_async(ehci, urb, &qtd_list, mem_flags); 1016 1017 case PIPE_INTERRUPT: 1018 if (!qh_urb_transaction (ehci, urb, &qtd_list, mem_flags)) 1019 return -ENOMEM; 1020 return intr_submit(ehci, urb, &qtd_list, mem_flags); 1021 1022 case PIPE_ISOCHRONOUS: 1023 if (urb->dev->speed == USB_SPEED_HIGH) 1024 return itd_submit (ehci, urb, mem_flags); 1025 else 1026 return sitd_submit (ehci, urb, mem_flags); 1027 } 1028 } 1029 1030 static void unlink_async (struct ehci_hcd *ehci, struct ehci_qh *qh) 1031 { 1032 /* failfast */ 1033 if (ehci->rh_state != EHCI_RH_RUNNING && ehci->reclaim) 1034 end_unlink_async(ehci); 1035 1036 /* If the QH isn't linked then there's nothing we can do 1037 * unless we were called during a giveback, in which case 1038 * qh_completions() has to deal with it. 1039 */ 1040 if (qh->qh_state != QH_STATE_LINKED) { 1041 if (qh->qh_state == QH_STATE_COMPLETING) 1042 qh->needs_rescan = 1; 1043 return; 1044 } 1045 1046 /* defer till later if busy */ 1047 if (ehci->reclaim) { 1048 struct ehci_qh *last; 1049 1050 for (last = ehci->reclaim; 1051 last->reclaim; 1052 last = last->reclaim) 1053 continue; 1054 qh->qh_state = QH_STATE_UNLINK_WAIT; 1055 last->reclaim = qh; 1056 1057 /* start IAA cycle */ 1058 } else 1059 start_unlink_async (ehci, qh); 1060 } 1061 1062 /* remove from hardware lists 1063 * completions normally happen asynchronously 1064 */ 1065 1066 static int ehci_urb_dequeue(struct usb_hcd *hcd, struct urb *urb, int status) 1067 { 1068 struct ehci_hcd *ehci = hcd_to_ehci (hcd); 1069 struct ehci_qh *qh; 1070 unsigned long flags; 1071 int rc; 1072 1073 spin_lock_irqsave (&ehci->lock, flags); 1074 rc = usb_hcd_check_unlink_urb(hcd, urb, status); 1075 if (rc) 1076 goto done; 1077 1078 switch (usb_pipetype (urb->pipe)) { 1079 // case PIPE_CONTROL: 1080 // case PIPE_BULK: 1081 default: 1082 qh = (struct ehci_qh *) urb->hcpriv; 1083 if (!qh) 1084 break; 1085 switch (qh->qh_state) { 1086 case QH_STATE_LINKED: 1087 case QH_STATE_COMPLETING: 1088 unlink_async(ehci, qh); 1089 break; 1090 case QH_STATE_UNLINK: 1091 case QH_STATE_UNLINK_WAIT: 1092 /* already started */ 1093 break; 1094 case QH_STATE_IDLE: 1095 /* QH might be waiting for a Clear-TT-Buffer */ 1096 qh_completions(ehci, qh); 1097 break; 1098 } 1099 break; 1100 1101 case PIPE_INTERRUPT: 1102 qh = (struct ehci_qh *) urb->hcpriv; 1103 if (!qh) 1104 break; 1105 switch (qh->qh_state) { 1106 case QH_STATE_LINKED: 1107 case QH_STATE_COMPLETING: 1108 intr_deschedule (ehci, qh); 1109 break; 1110 case QH_STATE_IDLE: 1111 qh_completions (ehci, qh); 1112 break; 1113 default: 1114 ehci_dbg (ehci, "bogus qh %p state %d\n", 1115 qh, qh->qh_state); 1116 goto done; 1117 } 1118 break; 1119 1120 case PIPE_ISOCHRONOUS: 1121 // itd or sitd ... 1122 1123 // wait till next completion, do it then. 1124 // completion irqs can wait up to 1024 msec, 1125 break; 1126 } 1127 done: 1128 spin_unlock_irqrestore (&ehci->lock, flags); 1129 return rc; 1130 } 1131 1132 /*-------------------------------------------------------------------------*/ 1133 1134 // bulk qh holds the data toggle 1135 1136 static void 1137 ehci_endpoint_disable (struct usb_hcd *hcd, struct usb_host_endpoint *ep) 1138 { 1139 struct ehci_hcd *ehci = hcd_to_ehci (hcd); 1140 unsigned long flags; 1141 struct ehci_qh *qh, *tmp; 1142 1143 /* ASSERT: any requests/urbs are being unlinked */ 1144 /* ASSERT: nobody can be submitting urbs for this any more */ 1145 1146 rescan: 1147 spin_lock_irqsave (&ehci->lock, flags); 1148 qh = ep->hcpriv; 1149 if (!qh) 1150 goto done; 1151 1152 /* endpoints can be iso streams. for now, we don't 1153 * accelerate iso completions ... so spin a while. 1154 */ 1155 if (qh->hw == NULL) { 1156 ehci_vdbg (ehci, "iso delay\n"); 1157 goto idle_timeout; 1158 } 1159 1160 if (ehci->rh_state != EHCI_RH_RUNNING) 1161 qh->qh_state = QH_STATE_IDLE; 1162 switch (qh->qh_state) { 1163 case QH_STATE_LINKED: 1164 case QH_STATE_COMPLETING: 1165 for (tmp = ehci->async->qh_next.qh; 1166 tmp && tmp != qh; 1167 tmp = tmp->qh_next.qh) 1168 continue; 1169 /* periodic qh self-unlinks on empty, and a COMPLETING qh 1170 * may already be unlinked. 1171 */ 1172 if (tmp) 1173 unlink_async(ehci, qh); 1174 /* FALL THROUGH */ 1175 case QH_STATE_UNLINK: /* wait for hw to finish? */ 1176 case QH_STATE_UNLINK_WAIT: 1177 idle_timeout: 1178 spin_unlock_irqrestore (&ehci->lock, flags); 1179 schedule_timeout_uninterruptible(1); 1180 goto rescan; 1181 case QH_STATE_IDLE: /* fully unlinked */ 1182 if (qh->clearing_tt) 1183 goto idle_timeout; 1184 if (list_empty (&qh->qtd_list)) { 1185 qh_put (qh); 1186 break; 1187 } 1188 /* else FALL THROUGH */ 1189 default: 1190 /* caller was supposed to have unlinked any requests; 1191 * that's not our job. just leak this memory. 1192 */ 1193 ehci_err (ehci, "qh %p (#%02x) state %d%s\n", 1194 qh, ep->desc.bEndpointAddress, qh->qh_state, 1195 list_empty (&qh->qtd_list) ? "" : "(has tds)"); 1196 break; 1197 } 1198 ep->hcpriv = NULL; 1199 done: 1200 spin_unlock_irqrestore (&ehci->lock, flags); 1201 } 1202 1203 static void 1204 ehci_endpoint_reset(struct usb_hcd *hcd, struct usb_host_endpoint *ep) 1205 { 1206 struct ehci_hcd *ehci = hcd_to_ehci(hcd); 1207 struct ehci_qh *qh; 1208 int eptype = usb_endpoint_type(&ep->desc); 1209 int epnum = usb_endpoint_num(&ep->desc); 1210 int is_out = usb_endpoint_dir_out(&ep->desc); 1211 unsigned long flags; 1212 1213 if (eptype != USB_ENDPOINT_XFER_BULK && eptype != USB_ENDPOINT_XFER_INT) 1214 return; 1215 1216 spin_lock_irqsave(&ehci->lock, flags); 1217 qh = ep->hcpriv; 1218 1219 /* For Bulk and Interrupt endpoints we maintain the toggle state 1220 * in the hardware; the toggle bits in udev aren't used at all. 1221 * When an endpoint is reset by usb_clear_halt() we must reset 1222 * the toggle bit in the QH. 1223 */ 1224 if (qh) { 1225 usb_settoggle(qh->dev, epnum, is_out, 0); 1226 if (!list_empty(&qh->qtd_list)) { 1227 WARN_ONCE(1, "clear_halt for a busy endpoint\n"); 1228 } else if (qh->qh_state == QH_STATE_LINKED || 1229 qh->qh_state == QH_STATE_COMPLETING) { 1230 1231 /* The toggle value in the QH can't be updated 1232 * while the QH is active. Unlink it now; 1233 * re-linking will call qh_refresh(). 1234 */ 1235 if (eptype == USB_ENDPOINT_XFER_BULK) 1236 unlink_async(ehci, qh); 1237 else 1238 intr_deschedule(ehci, qh); 1239 } 1240 } 1241 spin_unlock_irqrestore(&ehci->lock, flags); 1242 } 1243 1244 static int ehci_get_frame (struct usb_hcd *hcd) 1245 { 1246 struct ehci_hcd *ehci = hcd_to_ehci (hcd); 1247 return (ehci_read_frame_index(ehci) >> 3) % ehci->periodic_size; 1248 } 1249 1250 /*-------------------------------------------------------------------------*/ 1251 1252 MODULE_DESCRIPTION(DRIVER_DESC); 1253 MODULE_AUTHOR (DRIVER_AUTHOR); 1254 MODULE_LICENSE ("GPL"); 1255 1256 #ifdef CONFIG_PCI 1257 #include "ehci-pci.c" 1258 #define PCI_DRIVER ehci_pci_driver 1259 #endif 1260 1261 #ifdef CONFIG_USB_EHCI_FSL 1262 #include "ehci-fsl.c" 1263 #define PLATFORM_DRIVER ehci_fsl_driver 1264 #endif 1265 1266 #ifdef CONFIG_USB_EHCI_MXC 1267 #include "ehci-mxc.c" 1268 #define PLATFORM_DRIVER ehci_mxc_driver 1269 #endif 1270 1271 #ifdef CONFIG_USB_EHCI_SH 1272 #include "ehci-sh.c" 1273 #define PLATFORM_DRIVER ehci_hcd_sh_driver 1274 #endif 1275 1276 #ifdef CONFIG_MIPS_ALCHEMY 1277 #include "ehci-au1xxx.c" 1278 #define PLATFORM_DRIVER ehci_hcd_au1xxx_driver 1279 #endif 1280 1281 #ifdef CONFIG_USB_EHCI_HCD_OMAP 1282 #include "ehci-omap.c" 1283 #define PLATFORM_DRIVER ehci_hcd_omap_driver 1284 #endif 1285 1286 #ifdef CONFIG_PPC_PS3 1287 #include "ehci-ps3.c" 1288 #define PS3_SYSTEM_BUS_DRIVER ps3_ehci_driver 1289 #endif 1290 1291 #ifdef CONFIG_USB_EHCI_HCD_PPC_OF 1292 #include "ehci-ppc-of.c" 1293 #define OF_PLATFORM_DRIVER ehci_hcd_ppc_of_driver 1294 #endif 1295 1296 #ifdef CONFIG_XPS_USB_HCD_XILINX 1297 #include "ehci-xilinx-of.c" 1298 #define XILINX_OF_PLATFORM_DRIVER ehci_hcd_xilinx_of_driver 1299 #endif 1300 1301 #ifdef CONFIG_PLAT_ORION 1302 #include "ehci-orion.c" 1303 #define PLATFORM_DRIVER ehci_orion_driver 1304 #endif 1305 1306 #ifdef CONFIG_ARCH_IXP4XX 1307 #include "ehci-ixp4xx.c" 1308 #define PLATFORM_DRIVER ixp4xx_ehci_driver 1309 #endif 1310 1311 #ifdef CONFIG_USB_W90X900_EHCI 1312 #include "ehci-w90x900.c" 1313 #define PLATFORM_DRIVER ehci_hcd_w90x900_driver 1314 #endif 1315 1316 #ifdef CONFIG_ARCH_AT91 1317 #include "ehci-atmel.c" 1318 #define PLATFORM_DRIVER ehci_atmel_driver 1319 #endif 1320 1321 #ifdef CONFIG_USB_OCTEON_EHCI 1322 #include "ehci-octeon.c" 1323 #define PLATFORM_DRIVER ehci_octeon_driver 1324 #endif 1325 1326 #ifdef CONFIG_USB_CNS3XXX_EHCI 1327 #include "ehci-cns3xxx.c" 1328 #define PLATFORM_DRIVER cns3xxx_ehci_driver 1329 #endif 1330 1331 #ifdef CONFIG_ARCH_VT8500 1332 #include "ehci-vt8500.c" 1333 #define PLATFORM_DRIVER vt8500_ehci_driver 1334 #endif 1335 1336 #ifdef CONFIG_PLAT_SPEAR 1337 #include "ehci-spear.c" 1338 #define PLATFORM_DRIVER spear_ehci_hcd_driver 1339 #endif 1340 1341 #ifdef CONFIG_USB_EHCI_MSM 1342 #include "ehci-msm.c" 1343 #define PLATFORM_DRIVER ehci_msm_driver 1344 #endif 1345 1346 #ifdef CONFIG_USB_EHCI_HCD_PMC_MSP 1347 #include "ehci-pmcmsp.c" 1348 #define PLATFORM_DRIVER ehci_hcd_msp_driver 1349 #endif 1350 1351 #ifdef CONFIG_USB_EHCI_TEGRA 1352 #include "ehci-tegra.c" 1353 #define PLATFORM_DRIVER tegra_ehci_driver 1354 #endif 1355 1356 #ifdef CONFIG_USB_EHCI_S5P 1357 #include "ehci-s5p.c" 1358 #define PLATFORM_DRIVER s5p_ehci_driver 1359 #endif 1360 1361 #ifdef CONFIG_SPARC_LEON 1362 #include "ehci-grlib.c" 1363 #define PLATFORM_DRIVER ehci_grlib_driver 1364 #endif 1365 1366 #ifdef CONFIG_CPU_XLR 1367 #include "ehci-xls.c" 1368 #define PLATFORM_DRIVER ehci_xls_driver 1369 #endif 1370 1371 #ifdef CONFIG_USB_EHCI_MV 1372 #include "ehci-mv.c" 1373 #define PLATFORM_DRIVER ehci_mv_driver 1374 #endif 1375 1376 #ifdef CONFIG_MACH_LOONGSON1 1377 #include "ehci-ls1x.c" 1378 #define PLATFORM_DRIVER ehci_ls1x_driver 1379 #endif 1380 1381 #ifdef CONFIG_USB_EHCI_HCD_PLATFORM 1382 #include "ehci-platform.c" 1383 #define PLATFORM_DRIVER ehci_platform_driver 1384 #endif 1385 1386 #if !defined(PCI_DRIVER) && !defined(PLATFORM_DRIVER) && \ 1387 !defined(PS3_SYSTEM_BUS_DRIVER) && !defined(OF_PLATFORM_DRIVER) && \ 1388 !defined(XILINX_OF_PLATFORM_DRIVER) 1389 #error "missing bus glue for ehci-hcd" 1390 #endif 1391 1392 static int __init ehci_hcd_init(void) 1393 { 1394 int retval = 0; 1395 1396 if (usb_disabled()) 1397 return -ENODEV; 1398 1399 printk(KERN_INFO "%s: " DRIVER_DESC "\n", hcd_name); 1400 set_bit(USB_EHCI_LOADED, &usb_hcds_loaded); 1401 if (test_bit(USB_UHCI_LOADED, &usb_hcds_loaded) || 1402 test_bit(USB_OHCI_LOADED, &usb_hcds_loaded)) 1403 printk(KERN_WARNING "Warning! ehci_hcd should always be loaded" 1404 " before uhci_hcd and ohci_hcd, not after\n"); 1405 1406 pr_debug("%s: block sizes: qh %Zd qtd %Zd itd %Zd sitd %Zd\n", 1407 hcd_name, 1408 sizeof(struct ehci_qh), sizeof(struct ehci_qtd), 1409 sizeof(struct ehci_itd), sizeof(struct ehci_sitd)); 1410 1411 #ifdef DEBUG 1412 ehci_debug_root = debugfs_create_dir("ehci", usb_debug_root); 1413 if (!ehci_debug_root) { 1414 retval = -ENOENT; 1415 goto err_debug; 1416 } 1417 #endif 1418 1419 #ifdef PLATFORM_DRIVER 1420 retval = platform_driver_register(&PLATFORM_DRIVER); 1421 if (retval < 0) 1422 goto clean0; 1423 #endif 1424 1425 #ifdef PCI_DRIVER 1426 retval = pci_register_driver(&PCI_DRIVER); 1427 if (retval < 0) 1428 goto clean1; 1429 #endif 1430 1431 #ifdef PS3_SYSTEM_BUS_DRIVER 1432 retval = ps3_ehci_driver_register(&PS3_SYSTEM_BUS_DRIVER); 1433 if (retval < 0) 1434 goto clean2; 1435 #endif 1436 1437 #ifdef OF_PLATFORM_DRIVER 1438 retval = platform_driver_register(&OF_PLATFORM_DRIVER); 1439 if (retval < 0) 1440 goto clean3; 1441 #endif 1442 1443 #ifdef XILINX_OF_PLATFORM_DRIVER 1444 retval = platform_driver_register(&XILINX_OF_PLATFORM_DRIVER); 1445 if (retval < 0) 1446 goto clean4; 1447 #endif 1448 return retval; 1449 1450 #ifdef XILINX_OF_PLATFORM_DRIVER 1451 /* platform_driver_unregister(&XILINX_OF_PLATFORM_DRIVER); */ 1452 clean4: 1453 #endif 1454 #ifdef OF_PLATFORM_DRIVER 1455 platform_driver_unregister(&OF_PLATFORM_DRIVER); 1456 clean3: 1457 #endif 1458 #ifdef PS3_SYSTEM_BUS_DRIVER 1459 ps3_ehci_driver_unregister(&PS3_SYSTEM_BUS_DRIVER); 1460 clean2: 1461 #endif 1462 #ifdef PCI_DRIVER 1463 pci_unregister_driver(&PCI_DRIVER); 1464 clean1: 1465 #endif 1466 #ifdef PLATFORM_DRIVER 1467 platform_driver_unregister(&PLATFORM_DRIVER); 1468 clean0: 1469 #endif 1470 #ifdef DEBUG 1471 debugfs_remove(ehci_debug_root); 1472 ehci_debug_root = NULL; 1473 err_debug: 1474 #endif 1475 clear_bit(USB_EHCI_LOADED, &usb_hcds_loaded); 1476 return retval; 1477 } 1478 module_init(ehci_hcd_init); 1479 1480 static void __exit ehci_hcd_cleanup(void) 1481 { 1482 #ifdef XILINX_OF_PLATFORM_DRIVER 1483 platform_driver_unregister(&XILINX_OF_PLATFORM_DRIVER); 1484 #endif 1485 #ifdef OF_PLATFORM_DRIVER 1486 platform_driver_unregister(&OF_PLATFORM_DRIVER); 1487 #endif 1488 #ifdef PLATFORM_DRIVER 1489 platform_driver_unregister(&PLATFORM_DRIVER); 1490 #endif 1491 #ifdef PCI_DRIVER 1492 pci_unregister_driver(&PCI_DRIVER); 1493 #endif 1494 #ifdef PS3_SYSTEM_BUS_DRIVER 1495 ps3_ehci_driver_unregister(&PS3_SYSTEM_BUS_DRIVER); 1496 #endif 1497 #ifdef DEBUG 1498 debugfs_remove(ehci_debug_root); 1499 #endif 1500 clear_bit(USB_EHCI_LOADED, &usb_hcds_loaded); 1501 } 1502 module_exit(ehci_hcd_cleanup); 1503 1504