1 /* 2 * Enhanced Host Controller Interface (EHCI) driver for USB. 3 * 4 * Maintainer: Alan Stern <stern@rowland.harvard.edu> 5 * 6 * Copyright (c) 2000-2004 by David Brownell 7 * 8 * This program is free software; you can redistribute it and/or modify it 9 * under the terms of the GNU General Public License as published by the 10 * Free Software Foundation; either version 2 of the License, or (at your 11 * option) any later version. 12 * 13 * This program is distributed in the hope that it will be useful, but 14 * WITHOUT ANY WARRANTY; without even the implied warranty of MERCHANTABILITY 15 * or FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License 16 * for more details. 17 * 18 * You should have received a copy of the GNU General Public License 19 * along with this program; if not, write to the Free Software Foundation, 20 * Inc., 675 Mass Ave, Cambridge, MA 02139, USA. 21 */ 22 23 #include <linux/module.h> 24 #include <linux/pci.h> 25 #include <linux/dmapool.h> 26 #include <linux/kernel.h> 27 #include <linux/delay.h> 28 #include <linux/ioport.h> 29 #include <linux/sched.h> 30 #include <linux/vmalloc.h> 31 #include <linux/errno.h> 32 #include <linux/init.h> 33 #include <linux/timer.h> 34 #include <linux/ktime.h> 35 #include <linux/list.h> 36 #include <linux/interrupt.h> 37 #include <linux/usb.h> 38 #include <linux/usb/hcd.h> 39 #include <linux/moduleparam.h> 40 #include <linux/dma-mapping.h> 41 #include <linux/debugfs.h> 42 #include <linux/slab.h> 43 #include <linux/uaccess.h> 44 45 #include <asm/byteorder.h> 46 #include <asm/io.h> 47 #include <asm/irq.h> 48 #include <asm/system.h> 49 #include <asm/unaligned.h> 50 51 #if defined(CONFIG_PPC_PS3) 52 #include <asm/firmware.h> 53 #endif 54 55 /*-------------------------------------------------------------------------*/ 56 57 /* 58 * EHCI hc_driver implementation ... experimental, incomplete. 59 * Based on the final 1.0 register interface specification. 60 * 61 * USB 2.0 shows up in upcoming www.pcmcia.org technology. 62 * First was PCMCIA, like ISA; then CardBus, which is PCI. 63 * Next comes "CardBay", using USB 2.0 signals. 64 * 65 * Contains additional contributions by Brad Hards, Rory Bolt, and others. 66 * Special thanks to Intel and VIA for providing host controllers to 67 * test this driver on, and Cypress (including In-System Design) for 68 * providing early devices for those host controllers to talk to! 69 */ 70 71 #define DRIVER_AUTHOR "David Brownell" 72 #define DRIVER_DESC "USB 2.0 'Enhanced' Host Controller (EHCI) Driver" 73 74 static const char hcd_name [] = "ehci_hcd"; 75 76 77 #undef VERBOSE_DEBUG 78 #undef EHCI_URB_TRACE 79 80 #ifdef DEBUG 81 #define EHCI_STATS 82 #endif 83 84 /* magic numbers that can affect system performance */ 85 #define EHCI_TUNE_CERR 3 /* 0-3 qtd retries; 0 == don't stop */ 86 #define EHCI_TUNE_RL_HS 4 /* nak throttle; see 4.9 */ 87 #define EHCI_TUNE_RL_TT 0 88 #define EHCI_TUNE_MULT_HS 1 /* 1-3 transactions/uframe; 4.10.3 */ 89 #define EHCI_TUNE_MULT_TT 1 90 /* 91 * Some drivers think it's safe to schedule isochronous transfers more than 92 * 256 ms into the future (partly as a result of an old bug in the scheduling 93 * code). In an attempt to avoid trouble, we will use a minimum scheduling 94 * length of 512 frames instead of 256. 95 */ 96 #define EHCI_TUNE_FLS 1 /* (medium) 512-frame schedule */ 97 98 #define EHCI_IAA_MSECS 10 /* arbitrary */ 99 #define EHCI_IO_JIFFIES (HZ/10) /* io watchdog > irq_thresh */ 100 #define EHCI_ASYNC_JIFFIES (HZ/20) /* async idle timeout */ 101 #define EHCI_SHRINK_JIFFIES (DIV_ROUND_UP(HZ, 200) + 1) 102 /* 5-ms async qh unlink delay */ 103 104 /* Initial IRQ latency: faster than hw default */ 105 static int log2_irq_thresh = 0; // 0 to 6 106 module_param (log2_irq_thresh, int, S_IRUGO); 107 MODULE_PARM_DESC (log2_irq_thresh, "log2 IRQ latency, 1-64 microframes"); 108 109 /* initial park setting: slower than hw default */ 110 static unsigned park = 0; 111 module_param (park, uint, S_IRUGO); 112 MODULE_PARM_DESC (park, "park setting; 1-3 back-to-back async packets"); 113 114 /* for flakey hardware, ignore overcurrent indicators */ 115 static bool ignore_oc = 0; 116 module_param (ignore_oc, bool, S_IRUGO); 117 MODULE_PARM_DESC (ignore_oc, "ignore bogus hardware overcurrent indications"); 118 119 /* for link power management(LPM) feature */ 120 static unsigned int hird; 121 module_param(hird, int, S_IRUGO); 122 MODULE_PARM_DESC(hird, "host initiated resume duration, +1 for each 75us"); 123 124 #define INTR_MASK (STS_IAA | STS_FATAL | STS_PCD | STS_ERR | STS_INT) 125 126 /*-------------------------------------------------------------------------*/ 127 128 #include "ehci.h" 129 #include "ehci-dbg.c" 130 #include "pci-quirks.h" 131 132 /*-------------------------------------------------------------------------*/ 133 134 static void 135 timer_action(struct ehci_hcd *ehci, enum ehci_timer_action action) 136 { 137 /* Don't override timeouts which shrink or (later) disable 138 * the async ring; just the I/O watchdog. Note that if a 139 * SHRINK were pending, OFF would never be requested. 140 */ 141 if (timer_pending(&ehci->watchdog) 142 && ((BIT(TIMER_ASYNC_SHRINK) | BIT(TIMER_ASYNC_OFF)) 143 & ehci->actions)) 144 return; 145 146 if (!test_and_set_bit(action, &ehci->actions)) { 147 unsigned long t; 148 149 switch (action) { 150 case TIMER_IO_WATCHDOG: 151 if (!ehci->need_io_watchdog) 152 return; 153 t = EHCI_IO_JIFFIES; 154 break; 155 case TIMER_ASYNC_OFF: 156 t = EHCI_ASYNC_JIFFIES; 157 break; 158 /* case TIMER_ASYNC_SHRINK: */ 159 default: 160 t = EHCI_SHRINK_JIFFIES; 161 break; 162 } 163 mod_timer(&ehci->watchdog, t + jiffies); 164 } 165 } 166 167 /*-------------------------------------------------------------------------*/ 168 169 /* 170 * handshake - spin reading hc until handshake completes or fails 171 * @ptr: address of hc register to be read 172 * @mask: bits to look at in result of read 173 * @done: value of those bits when handshake succeeds 174 * @usec: timeout in microseconds 175 * 176 * Returns negative errno, or zero on success 177 * 178 * Success happens when the "mask" bits have the specified value (hardware 179 * handshake done). There are two failure modes: "usec" have passed (major 180 * hardware flakeout), or the register reads as all-ones (hardware removed). 181 * 182 * That last failure should_only happen in cases like physical cardbus eject 183 * before driver shutdown. But it also seems to be caused by bugs in cardbus 184 * bridge shutdown: shutting down the bridge before the devices using it. 185 */ 186 static int handshake (struct ehci_hcd *ehci, void __iomem *ptr, 187 u32 mask, u32 done, int usec) 188 { 189 u32 result; 190 191 do { 192 result = ehci_readl(ehci, ptr); 193 if (result == ~(u32)0) /* card removed */ 194 return -ENODEV; 195 result &= mask; 196 if (result == done) 197 return 0; 198 udelay (1); 199 usec--; 200 } while (usec > 0); 201 return -ETIMEDOUT; 202 } 203 204 /* check TDI/ARC silicon is in host mode */ 205 static int tdi_in_host_mode (struct ehci_hcd *ehci) 206 { 207 u32 __iomem *reg_ptr; 208 u32 tmp; 209 210 reg_ptr = (u32 __iomem *)(((u8 __iomem *)ehci->regs) + USBMODE); 211 tmp = ehci_readl(ehci, reg_ptr); 212 return (tmp & 3) == USBMODE_CM_HC; 213 } 214 215 /* force HC to halt state from unknown (EHCI spec section 2.3) */ 216 static int ehci_halt (struct ehci_hcd *ehci) 217 { 218 u32 temp = ehci_readl(ehci, &ehci->regs->status); 219 220 /* disable any irqs left enabled by previous code */ 221 ehci_writel(ehci, 0, &ehci->regs->intr_enable); 222 223 if (ehci_is_TDI(ehci) && tdi_in_host_mode(ehci) == 0) { 224 return 0; 225 } 226 227 if ((temp & STS_HALT) != 0) 228 return 0; 229 230 temp = ehci_readl(ehci, &ehci->regs->command); 231 temp &= ~CMD_RUN; 232 ehci_writel(ehci, temp, &ehci->regs->command); 233 return handshake (ehci, &ehci->regs->status, 234 STS_HALT, STS_HALT, 16 * 125); 235 } 236 237 #if defined(CONFIG_USB_SUSPEND) && defined(CONFIG_PPC_PS3) 238 239 /* 240 * The EHCI controller of the Cell Super Companion Chip used in the 241 * PS3 will stop the root hub after all root hub ports are suspended. 242 * When in this condition handshake will return -ETIMEDOUT. The 243 * STS_HLT bit will not be set, so inspection of the frame index is 244 * used here to test for the condition. If the condition is found 245 * return success to allow the USB suspend to complete. 246 */ 247 248 static int handshake_for_broken_root_hub(struct ehci_hcd *ehci, 249 void __iomem *ptr, u32 mask, u32 done, 250 int usec) 251 { 252 unsigned int old_index; 253 int error; 254 255 if (!firmware_has_feature(FW_FEATURE_PS3_LV1)) 256 return -ETIMEDOUT; 257 258 old_index = ehci_read_frame_index(ehci); 259 260 error = handshake(ehci, ptr, mask, done, usec); 261 262 if (error == -ETIMEDOUT && ehci_read_frame_index(ehci) == old_index) 263 return 0; 264 265 return error; 266 } 267 268 #else 269 270 static int handshake_for_broken_root_hub(struct ehci_hcd *ehci, 271 void __iomem *ptr, u32 mask, u32 done, 272 int usec) 273 { 274 return -ETIMEDOUT; 275 } 276 277 #endif 278 279 static int handshake_on_error_set_halt(struct ehci_hcd *ehci, void __iomem *ptr, 280 u32 mask, u32 done, int usec) 281 { 282 int error; 283 284 error = handshake(ehci, ptr, mask, done, usec); 285 if (error == -ETIMEDOUT) 286 error = handshake_for_broken_root_hub(ehci, ptr, mask, done, 287 usec); 288 289 if (error) { 290 ehci_halt(ehci); 291 ehci->rh_state = EHCI_RH_HALTED; 292 ehci_err(ehci, "force halt; handshake %p %08x %08x -> %d\n", 293 ptr, mask, done, error); 294 } 295 296 return error; 297 } 298 299 /* put TDI/ARC silicon into EHCI mode */ 300 static void tdi_reset (struct ehci_hcd *ehci) 301 { 302 u32 __iomem *reg_ptr; 303 u32 tmp; 304 305 reg_ptr = (u32 __iomem *)(((u8 __iomem *)ehci->regs) + USBMODE); 306 tmp = ehci_readl(ehci, reg_ptr); 307 tmp |= USBMODE_CM_HC; 308 /* The default byte access to MMR space is LE after 309 * controller reset. Set the required endian mode 310 * for transfer buffers to match the host microprocessor 311 */ 312 if (ehci_big_endian_mmio(ehci)) 313 tmp |= USBMODE_BE; 314 ehci_writel(ehci, tmp, reg_ptr); 315 } 316 317 /* reset a non-running (STS_HALT == 1) controller */ 318 static int ehci_reset (struct ehci_hcd *ehci) 319 { 320 int retval; 321 u32 command = ehci_readl(ehci, &ehci->regs->command); 322 323 /* If the EHCI debug controller is active, special care must be 324 * taken before and after a host controller reset */ 325 if (ehci->debug && !dbgp_reset_prep()) 326 ehci->debug = NULL; 327 328 command |= CMD_RESET; 329 dbg_cmd (ehci, "reset", command); 330 ehci_writel(ehci, command, &ehci->regs->command); 331 ehci->rh_state = EHCI_RH_HALTED; 332 ehci->next_statechange = jiffies; 333 retval = handshake (ehci, &ehci->regs->command, 334 CMD_RESET, 0, 250 * 1000); 335 336 if (ehci->has_hostpc) { 337 ehci_writel(ehci, USBMODE_EX_HC | USBMODE_EX_VBPS, 338 (u32 __iomem *)(((u8 *)ehci->regs) + USBMODE_EX)); 339 ehci_writel(ehci, TXFIFO_DEFAULT, 340 (u32 __iomem *)(((u8 *)ehci->regs) + TXFILLTUNING)); 341 } 342 if (retval) 343 return retval; 344 345 if (ehci_is_TDI(ehci)) 346 tdi_reset (ehci); 347 348 if (ehci->debug) 349 dbgp_external_startup(); 350 351 return retval; 352 } 353 354 /* idle the controller (from running) */ 355 static void ehci_quiesce (struct ehci_hcd *ehci) 356 { 357 u32 temp; 358 359 #ifdef DEBUG 360 if (ehci->rh_state != EHCI_RH_RUNNING) 361 BUG (); 362 #endif 363 364 /* wait for any schedule enables/disables to take effect */ 365 temp = ehci_readl(ehci, &ehci->regs->command) << 10; 366 temp &= STS_ASS | STS_PSS; 367 if (handshake_on_error_set_halt(ehci, &ehci->regs->status, 368 STS_ASS | STS_PSS, temp, 16 * 125)) 369 return; 370 371 /* then disable anything that's still active */ 372 temp = ehci_readl(ehci, &ehci->regs->command); 373 temp &= ~(CMD_ASE | CMD_IAAD | CMD_PSE); 374 ehci_writel(ehci, temp, &ehci->regs->command); 375 376 /* hardware can take 16 microframes to turn off ... */ 377 handshake_on_error_set_halt(ehci, &ehci->regs->status, 378 STS_ASS | STS_PSS, 0, 16 * 125); 379 } 380 381 /*-------------------------------------------------------------------------*/ 382 383 static void end_unlink_async(struct ehci_hcd *ehci); 384 static void ehci_work(struct ehci_hcd *ehci); 385 386 #include "ehci-hub.c" 387 #include "ehci-lpm.c" 388 #include "ehci-mem.c" 389 #include "ehci-q.c" 390 #include "ehci-sched.c" 391 #include "ehci-sysfs.c" 392 393 /*-------------------------------------------------------------------------*/ 394 395 static void ehci_iaa_watchdog(unsigned long param) 396 { 397 struct ehci_hcd *ehci = (struct ehci_hcd *) param; 398 unsigned long flags; 399 400 spin_lock_irqsave (&ehci->lock, flags); 401 402 /* Lost IAA irqs wedge things badly; seen first with a vt8235. 403 * So we need this watchdog, but must protect it against both 404 * (a) SMP races against real IAA firing and retriggering, and 405 * (b) clean HC shutdown, when IAA watchdog was pending. 406 */ 407 if (ehci->reclaim 408 && !timer_pending(&ehci->iaa_watchdog) 409 && ehci->rh_state == EHCI_RH_RUNNING) { 410 u32 cmd, status; 411 412 /* If we get here, IAA is *REALLY* late. It's barely 413 * conceivable that the system is so busy that CMD_IAAD 414 * is still legitimately set, so let's be sure it's 415 * clear before we read STS_IAA. (The HC should clear 416 * CMD_IAAD when it sets STS_IAA.) 417 */ 418 cmd = ehci_readl(ehci, &ehci->regs->command); 419 if (cmd & CMD_IAAD) 420 ehci_writel(ehci, cmd & ~CMD_IAAD, 421 &ehci->regs->command); 422 423 /* If IAA is set here it either legitimately triggered 424 * before we cleared IAAD above (but _way_ late, so we'll 425 * still count it as lost) ... or a silicon erratum: 426 * - VIA seems to set IAA without triggering the IRQ; 427 * - IAAD potentially cleared without setting IAA. 428 */ 429 status = ehci_readl(ehci, &ehci->regs->status); 430 if ((status & STS_IAA) || !(cmd & CMD_IAAD)) { 431 COUNT (ehci->stats.lost_iaa); 432 ehci_writel(ehci, STS_IAA, &ehci->regs->status); 433 } 434 435 ehci_vdbg(ehci, "IAA watchdog: status %x cmd %x\n", 436 status, cmd); 437 end_unlink_async(ehci); 438 } 439 440 spin_unlock_irqrestore(&ehci->lock, flags); 441 } 442 443 static void ehci_watchdog(unsigned long param) 444 { 445 struct ehci_hcd *ehci = (struct ehci_hcd *) param; 446 unsigned long flags; 447 448 spin_lock_irqsave(&ehci->lock, flags); 449 450 /* stop async processing after it's idled a bit */ 451 if (test_bit (TIMER_ASYNC_OFF, &ehci->actions)) 452 start_unlink_async (ehci, ehci->async); 453 454 /* ehci could run by timer, without IRQs ... */ 455 ehci_work (ehci); 456 457 spin_unlock_irqrestore (&ehci->lock, flags); 458 } 459 460 /* On some systems, leaving remote wakeup enabled prevents system shutdown. 461 * The firmware seems to think that powering off is a wakeup event! 462 * This routine turns off remote wakeup and everything else, on all ports. 463 */ 464 static void ehci_turn_off_all_ports(struct ehci_hcd *ehci) 465 { 466 int port = HCS_N_PORTS(ehci->hcs_params); 467 468 while (port--) 469 ehci_writel(ehci, PORT_RWC_BITS, 470 &ehci->regs->port_status[port]); 471 } 472 473 /* 474 * Halt HC, turn off all ports, and let the BIOS use the companion controllers. 475 * Should be called with ehci->lock held. 476 */ 477 static void ehci_silence_controller(struct ehci_hcd *ehci) 478 { 479 ehci_halt(ehci); 480 ehci_turn_off_all_ports(ehci); 481 482 /* make BIOS/etc use companion controller during reboot */ 483 ehci_writel(ehci, 0, &ehci->regs->configured_flag); 484 485 /* unblock posted writes */ 486 ehci_readl(ehci, &ehci->regs->configured_flag); 487 } 488 489 /* ehci_shutdown kick in for silicon on any bus (not just pci, etc). 490 * This forcibly disables dma and IRQs, helping kexec and other cases 491 * where the next system software may expect clean state. 492 */ 493 static void ehci_shutdown(struct usb_hcd *hcd) 494 { 495 struct ehci_hcd *ehci = hcd_to_ehci(hcd); 496 497 del_timer_sync(&ehci->watchdog); 498 del_timer_sync(&ehci->iaa_watchdog); 499 500 spin_lock_irq(&ehci->lock); 501 ehci_silence_controller(ehci); 502 spin_unlock_irq(&ehci->lock); 503 } 504 505 static void ehci_port_power (struct ehci_hcd *ehci, int is_on) 506 { 507 unsigned port; 508 509 if (!HCS_PPC (ehci->hcs_params)) 510 return; 511 512 ehci_dbg (ehci, "...power%s ports...\n", is_on ? "up" : "down"); 513 for (port = HCS_N_PORTS (ehci->hcs_params); port > 0; ) 514 (void) ehci_hub_control(ehci_to_hcd(ehci), 515 is_on ? SetPortFeature : ClearPortFeature, 516 USB_PORT_FEAT_POWER, 517 port--, NULL, 0); 518 /* Flush those writes */ 519 ehci_readl(ehci, &ehci->regs->command); 520 msleep(20); 521 } 522 523 /*-------------------------------------------------------------------------*/ 524 525 /* 526 * ehci_work is called from some interrupts, timers, and so on. 527 * it calls driver completion functions, after dropping ehci->lock. 528 */ 529 static void ehci_work (struct ehci_hcd *ehci) 530 { 531 timer_action_done (ehci, TIMER_IO_WATCHDOG); 532 533 /* another CPU may drop ehci->lock during a schedule scan while 534 * it reports urb completions. this flag guards against bogus 535 * attempts at re-entrant schedule scanning. 536 */ 537 if (ehci->scanning) 538 return; 539 ehci->scanning = 1; 540 scan_async (ehci); 541 if (ehci->next_uframe != -1) 542 scan_periodic (ehci); 543 ehci->scanning = 0; 544 545 /* the IO watchdog guards against hardware or driver bugs that 546 * misplace IRQs, and should let us run completely without IRQs. 547 * such lossage has been observed on both VT6202 and VT8235. 548 */ 549 if (ehci->rh_state == EHCI_RH_RUNNING && 550 (ehci->async->qh_next.ptr != NULL || 551 ehci->periodic_sched != 0)) 552 timer_action (ehci, TIMER_IO_WATCHDOG); 553 } 554 555 /* 556 * Called when the ehci_hcd module is removed. 557 */ 558 static void ehci_stop (struct usb_hcd *hcd) 559 { 560 struct ehci_hcd *ehci = hcd_to_ehci (hcd); 561 562 ehci_dbg (ehci, "stop\n"); 563 564 /* no more interrupts ... */ 565 del_timer_sync (&ehci->watchdog); 566 del_timer_sync(&ehci->iaa_watchdog); 567 568 spin_lock_irq(&ehci->lock); 569 if (ehci->rh_state == EHCI_RH_RUNNING) 570 ehci_quiesce (ehci); 571 572 ehci_silence_controller(ehci); 573 ehci_reset (ehci); 574 spin_unlock_irq(&ehci->lock); 575 576 remove_sysfs_files(ehci); 577 remove_debug_files (ehci); 578 579 /* root hub is shut down separately (first, when possible) */ 580 spin_lock_irq (&ehci->lock); 581 if (ehci->async) 582 ehci_work (ehci); 583 spin_unlock_irq (&ehci->lock); 584 ehci_mem_cleanup (ehci); 585 586 if (ehci->amd_pll_fix == 1) 587 usb_amd_dev_put(); 588 589 #ifdef EHCI_STATS 590 ehci_dbg (ehci, "irq normal %ld err %ld reclaim %ld (lost %ld)\n", 591 ehci->stats.normal, ehci->stats.error, ehci->stats.reclaim, 592 ehci->stats.lost_iaa); 593 ehci_dbg (ehci, "complete %ld unlink %ld\n", 594 ehci->stats.complete, ehci->stats.unlink); 595 #endif 596 597 dbg_status (ehci, "ehci_stop completed", 598 ehci_readl(ehci, &ehci->regs->status)); 599 } 600 601 /* one-time init, only for memory state */ 602 static int ehci_init(struct usb_hcd *hcd) 603 { 604 struct ehci_hcd *ehci = hcd_to_ehci(hcd); 605 u32 temp; 606 int retval; 607 u32 hcc_params; 608 struct ehci_qh_hw *hw; 609 610 spin_lock_init(&ehci->lock); 611 612 /* 613 * keep io watchdog by default, those good HCDs could turn off it later 614 */ 615 ehci->need_io_watchdog = 1; 616 init_timer(&ehci->watchdog); 617 ehci->watchdog.function = ehci_watchdog; 618 ehci->watchdog.data = (unsigned long) ehci; 619 620 init_timer(&ehci->iaa_watchdog); 621 ehci->iaa_watchdog.function = ehci_iaa_watchdog; 622 ehci->iaa_watchdog.data = (unsigned long) ehci; 623 624 hcc_params = ehci_readl(ehci, &ehci->caps->hcc_params); 625 626 /* 627 * by default set standard 80% (== 100 usec/uframe) max periodic 628 * bandwidth as required by USB 2.0 629 */ 630 ehci->uframe_periodic_max = 100; 631 632 /* 633 * hw default: 1K periodic list heads, one per frame. 634 * periodic_size can shrink by USBCMD update if hcc_params allows. 635 */ 636 ehci->periodic_size = DEFAULT_I_TDPS; 637 INIT_LIST_HEAD(&ehci->cached_itd_list); 638 INIT_LIST_HEAD(&ehci->cached_sitd_list); 639 640 if (HCC_PGM_FRAMELISTLEN(hcc_params)) { 641 /* periodic schedule size can be smaller than default */ 642 switch (EHCI_TUNE_FLS) { 643 case 0: ehci->periodic_size = 1024; break; 644 case 1: ehci->periodic_size = 512; break; 645 case 2: ehci->periodic_size = 256; break; 646 default: BUG(); 647 } 648 } 649 if ((retval = ehci_mem_init(ehci, GFP_KERNEL)) < 0) 650 return retval; 651 652 /* controllers may cache some of the periodic schedule ... */ 653 if (HCC_ISOC_CACHE(hcc_params)) // full frame cache 654 ehci->i_thresh = 2 + 8; 655 else // N microframes cached 656 ehci->i_thresh = 2 + HCC_ISOC_THRES(hcc_params); 657 658 ehci->reclaim = NULL; 659 ehci->next_uframe = -1; 660 ehci->clock_frame = -1; 661 662 /* 663 * dedicate a qh for the async ring head, since we couldn't unlink 664 * a 'real' qh without stopping the async schedule [4.8]. use it 665 * as the 'reclamation list head' too. 666 * its dummy is used in hw_alt_next of many tds, to prevent the qh 667 * from automatically advancing to the next td after short reads. 668 */ 669 ehci->async->qh_next.qh = NULL; 670 hw = ehci->async->hw; 671 hw->hw_next = QH_NEXT(ehci, ehci->async->qh_dma); 672 hw->hw_info1 = cpu_to_hc32(ehci, QH_HEAD); 673 hw->hw_info1 |= cpu_to_hc32(ehci, (1 << 7)); /* I = 1 */ 674 hw->hw_token = cpu_to_hc32(ehci, QTD_STS_HALT); 675 hw->hw_qtd_next = EHCI_LIST_END(ehci); 676 ehci->async->qh_state = QH_STATE_LINKED; 677 hw->hw_alt_next = QTD_NEXT(ehci, ehci->async->dummy->qtd_dma); 678 679 /* clear interrupt enables, set irq latency */ 680 if (log2_irq_thresh < 0 || log2_irq_thresh > 6) 681 log2_irq_thresh = 0; 682 temp = 1 << (16 + log2_irq_thresh); 683 if (HCC_PER_PORT_CHANGE_EVENT(hcc_params)) { 684 ehci->has_ppcd = 1; 685 ehci_dbg(ehci, "enable per-port change event\n"); 686 temp |= CMD_PPCEE; 687 } 688 if (HCC_CANPARK(hcc_params)) { 689 /* HW default park == 3, on hardware that supports it (like 690 * NVidia and ALI silicon), maximizes throughput on the async 691 * schedule by avoiding QH fetches between transfers. 692 * 693 * With fast usb storage devices and NForce2, "park" seems to 694 * make problems: throughput reduction (!), data errors... 695 */ 696 if (park) { 697 park = min(park, (unsigned) 3); 698 temp |= CMD_PARK; 699 temp |= park << 8; 700 } 701 ehci_dbg(ehci, "park %d\n", park); 702 } 703 if (HCC_PGM_FRAMELISTLEN(hcc_params)) { 704 /* periodic schedule size can be smaller than default */ 705 temp &= ~(3 << 2); 706 temp |= (EHCI_TUNE_FLS << 2); 707 } 708 if (HCC_LPM(hcc_params)) { 709 /* support link power management EHCI 1.1 addendum */ 710 ehci_dbg(ehci, "support lpm\n"); 711 ehci->has_lpm = 1; 712 if (hird > 0xf) { 713 ehci_dbg(ehci, "hird %d invalid, use default 0", 714 hird); 715 hird = 0; 716 } 717 temp |= hird << 24; 718 } 719 ehci->command = temp; 720 721 /* Accept arbitrarily long scatter-gather lists */ 722 if (!(hcd->driver->flags & HCD_LOCAL_MEM)) 723 hcd->self.sg_tablesize = ~0; 724 return 0; 725 } 726 727 /* start HC running; it's halted, ehci_init() has been run (once) */ 728 static int ehci_run (struct usb_hcd *hcd) 729 { 730 struct ehci_hcd *ehci = hcd_to_ehci (hcd); 731 u32 temp; 732 u32 hcc_params; 733 734 hcd->uses_new_polling = 1; 735 736 /* EHCI spec section 4.1 */ 737 738 ehci_writel(ehci, ehci->periodic_dma, &ehci->regs->frame_list); 739 ehci_writel(ehci, (u32)ehci->async->qh_dma, &ehci->regs->async_next); 740 741 /* 742 * hcc_params controls whether ehci->regs->segment must (!!!) 743 * be used; it constrains QH/ITD/SITD and QTD locations. 744 * pci_pool consistent memory always uses segment zero. 745 * streaming mappings for I/O buffers, like pci_map_single(), 746 * can return segments above 4GB, if the device allows. 747 * 748 * NOTE: the dma mask is visible through dma_supported(), so 749 * drivers can pass this info along ... like NETIF_F_HIGHDMA, 750 * Scsi_Host.highmem_io, and so forth. It's readonly to all 751 * host side drivers though. 752 */ 753 hcc_params = ehci_readl(ehci, &ehci->caps->hcc_params); 754 if (HCC_64BIT_ADDR(hcc_params)) { 755 ehci_writel(ehci, 0, &ehci->regs->segment); 756 #if 0 757 // this is deeply broken on almost all architectures 758 if (!dma_set_mask(hcd->self.controller, DMA_BIT_MASK(64))) 759 ehci_info(ehci, "enabled 64bit DMA\n"); 760 #endif 761 } 762 763 764 // Philips, Intel, and maybe others need CMD_RUN before the 765 // root hub will detect new devices (why?); NEC doesn't 766 ehci->command &= ~(CMD_LRESET|CMD_IAAD|CMD_PSE|CMD_ASE|CMD_RESET); 767 ehci->command |= CMD_RUN; 768 ehci_writel(ehci, ehci->command, &ehci->regs->command); 769 dbg_cmd (ehci, "init", ehci->command); 770 771 /* 772 * Start, enabling full USB 2.0 functionality ... usb 1.1 devices 773 * are explicitly handed to companion controller(s), so no TT is 774 * involved with the root hub. (Except where one is integrated, 775 * and there's no companion controller unless maybe for USB OTG.) 776 * 777 * Turning on the CF flag will transfer ownership of all ports 778 * from the companions to the EHCI controller. If any of the 779 * companions are in the middle of a port reset at the time, it 780 * could cause trouble. Write-locking ehci_cf_port_reset_rwsem 781 * guarantees that no resets are in progress. After we set CF, 782 * a short delay lets the hardware catch up; new resets shouldn't 783 * be started before the port switching actions could complete. 784 */ 785 down_write(&ehci_cf_port_reset_rwsem); 786 ehci->rh_state = EHCI_RH_RUNNING; 787 ehci_writel(ehci, FLAG_CF, &ehci->regs->configured_flag); 788 ehci_readl(ehci, &ehci->regs->command); /* unblock posted writes */ 789 msleep(5); 790 up_write(&ehci_cf_port_reset_rwsem); 791 ehci->last_periodic_enable = ktime_get_real(); 792 793 temp = HC_VERSION(ehci, ehci_readl(ehci, &ehci->caps->hc_capbase)); 794 ehci_info (ehci, 795 "USB %x.%x started, EHCI %x.%02x%s\n", 796 ((ehci->sbrn & 0xf0)>>4), (ehci->sbrn & 0x0f), 797 temp >> 8, temp & 0xff, 798 ignore_oc ? ", overcurrent ignored" : ""); 799 800 ehci_writel(ehci, INTR_MASK, 801 &ehci->regs->intr_enable); /* Turn On Interrupts */ 802 803 /* GRR this is run-once init(), being done every time the HC starts. 804 * So long as they're part of class devices, we can't do it init() 805 * since the class device isn't created that early. 806 */ 807 create_debug_files(ehci); 808 create_sysfs_files(ehci); 809 810 return 0; 811 } 812 813 static int __maybe_unused ehci_setup (struct usb_hcd *hcd) 814 { 815 struct ehci_hcd *ehci = hcd_to_ehci(hcd); 816 int retval; 817 818 ehci->regs = (void __iomem *)ehci->caps + 819 HC_LENGTH(ehci, ehci_readl(ehci, &ehci->caps->hc_capbase)); 820 dbg_hcs_params(ehci, "reset"); 821 dbg_hcc_params(ehci, "reset"); 822 823 /* cache this readonly data; minimize chip reads */ 824 ehci->hcs_params = ehci_readl(ehci, &ehci->caps->hcs_params); 825 826 ehci->sbrn = HCD_USB2; 827 828 retval = ehci_halt(ehci); 829 if (retval) 830 return retval; 831 832 /* data structure init */ 833 retval = ehci_init(hcd); 834 if (retval) 835 return retval; 836 837 ehci_reset(ehci); 838 839 return 0; 840 } 841 842 /*-------------------------------------------------------------------------*/ 843 844 static irqreturn_t ehci_irq (struct usb_hcd *hcd) 845 { 846 struct ehci_hcd *ehci = hcd_to_ehci (hcd); 847 u32 status, masked_status, pcd_status = 0, cmd; 848 int bh; 849 850 spin_lock (&ehci->lock); 851 852 status = ehci_readl(ehci, &ehci->regs->status); 853 854 /* e.g. cardbus physical eject */ 855 if (status == ~(u32) 0) { 856 ehci_dbg (ehci, "device removed\n"); 857 goto dead; 858 } 859 860 /* Shared IRQ? */ 861 masked_status = status & INTR_MASK; 862 if (!masked_status || unlikely(ehci->rh_state == EHCI_RH_HALTED)) { 863 spin_unlock(&ehci->lock); 864 return IRQ_NONE; 865 } 866 867 /* clear (just) interrupts */ 868 ehci_writel(ehci, masked_status, &ehci->regs->status); 869 cmd = ehci_readl(ehci, &ehci->regs->command); 870 bh = 0; 871 872 #ifdef VERBOSE_DEBUG 873 /* unrequested/ignored: Frame List Rollover */ 874 dbg_status (ehci, "irq", status); 875 #endif 876 877 /* INT, ERR, and IAA interrupt rates can be throttled */ 878 879 /* normal [4.15.1.2] or error [4.15.1.1] completion */ 880 if (likely ((status & (STS_INT|STS_ERR)) != 0)) { 881 if (likely ((status & STS_ERR) == 0)) 882 COUNT (ehci->stats.normal); 883 else 884 COUNT (ehci->stats.error); 885 bh = 1; 886 } 887 888 /* complete the unlinking of some qh [4.15.2.3] */ 889 if (status & STS_IAA) { 890 /* guard against (alleged) silicon errata */ 891 if (cmd & CMD_IAAD) { 892 ehci_writel(ehci, cmd & ~CMD_IAAD, 893 &ehci->regs->command); 894 ehci_dbg(ehci, "IAA with IAAD still set?\n"); 895 } 896 if (ehci->reclaim) { 897 COUNT(ehci->stats.reclaim); 898 end_unlink_async(ehci); 899 } else 900 ehci_dbg(ehci, "IAA with nothing to reclaim?\n"); 901 } 902 903 /* remote wakeup [4.3.1] */ 904 if (status & STS_PCD) { 905 unsigned i = HCS_N_PORTS (ehci->hcs_params); 906 u32 ppcd = 0; 907 908 /* kick root hub later */ 909 pcd_status = status; 910 911 /* resume root hub? */ 912 if (!(cmd & CMD_RUN)) 913 usb_hcd_resume_root_hub(hcd); 914 915 /* get per-port change detect bits */ 916 if (ehci->has_ppcd) 917 ppcd = status >> 16; 918 919 while (i--) { 920 int pstatus; 921 922 /* leverage per-port change bits feature */ 923 if (ehci->has_ppcd && !(ppcd & (1 << i))) 924 continue; 925 pstatus = ehci_readl(ehci, 926 &ehci->regs->port_status[i]); 927 928 if (pstatus & PORT_OWNER) 929 continue; 930 if (!(test_bit(i, &ehci->suspended_ports) && 931 ((pstatus & PORT_RESUME) || 932 !(pstatus & PORT_SUSPEND)) && 933 (pstatus & PORT_PE) && 934 ehci->reset_done[i] == 0)) 935 continue; 936 937 /* start 20 msec resume signaling from this port, 938 * and make khubd collect PORT_STAT_C_SUSPEND to 939 * stop that signaling. Use 5 ms extra for safety, 940 * like usb_port_resume() does. 941 */ 942 ehci->reset_done[i] = jiffies + msecs_to_jiffies(25); 943 ehci_dbg (ehci, "port %d remote wakeup\n", i + 1); 944 mod_timer(&hcd->rh_timer, ehci->reset_done[i]); 945 } 946 } 947 948 /* PCI errors [4.15.2.4] */ 949 if (unlikely ((status & STS_FATAL) != 0)) { 950 ehci_err(ehci, "fatal error\n"); 951 dbg_cmd(ehci, "fatal", cmd); 952 dbg_status(ehci, "fatal", status); 953 ehci_halt(ehci); 954 dead: 955 ehci_reset(ehci); 956 ehci_writel(ehci, 0, &ehci->regs->configured_flag); 957 usb_hc_died(hcd); 958 /* generic layer kills/unlinks all urbs, then 959 * uses ehci_stop to clean up the rest 960 */ 961 bh = 1; 962 } 963 964 if (bh) 965 ehci_work (ehci); 966 spin_unlock (&ehci->lock); 967 if (pcd_status) 968 usb_hcd_poll_rh_status(hcd); 969 return IRQ_HANDLED; 970 } 971 972 /*-------------------------------------------------------------------------*/ 973 974 /* 975 * non-error returns are a promise to giveback() the urb later 976 * we drop ownership so next owner (or urb unlink) can get it 977 * 978 * urb + dev is in hcd.self.controller.urb_list 979 * we're queueing TDs onto software and hardware lists 980 * 981 * hcd-specific init for hcpriv hasn't been done yet 982 * 983 * NOTE: control, bulk, and interrupt share the same code to append TDs 984 * to a (possibly active) QH, and the same QH scanning code. 985 */ 986 static int ehci_urb_enqueue ( 987 struct usb_hcd *hcd, 988 struct urb *urb, 989 gfp_t mem_flags 990 ) { 991 struct ehci_hcd *ehci = hcd_to_ehci (hcd); 992 struct list_head qtd_list; 993 994 INIT_LIST_HEAD (&qtd_list); 995 996 switch (usb_pipetype (urb->pipe)) { 997 case PIPE_CONTROL: 998 /* qh_completions() code doesn't handle all the fault cases 999 * in multi-TD control transfers. Even 1KB is rare anyway. 1000 */ 1001 if (urb->transfer_buffer_length > (16 * 1024)) 1002 return -EMSGSIZE; 1003 /* FALLTHROUGH */ 1004 /* case PIPE_BULK: */ 1005 default: 1006 if (!qh_urb_transaction (ehci, urb, &qtd_list, mem_flags)) 1007 return -ENOMEM; 1008 return submit_async(ehci, urb, &qtd_list, mem_flags); 1009 1010 case PIPE_INTERRUPT: 1011 if (!qh_urb_transaction (ehci, urb, &qtd_list, mem_flags)) 1012 return -ENOMEM; 1013 return intr_submit(ehci, urb, &qtd_list, mem_flags); 1014 1015 case PIPE_ISOCHRONOUS: 1016 if (urb->dev->speed == USB_SPEED_HIGH) 1017 return itd_submit (ehci, urb, mem_flags); 1018 else 1019 return sitd_submit (ehci, urb, mem_flags); 1020 } 1021 } 1022 1023 static void unlink_async (struct ehci_hcd *ehci, struct ehci_qh *qh) 1024 { 1025 /* failfast */ 1026 if (ehci->rh_state != EHCI_RH_RUNNING && ehci->reclaim) 1027 end_unlink_async(ehci); 1028 1029 /* If the QH isn't linked then there's nothing we can do 1030 * unless we were called during a giveback, in which case 1031 * qh_completions() has to deal with it. 1032 */ 1033 if (qh->qh_state != QH_STATE_LINKED) { 1034 if (qh->qh_state == QH_STATE_COMPLETING) 1035 qh->needs_rescan = 1; 1036 return; 1037 } 1038 1039 /* defer till later if busy */ 1040 if (ehci->reclaim) { 1041 struct ehci_qh *last; 1042 1043 for (last = ehci->reclaim; 1044 last->reclaim; 1045 last = last->reclaim) 1046 continue; 1047 qh->qh_state = QH_STATE_UNLINK_WAIT; 1048 last->reclaim = qh; 1049 1050 /* start IAA cycle */ 1051 } else 1052 start_unlink_async (ehci, qh); 1053 } 1054 1055 /* remove from hardware lists 1056 * completions normally happen asynchronously 1057 */ 1058 1059 static int ehci_urb_dequeue(struct usb_hcd *hcd, struct urb *urb, int status) 1060 { 1061 struct ehci_hcd *ehci = hcd_to_ehci (hcd); 1062 struct ehci_qh *qh; 1063 unsigned long flags; 1064 int rc; 1065 1066 spin_lock_irqsave (&ehci->lock, flags); 1067 rc = usb_hcd_check_unlink_urb(hcd, urb, status); 1068 if (rc) 1069 goto done; 1070 1071 switch (usb_pipetype (urb->pipe)) { 1072 // case PIPE_CONTROL: 1073 // case PIPE_BULK: 1074 default: 1075 qh = (struct ehci_qh *) urb->hcpriv; 1076 if (!qh) 1077 break; 1078 switch (qh->qh_state) { 1079 case QH_STATE_LINKED: 1080 case QH_STATE_COMPLETING: 1081 unlink_async(ehci, qh); 1082 break; 1083 case QH_STATE_UNLINK: 1084 case QH_STATE_UNLINK_WAIT: 1085 /* already started */ 1086 break; 1087 case QH_STATE_IDLE: 1088 /* QH might be waiting for a Clear-TT-Buffer */ 1089 qh_completions(ehci, qh); 1090 break; 1091 } 1092 break; 1093 1094 case PIPE_INTERRUPT: 1095 qh = (struct ehci_qh *) urb->hcpriv; 1096 if (!qh) 1097 break; 1098 switch (qh->qh_state) { 1099 case QH_STATE_LINKED: 1100 case QH_STATE_COMPLETING: 1101 intr_deschedule (ehci, qh); 1102 break; 1103 case QH_STATE_IDLE: 1104 qh_completions (ehci, qh); 1105 break; 1106 default: 1107 ehci_dbg (ehci, "bogus qh %p state %d\n", 1108 qh, qh->qh_state); 1109 goto done; 1110 } 1111 break; 1112 1113 case PIPE_ISOCHRONOUS: 1114 // itd or sitd ... 1115 1116 // wait till next completion, do it then. 1117 // completion irqs can wait up to 1024 msec, 1118 break; 1119 } 1120 done: 1121 spin_unlock_irqrestore (&ehci->lock, flags); 1122 return rc; 1123 } 1124 1125 /*-------------------------------------------------------------------------*/ 1126 1127 // bulk qh holds the data toggle 1128 1129 static void 1130 ehci_endpoint_disable (struct usb_hcd *hcd, struct usb_host_endpoint *ep) 1131 { 1132 struct ehci_hcd *ehci = hcd_to_ehci (hcd); 1133 unsigned long flags; 1134 struct ehci_qh *qh, *tmp; 1135 1136 /* ASSERT: any requests/urbs are being unlinked */ 1137 /* ASSERT: nobody can be submitting urbs for this any more */ 1138 1139 rescan: 1140 spin_lock_irqsave (&ehci->lock, flags); 1141 qh = ep->hcpriv; 1142 if (!qh) 1143 goto done; 1144 1145 /* endpoints can be iso streams. for now, we don't 1146 * accelerate iso completions ... so spin a while. 1147 */ 1148 if (qh->hw == NULL) { 1149 ehci_vdbg (ehci, "iso delay\n"); 1150 goto idle_timeout; 1151 } 1152 1153 if (ehci->rh_state != EHCI_RH_RUNNING) 1154 qh->qh_state = QH_STATE_IDLE; 1155 switch (qh->qh_state) { 1156 case QH_STATE_LINKED: 1157 case QH_STATE_COMPLETING: 1158 for (tmp = ehci->async->qh_next.qh; 1159 tmp && tmp != qh; 1160 tmp = tmp->qh_next.qh) 1161 continue; 1162 /* periodic qh self-unlinks on empty, and a COMPLETING qh 1163 * may already be unlinked. 1164 */ 1165 if (tmp) 1166 unlink_async(ehci, qh); 1167 /* FALL THROUGH */ 1168 case QH_STATE_UNLINK: /* wait for hw to finish? */ 1169 case QH_STATE_UNLINK_WAIT: 1170 idle_timeout: 1171 spin_unlock_irqrestore (&ehci->lock, flags); 1172 schedule_timeout_uninterruptible(1); 1173 goto rescan; 1174 case QH_STATE_IDLE: /* fully unlinked */ 1175 if (qh->clearing_tt) 1176 goto idle_timeout; 1177 if (list_empty (&qh->qtd_list)) { 1178 qh_put (qh); 1179 break; 1180 } 1181 /* else FALL THROUGH */ 1182 default: 1183 /* caller was supposed to have unlinked any requests; 1184 * that's not our job. just leak this memory. 1185 */ 1186 ehci_err (ehci, "qh %p (#%02x) state %d%s\n", 1187 qh, ep->desc.bEndpointAddress, qh->qh_state, 1188 list_empty (&qh->qtd_list) ? "" : "(has tds)"); 1189 break; 1190 } 1191 ep->hcpriv = NULL; 1192 done: 1193 spin_unlock_irqrestore (&ehci->lock, flags); 1194 } 1195 1196 static void 1197 ehci_endpoint_reset(struct usb_hcd *hcd, struct usb_host_endpoint *ep) 1198 { 1199 struct ehci_hcd *ehci = hcd_to_ehci(hcd); 1200 struct ehci_qh *qh; 1201 int eptype = usb_endpoint_type(&ep->desc); 1202 int epnum = usb_endpoint_num(&ep->desc); 1203 int is_out = usb_endpoint_dir_out(&ep->desc); 1204 unsigned long flags; 1205 1206 if (eptype != USB_ENDPOINT_XFER_BULK && eptype != USB_ENDPOINT_XFER_INT) 1207 return; 1208 1209 spin_lock_irqsave(&ehci->lock, flags); 1210 qh = ep->hcpriv; 1211 1212 /* For Bulk and Interrupt endpoints we maintain the toggle state 1213 * in the hardware; the toggle bits in udev aren't used at all. 1214 * When an endpoint is reset by usb_clear_halt() we must reset 1215 * the toggle bit in the QH. 1216 */ 1217 if (qh) { 1218 usb_settoggle(qh->dev, epnum, is_out, 0); 1219 if (!list_empty(&qh->qtd_list)) { 1220 WARN_ONCE(1, "clear_halt for a busy endpoint\n"); 1221 } else if (qh->qh_state == QH_STATE_LINKED || 1222 qh->qh_state == QH_STATE_COMPLETING) { 1223 1224 /* The toggle value in the QH can't be updated 1225 * while the QH is active. Unlink it now; 1226 * re-linking will call qh_refresh(). 1227 */ 1228 if (eptype == USB_ENDPOINT_XFER_BULK) 1229 unlink_async(ehci, qh); 1230 else 1231 intr_deschedule(ehci, qh); 1232 } 1233 } 1234 spin_unlock_irqrestore(&ehci->lock, flags); 1235 } 1236 1237 static int ehci_get_frame (struct usb_hcd *hcd) 1238 { 1239 struct ehci_hcd *ehci = hcd_to_ehci (hcd); 1240 return (ehci_read_frame_index(ehci) >> 3) % ehci->periodic_size; 1241 } 1242 1243 /*-------------------------------------------------------------------------*/ 1244 1245 MODULE_DESCRIPTION(DRIVER_DESC); 1246 MODULE_AUTHOR (DRIVER_AUTHOR); 1247 MODULE_LICENSE ("GPL"); 1248 1249 #ifdef CONFIG_PCI 1250 #include "ehci-pci.c" 1251 #define PCI_DRIVER ehci_pci_driver 1252 #endif 1253 1254 #ifdef CONFIG_USB_EHCI_FSL 1255 #include "ehci-fsl.c" 1256 #define PLATFORM_DRIVER ehci_fsl_driver 1257 #endif 1258 1259 #ifdef CONFIG_USB_EHCI_MXC 1260 #include "ehci-mxc.c" 1261 #define PLATFORM_DRIVER ehci_mxc_driver 1262 #endif 1263 1264 #ifdef CONFIG_USB_EHCI_SH 1265 #include "ehci-sh.c" 1266 #define PLATFORM_DRIVER ehci_hcd_sh_driver 1267 #endif 1268 1269 #ifdef CONFIG_MIPS_ALCHEMY 1270 #include "ehci-au1xxx.c" 1271 #define PLATFORM_DRIVER ehci_hcd_au1xxx_driver 1272 #endif 1273 1274 #ifdef CONFIG_USB_EHCI_HCD_OMAP 1275 #include "ehci-omap.c" 1276 #define PLATFORM_DRIVER ehci_hcd_omap_driver 1277 #endif 1278 1279 #ifdef CONFIG_PPC_PS3 1280 #include "ehci-ps3.c" 1281 #define PS3_SYSTEM_BUS_DRIVER ps3_ehci_driver 1282 #endif 1283 1284 #ifdef CONFIG_USB_EHCI_HCD_PPC_OF 1285 #include "ehci-ppc-of.c" 1286 #define OF_PLATFORM_DRIVER ehci_hcd_ppc_of_driver 1287 #endif 1288 1289 #ifdef CONFIG_XPS_USB_HCD_XILINX 1290 #include "ehci-xilinx-of.c" 1291 #define XILINX_OF_PLATFORM_DRIVER ehci_hcd_xilinx_of_driver 1292 #endif 1293 1294 #ifdef CONFIG_PLAT_ORION 1295 #include "ehci-orion.c" 1296 #define PLATFORM_DRIVER ehci_orion_driver 1297 #endif 1298 1299 #ifdef CONFIG_ARCH_IXP4XX 1300 #include "ehci-ixp4xx.c" 1301 #define PLATFORM_DRIVER ixp4xx_ehci_driver 1302 #endif 1303 1304 #ifdef CONFIG_USB_W90X900_EHCI 1305 #include "ehci-w90x900.c" 1306 #define PLATFORM_DRIVER ehci_hcd_w90x900_driver 1307 #endif 1308 1309 #ifdef CONFIG_ARCH_AT91 1310 #include "ehci-atmel.c" 1311 #define PLATFORM_DRIVER ehci_atmel_driver 1312 #endif 1313 1314 #ifdef CONFIG_USB_OCTEON_EHCI 1315 #include "ehci-octeon.c" 1316 #define PLATFORM_DRIVER ehci_octeon_driver 1317 #endif 1318 1319 #ifdef CONFIG_USB_CNS3XXX_EHCI 1320 #include "ehci-cns3xxx.c" 1321 #define PLATFORM_DRIVER cns3xxx_ehci_driver 1322 #endif 1323 1324 #ifdef CONFIG_ARCH_VT8500 1325 #include "ehci-vt8500.c" 1326 #define PLATFORM_DRIVER vt8500_ehci_driver 1327 #endif 1328 1329 #ifdef CONFIG_PLAT_SPEAR 1330 #include "ehci-spear.c" 1331 #define PLATFORM_DRIVER spear_ehci_hcd_driver 1332 #endif 1333 1334 #ifdef CONFIG_USB_EHCI_MSM 1335 #include "ehci-msm.c" 1336 #define PLATFORM_DRIVER ehci_msm_driver 1337 #endif 1338 1339 #ifdef CONFIG_USB_EHCI_HCD_PMC_MSP 1340 #include "ehci-pmcmsp.c" 1341 #define PLATFORM_DRIVER ehci_hcd_msp_driver 1342 #endif 1343 1344 #ifdef CONFIG_USB_EHCI_TEGRA 1345 #include "ehci-tegra.c" 1346 #define PLATFORM_DRIVER tegra_ehci_driver 1347 #endif 1348 1349 #ifdef CONFIG_USB_EHCI_S5P 1350 #include "ehci-s5p.c" 1351 #define PLATFORM_DRIVER s5p_ehci_driver 1352 #endif 1353 1354 #ifdef CONFIG_SPARC_LEON 1355 #include "ehci-grlib.c" 1356 #define PLATFORM_DRIVER ehci_grlib_driver 1357 #endif 1358 1359 #ifdef CONFIG_CPU_XLR 1360 #include "ehci-xls.c" 1361 #define PLATFORM_DRIVER ehci_xls_driver 1362 #endif 1363 1364 #ifdef CONFIG_USB_EHCI_MV 1365 #include "ehci-mv.c" 1366 #define PLATFORM_DRIVER ehci_mv_driver 1367 #endif 1368 1369 #ifdef CONFIG_MACH_LOONGSON1 1370 #include "ehci-ls1x.c" 1371 #define PLATFORM_DRIVER ehci_ls1x_driver 1372 #endif 1373 1374 #ifdef CONFIG_USB_EHCI_HCD_PLATFORM 1375 #include "ehci-platform.c" 1376 #define PLATFORM_DRIVER ehci_platform_driver 1377 #endif 1378 1379 #if !defined(PCI_DRIVER) && !defined(PLATFORM_DRIVER) && \ 1380 !defined(PS3_SYSTEM_BUS_DRIVER) && !defined(OF_PLATFORM_DRIVER) && \ 1381 !defined(XILINX_OF_PLATFORM_DRIVER) 1382 #error "missing bus glue for ehci-hcd" 1383 #endif 1384 1385 static int __init ehci_hcd_init(void) 1386 { 1387 int retval = 0; 1388 1389 if (usb_disabled()) 1390 return -ENODEV; 1391 1392 printk(KERN_INFO "%s: " DRIVER_DESC "\n", hcd_name); 1393 set_bit(USB_EHCI_LOADED, &usb_hcds_loaded); 1394 if (test_bit(USB_UHCI_LOADED, &usb_hcds_loaded) || 1395 test_bit(USB_OHCI_LOADED, &usb_hcds_loaded)) 1396 printk(KERN_WARNING "Warning! ehci_hcd should always be loaded" 1397 " before uhci_hcd and ohci_hcd, not after\n"); 1398 1399 pr_debug("%s: block sizes: qh %Zd qtd %Zd itd %Zd sitd %Zd\n", 1400 hcd_name, 1401 sizeof(struct ehci_qh), sizeof(struct ehci_qtd), 1402 sizeof(struct ehci_itd), sizeof(struct ehci_sitd)); 1403 1404 #ifdef DEBUG 1405 ehci_debug_root = debugfs_create_dir("ehci", usb_debug_root); 1406 if (!ehci_debug_root) { 1407 retval = -ENOENT; 1408 goto err_debug; 1409 } 1410 #endif 1411 1412 #ifdef PLATFORM_DRIVER 1413 retval = platform_driver_register(&PLATFORM_DRIVER); 1414 if (retval < 0) 1415 goto clean0; 1416 #endif 1417 1418 #ifdef PCI_DRIVER 1419 retval = pci_register_driver(&PCI_DRIVER); 1420 if (retval < 0) 1421 goto clean1; 1422 #endif 1423 1424 #ifdef PS3_SYSTEM_BUS_DRIVER 1425 retval = ps3_ehci_driver_register(&PS3_SYSTEM_BUS_DRIVER); 1426 if (retval < 0) 1427 goto clean2; 1428 #endif 1429 1430 #ifdef OF_PLATFORM_DRIVER 1431 retval = platform_driver_register(&OF_PLATFORM_DRIVER); 1432 if (retval < 0) 1433 goto clean3; 1434 #endif 1435 1436 #ifdef XILINX_OF_PLATFORM_DRIVER 1437 retval = platform_driver_register(&XILINX_OF_PLATFORM_DRIVER); 1438 if (retval < 0) 1439 goto clean4; 1440 #endif 1441 return retval; 1442 1443 #ifdef XILINX_OF_PLATFORM_DRIVER 1444 /* platform_driver_unregister(&XILINX_OF_PLATFORM_DRIVER); */ 1445 clean4: 1446 #endif 1447 #ifdef OF_PLATFORM_DRIVER 1448 platform_driver_unregister(&OF_PLATFORM_DRIVER); 1449 clean3: 1450 #endif 1451 #ifdef PS3_SYSTEM_BUS_DRIVER 1452 ps3_ehci_driver_unregister(&PS3_SYSTEM_BUS_DRIVER); 1453 clean2: 1454 #endif 1455 #ifdef PCI_DRIVER 1456 pci_unregister_driver(&PCI_DRIVER); 1457 clean1: 1458 #endif 1459 #ifdef PLATFORM_DRIVER 1460 platform_driver_unregister(&PLATFORM_DRIVER); 1461 clean0: 1462 #endif 1463 #ifdef DEBUG 1464 debugfs_remove(ehci_debug_root); 1465 ehci_debug_root = NULL; 1466 err_debug: 1467 #endif 1468 clear_bit(USB_EHCI_LOADED, &usb_hcds_loaded); 1469 return retval; 1470 } 1471 module_init(ehci_hcd_init); 1472 1473 static void __exit ehci_hcd_cleanup(void) 1474 { 1475 #ifdef XILINX_OF_PLATFORM_DRIVER 1476 platform_driver_unregister(&XILINX_OF_PLATFORM_DRIVER); 1477 #endif 1478 #ifdef OF_PLATFORM_DRIVER 1479 platform_driver_unregister(&OF_PLATFORM_DRIVER); 1480 #endif 1481 #ifdef PLATFORM_DRIVER 1482 platform_driver_unregister(&PLATFORM_DRIVER); 1483 #endif 1484 #ifdef PCI_DRIVER 1485 pci_unregister_driver(&PCI_DRIVER); 1486 #endif 1487 #ifdef PS3_SYSTEM_BUS_DRIVER 1488 ps3_ehci_driver_unregister(&PS3_SYSTEM_BUS_DRIVER); 1489 #endif 1490 #ifdef DEBUG 1491 debugfs_remove(ehci_debug_root); 1492 #endif 1493 clear_bit(USB_EHCI_LOADED, &usb_hcds_loaded); 1494 } 1495 module_exit(ehci_hcd_cleanup); 1496 1497