15fd54aceSGreg Kroah-Hartman // SPDX-License-Identifier: GPL-2.0+ 258c559e6SRamneek Mehresh /* Copyright (C) 2005-2010,2012 Freescale Semiconductor, Inc. 380cb9aeeSRandy Vinson * Copyright (c) 2005 MontaVista Software 480cb9aeeSRandy Vinson * 580cb9aeeSRandy Vinson * This program is free software; you can redistribute it and/or modify it 680cb9aeeSRandy Vinson * under the terms of the GNU General Public License as published by the 780cb9aeeSRandy Vinson * Free Software Foundation; either version 2 of the License, or (at your 880cb9aeeSRandy Vinson * option) any later version. 980cb9aeeSRandy Vinson * 1080cb9aeeSRandy Vinson * This program is distributed in the hope that it will be useful, but 1180cb9aeeSRandy Vinson * WITHOUT ANY WARRANTY; without even the implied warranty of 1280cb9aeeSRandy Vinson * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU 1380cb9aeeSRandy Vinson * General Public License for more details. 1480cb9aeeSRandy Vinson * 1580cb9aeeSRandy Vinson * You should have received a copy of the GNU General Public License along 1680cb9aeeSRandy Vinson * with this program; if not, write to the Free Software Foundation, Inc., 1780cb9aeeSRandy Vinson * 675 Mass Ave, Cambridge, MA 02139, USA. 1880cb9aeeSRandy Vinson */ 1980cb9aeeSRandy Vinson #ifndef _EHCI_FSL_H 2080cb9aeeSRandy Vinson #define _EHCI_FSL_H 2180cb9aeeSRandy Vinson 2280cb9aeeSRandy Vinson /* offsets for the non-ehci registers in the FSL SOC USB controller */ 23761bbcb7SAnatolij Gustschin #define FSL_SOC_USB_SBUSCFG 0x90 24761bbcb7SAnatolij Gustschin #define SBUSCFG_INCR8 0x02 /* INCR8, specified */ 2580cb9aeeSRandy Vinson #define FSL_SOC_USB_ULPIVP 0x170 2680cb9aeeSRandy Vinson #define FSL_SOC_USB_PORTSC1 0x184 2780cb9aeeSRandy Vinson #define PORT_PTS_MSK (3<<30) 2880cb9aeeSRandy Vinson #define PORT_PTS_UTMI (0<<30) 2980cb9aeeSRandy Vinson #define PORT_PTS_ULPI (2<<30) 3080cb9aeeSRandy Vinson #define PORT_PTS_SERIAL (3<<30) 3180cb9aeeSRandy Vinson #define PORT_PTS_PTW (1<<28) 3280cb9aeeSRandy Vinson #define FSL_SOC_USB_PORTSC2 0x188 3313b7ee2aSAnatolij Gustschin #define FSL_SOC_USB_USBMODE 0x1a8 3413b7ee2aSAnatolij Gustschin #define USBMODE_CM_MASK (3 << 0) /* controller mode mask */ 3513b7ee2aSAnatolij Gustschin #define USBMODE_CM_HOST (3 << 0) /* controller mode: host */ 3613b7ee2aSAnatolij Gustschin #define USBMODE_ES (1 << 2) /* (Big) Endian Select */ 37230f7edeSAnatolij Gustschin 38230f7edeSAnatolij Gustschin #define FSL_SOC_USB_USBGENCTRL 0x200 39230f7edeSAnatolij Gustschin #define USBGENCTRL_PPP (1 << 3) 40230f7edeSAnatolij Gustschin #define USBGENCTRL_PFP (1 << 2) 41230f7edeSAnatolij Gustschin #define FSL_SOC_USB_ISIPHYCTRL 0x204 42230f7edeSAnatolij Gustschin #define ISIPHYCTRL_PXE (1) 43230f7edeSAnatolij Gustschin #define ISIPHYCTRL_PHYE (1 << 4) 44230f7edeSAnatolij Gustschin 4580cb9aeeSRandy Vinson #define FSL_SOC_USB_SNOOP1 0x400 /* NOTE: big-endian */ 4680cb9aeeSRandy Vinson #define FSL_SOC_USB_SNOOP2 0x404 /* NOTE: big-endian */ 4780cb9aeeSRandy Vinson #define FSL_SOC_USB_AGECNTTHRSH 0x408 /* NOTE: big-endian */ 487378c57aSChristian Engelmayer #define FSL_SOC_USB_PRICTRL 0x40c /* NOTE: big-endian */ 497378c57aSChristian Engelmayer #define FSL_SOC_USB_SICTRL 0x410 /* NOTE: big-endian */ 5080cb9aeeSRandy Vinson #define FSL_SOC_USB_CTRL 0x500 /* NOTE: big-endian */ 5128c56ea1SShengzhou Liu #define CTRL_UTMI_PHY_EN (1<<9) 52529febeeSShengzhou Liu #define CTRL_PHY_CLK_VALID (1 << 17) 5340acc095SLi Yang #define SNOOP_SIZE_2GB 0x1e 5458c559e6SRamneek Mehresh 5558c559e6SRamneek Mehresh /* control Register Bit Masks */ 564e02bea8SNikhil Badola #define CONTROL_REGISTER_W1C_MASK 0x00020000 /* W1C: PHY_CLK_VALID */ 5758c559e6SRamneek Mehresh #define ULPI_INT_EN (1<<0) 5858c559e6SRamneek Mehresh #define WU_INT_EN (1<<1) 5958c559e6SRamneek Mehresh #define USB_CTRL_USB_EN (1<<2) 6058c559e6SRamneek Mehresh #define LINE_STATE_FILTER__EN (1<<3) 6158c559e6SRamneek Mehresh #define KEEP_OTG_ON (1<<4) 6258c559e6SRamneek Mehresh #define OTG_PORT (1<<5) 6358c559e6SRamneek Mehresh #define PLL_RESET (1<<8) 6458c559e6SRamneek Mehresh #define UTMI_PHY_EN (1<<9) 6558c559e6SRamneek Mehresh #define ULPI_PHY_CLK_SEL (1<<10) 663735ba8dSShengzhou Liu #define PHY_CLK_VALID (1<<17) 6780cb9aeeSRandy Vinson #endif /* _EHCI_FSL_H */ 68