1230f7edeSAnatolij Gustschin /* Copyright (C) 2005-2010 Freescale Semiconductor, Inc. 280cb9aeeSRandy Vinson * Copyright (c) 2005 MontaVista Software 380cb9aeeSRandy Vinson * 480cb9aeeSRandy Vinson * This program is free software; you can redistribute it and/or modify it 580cb9aeeSRandy Vinson * under the terms of the GNU General Public License as published by the 680cb9aeeSRandy Vinson * Free Software Foundation; either version 2 of the License, or (at your 780cb9aeeSRandy Vinson * option) any later version. 880cb9aeeSRandy Vinson * 980cb9aeeSRandy Vinson * This program is distributed in the hope that it will be useful, but 1080cb9aeeSRandy Vinson * WITHOUT ANY WARRANTY; without even the implied warranty of 1180cb9aeeSRandy Vinson * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU 1280cb9aeeSRandy Vinson * General Public License for more details. 1380cb9aeeSRandy Vinson * 1480cb9aeeSRandy Vinson * You should have received a copy of the GNU General Public License along 1580cb9aeeSRandy Vinson * with this program; if not, write to the Free Software Foundation, Inc., 1680cb9aeeSRandy Vinson * 675 Mass Ave, Cambridge, MA 02139, USA. 1780cb9aeeSRandy Vinson */ 1880cb9aeeSRandy Vinson #ifndef _EHCI_FSL_H 1980cb9aeeSRandy Vinson #define _EHCI_FSL_H 2080cb9aeeSRandy Vinson 2180cb9aeeSRandy Vinson /* offsets for the non-ehci registers in the FSL SOC USB controller */ 2280cb9aeeSRandy Vinson #define FSL_SOC_USB_ULPIVP 0x170 2380cb9aeeSRandy Vinson #define FSL_SOC_USB_PORTSC1 0x184 2480cb9aeeSRandy Vinson #define PORT_PTS_MSK (3<<30) 2580cb9aeeSRandy Vinson #define PORT_PTS_UTMI (0<<30) 2680cb9aeeSRandy Vinson #define PORT_PTS_ULPI (2<<30) 2780cb9aeeSRandy Vinson #define PORT_PTS_SERIAL (3<<30) 2880cb9aeeSRandy Vinson #define PORT_PTS_PTW (1<<28) 2980cb9aeeSRandy Vinson #define FSL_SOC_USB_PORTSC2 0x188 3013b7ee2aSAnatolij Gustschin #define FSL_SOC_USB_USBMODE 0x1a8 3113b7ee2aSAnatolij Gustschin #define USBMODE_CM_MASK (3 << 0) /* controller mode mask */ 3213b7ee2aSAnatolij Gustschin #define USBMODE_CM_HOST (3 << 0) /* controller mode: host */ 3313b7ee2aSAnatolij Gustschin #define USBMODE_ES (1 << 2) /* (Big) Endian Select */ 34230f7edeSAnatolij Gustschin 35230f7edeSAnatolij Gustschin #define FSL_SOC_USB_USBGENCTRL 0x200 36230f7edeSAnatolij Gustschin #define USBGENCTRL_PPP (1 << 3) 37230f7edeSAnatolij Gustschin #define USBGENCTRL_PFP (1 << 2) 38230f7edeSAnatolij Gustschin #define FSL_SOC_USB_ISIPHYCTRL 0x204 39230f7edeSAnatolij Gustschin #define ISIPHYCTRL_PXE (1) 40230f7edeSAnatolij Gustschin #define ISIPHYCTRL_PHYE (1 << 4) 41230f7edeSAnatolij Gustschin 4280cb9aeeSRandy Vinson #define FSL_SOC_USB_SNOOP1 0x400 /* NOTE: big-endian */ 4380cb9aeeSRandy Vinson #define FSL_SOC_USB_SNOOP2 0x404 /* NOTE: big-endian */ 4480cb9aeeSRandy Vinson #define FSL_SOC_USB_AGECNTTHRSH 0x408 /* NOTE: big-endian */ 457378c57aSChristian Engelmayer #define FSL_SOC_USB_PRICTRL 0x40c /* NOTE: big-endian */ 467378c57aSChristian Engelmayer #define FSL_SOC_USB_SICTRL 0x410 /* NOTE: big-endian */ 4780cb9aeeSRandy Vinson #define FSL_SOC_USB_CTRL 0x500 /* NOTE: big-endian */ 48529febeeSShengzhou Liu #define CTRL_PHY_CLK_VALID (1 << 17) 4940acc095SLi Yang #define SNOOP_SIZE_2GB 0x1e 5080cb9aeeSRandy Vinson #endif /* _EHCI_FSL_H */ 51