1 // SPDX-License-Identifier: GPL-2.0+ 2 /* 3 * Copyright 2005-2009 MontaVista Software, Inc. 4 * Copyright 2008,2012,2015 Freescale Semiconductor, Inc. 5 * 6 * Ported to 834x by Randy Vinson <rvinson@mvista.com> using code provided 7 * by Hunter Wu. 8 * Power Management support by Dave Liu <daveliu@freescale.com>, 9 * Jerry Huang <Chang-Ming.Huang@freescale.com> and 10 * Anton Vorontsov <avorontsov@ru.mvista.com>. 11 */ 12 13 #include <linux/kernel.h> 14 #include <linux/module.h> 15 #include <linux/types.h> 16 #include <linux/delay.h> 17 #include <linux/pm.h> 18 #include <linux/err.h> 19 #include <linux/usb.h> 20 #include <linux/usb/ehci_def.h> 21 #include <linux/usb/hcd.h> 22 #include <linux/usb/otg.h> 23 #include <linux/platform_device.h> 24 #include <linux/fsl_devices.h> 25 #include <linux/of_platform.h> 26 #include <linux/io.h> 27 28 #include "ehci.h" 29 #include "ehci-fsl.h" 30 31 #define DRIVER_DESC "Freescale EHCI Host controller driver" 32 #define DRV_NAME "fsl-ehci" 33 34 static struct hc_driver __read_mostly fsl_ehci_hc_driver; 35 36 /* configure so an HC device and id are always provided */ 37 /* always called with process context; sleeping is OK */ 38 39 /* 40 * fsl_ehci_drv_probe - initialize FSL-based HCDs 41 * @pdev: USB Host Controller being probed 42 * 43 * Context: task context, might sleep 44 * 45 * Allocates basic resources for this USB host controller. 46 */ 47 static int fsl_ehci_drv_probe(struct platform_device *pdev) 48 { 49 struct fsl_usb2_platform_data *pdata; 50 struct usb_hcd *hcd; 51 struct resource *res; 52 int irq; 53 int retval; 54 u32 tmp; 55 56 pr_debug("initializing FSL-SOC USB Controller\n"); 57 58 /* Need platform data for setup */ 59 pdata = dev_get_platdata(&pdev->dev); 60 if (!pdata) { 61 dev_err(&pdev->dev, 62 "No platform data for %s.\n", dev_name(&pdev->dev)); 63 return -ENODEV; 64 } 65 66 /* 67 * This is a host mode driver, verify that we're supposed to be 68 * in host mode. 69 */ 70 if (!((pdata->operating_mode == FSL_USB2_DR_HOST) || 71 (pdata->operating_mode == FSL_USB2_MPH_HOST) || 72 (pdata->operating_mode == FSL_USB2_DR_OTG))) { 73 dev_err(&pdev->dev, 74 "Non Host Mode configured for %s. Wrong driver linked.\n", 75 dev_name(&pdev->dev)); 76 return -ENODEV; 77 } 78 79 irq = platform_get_irq(pdev, 0); 80 if (irq < 0) 81 return irq; 82 83 hcd = __usb_create_hcd(&fsl_ehci_hc_driver, pdev->dev.parent, 84 &pdev->dev, dev_name(&pdev->dev), NULL); 85 if (!hcd) { 86 retval = -ENOMEM; 87 goto err1; 88 } 89 90 res = platform_get_resource(pdev, IORESOURCE_MEM, 0); 91 hcd->regs = devm_ioremap_resource(&pdev->dev, res); 92 if (IS_ERR(hcd->regs)) { 93 retval = PTR_ERR(hcd->regs); 94 goto err2; 95 } 96 97 hcd->rsrc_start = res->start; 98 hcd->rsrc_len = resource_size(res); 99 100 pdata->regs = hcd->regs; 101 102 if (pdata->power_budget) 103 hcd->power_budget = pdata->power_budget; 104 105 /* 106 * do platform specific init: check the clock, grab/config pins, etc. 107 */ 108 if (pdata->init && pdata->init(pdev)) { 109 retval = -ENODEV; 110 goto err2; 111 } 112 113 /* Enable USB controller, 83xx or 8536 */ 114 if (pdata->have_sysif_regs && pdata->controller_ver < FSL_USB_VER_1_6) { 115 tmp = ioread32be(hcd->regs + FSL_SOC_USB_CTRL); 116 tmp &= ~CONTROL_REGISTER_W1C_MASK; 117 tmp |= 0x4; 118 iowrite32be(tmp, hcd->regs + FSL_SOC_USB_CTRL); 119 } 120 121 /* Set USB_EN bit to select ULPI phy for USB controller version 2.5 */ 122 if (pdata->controller_ver == FSL_USB_VER_2_5 && 123 pdata->phy_mode == FSL_USB2_PHY_ULPI) 124 iowrite32be(USB_CTRL_USB_EN, hcd->regs + FSL_SOC_USB_CTRL); 125 126 /* 127 * Enable UTMI phy and program PTS field in UTMI mode before asserting 128 * controller reset for USB Controller version 2.5 129 */ 130 if (pdata->has_fsl_erratum_a007792) { 131 tmp = ioread32be(hcd->regs + FSL_SOC_USB_CTRL); 132 tmp &= ~CONTROL_REGISTER_W1C_MASK; 133 tmp |= CTRL_UTMI_PHY_EN; 134 iowrite32be(tmp, hcd->regs + FSL_SOC_USB_CTRL); 135 136 writel(PORT_PTS_UTMI, hcd->regs + FSL_SOC_USB_PORTSC1); 137 } 138 139 /* Don't need to set host mode here. It will be done by tdi_reset() */ 140 141 retval = usb_add_hcd(hcd, irq, IRQF_SHARED); 142 if (retval != 0) 143 goto err2; 144 device_wakeup_enable(hcd->self.controller); 145 146 #ifdef CONFIG_USB_OTG 147 if (pdata->operating_mode == FSL_USB2_DR_OTG) { 148 struct ehci_hcd *ehci = hcd_to_ehci(hcd); 149 150 hcd->usb_phy = usb_get_phy(USB_PHY_TYPE_USB2); 151 dev_dbg(&pdev->dev, "hcd=0x%p ehci=0x%p, phy=0x%p\n", 152 hcd, ehci, hcd->usb_phy); 153 154 if (!IS_ERR_OR_NULL(hcd->usb_phy)) { 155 retval = otg_set_host(hcd->usb_phy->otg, 156 &ehci_to_hcd(ehci)->self); 157 if (retval) { 158 usb_put_phy(hcd->usb_phy); 159 goto err2; 160 } 161 } else { 162 dev_err(&pdev->dev, "can't find phy\n"); 163 retval = -ENODEV; 164 goto err2; 165 } 166 167 hcd->skip_phy_initialization = 1; 168 } 169 #endif 170 return retval; 171 172 err2: 173 usb_put_hcd(hcd); 174 err1: 175 dev_err(&pdev->dev, "init %s fail, %d\n", dev_name(&pdev->dev), retval); 176 if (pdata->exit) 177 pdata->exit(pdev); 178 return retval; 179 } 180 181 static bool usb_phy_clk_valid(struct usb_hcd *hcd) 182 { 183 void __iomem *non_ehci = hcd->regs; 184 bool ret = true; 185 186 if (!(ioread32be(non_ehci + FSL_SOC_USB_CTRL) & PHY_CLK_VALID)) 187 ret = false; 188 189 return ret; 190 } 191 192 static int ehci_fsl_setup_phy(struct usb_hcd *hcd, 193 enum fsl_usb2_phy_modes phy_mode, 194 unsigned int port_offset) 195 { 196 u32 portsc, tmp; 197 struct ehci_hcd *ehci = hcd_to_ehci(hcd); 198 void __iomem *non_ehci = hcd->regs; 199 struct device *dev = hcd->self.controller; 200 struct fsl_usb2_platform_data *pdata = dev_get_platdata(dev); 201 202 if (pdata->controller_ver < 0) { 203 dev_warn(hcd->self.controller, "Could not get controller version\n"); 204 return -ENODEV; 205 } 206 207 portsc = ehci_readl(ehci, &ehci->regs->port_status[port_offset]); 208 portsc &= ~(PORT_PTS_MSK | PORT_PTS_PTW); 209 210 switch (phy_mode) { 211 case FSL_USB2_PHY_ULPI: 212 if (pdata->have_sysif_regs && pdata->controller_ver) { 213 /* controller version 1.6 or above */ 214 /* turn off UTMI PHY first */ 215 tmp = ioread32be(non_ehci + FSL_SOC_USB_CTRL); 216 tmp &= ~(CONTROL_REGISTER_W1C_MASK | UTMI_PHY_EN); 217 iowrite32be(tmp, non_ehci + FSL_SOC_USB_CTRL); 218 219 /* then turn on ULPI and enable USB controller */ 220 tmp = ioread32be(non_ehci + FSL_SOC_USB_CTRL); 221 tmp &= ~CONTROL_REGISTER_W1C_MASK; 222 tmp |= ULPI_PHY_CLK_SEL | USB_CTRL_USB_EN; 223 iowrite32be(tmp, non_ehci + FSL_SOC_USB_CTRL); 224 } 225 portsc |= PORT_PTS_ULPI; 226 break; 227 case FSL_USB2_PHY_SERIAL: 228 portsc |= PORT_PTS_SERIAL; 229 break; 230 case FSL_USB2_PHY_UTMI_WIDE: 231 portsc |= PORT_PTS_PTW; 232 fallthrough; 233 case FSL_USB2_PHY_UTMI: 234 /* Presence of this node "has_fsl_erratum_a006918" 235 * in device-tree is used to stop USB controller 236 * initialization in Linux 237 */ 238 if (pdata->has_fsl_erratum_a006918) { 239 dev_warn(dev, "USB PHY clock invalid\n"); 240 return -EINVAL; 241 } 242 fallthrough; 243 case FSL_USB2_PHY_UTMI_DUAL: 244 /* PHY_CLK_VALID bit is de-featured from all controller 245 * versions below 2.4 and is to be checked only for 246 * internal UTMI phy 247 */ 248 if (pdata->controller_ver > FSL_USB_VER_2_4 && 249 pdata->have_sysif_regs && !usb_phy_clk_valid(hcd)) { 250 dev_err(dev, "USB PHY clock invalid\n"); 251 return -EINVAL; 252 } 253 254 if (pdata->have_sysif_regs && pdata->controller_ver) { 255 /* controller version 1.6 or above */ 256 tmp = ioread32be(non_ehci + FSL_SOC_USB_CTRL); 257 tmp &= ~CONTROL_REGISTER_W1C_MASK; 258 tmp |= UTMI_PHY_EN; 259 iowrite32be(tmp, non_ehci + FSL_SOC_USB_CTRL); 260 261 mdelay(FSL_UTMI_PHY_DLY); /* Delay for UTMI PHY CLK to 262 become stable - 10ms*/ 263 } 264 /* enable UTMI PHY */ 265 if (pdata->have_sysif_regs) { 266 tmp = ioread32be(non_ehci + FSL_SOC_USB_CTRL); 267 tmp &= ~CONTROL_REGISTER_W1C_MASK; 268 tmp |= CTRL_UTMI_PHY_EN; 269 iowrite32be(tmp, non_ehci + FSL_SOC_USB_CTRL); 270 } 271 portsc |= PORT_PTS_UTMI; 272 break; 273 case FSL_USB2_PHY_NONE: 274 break; 275 } 276 277 if (pdata->have_sysif_regs && 278 pdata->controller_ver > FSL_USB_VER_1_6 && 279 !usb_phy_clk_valid(hcd)) { 280 dev_warn(hcd->self.controller, "USB PHY clock invalid\n"); 281 return -EINVAL; 282 } 283 284 ehci_writel(ehci, portsc, &ehci->regs->port_status[port_offset]); 285 286 if (phy_mode != FSL_USB2_PHY_ULPI && pdata->have_sysif_regs) { 287 tmp = ioread32be(non_ehci + FSL_SOC_USB_CTRL); 288 tmp &= ~CONTROL_REGISTER_W1C_MASK; 289 tmp |= USB_CTRL_USB_EN; 290 iowrite32be(tmp, non_ehci + FSL_SOC_USB_CTRL); 291 } 292 293 return 0; 294 } 295 296 static int ehci_fsl_usb_setup(struct ehci_hcd *ehci) 297 { 298 struct usb_hcd *hcd = ehci_to_hcd(ehci); 299 struct fsl_usb2_platform_data *pdata; 300 void __iomem *non_ehci = hcd->regs; 301 302 pdata = dev_get_platdata(hcd->self.controller); 303 304 if (pdata->have_sysif_regs) { 305 /* 306 * Turn on cache snooping hardware, since some PowerPC platforms 307 * wholly rely on hardware to deal with cache coherent 308 */ 309 310 /* Setup Snooping for all the 4GB space */ 311 /* SNOOP1 starts from 0x0, size 2G */ 312 iowrite32be(0x0 | SNOOP_SIZE_2GB, 313 non_ehci + FSL_SOC_USB_SNOOP1); 314 /* SNOOP2 starts from 0x80000000, size 2G */ 315 iowrite32be(0x80000000 | SNOOP_SIZE_2GB, 316 non_ehci + FSL_SOC_USB_SNOOP2); 317 } 318 319 /* Deal with USB erratum A-005275 */ 320 if (pdata->has_fsl_erratum_a005275 == 1) 321 ehci->has_fsl_hs_errata = 1; 322 323 if (pdata->has_fsl_erratum_a005697 == 1) 324 ehci->has_fsl_susp_errata = 1; 325 326 if ((pdata->operating_mode == FSL_USB2_DR_HOST) || 327 (pdata->operating_mode == FSL_USB2_DR_OTG)) 328 if (ehci_fsl_setup_phy(hcd, pdata->phy_mode, 0)) 329 return -EINVAL; 330 331 if (pdata->operating_mode == FSL_USB2_MPH_HOST) { 332 333 /* Deal with USB Erratum #14 on MPC834x Rev 1.0 & 1.1 chips */ 334 if (pdata->has_fsl_erratum_14 == 1) 335 ehci->has_fsl_port_bug = 1; 336 337 if (pdata->port_enables & FSL_USB2_PORT0_ENABLED) 338 if (ehci_fsl_setup_phy(hcd, pdata->phy_mode, 0)) 339 return -EINVAL; 340 341 if (pdata->port_enables & FSL_USB2_PORT1_ENABLED) 342 if (ehci_fsl_setup_phy(hcd, pdata->phy_mode, 1)) 343 return -EINVAL; 344 } 345 346 if (pdata->have_sysif_regs) { 347 #ifdef CONFIG_FSL_SOC_BOOKE 348 iowrite32be(0x00000008, non_ehci + FSL_SOC_USB_PRICTRL); 349 iowrite32be(0x00000080, non_ehci + FSL_SOC_USB_AGECNTTHRSH); 350 #else 351 iowrite32be(0x0000000c, non_ehci + FSL_SOC_USB_PRICTRL); 352 iowrite32be(0x00000040, non_ehci + FSL_SOC_USB_AGECNTTHRSH); 353 #endif 354 iowrite32be(0x00000001, non_ehci + FSL_SOC_USB_SICTRL); 355 } 356 357 return 0; 358 } 359 360 /* called after powerup, by probe or system-pm "wakeup" */ 361 static int ehci_fsl_reinit(struct ehci_hcd *ehci) 362 { 363 if (ehci_fsl_usb_setup(ehci)) 364 return -EINVAL; 365 366 return 0; 367 } 368 369 /* called during probe() after chip reset completes */ 370 static int ehci_fsl_setup(struct usb_hcd *hcd) 371 { 372 struct ehci_hcd *ehci = hcd_to_ehci(hcd); 373 int retval; 374 struct fsl_usb2_platform_data *pdata; 375 struct device *dev; 376 377 dev = hcd->self.controller; 378 pdata = dev_get_platdata(hcd->self.controller); 379 ehci->big_endian_desc = pdata->big_endian_desc; 380 ehci->big_endian_mmio = pdata->big_endian_mmio; 381 382 /* EHCI registers start at offset 0x100 */ 383 ehci->caps = hcd->regs + 0x100; 384 385 #if defined(CONFIG_PPC_83xx) || defined(CONFIG_PPC_85xx) 386 /* 387 * Deal with MPC834X/85XX that need port power to be cycled 388 * after the power fault condition is removed. Otherwise the 389 * state machine does not reflect PORTSC[CSC] correctly. 390 */ 391 ehci->need_oc_pp_cycle = 1; 392 #endif 393 394 hcd->has_tt = 1; 395 396 retval = ehci_setup(hcd); 397 if (retval) 398 return retval; 399 400 if (of_device_is_compatible(dev->parent->of_node, 401 "fsl,mpc5121-usb2-dr")) { 402 /* 403 * set SBUSCFG:AHBBRST so that control msgs don't 404 * fail when doing heavy PATA writes. 405 */ 406 ehci_writel(ehci, SBUSCFG_INCR8, 407 hcd->regs + FSL_SOC_USB_SBUSCFG); 408 } 409 410 retval = ehci_fsl_reinit(ehci); 411 return retval; 412 } 413 414 struct ehci_fsl { 415 struct ehci_hcd ehci; 416 417 #ifdef CONFIG_PM 418 /* Saved USB PHY settings, need to restore after deep sleep. */ 419 u32 usb_ctrl; 420 #endif 421 }; 422 423 #ifdef CONFIG_PM 424 425 #ifdef CONFIG_PPC_MPC512x 426 static int ehci_fsl_mpc512x_drv_suspend(struct device *dev) 427 { 428 struct usb_hcd *hcd = dev_get_drvdata(dev); 429 struct ehci_hcd *ehci = hcd_to_ehci(hcd); 430 struct fsl_usb2_platform_data *pdata = dev_get_platdata(dev); 431 u32 tmp; 432 433 #ifdef CONFIG_DYNAMIC_DEBUG 434 u32 mode = ehci_readl(ehci, hcd->regs + FSL_SOC_USB_USBMODE); 435 mode &= USBMODE_CM_MASK; 436 tmp = ehci_readl(ehci, hcd->regs + 0x140); /* usbcmd */ 437 438 dev_dbg(dev, "suspend=%d already_suspended=%d " 439 "mode=%d usbcmd %08x\n", pdata->suspended, 440 pdata->already_suspended, mode, tmp); 441 #endif 442 443 /* 444 * If the controller is already suspended, then this must be a 445 * PM suspend. Remember this fact, so that we will leave the 446 * controller suspended at PM resume time. 447 */ 448 if (pdata->suspended) { 449 dev_dbg(dev, "already suspended, leaving early\n"); 450 pdata->already_suspended = 1; 451 return 0; 452 } 453 454 dev_dbg(dev, "suspending...\n"); 455 456 ehci->rh_state = EHCI_RH_SUSPENDED; 457 dev->power.power_state = PMSG_SUSPEND; 458 459 /* ignore non-host interrupts */ 460 clear_bit(HCD_FLAG_HW_ACCESSIBLE, &hcd->flags); 461 462 /* stop the controller */ 463 tmp = ehci_readl(ehci, &ehci->regs->command); 464 tmp &= ~CMD_RUN; 465 ehci_writel(ehci, tmp, &ehci->regs->command); 466 467 /* save EHCI registers */ 468 pdata->pm_command = ehci_readl(ehci, &ehci->regs->command); 469 pdata->pm_command &= ~CMD_RUN; 470 pdata->pm_status = ehci_readl(ehci, &ehci->regs->status); 471 pdata->pm_intr_enable = ehci_readl(ehci, &ehci->regs->intr_enable); 472 pdata->pm_frame_index = ehci_readl(ehci, &ehci->regs->frame_index); 473 pdata->pm_segment = ehci_readl(ehci, &ehci->regs->segment); 474 pdata->pm_frame_list = ehci_readl(ehci, &ehci->regs->frame_list); 475 pdata->pm_async_next = ehci_readl(ehci, &ehci->regs->async_next); 476 pdata->pm_configured_flag = 477 ehci_readl(ehci, &ehci->regs->configured_flag); 478 pdata->pm_portsc = ehci_readl(ehci, &ehci->regs->port_status[0]); 479 pdata->pm_usbgenctrl = ehci_readl(ehci, 480 hcd->regs + FSL_SOC_USB_USBGENCTRL); 481 482 /* clear the W1C bits */ 483 pdata->pm_portsc &= cpu_to_hc32(ehci, ~PORT_RWC_BITS); 484 485 pdata->suspended = 1; 486 487 /* clear PP to cut power to the port */ 488 tmp = ehci_readl(ehci, &ehci->regs->port_status[0]); 489 tmp &= ~PORT_POWER; 490 ehci_writel(ehci, tmp, &ehci->regs->port_status[0]); 491 492 return 0; 493 } 494 495 static int ehci_fsl_mpc512x_drv_resume(struct device *dev) 496 { 497 struct usb_hcd *hcd = dev_get_drvdata(dev); 498 struct ehci_hcd *ehci = hcd_to_ehci(hcd); 499 struct fsl_usb2_platform_data *pdata = dev_get_platdata(dev); 500 u32 tmp; 501 502 dev_dbg(dev, "suspend=%d already_suspended=%d\n", 503 pdata->suspended, pdata->already_suspended); 504 505 /* 506 * If the controller was already suspended at suspend time, 507 * then don't resume it now. 508 */ 509 if (pdata->already_suspended) { 510 dev_dbg(dev, "already suspended, leaving early\n"); 511 pdata->already_suspended = 0; 512 return 0; 513 } 514 515 if (!pdata->suspended) { 516 dev_dbg(dev, "not suspended, leaving early\n"); 517 return 0; 518 } 519 520 pdata->suspended = 0; 521 522 dev_dbg(dev, "resuming...\n"); 523 524 /* set host mode */ 525 tmp = USBMODE_CM_HOST | (pdata->es ? USBMODE_ES : 0); 526 ehci_writel(ehci, tmp, hcd->regs + FSL_SOC_USB_USBMODE); 527 528 ehci_writel(ehci, pdata->pm_usbgenctrl, 529 hcd->regs + FSL_SOC_USB_USBGENCTRL); 530 ehci_writel(ehci, ISIPHYCTRL_PXE | ISIPHYCTRL_PHYE, 531 hcd->regs + FSL_SOC_USB_ISIPHYCTRL); 532 533 ehci_writel(ehci, SBUSCFG_INCR8, hcd->regs + FSL_SOC_USB_SBUSCFG); 534 535 /* restore EHCI registers */ 536 ehci_writel(ehci, pdata->pm_command, &ehci->regs->command); 537 ehci_writel(ehci, pdata->pm_intr_enable, &ehci->regs->intr_enable); 538 ehci_writel(ehci, pdata->pm_frame_index, &ehci->regs->frame_index); 539 ehci_writel(ehci, pdata->pm_segment, &ehci->regs->segment); 540 ehci_writel(ehci, pdata->pm_frame_list, &ehci->regs->frame_list); 541 ehci_writel(ehci, pdata->pm_async_next, &ehci->regs->async_next); 542 ehci_writel(ehci, pdata->pm_configured_flag, 543 &ehci->regs->configured_flag); 544 ehci_writel(ehci, pdata->pm_portsc, &ehci->regs->port_status[0]); 545 546 set_bit(HCD_FLAG_HW_ACCESSIBLE, &hcd->flags); 547 ehci->rh_state = EHCI_RH_RUNNING; 548 dev->power.power_state = PMSG_ON; 549 550 tmp = ehci_readl(ehci, &ehci->regs->command); 551 tmp |= CMD_RUN; 552 ehci_writel(ehci, tmp, &ehci->regs->command); 553 554 usb_hcd_resume_root_hub(hcd); 555 556 return 0; 557 } 558 #else 559 static inline int ehci_fsl_mpc512x_drv_suspend(struct device *dev) 560 { 561 return 0; 562 } 563 564 static inline int ehci_fsl_mpc512x_drv_resume(struct device *dev) 565 { 566 return 0; 567 } 568 #endif /* CONFIG_PPC_MPC512x */ 569 570 static struct ehci_fsl *hcd_to_ehci_fsl(struct usb_hcd *hcd) 571 { 572 struct ehci_hcd *ehci = hcd_to_ehci(hcd); 573 574 return container_of(ehci, struct ehci_fsl, ehci); 575 } 576 577 static int ehci_fsl_drv_suspend(struct device *dev) 578 { 579 struct usb_hcd *hcd = dev_get_drvdata(dev); 580 struct ehci_fsl *ehci_fsl = hcd_to_ehci_fsl(hcd); 581 void __iomem *non_ehci = hcd->regs; 582 583 if (of_device_is_compatible(dev->parent->of_node, 584 "fsl,mpc5121-usb2-dr")) { 585 return ehci_fsl_mpc512x_drv_suspend(dev); 586 } 587 588 ehci_prepare_ports_for_controller_suspend(hcd_to_ehci(hcd), 589 device_may_wakeup(dev)); 590 if (!fsl_deep_sleep()) 591 return 0; 592 593 ehci_fsl->usb_ctrl = ioread32be(non_ehci + FSL_SOC_USB_CTRL); 594 return 0; 595 } 596 597 static int ehci_fsl_drv_resume(struct device *dev) 598 { 599 struct usb_hcd *hcd = dev_get_drvdata(dev); 600 struct ehci_fsl *ehci_fsl = hcd_to_ehci_fsl(hcd); 601 struct ehci_hcd *ehci = hcd_to_ehci(hcd); 602 void __iomem *non_ehci = hcd->regs; 603 604 if (of_device_is_compatible(dev->parent->of_node, 605 "fsl,mpc5121-usb2-dr")) { 606 return ehci_fsl_mpc512x_drv_resume(dev); 607 } 608 609 ehci_prepare_ports_for_controller_resume(ehci); 610 if (!fsl_deep_sleep()) 611 return 0; 612 613 usb_root_hub_lost_power(hcd->self.root_hub); 614 615 /* Restore USB PHY settings and enable the controller. */ 616 iowrite32be(ehci_fsl->usb_ctrl, non_ehci + FSL_SOC_USB_CTRL); 617 618 ehci_reset(ehci); 619 ehci_fsl_reinit(ehci); 620 621 return 0; 622 } 623 624 static int ehci_fsl_drv_restore(struct device *dev) 625 { 626 struct usb_hcd *hcd = dev_get_drvdata(dev); 627 628 usb_root_hub_lost_power(hcd->self.root_hub); 629 return 0; 630 } 631 632 static const struct dev_pm_ops ehci_fsl_pm_ops = { 633 .suspend = ehci_fsl_drv_suspend, 634 .resume = ehci_fsl_drv_resume, 635 .restore = ehci_fsl_drv_restore, 636 }; 637 638 #define EHCI_FSL_PM_OPS (&ehci_fsl_pm_ops) 639 #else 640 #define EHCI_FSL_PM_OPS NULL 641 #endif /* CONFIG_PM */ 642 643 #ifdef CONFIG_USB_OTG 644 static int ehci_start_port_reset(struct usb_hcd *hcd, unsigned port) 645 { 646 struct ehci_hcd *ehci = hcd_to_ehci(hcd); 647 u32 status; 648 649 if (!port) 650 return -EINVAL; 651 652 port--; 653 654 /* start port reset before HNP protocol time out */ 655 status = readl(&ehci->regs->port_status[port]); 656 if (!(status & PORT_CONNECT)) 657 return -ENODEV; 658 659 /* hub_wq will finish the reset later */ 660 if (ehci_is_TDI(ehci)) { 661 writel(PORT_RESET | 662 (status & ~(PORT_CSC | PORT_PEC | PORT_OCC)), 663 &ehci->regs->port_status[port]); 664 } else { 665 writel(PORT_RESET, &ehci->regs->port_status[port]); 666 } 667 668 return 0; 669 } 670 #else 671 #define ehci_start_port_reset NULL 672 #endif /* CONFIG_USB_OTG */ 673 674 static const struct ehci_driver_overrides ehci_fsl_overrides __initconst = { 675 .extra_priv_size = sizeof(struct ehci_fsl), 676 .reset = ehci_fsl_setup, 677 }; 678 679 /** 680 * fsl_ehci_drv_remove - shutdown processing for FSL-based HCDs 681 * @pdev: USB Host Controller being removed 682 * 683 * Context: task context, might sleep 684 * 685 * Reverses the effect of usb_hcd_fsl_probe(). 686 */ 687 static void fsl_ehci_drv_remove(struct platform_device *pdev) 688 { 689 struct fsl_usb2_platform_data *pdata = dev_get_platdata(&pdev->dev); 690 struct usb_hcd *hcd = platform_get_drvdata(pdev); 691 692 if (!IS_ERR_OR_NULL(hcd->usb_phy)) { 693 otg_set_host(hcd->usb_phy->otg, NULL); 694 usb_put_phy(hcd->usb_phy); 695 } 696 697 usb_remove_hcd(hcd); 698 699 /* 700 * do platform specific un-initialization: 701 * release iomux pins, disable clock, etc. 702 */ 703 if (pdata->exit) 704 pdata->exit(pdev); 705 usb_put_hcd(hcd); 706 } 707 708 static struct platform_driver ehci_fsl_driver = { 709 .probe = fsl_ehci_drv_probe, 710 .remove_new = fsl_ehci_drv_remove, 711 .shutdown = usb_hcd_platform_shutdown, 712 .driver = { 713 .name = DRV_NAME, 714 .pm = EHCI_FSL_PM_OPS, 715 }, 716 }; 717 718 static int __init ehci_fsl_init(void) 719 { 720 if (usb_disabled()) 721 return -ENODEV; 722 723 ehci_init_driver(&fsl_ehci_hc_driver, &ehci_fsl_overrides); 724 725 fsl_ehci_hc_driver.product_desc = 726 "Freescale On-Chip EHCI Host Controller"; 727 fsl_ehci_hc_driver.start_port_reset = ehci_start_port_reset; 728 729 730 return platform_driver_register(&ehci_fsl_driver); 731 } 732 module_init(ehci_fsl_init); 733 734 static void __exit ehci_fsl_cleanup(void) 735 { 736 platform_driver_unregister(&ehci_fsl_driver); 737 } 738 module_exit(ehci_fsl_cleanup); 739 740 MODULE_DESCRIPTION(DRIVER_DESC); 741 MODULE_LICENSE("GPL"); 742 MODULE_ALIAS("platform:" DRV_NAME); 743