1 // SPDX-License-Identifier: GPL-2.0+ 2 /* 3 * Copyright 2005-2009 MontaVista Software, Inc. 4 * Copyright 2008,2012,2015 Freescale Semiconductor, Inc. 5 * 6 * Ported to 834x by Randy Vinson <rvinson@mvista.com> using code provided 7 * by Hunter Wu. 8 * Power Management support by Dave Liu <daveliu@freescale.com>, 9 * Jerry Huang <Chang-Ming.Huang@freescale.com> and 10 * Anton Vorontsov <avorontsov@ru.mvista.com>. 11 */ 12 13 #include <linux/kernel.h> 14 #include <linux/module.h> 15 #include <linux/types.h> 16 #include <linux/delay.h> 17 #include <linux/pm.h> 18 #include <linux/err.h> 19 #include <linux/usb.h> 20 #include <linux/usb/ehci_def.h> 21 #include <linux/usb/hcd.h> 22 #include <linux/usb/otg.h> 23 #include <linux/platform_device.h> 24 #include <linux/fsl_devices.h> 25 #include <linux/of_platform.h> 26 #include <linux/io.h> 27 28 #include "ehci.h" 29 #include "ehci-fsl.h" 30 31 #define DRIVER_DESC "Freescale EHCI Host controller driver" 32 #define DRV_NAME "ehci-fsl" 33 34 static struct hc_driver __read_mostly fsl_ehci_hc_driver; 35 36 /* configure so an HC device and id are always provided */ 37 /* always called with process context; sleeping is OK */ 38 39 /* 40 * fsl_ehci_drv_probe - initialize FSL-based HCDs 41 * @pdev: USB Host Controller being probed 42 * Context: !in_interrupt() 43 * 44 * Allocates basic resources for this USB host controller. 45 * 46 */ 47 static int fsl_ehci_drv_probe(struct platform_device *pdev) 48 { 49 struct fsl_usb2_platform_data *pdata; 50 struct usb_hcd *hcd; 51 struct resource *res; 52 int irq; 53 int retval; 54 u32 tmp; 55 56 pr_debug("initializing FSL-SOC USB Controller\n"); 57 58 /* Need platform data for setup */ 59 pdata = dev_get_platdata(&pdev->dev); 60 if (!pdata) { 61 dev_err(&pdev->dev, 62 "No platform data for %s.\n", dev_name(&pdev->dev)); 63 return -ENODEV; 64 } 65 66 /* 67 * This is a host mode driver, verify that we're supposed to be 68 * in host mode. 69 */ 70 if (!((pdata->operating_mode == FSL_USB2_DR_HOST) || 71 (pdata->operating_mode == FSL_USB2_MPH_HOST) || 72 (pdata->operating_mode == FSL_USB2_DR_OTG))) { 73 dev_err(&pdev->dev, 74 "Non Host Mode configured for %s. Wrong driver linked.\n", 75 dev_name(&pdev->dev)); 76 return -ENODEV; 77 } 78 79 res = platform_get_resource(pdev, IORESOURCE_IRQ, 0); 80 if (!res) { 81 dev_err(&pdev->dev, 82 "Found HC with no IRQ. Check %s setup!\n", 83 dev_name(&pdev->dev)); 84 return -ENODEV; 85 } 86 irq = res->start; 87 88 hcd = __usb_create_hcd(&fsl_ehci_hc_driver, pdev->dev.parent, 89 &pdev->dev, dev_name(&pdev->dev), NULL); 90 if (!hcd) { 91 retval = -ENOMEM; 92 goto err1; 93 } 94 95 res = platform_get_resource(pdev, IORESOURCE_MEM, 0); 96 hcd->regs = devm_ioremap_resource(&pdev->dev, res); 97 if (IS_ERR(hcd->regs)) { 98 retval = PTR_ERR(hcd->regs); 99 goto err2; 100 } 101 102 hcd->rsrc_start = res->start; 103 hcd->rsrc_len = resource_size(res); 104 105 pdata->regs = hcd->regs; 106 107 if (pdata->power_budget) 108 hcd->power_budget = pdata->power_budget; 109 110 /* 111 * do platform specific init: check the clock, grab/config pins, etc. 112 */ 113 if (pdata->init && pdata->init(pdev)) { 114 retval = -ENODEV; 115 goto err2; 116 } 117 118 /* Enable USB controller, 83xx or 8536 */ 119 if (pdata->have_sysif_regs && pdata->controller_ver < FSL_USB_VER_1_6) { 120 tmp = ioread32be(hcd->regs + FSL_SOC_USB_CTRL); 121 tmp &= ~CONTROL_REGISTER_W1C_MASK; 122 tmp |= 0x4; 123 iowrite32be(tmp, hcd->regs + FSL_SOC_USB_CTRL); 124 } 125 /* 126 * Enable UTMI phy and program PTS field in UTMI mode before asserting 127 * controller reset for USB Controller version 2.5 128 */ 129 if (pdata->has_fsl_erratum_a007792) { 130 tmp = ioread32be(hcd->regs + FSL_SOC_USB_CTRL); 131 tmp &= ~CONTROL_REGISTER_W1C_MASK; 132 tmp |= CTRL_UTMI_PHY_EN; 133 iowrite32be(tmp, hcd->regs + FSL_SOC_USB_CTRL); 134 135 writel(PORT_PTS_UTMI, hcd->regs + FSL_SOC_USB_PORTSC1); 136 } 137 138 /* Don't need to set host mode here. It will be done by tdi_reset() */ 139 140 retval = usb_add_hcd(hcd, irq, IRQF_SHARED); 141 if (retval != 0) 142 goto err2; 143 device_wakeup_enable(hcd->self.controller); 144 145 #ifdef CONFIG_USB_OTG 146 if (pdata->operating_mode == FSL_USB2_DR_OTG) { 147 struct ehci_hcd *ehci = hcd_to_ehci(hcd); 148 149 hcd->usb_phy = usb_get_phy(USB_PHY_TYPE_USB2); 150 dev_dbg(&pdev->dev, "hcd=0x%p ehci=0x%p, phy=0x%p\n", 151 hcd, ehci, hcd->usb_phy); 152 153 if (!IS_ERR_OR_NULL(hcd->usb_phy)) { 154 retval = otg_set_host(hcd->usb_phy->otg, 155 &ehci_to_hcd(ehci)->self); 156 if (retval) { 157 usb_put_phy(hcd->usb_phy); 158 goto err2; 159 } 160 } else { 161 dev_err(&pdev->dev, "can't find phy\n"); 162 retval = -ENODEV; 163 goto err2; 164 } 165 166 hcd->skip_phy_initialization = 1; 167 } 168 #endif 169 return retval; 170 171 err2: 172 usb_put_hcd(hcd); 173 err1: 174 dev_err(&pdev->dev, "init %s fail, %d\n", dev_name(&pdev->dev), retval); 175 if (pdata->exit) 176 pdata->exit(pdev); 177 return retval; 178 } 179 180 static int ehci_fsl_setup_phy(struct usb_hcd *hcd, 181 enum fsl_usb2_phy_modes phy_mode, 182 unsigned int port_offset) 183 { 184 u32 portsc, tmp; 185 struct ehci_hcd *ehci = hcd_to_ehci(hcd); 186 void __iomem *non_ehci = hcd->regs; 187 struct device *dev = hcd->self.controller; 188 struct fsl_usb2_platform_data *pdata = dev_get_platdata(dev); 189 190 if (pdata->controller_ver < 0) { 191 dev_warn(hcd->self.controller, "Could not get controller version\n"); 192 return -ENODEV; 193 } 194 195 portsc = ehci_readl(ehci, &ehci->regs->port_status[port_offset]); 196 portsc &= ~(PORT_PTS_MSK | PORT_PTS_PTW); 197 198 switch (phy_mode) { 199 case FSL_USB2_PHY_ULPI: 200 if (pdata->have_sysif_regs && pdata->controller_ver) { 201 /* controller version 1.6 or above */ 202 /* turn off UTMI PHY first */ 203 tmp = ioread32be(non_ehci + FSL_SOC_USB_CTRL); 204 tmp &= ~(CONTROL_REGISTER_W1C_MASK | UTMI_PHY_EN); 205 iowrite32be(tmp, non_ehci + FSL_SOC_USB_CTRL); 206 207 /* then turn on ULPI and enable USB controller */ 208 tmp = ioread32be(non_ehci + FSL_SOC_USB_CTRL); 209 tmp &= ~CONTROL_REGISTER_W1C_MASK; 210 tmp |= ULPI_PHY_CLK_SEL | USB_CTRL_USB_EN; 211 iowrite32be(tmp, non_ehci + FSL_SOC_USB_CTRL); 212 } 213 portsc |= PORT_PTS_ULPI; 214 break; 215 case FSL_USB2_PHY_SERIAL: 216 portsc |= PORT_PTS_SERIAL; 217 break; 218 case FSL_USB2_PHY_UTMI_WIDE: 219 portsc |= PORT_PTS_PTW; 220 /* fall through */ 221 case FSL_USB2_PHY_UTMI: 222 case FSL_USB2_PHY_UTMI_DUAL: 223 if (pdata->have_sysif_regs && pdata->controller_ver) { 224 /* controller version 1.6 or above */ 225 tmp = ioread32be(non_ehci + FSL_SOC_USB_CTRL); 226 tmp &= ~CONTROL_REGISTER_W1C_MASK; 227 tmp |= UTMI_PHY_EN; 228 iowrite32be(tmp, non_ehci + FSL_SOC_USB_CTRL); 229 230 mdelay(FSL_UTMI_PHY_DLY); /* Delay for UTMI PHY CLK to 231 become stable - 10ms*/ 232 } 233 /* enable UTMI PHY */ 234 if (pdata->have_sysif_regs) { 235 tmp = ioread32be(non_ehci + FSL_SOC_USB_CTRL); 236 tmp &= ~CONTROL_REGISTER_W1C_MASK; 237 tmp |= CTRL_UTMI_PHY_EN; 238 iowrite32be(tmp, non_ehci + FSL_SOC_USB_CTRL); 239 } 240 portsc |= PORT_PTS_UTMI; 241 break; 242 case FSL_USB2_PHY_NONE: 243 break; 244 } 245 246 /* 247 * check PHY_CLK_VALID to determine phy clock presence before writing 248 * to portsc 249 */ 250 if (pdata->check_phy_clk_valid) { 251 if (!(ioread32be(non_ehci + FSL_SOC_USB_CTRL) & 252 PHY_CLK_VALID)) { 253 dev_warn(hcd->self.controller, 254 "USB PHY clock invalid\n"); 255 return -EINVAL; 256 } 257 } 258 259 ehci_writel(ehci, portsc, &ehci->regs->port_status[port_offset]); 260 261 if (phy_mode != FSL_USB2_PHY_ULPI && pdata->have_sysif_regs) { 262 tmp = ioread32be(non_ehci + FSL_SOC_USB_CTRL); 263 tmp &= ~CONTROL_REGISTER_W1C_MASK; 264 tmp |= USB_CTRL_USB_EN; 265 iowrite32be(tmp, non_ehci + FSL_SOC_USB_CTRL); 266 } 267 268 return 0; 269 } 270 271 static int ehci_fsl_usb_setup(struct ehci_hcd *ehci) 272 { 273 struct usb_hcd *hcd = ehci_to_hcd(ehci); 274 struct fsl_usb2_platform_data *pdata; 275 void __iomem *non_ehci = hcd->regs; 276 277 pdata = dev_get_platdata(hcd->self.controller); 278 279 if (pdata->have_sysif_regs) { 280 /* 281 * Turn on cache snooping hardware, since some PowerPC platforms 282 * wholly rely on hardware to deal with cache coherent 283 */ 284 285 /* Setup Snooping for all the 4GB space */ 286 /* SNOOP1 starts from 0x0, size 2G */ 287 iowrite32be(0x0 | SNOOP_SIZE_2GB, 288 non_ehci + FSL_SOC_USB_SNOOP1); 289 /* SNOOP2 starts from 0x80000000, size 2G */ 290 iowrite32be(0x80000000 | SNOOP_SIZE_2GB, 291 non_ehci + FSL_SOC_USB_SNOOP2); 292 } 293 294 /* Deal with USB erratum A-005275 */ 295 if (pdata->has_fsl_erratum_a005275 == 1) 296 ehci->has_fsl_hs_errata = 1; 297 298 if (pdata->has_fsl_erratum_a005697 == 1) 299 ehci->has_fsl_susp_errata = 1; 300 301 if ((pdata->operating_mode == FSL_USB2_DR_HOST) || 302 (pdata->operating_mode == FSL_USB2_DR_OTG)) 303 if (ehci_fsl_setup_phy(hcd, pdata->phy_mode, 0)) 304 return -EINVAL; 305 306 if (pdata->operating_mode == FSL_USB2_MPH_HOST) { 307 308 /* Deal with USB Erratum #14 on MPC834x Rev 1.0 & 1.1 chips */ 309 if (pdata->has_fsl_erratum_14 == 1) 310 ehci->has_fsl_port_bug = 1; 311 312 if (pdata->port_enables & FSL_USB2_PORT0_ENABLED) 313 if (ehci_fsl_setup_phy(hcd, pdata->phy_mode, 0)) 314 return -EINVAL; 315 316 if (pdata->port_enables & FSL_USB2_PORT1_ENABLED) 317 if (ehci_fsl_setup_phy(hcd, pdata->phy_mode, 1)) 318 return -EINVAL; 319 } 320 321 if (pdata->have_sysif_regs) { 322 #ifdef CONFIG_FSL_SOC_BOOKE 323 iowrite32be(0x00000008, non_ehci + FSL_SOC_USB_PRICTRL); 324 iowrite32be(0x00000080, non_ehci + FSL_SOC_USB_AGECNTTHRSH); 325 #else 326 iowrite32be(0x0000000c, non_ehci + FSL_SOC_USB_PRICTRL); 327 iowrite32be(0x00000040, non_ehci + FSL_SOC_USB_AGECNTTHRSH); 328 #endif 329 iowrite32be(0x00000001, non_ehci + FSL_SOC_USB_SICTRL); 330 } 331 332 return 0; 333 } 334 335 /* called after powerup, by probe or system-pm "wakeup" */ 336 static int ehci_fsl_reinit(struct ehci_hcd *ehci) 337 { 338 if (ehci_fsl_usb_setup(ehci)) 339 return -EINVAL; 340 341 return 0; 342 } 343 344 /* called during probe() after chip reset completes */ 345 static int ehci_fsl_setup(struct usb_hcd *hcd) 346 { 347 struct ehci_hcd *ehci = hcd_to_ehci(hcd); 348 int retval; 349 struct fsl_usb2_platform_data *pdata; 350 struct device *dev; 351 352 dev = hcd->self.controller; 353 pdata = dev_get_platdata(hcd->self.controller); 354 ehci->big_endian_desc = pdata->big_endian_desc; 355 ehci->big_endian_mmio = pdata->big_endian_mmio; 356 357 /* EHCI registers start at offset 0x100 */ 358 ehci->caps = hcd->regs + 0x100; 359 360 #ifdef CONFIG_PPC_83xx 361 /* 362 * Deal with MPC834X that need port power to be cycled after the power 363 * fault condition is removed. Otherwise the state machine does not 364 * reflect PORTSC[CSC] correctly. 365 */ 366 ehci->need_oc_pp_cycle = 1; 367 #endif 368 369 hcd->has_tt = 1; 370 371 retval = ehci_setup(hcd); 372 if (retval) 373 return retval; 374 375 if (of_device_is_compatible(dev->parent->of_node, 376 "fsl,mpc5121-usb2-dr")) { 377 /* 378 * set SBUSCFG:AHBBRST so that control msgs don't 379 * fail when doing heavy PATA writes. 380 */ 381 ehci_writel(ehci, SBUSCFG_INCR8, 382 hcd->regs + FSL_SOC_USB_SBUSCFG); 383 } 384 385 retval = ehci_fsl_reinit(ehci); 386 return retval; 387 } 388 389 struct ehci_fsl { 390 struct ehci_hcd ehci; 391 392 #ifdef CONFIG_PM 393 /* Saved USB PHY settings, need to restore after deep sleep. */ 394 u32 usb_ctrl; 395 #endif 396 }; 397 398 #ifdef CONFIG_PM 399 400 #ifdef CONFIG_PPC_MPC512x 401 static int ehci_fsl_mpc512x_drv_suspend(struct device *dev) 402 { 403 struct usb_hcd *hcd = dev_get_drvdata(dev); 404 struct ehci_hcd *ehci = hcd_to_ehci(hcd); 405 struct fsl_usb2_platform_data *pdata = dev_get_platdata(dev); 406 u32 tmp; 407 408 #ifdef CONFIG_DYNAMIC_DEBUG 409 u32 mode = ehci_readl(ehci, hcd->regs + FSL_SOC_USB_USBMODE); 410 mode &= USBMODE_CM_MASK; 411 tmp = ehci_readl(ehci, hcd->regs + 0x140); /* usbcmd */ 412 413 dev_dbg(dev, "suspend=%d already_suspended=%d " 414 "mode=%d usbcmd %08x\n", pdata->suspended, 415 pdata->already_suspended, mode, tmp); 416 #endif 417 418 /* 419 * If the controller is already suspended, then this must be a 420 * PM suspend. Remember this fact, so that we will leave the 421 * controller suspended at PM resume time. 422 */ 423 if (pdata->suspended) { 424 dev_dbg(dev, "already suspended, leaving early\n"); 425 pdata->already_suspended = 1; 426 return 0; 427 } 428 429 dev_dbg(dev, "suspending...\n"); 430 431 ehci->rh_state = EHCI_RH_SUSPENDED; 432 dev->power.power_state = PMSG_SUSPEND; 433 434 /* ignore non-host interrupts */ 435 clear_bit(HCD_FLAG_HW_ACCESSIBLE, &hcd->flags); 436 437 /* stop the controller */ 438 tmp = ehci_readl(ehci, &ehci->regs->command); 439 tmp &= ~CMD_RUN; 440 ehci_writel(ehci, tmp, &ehci->regs->command); 441 442 /* save EHCI registers */ 443 pdata->pm_command = ehci_readl(ehci, &ehci->regs->command); 444 pdata->pm_command &= ~CMD_RUN; 445 pdata->pm_status = ehci_readl(ehci, &ehci->regs->status); 446 pdata->pm_intr_enable = ehci_readl(ehci, &ehci->regs->intr_enable); 447 pdata->pm_frame_index = ehci_readl(ehci, &ehci->regs->frame_index); 448 pdata->pm_segment = ehci_readl(ehci, &ehci->regs->segment); 449 pdata->pm_frame_list = ehci_readl(ehci, &ehci->regs->frame_list); 450 pdata->pm_async_next = ehci_readl(ehci, &ehci->regs->async_next); 451 pdata->pm_configured_flag = 452 ehci_readl(ehci, &ehci->regs->configured_flag); 453 pdata->pm_portsc = ehci_readl(ehci, &ehci->regs->port_status[0]); 454 pdata->pm_usbgenctrl = ehci_readl(ehci, 455 hcd->regs + FSL_SOC_USB_USBGENCTRL); 456 457 /* clear the W1C bits */ 458 pdata->pm_portsc &= cpu_to_hc32(ehci, ~PORT_RWC_BITS); 459 460 pdata->suspended = 1; 461 462 /* clear PP to cut power to the port */ 463 tmp = ehci_readl(ehci, &ehci->regs->port_status[0]); 464 tmp &= ~PORT_POWER; 465 ehci_writel(ehci, tmp, &ehci->regs->port_status[0]); 466 467 return 0; 468 } 469 470 static int ehci_fsl_mpc512x_drv_resume(struct device *dev) 471 { 472 struct usb_hcd *hcd = dev_get_drvdata(dev); 473 struct ehci_hcd *ehci = hcd_to_ehci(hcd); 474 struct fsl_usb2_platform_data *pdata = dev_get_platdata(dev); 475 u32 tmp; 476 477 dev_dbg(dev, "suspend=%d already_suspended=%d\n", 478 pdata->suspended, pdata->already_suspended); 479 480 /* 481 * If the controller was already suspended at suspend time, 482 * then don't resume it now. 483 */ 484 if (pdata->already_suspended) { 485 dev_dbg(dev, "already suspended, leaving early\n"); 486 pdata->already_suspended = 0; 487 return 0; 488 } 489 490 if (!pdata->suspended) { 491 dev_dbg(dev, "not suspended, leaving early\n"); 492 return 0; 493 } 494 495 pdata->suspended = 0; 496 497 dev_dbg(dev, "resuming...\n"); 498 499 /* set host mode */ 500 tmp = USBMODE_CM_HOST | (pdata->es ? USBMODE_ES : 0); 501 ehci_writel(ehci, tmp, hcd->regs + FSL_SOC_USB_USBMODE); 502 503 ehci_writel(ehci, pdata->pm_usbgenctrl, 504 hcd->regs + FSL_SOC_USB_USBGENCTRL); 505 ehci_writel(ehci, ISIPHYCTRL_PXE | ISIPHYCTRL_PHYE, 506 hcd->regs + FSL_SOC_USB_ISIPHYCTRL); 507 508 ehci_writel(ehci, SBUSCFG_INCR8, hcd->regs + FSL_SOC_USB_SBUSCFG); 509 510 /* restore EHCI registers */ 511 ehci_writel(ehci, pdata->pm_command, &ehci->regs->command); 512 ehci_writel(ehci, pdata->pm_intr_enable, &ehci->regs->intr_enable); 513 ehci_writel(ehci, pdata->pm_frame_index, &ehci->regs->frame_index); 514 ehci_writel(ehci, pdata->pm_segment, &ehci->regs->segment); 515 ehci_writel(ehci, pdata->pm_frame_list, &ehci->regs->frame_list); 516 ehci_writel(ehci, pdata->pm_async_next, &ehci->regs->async_next); 517 ehci_writel(ehci, pdata->pm_configured_flag, 518 &ehci->regs->configured_flag); 519 ehci_writel(ehci, pdata->pm_portsc, &ehci->regs->port_status[0]); 520 521 set_bit(HCD_FLAG_HW_ACCESSIBLE, &hcd->flags); 522 ehci->rh_state = EHCI_RH_RUNNING; 523 dev->power.power_state = PMSG_ON; 524 525 tmp = ehci_readl(ehci, &ehci->regs->command); 526 tmp |= CMD_RUN; 527 ehci_writel(ehci, tmp, &ehci->regs->command); 528 529 usb_hcd_resume_root_hub(hcd); 530 531 return 0; 532 } 533 #else 534 static inline int ehci_fsl_mpc512x_drv_suspend(struct device *dev) 535 { 536 return 0; 537 } 538 539 static inline int ehci_fsl_mpc512x_drv_resume(struct device *dev) 540 { 541 return 0; 542 } 543 #endif /* CONFIG_PPC_MPC512x */ 544 545 static struct ehci_fsl *hcd_to_ehci_fsl(struct usb_hcd *hcd) 546 { 547 struct ehci_hcd *ehci = hcd_to_ehci(hcd); 548 549 return container_of(ehci, struct ehci_fsl, ehci); 550 } 551 552 static int ehci_fsl_drv_suspend(struct device *dev) 553 { 554 struct usb_hcd *hcd = dev_get_drvdata(dev); 555 struct ehci_fsl *ehci_fsl = hcd_to_ehci_fsl(hcd); 556 void __iomem *non_ehci = hcd->regs; 557 558 if (of_device_is_compatible(dev->parent->of_node, 559 "fsl,mpc5121-usb2-dr")) { 560 return ehci_fsl_mpc512x_drv_suspend(dev); 561 } 562 563 ehci_prepare_ports_for_controller_suspend(hcd_to_ehci(hcd), 564 device_may_wakeup(dev)); 565 if (!fsl_deep_sleep()) 566 return 0; 567 568 ehci_fsl->usb_ctrl = ioread32be(non_ehci + FSL_SOC_USB_CTRL); 569 return 0; 570 } 571 572 static int ehci_fsl_drv_resume(struct device *dev) 573 { 574 struct usb_hcd *hcd = dev_get_drvdata(dev); 575 struct ehci_fsl *ehci_fsl = hcd_to_ehci_fsl(hcd); 576 struct ehci_hcd *ehci = hcd_to_ehci(hcd); 577 void __iomem *non_ehci = hcd->regs; 578 579 if (of_device_is_compatible(dev->parent->of_node, 580 "fsl,mpc5121-usb2-dr")) { 581 return ehci_fsl_mpc512x_drv_resume(dev); 582 } 583 584 ehci_prepare_ports_for_controller_resume(ehci); 585 if (!fsl_deep_sleep()) 586 return 0; 587 588 usb_root_hub_lost_power(hcd->self.root_hub); 589 590 /* Restore USB PHY settings and enable the controller. */ 591 iowrite32be(ehci_fsl->usb_ctrl, non_ehci + FSL_SOC_USB_CTRL); 592 593 ehci_reset(ehci); 594 ehci_fsl_reinit(ehci); 595 596 return 0; 597 } 598 599 static int ehci_fsl_drv_restore(struct device *dev) 600 { 601 struct usb_hcd *hcd = dev_get_drvdata(dev); 602 603 usb_root_hub_lost_power(hcd->self.root_hub); 604 return 0; 605 } 606 607 static const struct dev_pm_ops ehci_fsl_pm_ops = { 608 .suspend = ehci_fsl_drv_suspend, 609 .resume = ehci_fsl_drv_resume, 610 .restore = ehci_fsl_drv_restore, 611 }; 612 613 #define EHCI_FSL_PM_OPS (&ehci_fsl_pm_ops) 614 #else 615 #define EHCI_FSL_PM_OPS NULL 616 #endif /* CONFIG_PM */ 617 618 #ifdef CONFIG_USB_OTG 619 static int ehci_start_port_reset(struct usb_hcd *hcd, unsigned port) 620 { 621 struct ehci_hcd *ehci = hcd_to_ehci(hcd); 622 u32 status; 623 624 if (!port) 625 return -EINVAL; 626 627 port--; 628 629 /* start port reset before HNP protocol time out */ 630 status = readl(&ehci->regs->port_status[port]); 631 if (!(status & PORT_CONNECT)) 632 return -ENODEV; 633 634 /* hub_wq will finish the reset later */ 635 if (ehci_is_TDI(ehci)) { 636 writel(PORT_RESET | 637 (status & ~(PORT_CSC | PORT_PEC | PORT_OCC)), 638 &ehci->regs->port_status[port]); 639 } else { 640 writel(PORT_RESET, &ehci->regs->port_status[port]); 641 } 642 643 return 0; 644 } 645 #else 646 #define ehci_start_port_reset NULL 647 #endif /* CONFIG_USB_OTG */ 648 649 static const struct ehci_driver_overrides ehci_fsl_overrides __initconst = { 650 .extra_priv_size = sizeof(struct ehci_fsl), 651 .reset = ehci_fsl_setup, 652 }; 653 654 /** 655 * fsl_ehci_drv_remove - shutdown processing for FSL-based HCDs 656 * @dev: USB Host Controller being removed 657 * Context: !in_interrupt() 658 * 659 * Reverses the effect of usb_hcd_fsl_probe(). 660 * 661 */ 662 663 static int fsl_ehci_drv_remove(struct platform_device *pdev) 664 { 665 struct fsl_usb2_platform_data *pdata = dev_get_platdata(&pdev->dev); 666 struct usb_hcd *hcd = platform_get_drvdata(pdev); 667 668 if (!IS_ERR_OR_NULL(hcd->usb_phy)) { 669 otg_set_host(hcd->usb_phy->otg, NULL); 670 usb_put_phy(hcd->usb_phy); 671 } 672 673 usb_remove_hcd(hcd); 674 675 /* 676 * do platform specific un-initialization: 677 * release iomux pins, disable clock, etc. 678 */ 679 if (pdata->exit) 680 pdata->exit(pdev); 681 usb_put_hcd(hcd); 682 683 return 0; 684 } 685 686 static struct platform_driver ehci_fsl_driver = { 687 .probe = fsl_ehci_drv_probe, 688 .remove = fsl_ehci_drv_remove, 689 .shutdown = usb_hcd_platform_shutdown, 690 .driver = { 691 .name = "fsl-ehci", 692 .pm = EHCI_FSL_PM_OPS, 693 }, 694 }; 695 696 static int __init ehci_fsl_init(void) 697 { 698 if (usb_disabled()) 699 return -ENODEV; 700 701 pr_info(DRV_NAME ": " DRIVER_DESC "\n"); 702 703 ehci_init_driver(&fsl_ehci_hc_driver, &ehci_fsl_overrides); 704 705 fsl_ehci_hc_driver.product_desc = 706 "Freescale On-Chip EHCI Host Controller"; 707 fsl_ehci_hc_driver.start_port_reset = ehci_start_port_reset; 708 709 710 return platform_driver_register(&ehci_fsl_driver); 711 } 712 module_init(ehci_fsl_init); 713 714 static void __exit ehci_fsl_cleanup(void) 715 { 716 platform_driver_unregister(&ehci_fsl_driver); 717 } 718 module_exit(ehci_fsl_cleanup); 719 720 MODULE_DESCRIPTION(DRIVER_DESC); 721 MODULE_LICENSE("GPL"); 722 MODULE_ALIAS("platform:" DRV_NAME); 723