1 // SPDX-License-Identifier: GPL-2.0+
2 /*
3  * Xilinx USB peripheral controller driver
4  *
5  * Copyright (C) 2004 by Thomas Rathbone
6  * Copyright (C) 2005 by HP Labs
7  * Copyright (C) 2005 by David Brownell
8  * Copyright (C) 2010 - 2014 Xilinx, Inc.
9  *
10  * Some parts of this driver code is based on the driver for at91-series
11  * USB peripheral controller (at91_udc.c).
12  */
13 
14 #include <linux/delay.h>
15 #include <linux/device.h>
16 #include <linux/dma-mapping.h>
17 #include <linux/interrupt.h>
18 #include <linux/io.h>
19 #include <linux/module.h>
20 #include <linux/of_address.h>
21 #include <linux/of_device.h>
22 #include <linux/of_platform.h>
23 #include <linux/of_irq.h>
24 #include <linux/prefetch.h>
25 #include <linux/usb/ch9.h>
26 #include <linux/usb/gadget.h>
27 
28 /* Register offsets for the USB device.*/
29 #define XUSB_EP0_CONFIG_OFFSET		0x0000  /* EP0 Config Reg Offset */
30 #define XUSB_SETUP_PKT_ADDR_OFFSET	0x0080  /* Setup Packet Address */
31 #define XUSB_ADDRESS_OFFSET		0x0100  /* Address Register */
32 #define XUSB_CONTROL_OFFSET		0x0104  /* Control Register */
33 #define XUSB_STATUS_OFFSET		0x0108  /* Status Register */
34 #define XUSB_FRAMENUM_OFFSET		0x010C	/* Frame Number Register */
35 #define XUSB_IER_OFFSET			0x0110	/* Interrupt Enable Register */
36 #define XUSB_BUFFREADY_OFFSET		0x0114	/* Buffer Ready Register */
37 #define XUSB_TESTMODE_OFFSET		0x0118	/* Test Mode Register */
38 #define XUSB_DMA_RESET_OFFSET		0x0200  /* DMA Soft Reset Register */
39 #define XUSB_DMA_CONTROL_OFFSET		0x0204	/* DMA Control Register */
40 #define XUSB_DMA_DSAR_ADDR_OFFSET	0x0208	/* DMA source Address Reg */
41 #define XUSB_DMA_DDAR_ADDR_OFFSET	0x020C	/* DMA destination Addr Reg */
42 #define XUSB_DMA_LENGTH_OFFSET		0x0210	/* DMA Length Register */
43 #define XUSB_DMA_STATUS_OFFSET		0x0214	/* DMA Status Register */
44 
45 /* Endpoint Configuration Space offsets */
46 #define XUSB_EP_CFGSTATUS_OFFSET	0x00	/* Endpoint Config Status  */
47 #define XUSB_EP_BUF0COUNT_OFFSET	0x08	/* Buffer 0 Count */
48 #define XUSB_EP_BUF1COUNT_OFFSET	0x0C	/* Buffer 1 Count */
49 
50 #define XUSB_CONTROL_USB_READY_MASK	0x80000000 /* USB ready Mask */
51 #define XUSB_CONTROL_USB_RMTWAKE_MASK	0x40000000 /* Remote wake up mask */
52 
53 /* Interrupt register related masks.*/
54 #define XUSB_STATUS_GLOBAL_INTR_MASK	0x80000000 /* Global Intr Enable */
55 #define XUSB_STATUS_DMADONE_MASK	0x04000000 /* DMA done Mask */
56 #define XUSB_STATUS_DMAERR_MASK		0x02000000 /* DMA Error Mask */
57 #define XUSB_STATUS_DMABUSY_MASK	0x80000000 /* DMA Error Mask */
58 #define XUSB_STATUS_RESUME_MASK		0x01000000 /* USB Resume Mask */
59 #define XUSB_STATUS_RESET_MASK		0x00800000 /* USB Reset Mask */
60 #define XUSB_STATUS_SUSPEND_MASK	0x00400000 /* USB Suspend Mask */
61 #define XUSB_STATUS_DISCONNECT_MASK	0x00200000 /* USB Disconnect Mask */
62 #define XUSB_STATUS_FIFO_BUFF_RDY_MASK	0x00100000 /* FIFO Buff Ready Mask */
63 #define XUSB_STATUS_FIFO_BUFF_FREE_MASK	0x00080000 /* FIFO Buff Free Mask */
64 #define XUSB_STATUS_SETUP_PACKET_MASK	0x00040000 /* Setup packet received */
65 #define XUSB_STATUS_EP1_BUFF2_COMP_MASK	0x00000200 /* EP 1 Buff 2 Processed */
66 #define XUSB_STATUS_EP1_BUFF1_COMP_MASK	0x00000002 /* EP 1 Buff 1 Processed */
67 #define XUSB_STATUS_EP0_BUFF2_COMP_MASK	0x00000100 /* EP 0 Buff 2 Processed */
68 #define XUSB_STATUS_EP0_BUFF1_COMP_MASK	0x00000001 /* EP 0 Buff 1 Processed */
69 #define XUSB_STATUS_HIGH_SPEED_MASK	0x00010000 /* USB Speed Mask */
70 /* Suspend,Reset,Suspend and Disconnect Mask */
71 #define XUSB_STATUS_INTR_EVENT_MASK	0x01E00000
72 /* Buffers  completion Mask */
73 #define XUSB_STATUS_INTR_BUFF_COMP_ALL_MASK	0x0000FEFF
74 /* Mask for buffer 0 and buffer 1 completion for all Endpoints */
75 #define XUSB_STATUS_INTR_BUFF_COMP_SHIFT_MASK	0x00000101
76 #define XUSB_STATUS_EP_BUFF2_SHIFT	8	   /* EP buffer offset */
77 
78 /* Endpoint Configuration Status Register */
79 #define XUSB_EP_CFG_VALID_MASK		0x80000000 /* Endpoint Valid bit */
80 #define XUSB_EP_CFG_STALL_MASK		0x40000000 /* Endpoint Stall bit */
81 #define XUSB_EP_CFG_DATA_TOGGLE_MASK	0x08000000 /* Endpoint Data toggle */
82 
83 /* USB device specific global configuration constants.*/
84 #define XUSB_MAX_ENDPOINTS		8	/* Maximum End Points */
85 #define XUSB_EP_NUMBER_ZERO		0	/* End point Zero */
86 /* DPRAM is the source address for DMA transfer */
87 #define XUSB_DMA_READ_FROM_DPRAM	0x80000000
88 #define XUSB_DMA_DMASR_BUSY		0x80000000 /* DMA busy */
89 #define XUSB_DMA_DMASR_ERROR		0x40000000 /* DMA Error */
90 /*
91  * When this bit is set, the DMA buffer ready bit is set by hardware upon
92  * DMA transfer completion.
93  */
94 #define XUSB_DMA_BRR_CTRL		0x40000000 /* DMA bufready ctrl bit */
95 /* Phase States */
96 #define SETUP_PHASE			0x0000	/* Setup Phase */
97 #define DATA_PHASE			0x0001  /* Data Phase */
98 #define STATUS_PHASE			0x0002  /* Status Phase */
99 
100 #define EP0_MAX_PACKET		64 /* Endpoint 0 maximum packet length */
101 #define STATUSBUFF_SIZE		2  /* Buffer size for GET_STATUS command */
102 #define EPNAME_SIZE		4  /* Buffer size for endpoint name */
103 
104 /* container_of helper macros */
105 #define to_udc(g)	 container_of((g), struct xusb_udc, gadget)
106 #define to_xusb_ep(ep)	 container_of((ep), struct xusb_ep, ep_usb)
107 #define to_xusb_req(req) container_of((req), struct xusb_req, usb_req)
108 
109 /**
110  * struct xusb_req - Xilinx USB device request structure
111  * @usb_req: Linux usb request structure
112  * @queue: usb device request queue
113  * @ep: pointer to xusb_endpoint structure
114  */
115 struct xusb_req {
116 	struct usb_request usb_req;
117 	struct list_head queue;
118 	struct xusb_ep *ep;
119 };
120 
121 /**
122  * struct xusb_ep - USB end point structure.
123  * @ep_usb: usb endpoint instance
124  * @queue: endpoint message queue
125  * @udc: xilinx usb peripheral driver instance pointer
126  * @desc: pointer to the usb endpoint descriptor
127  * @rambase: the endpoint buffer address
128  * @offset: the endpoint register offset value
129  * @name: name of the endpoint
130  * @epnumber: endpoint number
131  * @maxpacket: maximum packet size the endpoint can store
132  * @buffer0count: the size of the packet recieved in the first buffer
133  * @buffer1count: the size of the packet received in the second buffer
134  * @curbufnum: current buffer of endpoint that will be processed next
135  * @buffer0ready: the busy state of first buffer
136  * @buffer1ready: the busy state of second buffer
137  * @is_in: endpoint direction (IN or OUT)
138  * @is_iso: endpoint type(isochronous or non isochronous)
139  */
140 struct xusb_ep {
141 	struct usb_ep ep_usb;
142 	struct list_head queue;
143 	struct xusb_udc *udc;
144 	const struct usb_endpoint_descriptor *desc;
145 	u32  rambase;
146 	u32  offset;
147 	char name[4];
148 	u16  epnumber;
149 	u16  maxpacket;
150 	u16  buffer0count;
151 	u16  buffer1count;
152 	u8   curbufnum;
153 	bool buffer0ready;
154 	bool buffer1ready;
155 	bool is_in;
156 	bool is_iso;
157 };
158 
159 /**
160  * struct xusb_udc -  USB peripheral driver structure
161  * @gadget: USB gadget driver instance
162  * @ep: an array of endpoint structures
163  * @driver: pointer to the usb gadget driver instance
164  * @setup: usb_ctrlrequest structure for control requests
165  * @req: pointer to dummy request for get status command
166  * @dev: pointer to device structure in gadget
167  * @usb_state: device in suspended state or not
168  * @remote_wkp: remote wakeup enabled by host
169  * @setupseqtx: tx status
170  * @setupseqrx: rx status
171  * @addr: the usb device base address
172  * @lock: instance of spinlock
173  * @dma_enabled: flag indicating whether the dma is included in the system
174  * @read_fn: function pointer to read device registers
175  * @write_fn: function pointer to write to device registers
176  */
177 struct xusb_udc {
178 	struct usb_gadget gadget;
179 	struct xusb_ep ep[8];
180 	struct usb_gadget_driver *driver;
181 	struct usb_ctrlrequest setup;
182 	struct xusb_req *req;
183 	struct device *dev;
184 	u32 usb_state;
185 	u32 remote_wkp;
186 	u32 setupseqtx;
187 	u32 setupseqrx;
188 	void __iomem *addr;
189 	spinlock_t lock;
190 	bool dma_enabled;
191 
192 	unsigned int (*read_fn)(void __iomem *);
193 	void (*write_fn)(void __iomem *, u32, u32);
194 };
195 
196 /* Endpoint buffer start addresses in the core */
197 static u32 rambase[8] = { 0x22, 0x1000, 0x1100, 0x1200, 0x1300, 0x1400, 0x1500,
198 			  0x1600 };
199 
200 static const char driver_name[] = "xilinx-udc";
201 static const char ep0name[] = "ep0";
202 
203 /* Control endpoint configuration.*/
204 static const struct usb_endpoint_descriptor config_bulk_out_desc = {
205 	.bLength		= USB_DT_ENDPOINT_SIZE,
206 	.bDescriptorType	= USB_DT_ENDPOINT,
207 	.bEndpointAddress	= USB_DIR_OUT,
208 	.bmAttributes		= USB_ENDPOINT_XFER_BULK,
209 	.wMaxPacketSize		= cpu_to_le16(EP0_MAX_PACKET),
210 };
211 
212 /**
213  * xudc_write32 - little endian write to device registers
214  * @addr: base addr of device registers
215  * @offset: register offset
216  * @val: data to be written
217  */
218 static void xudc_write32(void __iomem *addr, u32 offset, u32 val)
219 {
220 	iowrite32(val, addr + offset);
221 }
222 
223 /**
224  * xudc_read32 - little endian read from device registers
225  * @addr: addr of device register
226  * Return: value at addr
227  */
228 static unsigned int xudc_read32(void __iomem *addr)
229 {
230 	return ioread32(addr);
231 }
232 
233 /**
234  * xudc_write32_be - big endian write to device registers
235  * @addr: base addr of device registers
236  * @offset: register offset
237  * @val: data to be written
238  */
239 static void xudc_write32_be(void __iomem *addr, u32 offset, u32 val)
240 {
241 	iowrite32be(val, addr + offset);
242 }
243 
244 /**
245  * xudc_read32_be - big endian read from device registers
246  * @addr: addr of device register
247  * Return: value at addr
248  */
249 static unsigned int xudc_read32_be(void __iomem *addr)
250 {
251 	return ioread32be(addr);
252 }
253 
254 /**
255  * xudc_wrstatus - Sets up the usb device status stages.
256  * @udc: pointer to the usb device controller structure.
257  */
258 static void xudc_wrstatus(struct xusb_udc *udc)
259 {
260 	struct xusb_ep *ep0 = &udc->ep[XUSB_EP_NUMBER_ZERO];
261 	u32 epcfgreg;
262 
263 	epcfgreg = udc->read_fn(udc->addr + ep0->offset)|
264 				XUSB_EP_CFG_DATA_TOGGLE_MASK;
265 	udc->write_fn(udc->addr, ep0->offset, epcfgreg);
266 	udc->write_fn(udc->addr, ep0->offset + XUSB_EP_BUF0COUNT_OFFSET, 0);
267 	udc->write_fn(udc->addr, XUSB_BUFFREADY_OFFSET, 1);
268 }
269 
270 /**
271  * xudc_epconfig - Configures the given endpoint.
272  * @ep: pointer to the usb device endpoint structure.
273  * @udc: pointer to the usb peripheral controller structure.
274  *
275  * This function configures a specific endpoint with the given configuration
276  * data.
277  */
278 static void xudc_epconfig(struct xusb_ep *ep, struct xusb_udc *udc)
279 {
280 	u32 epcfgreg;
281 
282 	/*
283 	 * Configure the end point direction, type, Max Packet Size and the
284 	 * EP buffer location.
285 	 */
286 	epcfgreg = ((ep->is_in << 29) | (ep->is_iso << 28) |
287 		   (ep->ep_usb.maxpacket << 15) | (ep->rambase));
288 	udc->write_fn(udc->addr, ep->offset, epcfgreg);
289 
290 	/* Set the Buffer count and the Buffer ready bits.*/
291 	udc->write_fn(udc->addr, ep->offset + XUSB_EP_BUF0COUNT_OFFSET,
292 		      ep->buffer0count);
293 	udc->write_fn(udc->addr, ep->offset + XUSB_EP_BUF1COUNT_OFFSET,
294 		      ep->buffer1count);
295 	if (ep->buffer0ready)
296 		udc->write_fn(udc->addr, XUSB_BUFFREADY_OFFSET,
297 			      1 << ep->epnumber);
298 	if (ep->buffer1ready)
299 		udc->write_fn(udc->addr, XUSB_BUFFREADY_OFFSET,
300 			      1 << (ep->epnumber + XUSB_STATUS_EP_BUFF2_SHIFT));
301 }
302 
303 /**
304  * xudc_start_dma - Starts DMA transfer.
305  * @ep: pointer to the usb device endpoint structure.
306  * @src: DMA source address.
307  * @dst: DMA destination address.
308  * @length: number of bytes to transfer.
309  *
310  * Return: 0 on success, error code on failure
311  *
312  * This function starts DMA transfer by writing to DMA source,
313  * destination and lenth registers.
314  */
315 static int xudc_start_dma(struct xusb_ep *ep, dma_addr_t src,
316 			  dma_addr_t dst, u32 length)
317 {
318 	struct xusb_udc *udc = ep->udc;
319 	int rc = 0;
320 	u32 timeout = 500;
321 	u32 reg;
322 
323 	/*
324 	 * Set the addresses in the DMA source and
325 	 * destination registers and then set the length
326 	 * into the DMA length register.
327 	 */
328 	udc->write_fn(udc->addr, XUSB_DMA_DSAR_ADDR_OFFSET, src);
329 	udc->write_fn(udc->addr, XUSB_DMA_DDAR_ADDR_OFFSET, dst);
330 	udc->write_fn(udc->addr, XUSB_DMA_LENGTH_OFFSET, length);
331 
332 	/*
333 	 * Wait till DMA transaction is complete and
334 	 * check whether the DMA transaction was
335 	 * successful.
336 	 */
337 	do {
338 		reg = udc->read_fn(udc->addr + XUSB_DMA_STATUS_OFFSET);
339 		if (!(reg &  XUSB_DMA_DMASR_BUSY))
340 			break;
341 
342 		/*
343 		 * We can't sleep here, because it's also called from
344 		 * interrupt context.
345 		 */
346 		timeout--;
347 		if (!timeout) {
348 			dev_err(udc->dev, "DMA timeout\n");
349 			return -ETIMEDOUT;
350 		}
351 		udelay(1);
352 	} while (1);
353 
354 	if ((udc->read_fn(udc->addr + XUSB_DMA_STATUS_OFFSET) &
355 			  XUSB_DMA_DMASR_ERROR) == XUSB_DMA_DMASR_ERROR){
356 		dev_err(udc->dev, "DMA Error\n");
357 		rc = -EINVAL;
358 	}
359 
360 	return rc;
361 }
362 
363 /**
364  * xudc_dma_send - Sends IN data using DMA.
365  * @ep: pointer to the usb device endpoint structure.
366  * @req: pointer to the usb request structure.
367  * @buffer: pointer to data to be sent.
368  * @length: number of bytes to send.
369  *
370  * Return: 0 on success, -EAGAIN if no buffer is free and error
371  *	   code on failure.
372  *
373  * This function sends data using DMA.
374  */
375 static int xudc_dma_send(struct xusb_ep *ep, struct xusb_req *req,
376 			 u8 *buffer, u32 length)
377 {
378 	u32 *eprambase;
379 	dma_addr_t src;
380 	dma_addr_t dst;
381 	struct xusb_udc *udc = ep->udc;
382 
383 	src = req->usb_req.dma + req->usb_req.actual;
384 	if (req->usb_req.length)
385 		dma_sync_single_for_device(udc->dev, src,
386 					   length, DMA_TO_DEVICE);
387 	if (!ep->curbufnum && !ep->buffer0ready) {
388 		/* Get the Buffer address and copy the transmit data.*/
389 		eprambase = (u32 __force *)(udc->addr + ep->rambase);
390 		dst = virt_to_phys(eprambase);
391 		udc->write_fn(udc->addr, ep->offset +
392 			      XUSB_EP_BUF0COUNT_OFFSET, length);
393 		udc->write_fn(udc->addr, XUSB_DMA_CONTROL_OFFSET,
394 			      XUSB_DMA_BRR_CTRL | (1 << ep->epnumber));
395 		ep->buffer0ready = 1;
396 		ep->curbufnum = 1;
397 	} else if (ep->curbufnum && !ep->buffer1ready) {
398 		/* Get the Buffer address and copy the transmit data.*/
399 		eprambase = (u32 __force *)(udc->addr + ep->rambase +
400 			     ep->ep_usb.maxpacket);
401 		dst = virt_to_phys(eprambase);
402 		udc->write_fn(udc->addr, ep->offset +
403 			      XUSB_EP_BUF1COUNT_OFFSET, length);
404 		udc->write_fn(udc->addr, XUSB_DMA_CONTROL_OFFSET,
405 			      XUSB_DMA_BRR_CTRL | (1 << (ep->epnumber +
406 			      XUSB_STATUS_EP_BUFF2_SHIFT)));
407 		ep->buffer1ready = 1;
408 		ep->curbufnum = 0;
409 	} else {
410 		/* None of ping pong buffers are ready currently .*/
411 		return -EAGAIN;
412 	}
413 
414 	return xudc_start_dma(ep, src, dst, length);
415 }
416 
417 /**
418  * xudc_dma_receive - Receives OUT data using DMA.
419  * @ep: pointer to the usb device endpoint structure.
420  * @req: pointer to the usb request structure.
421  * @buffer: pointer to storage buffer of received data.
422  * @length: number of bytes to receive.
423  *
424  * Return: 0 on success, -EAGAIN if no buffer is free and error
425  *	   code on failure.
426  *
427  * This function receives data using DMA.
428  */
429 static int xudc_dma_receive(struct xusb_ep *ep, struct xusb_req *req,
430 			    u8 *buffer, u32 length)
431 {
432 	u32 *eprambase;
433 	dma_addr_t src;
434 	dma_addr_t dst;
435 	struct xusb_udc *udc = ep->udc;
436 
437 	dst = req->usb_req.dma + req->usb_req.actual;
438 	if (!ep->curbufnum && !ep->buffer0ready) {
439 		/* Get the Buffer address and copy the transmit data */
440 		eprambase = (u32 __force *)(udc->addr + ep->rambase);
441 		src = virt_to_phys(eprambase);
442 		udc->write_fn(udc->addr, XUSB_DMA_CONTROL_OFFSET,
443 			      XUSB_DMA_BRR_CTRL | XUSB_DMA_READ_FROM_DPRAM |
444 			      (1 << ep->epnumber));
445 		ep->buffer0ready = 1;
446 		ep->curbufnum = 1;
447 	} else if (ep->curbufnum && !ep->buffer1ready) {
448 		/* Get the Buffer address and copy the transmit data */
449 		eprambase = (u32 __force *)(udc->addr +
450 			     ep->rambase + ep->ep_usb.maxpacket);
451 		src = virt_to_phys(eprambase);
452 		udc->write_fn(udc->addr, XUSB_DMA_CONTROL_OFFSET,
453 			      XUSB_DMA_BRR_CTRL | XUSB_DMA_READ_FROM_DPRAM |
454 			      (1 << (ep->epnumber +
455 			      XUSB_STATUS_EP_BUFF2_SHIFT)));
456 		ep->buffer1ready = 1;
457 		ep->curbufnum = 0;
458 	} else {
459 		/* None of the ping-pong buffers are ready currently */
460 		return -EAGAIN;
461 	}
462 
463 	return xudc_start_dma(ep, src, dst, length);
464 }
465 
466 /**
467  * xudc_eptxrx - Transmits or receives data to or from an endpoint.
468  * @ep: pointer to the usb endpoint configuration structure.
469  * @req: pointer to the usb request structure.
470  * @bufferptr: pointer to buffer containing the data to be sent.
471  * @bufferlen: The number of data bytes to be sent.
472  *
473  * Return: 0 on success, -EAGAIN if no buffer is free.
474  *
475  * This function copies the transmit/receive data to/from the end point buffer
476  * and enables the buffer for transmission/reception.
477  */
478 static int xudc_eptxrx(struct xusb_ep *ep, struct xusb_req *req,
479 		       u8 *bufferptr, u32 bufferlen)
480 {
481 	u32 *eprambase;
482 	u32 bytestosend;
483 	int rc = 0;
484 	struct xusb_udc *udc = ep->udc;
485 
486 	bytestosend = bufferlen;
487 	if (udc->dma_enabled) {
488 		if (ep->is_in)
489 			rc = xudc_dma_send(ep, req, bufferptr, bufferlen);
490 		else
491 			rc = xudc_dma_receive(ep, req, bufferptr, bufferlen);
492 		return rc;
493 	}
494 	/* Put the transmit buffer into the correct ping-pong buffer.*/
495 	if (!ep->curbufnum && !ep->buffer0ready) {
496 		/* Get the Buffer address and copy the transmit data.*/
497 		eprambase = (u32 __force *)(udc->addr + ep->rambase);
498 		if (ep->is_in) {
499 			memcpy(eprambase, bufferptr, bytestosend);
500 			udc->write_fn(udc->addr, ep->offset +
501 				      XUSB_EP_BUF0COUNT_OFFSET, bufferlen);
502 		} else {
503 			memcpy(bufferptr, eprambase, bytestosend);
504 		}
505 		/*
506 		 * Enable the buffer for transmission.
507 		 */
508 		udc->write_fn(udc->addr, XUSB_BUFFREADY_OFFSET,
509 			      1 << ep->epnumber);
510 		ep->buffer0ready = 1;
511 		ep->curbufnum = 1;
512 	} else if (ep->curbufnum && !ep->buffer1ready) {
513 		/* Get the Buffer address and copy the transmit data.*/
514 		eprambase = (u32 __force *)(udc->addr + ep->rambase +
515 			     ep->ep_usb.maxpacket);
516 		if (ep->is_in) {
517 			memcpy(eprambase, bufferptr, bytestosend);
518 			udc->write_fn(udc->addr, ep->offset +
519 				      XUSB_EP_BUF1COUNT_OFFSET, bufferlen);
520 		} else {
521 			memcpy(bufferptr, eprambase, bytestosend);
522 		}
523 		/*
524 		 * Enable the buffer for transmission.
525 		 */
526 		udc->write_fn(udc->addr, XUSB_BUFFREADY_OFFSET,
527 			      1 << (ep->epnumber + XUSB_STATUS_EP_BUFF2_SHIFT));
528 		ep->buffer1ready = 1;
529 		ep->curbufnum = 0;
530 	} else {
531 		/* None of the ping-pong buffers are ready currently */
532 		return -EAGAIN;
533 	}
534 	return rc;
535 }
536 
537 /**
538  * xudc_done - Exeutes the endpoint data transfer completion tasks.
539  * @ep: pointer to the usb device endpoint structure.
540  * @req: pointer to the usb request structure.
541  * @status: Status of the data transfer.
542  *
543  * Deletes the message from the queue and updates data transfer completion
544  * status.
545  */
546 static void xudc_done(struct xusb_ep *ep, struct xusb_req *req, int status)
547 {
548 	struct xusb_udc *udc = ep->udc;
549 
550 	list_del_init(&req->queue);
551 
552 	if (req->usb_req.status == -EINPROGRESS)
553 		req->usb_req.status = status;
554 	else
555 		status = req->usb_req.status;
556 
557 	if (status && status != -ESHUTDOWN)
558 		dev_dbg(udc->dev, "%s done %p, status %d\n",
559 			ep->ep_usb.name, req, status);
560 	/* unmap request if DMA is present*/
561 	if (udc->dma_enabled && ep->epnumber && req->usb_req.length)
562 		usb_gadget_unmap_request(&udc->gadget, &req->usb_req,
563 					 ep->is_in);
564 
565 	if (req->usb_req.complete) {
566 		spin_unlock(&udc->lock);
567 		req->usb_req.complete(&ep->ep_usb, &req->usb_req);
568 		spin_lock(&udc->lock);
569 	}
570 }
571 
572 /**
573  * xudc_read_fifo - Reads the data from the given endpoint buffer.
574  * @ep: pointer to the usb device endpoint structure.
575  * @req: pointer to the usb request structure.
576  *
577  * Return: 0 if request is completed and -EAGAIN if not completed.
578  *
579  * Pulls OUT packet data from the endpoint buffer.
580  */
581 static int xudc_read_fifo(struct xusb_ep *ep, struct xusb_req *req)
582 {
583 	u8 *buf;
584 	u32 is_short, count, bufferspace;
585 	u8 bufoffset;
586 	u8 two_pkts = 0;
587 	int ret;
588 	int retval = -EAGAIN;
589 	struct xusb_udc *udc = ep->udc;
590 
591 	if (ep->buffer0ready && ep->buffer1ready) {
592 		dev_dbg(udc->dev, "Packet NOT ready!\n");
593 		return retval;
594 	}
595 top:
596 	if (ep->curbufnum)
597 		bufoffset = XUSB_EP_BUF1COUNT_OFFSET;
598 	else
599 		bufoffset = XUSB_EP_BUF0COUNT_OFFSET;
600 
601 	count = udc->read_fn(udc->addr + ep->offset + bufoffset);
602 
603 	if (!ep->buffer0ready && !ep->buffer1ready)
604 		two_pkts = 1;
605 
606 	buf = req->usb_req.buf + req->usb_req.actual;
607 	prefetchw(buf);
608 	bufferspace = req->usb_req.length - req->usb_req.actual;
609 	is_short = count < ep->ep_usb.maxpacket;
610 
611 	if (unlikely(!bufferspace)) {
612 		/*
613 		 * This happens when the driver's buffer
614 		 * is smaller than what the host sent.
615 		 * discard the extra data.
616 		 */
617 		if (req->usb_req.status != -EOVERFLOW)
618 			dev_dbg(udc->dev, "%s overflow %d\n",
619 				ep->ep_usb.name, count);
620 		req->usb_req.status = -EOVERFLOW;
621 		xudc_done(ep, req, -EOVERFLOW);
622 		return 0;
623 	}
624 
625 	ret = xudc_eptxrx(ep, req, buf, count);
626 	switch (ret) {
627 	case 0:
628 		req->usb_req.actual += min(count, bufferspace);
629 		dev_dbg(udc->dev, "read %s, %d bytes%s req %p %d/%d\n",
630 			ep->ep_usb.name, count, is_short ? "/S" : "", req,
631 			req->usb_req.actual, req->usb_req.length);
632 		bufferspace -= count;
633 		/* Completion */
634 		if ((req->usb_req.actual == req->usb_req.length) || is_short) {
635 			if (udc->dma_enabled && req->usb_req.length)
636 				dma_sync_single_for_cpu(udc->dev,
637 							req->usb_req.dma,
638 							req->usb_req.actual,
639 							DMA_FROM_DEVICE);
640 			xudc_done(ep, req, 0);
641 			return 0;
642 		}
643 		if (two_pkts) {
644 			two_pkts = 0;
645 			goto top;
646 		}
647 		break;
648 	case -EAGAIN:
649 		dev_dbg(udc->dev, "receive busy\n");
650 		break;
651 	case -EINVAL:
652 	case -ETIMEDOUT:
653 		/* DMA error, dequeue the request */
654 		xudc_done(ep, req, -ECONNRESET);
655 		retval = 0;
656 		break;
657 	}
658 
659 	return retval;
660 }
661 
662 /**
663  * xudc_write_fifo - Writes data into the given endpoint buffer.
664  * @ep: pointer to the usb device endpoint structure.
665  * @req: pointer to the usb request structure.
666  *
667  * Return: 0 if request is completed and -EAGAIN if not completed.
668  *
669  * Loads endpoint buffer for an IN packet.
670  */
671 static int xudc_write_fifo(struct xusb_ep *ep, struct xusb_req *req)
672 {
673 	u32 max;
674 	u32 length;
675 	int ret;
676 	int retval = -EAGAIN;
677 	struct xusb_udc *udc = ep->udc;
678 	int is_last, is_short = 0;
679 	u8 *buf;
680 
681 	max = le16_to_cpu(ep->desc->wMaxPacketSize);
682 	buf = req->usb_req.buf + req->usb_req.actual;
683 	prefetch(buf);
684 	length = req->usb_req.length - req->usb_req.actual;
685 	length = min(length, max);
686 
687 	ret = xudc_eptxrx(ep, req, buf, length);
688 	switch (ret) {
689 	case 0:
690 		req->usb_req.actual += length;
691 		if (unlikely(length != max)) {
692 			is_last = is_short = 1;
693 		} else {
694 			if (likely(req->usb_req.length !=
695 				   req->usb_req.actual) || req->usb_req.zero)
696 				is_last = 0;
697 			else
698 				is_last = 1;
699 		}
700 		dev_dbg(udc->dev, "%s: wrote %s %d bytes%s%s %d left %p\n",
701 			__func__, ep->ep_usb.name, length, is_last ? "/L" : "",
702 			is_short ? "/S" : "",
703 			req->usb_req.length - req->usb_req.actual, req);
704 		/* completion */
705 		if (is_last) {
706 			xudc_done(ep, req, 0);
707 			retval = 0;
708 		}
709 		break;
710 	case -EAGAIN:
711 		dev_dbg(udc->dev, "Send busy\n");
712 		break;
713 	case -EINVAL:
714 	case -ETIMEDOUT:
715 		/* DMA error, dequeue the request */
716 		xudc_done(ep, req, -ECONNRESET);
717 		retval = 0;
718 		break;
719 	}
720 
721 	return retval;
722 }
723 
724 /**
725  * xudc_nuke - Cleans up the data transfer message list.
726  * @ep: pointer to the usb device endpoint structure.
727  * @status: Status of the data transfer.
728  */
729 static void xudc_nuke(struct xusb_ep *ep, int status)
730 {
731 	struct xusb_req *req;
732 
733 	while (!list_empty(&ep->queue)) {
734 		req = list_first_entry(&ep->queue, struct xusb_req, queue);
735 		xudc_done(ep, req, status);
736 	}
737 }
738 
739 /**
740  * xudc_ep_set_halt - Stalls/unstalls the given endpoint.
741  * @_ep: pointer to the usb device endpoint structure.
742  * @value: value to indicate stall/unstall.
743  *
744  * Return: 0 for success and error value on failure
745  */
746 static int xudc_ep_set_halt(struct usb_ep *_ep, int value)
747 {
748 	struct xusb_ep *ep = to_xusb_ep(_ep);
749 	struct xusb_udc *udc;
750 	unsigned long flags;
751 	u32 epcfgreg;
752 
753 	if (!_ep || (!ep->desc && ep->epnumber)) {
754 		pr_debug("%s: bad ep or descriptor\n", __func__);
755 		return -EINVAL;
756 	}
757 	udc = ep->udc;
758 
759 	if (ep->is_in && (!list_empty(&ep->queue)) && value) {
760 		dev_dbg(udc->dev, "requests pending can't halt\n");
761 		return -EAGAIN;
762 	}
763 
764 	if (ep->buffer0ready || ep->buffer1ready) {
765 		dev_dbg(udc->dev, "HW buffers busy can't halt\n");
766 		return -EAGAIN;
767 	}
768 
769 	spin_lock_irqsave(&udc->lock, flags);
770 
771 	if (value) {
772 		/* Stall the device.*/
773 		epcfgreg = udc->read_fn(udc->addr + ep->offset);
774 		epcfgreg |= XUSB_EP_CFG_STALL_MASK;
775 		udc->write_fn(udc->addr, ep->offset, epcfgreg);
776 	} else {
777 		/* Unstall the device.*/
778 		epcfgreg = udc->read_fn(udc->addr + ep->offset);
779 		epcfgreg &= ~XUSB_EP_CFG_STALL_MASK;
780 		udc->write_fn(udc->addr, ep->offset, epcfgreg);
781 		if (ep->epnumber) {
782 			/* Reset the toggle bit.*/
783 			epcfgreg = udc->read_fn(ep->udc->addr + ep->offset);
784 			epcfgreg &= ~XUSB_EP_CFG_DATA_TOGGLE_MASK;
785 			udc->write_fn(udc->addr, ep->offset, epcfgreg);
786 		}
787 	}
788 
789 	spin_unlock_irqrestore(&udc->lock, flags);
790 	return 0;
791 }
792 
793 /**
794  * xudc_ep_enable - Enables the given endpoint.
795  * @ep: pointer to the xusb endpoint structure.
796  * @desc: pointer to usb endpoint descriptor.
797  *
798  * Return: 0 for success and error value on failure
799  */
800 static int __xudc_ep_enable(struct xusb_ep *ep,
801 			    const struct usb_endpoint_descriptor *desc)
802 {
803 	struct xusb_udc *udc = ep->udc;
804 	u32 tmp;
805 	u32 epcfg;
806 	u32 ier;
807 	u16 maxpacket;
808 
809 	ep->is_in = ((desc->bEndpointAddress & USB_DIR_IN) != 0);
810 	/* Bit 3...0:endpoint number */
811 	ep->epnumber = (desc->bEndpointAddress & 0x0f);
812 	ep->desc = desc;
813 	ep->ep_usb.desc = desc;
814 	tmp = desc->bmAttributes & USB_ENDPOINT_XFERTYPE_MASK;
815 	ep->ep_usb.maxpacket = maxpacket = le16_to_cpu(desc->wMaxPacketSize);
816 
817 	switch (tmp) {
818 	case USB_ENDPOINT_XFER_CONTROL:
819 		dev_dbg(udc->dev, "only one control endpoint\n");
820 		/* NON- ISO */
821 		ep->is_iso = 0;
822 		return -EINVAL;
823 	case USB_ENDPOINT_XFER_INT:
824 		/* NON- ISO */
825 		ep->is_iso = 0;
826 		if (maxpacket > 64) {
827 			dev_dbg(udc->dev, "bogus maxpacket %d\n", maxpacket);
828 			return -EINVAL;
829 		}
830 		break;
831 	case USB_ENDPOINT_XFER_BULK:
832 		/* NON- ISO */
833 		ep->is_iso = 0;
834 		if (!(is_power_of_2(maxpacket) && maxpacket >= 8 &&
835 				maxpacket <= 512)) {
836 			dev_dbg(udc->dev, "bogus maxpacket %d\n", maxpacket);
837 			return -EINVAL;
838 		}
839 		break;
840 	case USB_ENDPOINT_XFER_ISOC:
841 		/* ISO */
842 		ep->is_iso = 1;
843 		break;
844 	}
845 
846 	ep->buffer0ready = false;
847 	ep->buffer1ready = false;
848 	ep->curbufnum = 0;
849 	ep->rambase = rambase[ep->epnumber];
850 	xudc_epconfig(ep, udc);
851 
852 	dev_dbg(udc->dev, "Enable Endpoint %d max pkt is %d\n",
853 		ep->epnumber, maxpacket);
854 
855 	/* Enable the End point.*/
856 	epcfg = udc->read_fn(udc->addr + ep->offset);
857 	epcfg |= XUSB_EP_CFG_VALID_MASK;
858 	udc->write_fn(udc->addr, ep->offset, epcfg);
859 	if (ep->epnumber)
860 		ep->rambase <<= 2;
861 
862 	/* Enable buffer completion interrupts for endpoint */
863 	ier = udc->read_fn(udc->addr + XUSB_IER_OFFSET);
864 	ier |= (XUSB_STATUS_INTR_BUFF_COMP_SHIFT_MASK << ep->epnumber);
865 	udc->write_fn(udc->addr, XUSB_IER_OFFSET, ier);
866 
867 	/* for OUT endpoint set buffers ready to receive */
868 	if (ep->epnumber && !ep->is_in) {
869 		udc->write_fn(udc->addr, XUSB_BUFFREADY_OFFSET,
870 			      1 << ep->epnumber);
871 		ep->buffer0ready = true;
872 		udc->write_fn(udc->addr, XUSB_BUFFREADY_OFFSET,
873 			     (1 << (ep->epnumber +
874 			      XUSB_STATUS_EP_BUFF2_SHIFT)));
875 		ep->buffer1ready = true;
876 	}
877 
878 	return 0;
879 }
880 
881 /**
882  * xudc_ep_enable - Enables the given endpoint.
883  * @_ep: pointer to the usb endpoint structure.
884  * @desc: pointer to usb endpoint descriptor.
885  *
886  * Return: 0 for success and error value on failure
887  */
888 static int xudc_ep_enable(struct usb_ep *_ep,
889 			  const struct usb_endpoint_descriptor *desc)
890 {
891 	struct xusb_ep *ep;
892 	struct xusb_udc *udc;
893 	unsigned long flags;
894 	int ret;
895 
896 	if (!_ep || !desc || desc->bDescriptorType != USB_DT_ENDPOINT) {
897 		pr_debug("%s: bad ep or descriptor\n", __func__);
898 		return -EINVAL;
899 	}
900 
901 	ep = to_xusb_ep(_ep);
902 	udc = ep->udc;
903 
904 	if (!udc->driver || udc->gadget.speed == USB_SPEED_UNKNOWN) {
905 		dev_dbg(udc->dev, "bogus device state\n");
906 		return -ESHUTDOWN;
907 	}
908 
909 	spin_lock_irqsave(&udc->lock, flags);
910 	ret = __xudc_ep_enable(ep, desc);
911 	spin_unlock_irqrestore(&udc->lock, flags);
912 
913 	return ret;
914 }
915 
916 /**
917  * xudc_ep_disable - Disables the given endpoint.
918  * @_ep: pointer to the usb endpoint structure.
919  *
920  * Return: 0 for success and error value on failure
921  */
922 static int xudc_ep_disable(struct usb_ep *_ep)
923 {
924 	struct xusb_ep *ep;
925 	unsigned long flags;
926 	u32 epcfg;
927 	struct xusb_udc *udc;
928 
929 	if (!_ep) {
930 		pr_debug("%s: invalid ep\n", __func__);
931 		return -EINVAL;
932 	}
933 
934 	ep = to_xusb_ep(_ep);
935 	udc = ep->udc;
936 
937 	spin_lock_irqsave(&udc->lock, flags);
938 
939 	xudc_nuke(ep, -ESHUTDOWN);
940 
941 	/* Restore the endpoint's pristine config */
942 	ep->desc = NULL;
943 	ep->ep_usb.desc = NULL;
944 
945 	dev_dbg(udc->dev, "USB Ep %d disable\n ", ep->epnumber);
946 	/* Disable the endpoint.*/
947 	epcfg = udc->read_fn(udc->addr + ep->offset);
948 	epcfg &= ~XUSB_EP_CFG_VALID_MASK;
949 	udc->write_fn(udc->addr, ep->offset, epcfg);
950 
951 	spin_unlock_irqrestore(&udc->lock, flags);
952 	return 0;
953 }
954 
955 /**
956  * xudc_ep_alloc_request - Initializes the request queue.
957  * @_ep: pointer to the usb endpoint structure.
958  * @gfp_flags: Flags related to the request call.
959  *
960  * Return: pointer to request structure on success and a NULL on failure.
961  */
962 static struct usb_request *xudc_ep_alloc_request(struct usb_ep *_ep,
963 						 gfp_t gfp_flags)
964 {
965 	struct xusb_ep *ep = to_xusb_ep(_ep);
966 	struct xusb_req *req;
967 
968 	req = kzalloc(sizeof(*req), gfp_flags);
969 	if (!req)
970 		return NULL;
971 
972 	req->ep = ep;
973 	INIT_LIST_HEAD(&req->queue);
974 	return &req->usb_req;
975 }
976 
977 /**
978  * xudc_free_request - Releases the request from queue.
979  * @_ep: pointer to the usb device endpoint structure.
980  * @_req: pointer to the usb request structure.
981  */
982 static void xudc_free_request(struct usb_ep *_ep, struct usb_request *_req)
983 {
984 	struct xusb_req *req = to_xusb_req(_req);
985 
986 	kfree(req);
987 }
988 
989 /**
990  * xudc_ep0_queue - Adds the request to endpoint 0 queue.
991  * @ep0: pointer to the xusb endpoint 0 structure.
992  * @req: pointer to the xusb request structure.
993  *
994  * Return: 0 for success and error value on failure
995  */
996 static int __xudc_ep0_queue(struct xusb_ep *ep0, struct xusb_req *req)
997 {
998 	struct xusb_udc *udc = ep0->udc;
999 	u32 length;
1000 	u8 *corebuf;
1001 
1002 	if (!udc->driver || udc->gadget.speed == USB_SPEED_UNKNOWN) {
1003 		dev_dbg(udc->dev, "%s, bogus device state\n", __func__);
1004 		return -EINVAL;
1005 	}
1006 	if (!list_empty(&ep0->queue)) {
1007 		dev_dbg(udc->dev, "%s:ep0 busy\n", __func__);
1008 		return -EBUSY;
1009 	}
1010 
1011 	req->usb_req.status = -EINPROGRESS;
1012 	req->usb_req.actual = 0;
1013 
1014 	list_add_tail(&req->queue, &ep0->queue);
1015 
1016 	if (udc->setup.bRequestType & USB_DIR_IN) {
1017 		prefetch(req->usb_req.buf);
1018 		length = req->usb_req.length;
1019 		corebuf = (void __force *) ((ep0->rambase << 2) +
1020 			   udc->addr);
1021 		length = req->usb_req.actual = min_t(u32, length,
1022 						     EP0_MAX_PACKET);
1023 		memcpy(corebuf, req->usb_req.buf, length);
1024 		udc->write_fn(udc->addr, XUSB_EP_BUF0COUNT_OFFSET, length);
1025 		udc->write_fn(udc->addr, XUSB_BUFFREADY_OFFSET, 1);
1026 	} else {
1027 		if (udc->setup.wLength) {
1028 			/* Enable EP0 buffer to receive data */
1029 			udc->write_fn(udc->addr, XUSB_EP_BUF0COUNT_OFFSET, 0);
1030 			udc->write_fn(udc->addr, XUSB_BUFFREADY_OFFSET, 1);
1031 		} else {
1032 			xudc_wrstatus(udc);
1033 		}
1034 	}
1035 
1036 	return 0;
1037 }
1038 
1039 /**
1040  * xudc_ep0_queue - Adds the request to endpoint 0 queue.
1041  * @_ep: pointer to the usb endpoint 0 structure.
1042  * @_req: pointer to the usb request structure.
1043  * @gfp_flags: Flags related to the request call.
1044  *
1045  * Return: 0 for success and error value on failure
1046  */
1047 static int xudc_ep0_queue(struct usb_ep *_ep, struct usb_request *_req,
1048 			  gfp_t gfp_flags)
1049 {
1050 	struct xusb_req *req	= to_xusb_req(_req);
1051 	struct xusb_ep	*ep0	= to_xusb_ep(_ep);
1052 	struct xusb_udc *udc	= ep0->udc;
1053 	unsigned long flags;
1054 	int ret;
1055 
1056 	spin_lock_irqsave(&udc->lock, flags);
1057 	ret = __xudc_ep0_queue(ep0, req);
1058 	spin_unlock_irqrestore(&udc->lock, flags);
1059 
1060 	return ret;
1061 }
1062 
1063 /**
1064  * xudc_ep_queue - Adds the request to endpoint queue.
1065  * @_ep: pointer to the usb endpoint structure.
1066  * @_req: pointer to the usb request structure.
1067  * @gfp_flags: Flags related to the request call.
1068  *
1069  * Return: 0 for success and error value on failure
1070  */
1071 static int xudc_ep_queue(struct usb_ep *_ep, struct usb_request *_req,
1072 			 gfp_t gfp_flags)
1073 {
1074 	struct xusb_req *req = to_xusb_req(_req);
1075 	struct xusb_ep	*ep  = to_xusb_ep(_ep);
1076 	struct xusb_udc *udc = ep->udc;
1077 	int  ret;
1078 	unsigned long flags;
1079 
1080 	if (!ep->desc) {
1081 		dev_dbg(udc->dev, "%s: queuing request to disabled %s\n",
1082 			__func__, ep->name);
1083 		return -ESHUTDOWN;
1084 	}
1085 
1086 	if (!udc->driver || udc->gadget.speed == USB_SPEED_UNKNOWN) {
1087 		dev_dbg(udc->dev, "%s, bogus device state\n", __func__);
1088 		return -EINVAL;
1089 	}
1090 
1091 	spin_lock_irqsave(&udc->lock, flags);
1092 
1093 	_req->status = -EINPROGRESS;
1094 	_req->actual = 0;
1095 
1096 	if (udc->dma_enabled) {
1097 		ret = usb_gadget_map_request(&udc->gadget, &req->usb_req,
1098 					     ep->is_in);
1099 		if (ret) {
1100 			dev_dbg(udc->dev, "gadget_map failed ep%d\n",
1101 				ep->epnumber);
1102 			spin_unlock_irqrestore(&udc->lock, flags);
1103 			return -EAGAIN;
1104 		}
1105 	}
1106 
1107 	if (list_empty(&ep->queue)) {
1108 		if (ep->is_in) {
1109 			dev_dbg(udc->dev, "xudc_write_fifo from ep_queue\n");
1110 			if (!xudc_write_fifo(ep, req))
1111 				req = NULL;
1112 		} else {
1113 			dev_dbg(udc->dev, "xudc_read_fifo from ep_queue\n");
1114 			if (!xudc_read_fifo(ep, req))
1115 				req = NULL;
1116 		}
1117 	}
1118 
1119 	if (req != NULL)
1120 		list_add_tail(&req->queue, &ep->queue);
1121 
1122 	spin_unlock_irqrestore(&udc->lock, flags);
1123 	return 0;
1124 }
1125 
1126 /**
1127  * xudc_ep_dequeue - Removes the request from the queue.
1128  * @_ep: pointer to the usb device endpoint structure.
1129  * @_req: pointer to the usb request structure.
1130  *
1131  * Return: 0 for success and error value on failure
1132  */
1133 static int xudc_ep_dequeue(struct usb_ep *_ep, struct usb_request *_req)
1134 {
1135 	struct xusb_ep *ep	= to_xusb_ep(_ep);
1136 	struct xusb_req *req	= to_xusb_req(_req);
1137 	struct xusb_udc *udc	= ep->udc;
1138 	unsigned long flags;
1139 
1140 	spin_lock_irqsave(&udc->lock, flags);
1141 	/* Make sure it's actually queued on this endpoint */
1142 	list_for_each_entry(req, &ep->queue, queue) {
1143 		if (&req->usb_req == _req)
1144 			break;
1145 	}
1146 	if (&req->usb_req != _req) {
1147 		spin_unlock_irqrestore(&udc->lock, flags);
1148 		return -EINVAL;
1149 	}
1150 	xudc_done(ep, req, -ECONNRESET);
1151 	spin_unlock_irqrestore(&udc->lock, flags);
1152 
1153 	return 0;
1154 }
1155 
1156 /**
1157  * xudc_ep0_enable - Enables the given endpoint.
1158  * @ep: pointer to the usb endpoint structure.
1159  * @desc: pointer to usb endpoint descriptor.
1160  *
1161  * Return: error always.
1162  *
1163  * endpoint 0 enable should not be called by gadget layer.
1164  */
1165 static int xudc_ep0_enable(struct usb_ep *ep,
1166 			   const struct usb_endpoint_descriptor *desc)
1167 {
1168 	return -EINVAL;
1169 }
1170 
1171 /**
1172  * xudc_ep0_disable - Disables the given endpoint.
1173  * @ep: pointer to the usb endpoint structure.
1174  *
1175  * Return: error always.
1176  *
1177  * endpoint 0 disable should not be called by gadget layer.
1178  */
1179 static int xudc_ep0_disable(struct usb_ep *ep)
1180 {
1181 	return -EINVAL;
1182 }
1183 
1184 static const struct usb_ep_ops xusb_ep0_ops = {
1185 	.enable		= xudc_ep0_enable,
1186 	.disable	= xudc_ep0_disable,
1187 	.alloc_request	= xudc_ep_alloc_request,
1188 	.free_request	= xudc_free_request,
1189 	.queue		= xudc_ep0_queue,
1190 	.dequeue	= xudc_ep_dequeue,
1191 	.set_halt	= xudc_ep_set_halt,
1192 };
1193 
1194 static const struct usb_ep_ops xusb_ep_ops = {
1195 	.enable		= xudc_ep_enable,
1196 	.disable	= xudc_ep_disable,
1197 	.alloc_request	= xudc_ep_alloc_request,
1198 	.free_request	= xudc_free_request,
1199 	.queue		= xudc_ep_queue,
1200 	.dequeue	= xudc_ep_dequeue,
1201 	.set_halt	= xudc_ep_set_halt,
1202 };
1203 
1204 /**
1205  * xudc_get_frame - Reads the current usb frame number.
1206  * @gadget: pointer to the usb gadget structure.
1207  *
1208  * Return: current frame number for success and error value on failure.
1209  */
1210 static int xudc_get_frame(struct usb_gadget *gadget)
1211 {
1212 	struct xusb_udc *udc;
1213 	int frame;
1214 
1215 	if (!gadget)
1216 		return -ENODEV;
1217 
1218 	udc = to_udc(gadget);
1219 	frame = udc->read_fn(udc->addr + XUSB_FRAMENUM_OFFSET);
1220 	return frame;
1221 }
1222 
1223 /**
1224  * xudc_wakeup - Send remote wakeup signal to host
1225  * @gadget: pointer to the usb gadget structure.
1226  *
1227  * Return: 0 on success and error on failure
1228  */
1229 static int xudc_wakeup(struct usb_gadget *gadget)
1230 {
1231 	struct xusb_udc *udc = to_udc(gadget);
1232 	u32 crtlreg;
1233 	int status = -EINVAL;
1234 	unsigned long flags;
1235 
1236 	spin_lock_irqsave(&udc->lock, flags);
1237 
1238 	/* Remote wake up not enabled by host */
1239 	if (!udc->remote_wkp)
1240 		goto done;
1241 
1242 	crtlreg = udc->read_fn(udc->addr + XUSB_CONTROL_OFFSET);
1243 	crtlreg |= XUSB_CONTROL_USB_RMTWAKE_MASK;
1244 	/* set remote wake up bit */
1245 	udc->write_fn(udc->addr, XUSB_CONTROL_OFFSET, crtlreg);
1246 	/*
1247 	 * wait for a while and reset remote wake up bit since this bit
1248 	 * is not cleared by HW after sending remote wakeup to host.
1249 	 */
1250 	mdelay(2);
1251 
1252 	crtlreg &= ~XUSB_CONTROL_USB_RMTWAKE_MASK;
1253 	udc->write_fn(udc->addr, XUSB_CONTROL_OFFSET, crtlreg);
1254 	status = 0;
1255 done:
1256 	spin_unlock_irqrestore(&udc->lock, flags);
1257 	return status;
1258 }
1259 
1260 /**
1261  * xudc_pullup - start/stop USB traffic
1262  * @gadget: pointer to the usb gadget structure.
1263  * @is_on: flag to start or stop
1264  *
1265  * Return: 0 always
1266  *
1267  * This function starts/stops SIE engine of IP based on is_on.
1268  */
1269 static int xudc_pullup(struct usb_gadget *gadget, int is_on)
1270 {
1271 	struct xusb_udc *udc = to_udc(gadget);
1272 	unsigned long flags;
1273 	u32 crtlreg;
1274 
1275 	spin_lock_irqsave(&udc->lock, flags);
1276 
1277 	crtlreg = udc->read_fn(udc->addr + XUSB_CONTROL_OFFSET);
1278 	if (is_on)
1279 		crtlreg |= XUSB_CONTROL_USB_READY_MASK;
1280 	else
1281 		crtlreg &= ~XUSB_CONTROL_USB_READY_MASK;
1282 
1283 	udc->write_fn(udc->addr, XUSB_CONTROL_OFFSET, crtlreg);
1284 
1285 	spin_unlock_irqrestore(&udc->lock, flags);
1286 
1287 	return 0;
1288 }
1289 
1290 /**
1291  * xudc_eps_init - initialize endpoints.
1292  * @udc: pointer to the usb device controller structure.
1293  */
1294 static void xudc_eps_init(struct xusb_udc *udc)
1295 {
1296 	u32 ep_number;
1297 
1298 	INIT_LIST_HEAD(&udc->gadget.ep_list);
1299 
1300 	for (ep_number = 0; ep_number < XUSB_MAX_ENDPOINTS; ep_number++) {
1301 		struct xusb_ep *ep = &udc->ep[ep_number];
1302 
1303 		if (ep_number) {
1304 			list_add_tail(&ep->ep_usb.ep_list,
1305 				      &udc->gadget.ep_list);
1306 			usb_ep_set_maxpacket_limit(&ep->ep_usb,
1307 						  (unsigned short) ~0);
1308 			snprintf(ep->name, EPNAME_SIZE, "ep%d", ep_number);
1309 			ep->ep_usb.name = ep->name;
1310 			ep->ep_usb.ops = &xusb_ep_ops;
1311 
1312 			ep->ep_usb.caps.type_iso = true;
1313 			ep->ep_usb.caps.type_bulk = true;
1314 			ep->ep_usb.caps.type_int = true;
1315 		} else {
1316 			ep->ep_usb.name = ep0name;
1317 			usb_ep_set_maxpacket_limit(&ep->ep_usb, EP0_MAX_PACKET);
1318 			ep->ep_usb.ops = &xusb_ep0_ops;
1319 
1320 			ep->ep_usb.caps.type_control = true;
1321 		}
1322 
1323 		ep->ep_usb.caps.dir_in = true;
1324 		ep->ep_usb.caps.dir_out = true;
1325 
1326 		ep->udc = udc;
1327 		ep->epnumber = ep_number;
1328 		ep->desc = NULL;
1329 		/*
1330 		 * The configuration register address offset between
1331 		 * each endpoint is 0x10.
1332 		 */
1333 		ep->offset = XUSB_EP0_CONFIG_OFFSET + (ep_number * 0x10);
1334 		ep->is_in = 0;
1335 		ep->is_iso = 0;
1336 		ep->maxpacket = 0;
1337 		xudc_epconfig(ep, udc);
1338 
1339 		/* Initialize one queue per endpoint */
1340 		INIT_LIST_HEAD(&ep->queue);
1341 	}
1342 }
1343 
1344 /**
1345  * xudc_stop_activity - Stops any further activity on the device.
1346  * @udc: pointer to the usb device controller structure.
1347  */
1348 static void xudc_stop_activity(struct xusb_udc *udc)
1349 {
1350 	int i;
1351 	struct xusb_ep *ep;
1352 
1353 	for (i = 0; i < XUSB_MAX_ENDPOINTS; i++) {
1354 		ep = &udc->ep[i];
1355 		xudc_nuke(ep, -ESHUTDOWN);
1356 	}
1357 }
1358 
1359 /**
1360  * xudc_start - Starts the device.
1361  * @gadget: pointer to the usb gadget structure
1362  * @driver: pointer to gadget driver structure
1363  *
1364  * Return: zero on success and error on failure
1365  */
1366 static int xudc_start(struct usb_gadget *gadget,
1367 		      struct usb_gadget_driver *driver)
1368 {
1369 	struct xusb_udc *udc	= to_udc(gadget);
1370 	struct xusb_ep *ep0	= &udc->ep[XUSB_EP_NUMBER_ZERO];
1371 	const struct usb_endpoint_descriptor *desc = &config_bulk_out_desc;
1372 	unsigned long flags;
1373 	int ret = 0;
1374 
1375 	spin_lock_irqsave(&udc->lock, flags);
1376 
1377 	if (udc->driver) {
1378 		dev_err(udc->dev, "%s is already bound to %s\n",
1379 			udc->gadget.name, udc->driver->driver.name);
1380 		ret = -EBUSY;
1381 		goto err;
1382 	}
1383 
1384 	/* hook up the driver */
1385 	udc->driver = driver;
1386 	udc->gadget.speed = driver->max_speed;
1387 
1388 	/* Enable the control endpoint. */
1389 	ret = __xudc_ep_enable(ep0, desc);
1390 
1391 	/* Set device address and remote wakeup to 0 */
1392 	udc->write_fn(udc->addr, XUSB_ADDRESS_OFFSET, 0);
1393 	udc->remote_wkp = 0;
1394 err:
1395 	spin_unlock_irqrestore(&udc->lock, flags);
1396 	return ret;
1397 }
1398 
1399 /**
1400  * xudc_stop - stops the device.
1401  * @gadget: pointer to the usb gadget structure
1402  *
1403  * Return: zero always
1404  */
1405 static int xudc_stop(struct usb_gadget *gadget)
1406 {
1407 	struct xusb_udc *udc = to_udc(gadget);
1408 	unsigned long flags;
1409 
1410 	spin_lock_irqsave(&udc->lock, flags);
1411 
1412 	udc->gadget.speed = USB_SPEED_UNKNOWN;
1413 	udc->driver = NULL;
1414 
1415 	/* Set device address and remote wakeup to 0 */
1416 	udc->write_fn(udc->addr, XUSB_ADDRESS_OFFSET, 0);
1417 	udc->remote_wkp = 0;
1418 
1419 	xudc_stop_activity(udc);
1420 
1421 	spin_unlock_irqrestore(&udc->lock, flags);
1422 
1423 	return 0;
1424 }
1425 
1426 static const struct usb_gadget_ops xusb_udc_ops = {
1427 	.get_frame	= xudc_get_frame,
1428 	.wakeup		= xudc_wakeup,
1429 	.pullup		= xudc_pullup,
1430 	.udc_start	= xudc_start,
1431 	.udc_stop	= xudc_stop,
1432 };
1433 
1434 /**
1435  * xudc_clear_stall_all_ep - clears stall of every endpoint.
1436  * @udc: pointer to the udc structure.
1437  */
1438 static void xudc_clear_stall_all_ep(struct xusb_udc *udc)
1439 {
1440 	struct xusb_ep *ep;
1441 	u32 epcfgreg;
1442 	int i;
1443 
1444 	for (i = 0; i < XUSB_MAX_ENDPOINTS; i++) {
1445 		ep = &udc->ep[i];
1446 		epcfgreg = udc->read_fn(udc->addr + ep->offset);
1447 		epcfgreg &= ~XUSB_EP_CFG_STALL_MASK;
1448 		udc->write_fn(udc->addr, ep->offset, epcfgreg);
1449 		if (ep->epnumber) {
1450 			/* Reset the toggle bit.*/
1451 			epcfgreg = udc->read_fn(udc->addr + ep->offset);
1452 			epcfgreg &= ~XUSB_EP_CFG_DATA_TOGGLE_MASK;
1453 			udc->write_fn(udc->addr, ep->offset, epcfgreg);
1454 		}
1455 	}
1456 }
1457 
1458 /**
1459  * xudc_startup_handler - The usb device controller interrupt handler.
1460  * @udc: pointer to the udc structure.
1461  * @intrstatus: The mask value containing the interrupt sources.
1462  *
1463  * This function handles the RESET,SUSPEND,RESUME and DISCONNECT interrupts.
1464  */
1465 static void xudc_startup_handler(struct xusb_udc *udc, u32 intrstatus)
1466 {
1467 	u32 intrreg;
1468 
1469 	if (intrstatus & XUSB_STATUS_RESET_MASK) {
1470 
1471 		dev_dbg(udc->dev, "Reset\n");
1472 
1473 		if (intrstatus & XUSB_STATUS_HIGH_SPEED_MASK)
1474 			udc->gadget.speed = USB_SPEED_HIGH;
1475 		else
1476 			udc->gadget.speed = USB_SPEED_FULL;
1477 
1478 		xudc_stop_activity(udc);
1479 		xudc_clear_stall_all_ep(udc);
1480 		udc->write_fn(udc->addr, XUSB_TESTMODE_OFFSET, 0);
1481 
1482 		/* Set device address and remote wakeup to 0 */
1483 		udc->write_fn(udc->addr, XUSB_ADDRESS_OFFSET, 0);
1484 		udc->remote_wkp = 0;
1485 
1486 		/* Enable the suspend, resume and disconnect */
1487 		intrreg = udc->read_fn(udc->addr + XUSB_IER_OFFSET);
1488 		intrreg |= XUSB_STATUS_SUSPEND_MASK | XUSB_STATUS_RESUME_MASK |
1489 			   XUSB_STATUS_DISCONNECT_MASK;
1490 		udc->write_fn(udc->addr, XUSB_IER_OFFSET, intrreg);
1491 	}
1492 	if (intrstatus & XUSB_STATUS_SUSPEND_MASK) {
1493 
1494 		dev_dbg(udc->dev, "Suspend\n");
1495 
1496 		/* Enable the reset, resume and disconnect */
1497 		intrreg = udc->read_fn(udc->addr + XUSB_IER_OFFSET);
1498 		intrreg |= XUSB_STATUS_RESET_MASK | XUSB_STATUS_RESUME_MASK |
1499 			   XUSB_STATUS_DISCONNECT_MASK;
1500 		udc->write_fn(udc->addr, XUSB_IER_OFFSET, intrreg);
1501 
1502 		udc->usb_state = USB_STATE_SUSPENDED;
1503 
1504 		if (udc->driver->suspend) {
1505 			spin_unlock(&udc->lock);
1506 			udc->driver->suspend(&udc->gadget);
1507 			spin_lock(&udc->lock);
1508 		}
1509 	}
1510 	if (intrstatus & XUSB_STATUS_RESUME_MASK) {
1511 		bool condition = (udc->usb_state != USB_STATE_SUSPENDED);
1512 
1513 		dev_WARN_ONCE(udc->dev, condition,
1514 				"Resume IRQ while not suspended\n");
1515 
1516 		dev_dbg(udc->dev, "Resume\n");
1517 
1518 		/* Enable the reset, suspend and disconnect */
1519 		intrreg = udc->read_fn(udc->addr + XUSB_IER_OFFSET);
1520 		intrreg |= XUSB_STATUS_RESET_MASK | XUSB_STATUS_SUSPEND_MASK |
1521 			   XUSB_STATUS_DISCONNECT_MASK;
1522 		udc->write_fn(udc->addr, XUSB_IER_OFFSET, intrreg);
1523 
1524 		udc->usb_state = 0;
1525 
1526 		if (udc->driver->resume) {
1527 			spin_unlock(&udc->lock);
1528 			udc->driver->resume(&udc->gadget);
1529 			spin_lock(&udc->lock);
1530 		}
1531 	}
1532 	if (intrstatus & XUSB_STATUS_DISCONNECT_MASK) {
1533 
1534 		dev_dbg(udc->dev, "Disconnect\n");
1535 
1536 		/* Enable the reset, resume and suspend */
1537 		intrreg = udc->read_fn(udc->addr + XUSB_IER_OFFSET);
1538 		intrreg |= XUSB_STATUS_RESET_MASK | XUSB_STATUS_RESUME_MASK |
1539 			   XUSB_STATUS_SUSPEND_MASK;
1540 		udc->write_fn(udc->addr, XUSB_IER_OFFSET, intrreg);
1541 
1542 		if (udc->driver && udc->driver->disconnect) {
1543 			spin_unlock(&udc->lock);
1544 			udc->driver->disconnect(&udc->gadget);
1545 			spin_lock(&udc->lock);
1546 		}
1547 	}
1548 }
1549 
1550 /**
1551  * xudc_ep0_stall - Stall endpoint zero.
1552  * @udc: pointer to the udc structure.
1553  *
1554  * This function stalls endpoint zero.
1555  */
1556 static void xudc_ep0_stall(struct xusb_udc *udc)
1557 {
1558 	u32 epcfgreg;
1559 	struct xusb_ep *ep0 = &udc->ep[XUSB_EP_NUMBER_ZERO];
1560 
1561 	epcfgreg = udc->read_fn(udc->addr + ep0->offset);
1562 	epcfgreg |= XUSB_EP_CFG_STALL_MASK;
1563 	udc->write_fn(udc->addr, ep0->offset, epcfgreg);
1564 }
1565 
1566 /**
1567  * xudc_setaddress - executes SET_ADDRESS command
1568  * @udc: pointer to the udc structure.
1569  *
1570  * This function executes USB SET_ADDRESS command
1571  */
1572 static void xudc_setaddress(struct xusb_udc *udc)
1573 {
1574 	struct xusb_ep *ep0	= &udc->ep[0];
1575 	struct xusb_req *req	= udc->req;
1576 	int ret;
1577 
1578 	req->usb_req.length = 0;
1579 	ret = __xudc_ep0_queue(ep0, req);
1580 	if (ret == 0)
1581 		return;
1582 
1583 	dev_err(udc->dev, "Can't respond to SET ADDRESS request\n");
1584 	xudc_ep0_stall(udc);
1585 }
1586 
1587 /**
1588  * xudc_getstatus - executes GET_STATUS command
1589  * @udc: pointer to the udc structure.
1590  *
1591  * This function executes USB GET_STATUS command
1592  */
1593 static void xudc_getstatus(struct xusb_udc *udc)
1594 {
1595 	struct xusb_ep *ep0	= &udc->ep[0];
1596 	struct xusb_req *req	= udc->req;
1597 	struct xusb_ep *target_ep;
1598 	u16 status = 0;
1599 	u32 epcfgreg;
1600 	int epnum;
1601 	u32 halt;
1602 	int ret;
1603 
1604 	switch (udc->setup.bRequestType & USB_RECIP_MASK) {
1605 	case USB_RECIP_DEVICE:
1606 		/* Get device status */
1607 		status = 1 << USB_DEVICE_SELF_POWERED;
1608 		if (udc->remote_wkp)
1609 			status |= (1 << USB_DEVICE_REMOTE_WAKEUP);
1610 		break;
1611 	case USB_RECIP_INTERFACE:
1612 		break;
1613 	case USB_RECIP_ENDPOINT:
1614 		epnum = udc->setup.wIndex & USB_ENDPOINT_NUMBER_MASK;
1615 		target_ep = &udc->ep[epnum];
1616 		epcfgreg = udc->read_fn(udc->addr + target_ep->offset);
1617 		halt = epcfgreg & XUSB_EP_CFG_STALL_MASK;
1618 		if (udc->setup.wIndex & USB_DIR_IN) {
1619 			if (!target_ep->is_in)
1620 				goto stall;
1621 		} else {
1622 			if (target_ep->is_in)
1623 				goto stall;
1624 		}
1625 		if (halt)
1626 			status = 1 << USB_ENDPOINT_HALT;
1627 		break;
1628 	default:
1629 		goto stall;
1630 	}
1631 
1632 	req->usb_req.length = 2;
1633 	*(u16 *)req->usb_req.buf = cpu_to_le16(status);
1634 	ret = __xudc_ep0_queue(ep0, req);
1635 	if (ret == 0)
1636 		return;
1637 stall:
1638 	dev_err(udc->dev, "Can't respond to getstatus request\n");
1639 	xudc_ep0_stall(udc);
1640 }
1641 
1642 /**
1643  * xudc_set_clear_feature - Executes the set feature and clear feature commands.
1644  * @udc: pointer to the usb device controller structure.
1645  *
1646  * Processes the SET_FEATURE and CLEAR_FEATURE commands.
1647  */
1648 static void xudc_set_clear_feature(struct xusb_udc *udc)
1649 {
1650 	struct xusb_ep *ep0	= &udc->ep[0];
1651 	struct xusb_req *req	= udc->req;
1652 	struct xusb_ep *target_ep;
1653 	u8 endpoint;
1654 	u8 outinbit;
1655 	u32 epcfgreg;
1656 	int flag = (udc->setup.bRequest == USB_REQ_SET_FEATURE ? 1 : 0);
1657 	int ret;
1658 
1659 	switch (udc->setup.bRequestType) {
1660 	case USB_RECIP_DEVICE:
1661 		switch (udc->setup.wValue) {
1662 		case USB_DEVICE_TEST_MODE:
1663 			/*
1664 			 * The Test Mode will be executed
1665 			 * after the status phase.
1666 			 */
1667 			break;
1668 		case USB_DEVICE_REMOTE_WAKEUP:
1669 			if (flag)
1670 				udc->remote_wkp = 1;
1671 			else
1672 				udc->remote_wkp = 0;
1673 			break;
1674 		default:
1675 			xudc_ep0_stall(udc);
1676 			break;
1677 		}
1678 		break;
1679 	case USB_RECIP_ENDPOINT:
1680 		if (!udc->setup.wValue) {
1681 			endpoint = udc->setup.wIndex & USB_ENDPOINT_NUMBER_MASK;
1682 			target_ep = &udc->ep[endpoint];
1683 			outinbit = udc->setup.wIndex & USB_ENDPOINT_DIR_MASK;
1684 			outinbit = outinbit >> 7;
1685 
1686 			/* Make sure direction matches.*/
1687 			if (outinbit != target_ep->is_in) {
1688 				xudc_ep0_stall(udc);
1689 				return;
1690 			}
1691 			epcfgreg = udc->read_fn(udc->addr + target_ep->offset);
1692 			if (!endpoint) {
1693 				/* Clear the stall.*/
1694 				epcfgreg &= ~XUSB_EP_CFG_STALL_MASK;
1695 				udc->write_fn(udc->addr,
1696 					      target_ep->offset, epcfgreg);
1697 			} else {
1698 				if (flag) {
1699 					epcfgreg |= XUSB_EP_CFG_STALL_MASK;
1700 					udc->write_fn(udc->addr,
1701 						      target_ep->offset,
1702 						      epcfgreg);
1703 				} else {
1704 					/* Unstall the endpoint.*/
1705 					epcfgreg &= ~(XUSB_EP_CFG_STALL_MASK |
1706 						XUSB_EP_CFG_DATA_TOGGLE_MASK);
1707 					udc->write_fn(udc->addr,
1708 						      target_ep->offset,
1709 						      epcfgreg);
1710 				}
1711 			}
1712 		}
1713 		break;
1714 	default:
1715 		xudc_ep0_stall(udc);
1716 		return;
1717 	}
1718 
1719 	req->usb_req.length = 0;
1720 	ret = __xudc_ep0_queue(ep0, req);
1721 	if (ret == 0)
1722 		return;
1723 
1724 	dev_err(udc->dev, "Can't respond to SET/CLEAR FEATURE\n");
1725 	xudc_ep0_stall(udc);
1726 }
1727 
1728 /**
1729  * xudc_handle_setup - Processes the setup packet.
1730  * @udc: pointer to the usb device controller structure.
1731  *
1732  * Process setup packet and delegate to gadget layer.
1733  */
1734 static void xudc_handle_setup(struct xusb_udc *udc)
1735 	__must_hold(&udc->lock)
1736 {
1737 	struct xusb_ep *ep0 = &udc->ep[0];
1738 	struct usb_ctrlrequest setup;
1739 	u32 *ep0rambase;
1740 
1741 	/* Load up the chapter 9 command buffer.*/
1742 	ep0rambase = (u32 __force *) (udc->addr + XUSB_SETUP_PKT_ADDR_OFFSET);
1743 	memcpy(&setup, ep0rambase, 8);
1744 
1745 	udc->setup = setup;
1746 	udc->setup.wValue = cpu_to_le16(setup.wValue);
1747 	udc->setup.wIndex = cpu_to_le16(setup.wIndex);
1748 	udc->setup.wLength = cpu_to_le16(setup.wLength);
1749 
1750 	/* Clear previous requests */
1751 	xudc_nuke(ep0, -ECONNRESET);
1752 
1753 	if (udc->setup.bRequestType & USB_DIR_IN) {
1754 		/* Execute the get command.*/
1755 		udc->setupseqrx = STATUS_PHASE;
1756 		udc->setupseqtx = DATA_PHASE;
1757 	} else {
1758 		/* Execute the put command.*/
1759 		udc->setupseqrx = DATA_PHASE;
1760 		udc->setupseqtx = STATUS_PHASE;
1761 	}
1762 
1763 	switch (udc->setup.bRequest) {
1764 	case USB_REQ_GET_STATUS:
1765 		/* Data+Status phase form udc */
1766 		if ((udc->setup.bRequestType &
1767 				(USB_DIR_IN | USB_TYPE_MASK)) !=
1768 				(USB_DIR_IN | USB_TYPE_STANDARD))
1769 			break;
1770 		xudc_getstatus(udc);
1771 		return;
1772 	case USB_REQ_SET_ADDRESS:
1773 		/* Status phase from udc */
1774 		if (udc->setup.bRequestType != (USB_DIR_OUT |
1775 				USB_TYPE_STANDARD | USB_RECIP_DEVICE))
1776 			break;
1777 		xudc_setaddress(udc);
1778 		return;
1779 	case USB_REQ_CLEAR_FEATURE:
1780 	case USB_REQ_SET_FEATURE:
1781 		/* Requests with no data phase, status phase from udc */
1782 		if ((udc->setup.bRequestType & USB_TYPE_MASK)
1783 				!= USB_TYPE_STANDARD)
1784 			break;
1785 		xudc_set_clear_feature(udc);
1786 		return;
1787 	default:
1788 		break;
1789 	}
1790 
1791 	spin_unlock(&udc->lock);
1792 	if (udc->driver->setup(&udc->gadget, &setup) < 0)
1793 		xudc_ep0_stall(udc);
1794 	spin_lock(&udc->lock);
1795 }
1796 
1797 /**
1798  * xudc_ep0_out - Processes the endpoint 0 OUT token.
1799  * @udc: pointer to the usb device controller structure.
1800  */
1801 static void xudc_ep0_out(struct xusb_udc *udc)
1802 {
1803 	struct xusb_ep *ep0 = &udc->ep[0];
1804 	struct xusb_req *req;
1805 	u8 *ep0rambase;
1806 	unsigned int bytes_to_rx;
1807 	void *buffer;
1808 
1809 	req = list_first_entry(&ep0->queue, struct xusb_req, queue);
1810 
1811 	switch (udc->setupseqrx) {
1812 	case STATUS_PHASE:
1813 		/*
1814 		 * This resets both state machines for the next
1815 		 * Setup packet.
1816 		 */
1817 		udc->setupseqrx = SETUP_PHASE;
1818 		udc->setupseqtx = SETUP_PHASE;
1819 		req->usb_req.actual = req->usb_req.length;
1820 		xudc_done(ep0, req, 0);
1821 		break;
1822 	case DATA_PHASE:
1823 		bytes_to_rx = udc->read_fn(udc->addr +
1824 					   XUSB_EP_BUF0COUNT_OFFSET);
1825 		/* Copy the data to be received from the DPRAM. */
1826 		ep0rambase = (u8 __force *) (udc->addr +
1827 			     (ep0->rambase << 2));
1828 		buffer = req->usb_req.buf + req->usb_req.actual;
1829 		req->usb_req.actual = req->usb_req.actual + bytes_to_rx;
1830 		memcpy(buffer, ep0rambase, bytes_to_rx);
1831 
1832 		if (req->usb_req.length == req->usb_req.actual) {
1833 			/* Data transfer completed get ready for Status stage */
1834 			xudc_wrstatus(udc);
1835 		} else {
1836 			/* Enable EP0 buffer to receive data */
1837 			udc->write_fn(udc->addr, XUSB_EP_BUF0COUNT_OFFSET, 0);
1838 			udc->write_fn(udc->addr, XUSB_BUFFREADY_OFFSET, 1);
1839 		}
1840 		break;
1841 	default:
1842 		break;
1843 	}
1844 }
1845 
1846 /**
1847  * xudc_ep0_in - Processes the endpoint 0 IN token.
1848  * @udc: pointer to the usb device controller structure.
1849  */
1850 static void xudc_ep0_in(struct xusb_udc *udc)
1851 {
1852 	struct xusb_ep *ep0 = &udc->ep[0];
1853 	struct xusb_req *req;
1854 	unsigned int bytes_to_tx;
1855 	void *buffer;
1856 	u32 epcfgreg;
1857 	u16 count = 0;
1858 	u16 length;
1859 	u8 *ep0rambase;
1860 	u8 test_mode = udc->setup.wIndex >> 8;
1861 
1862 	req = list_first_entry(&ep0->queue, struct xusb_req, queue);
1863 	bytes_to_tx = req->usb_req.length - req->usb_req.actual;
1864 
1865 	switch (udc->setupseqtx) {
1866 	case STATUS_PHASE:
1867 		switch (udc->setup.bRequest) {
1868 		case USB_REQ_SET_ADDRESS:
1869 			/* Set the address of the device.*/
1870 			udc->write_fn(udc->addr, XUSB_ADDRESS_OFFSET,
1871 				      udc->setup.wValue);
1872 			break;
1873 		case USB_REQ_SET_FEATURE:
1874 			if (udc->setup.bRequestType ==
1875 					USB_RECIP_DEVICE) {
1876 				if (udc->setup.wValue ==
1877 						USB_DEVICE_TEST_MODE)
1878 					udc->write_fn(udc->addr,
1879 						      XUSB_TESTMODE_OFFSET,
1880 						      test_mode);
1881 			}
1882 			break;
1883 		}
1884 		req->usb_req.actual = req->usb_req.length;
1885 		xudc_done(ep0, req, 0);
1886 		break;
1887 	case DATA_PHASE:
1888 		if (!bytes_to_tx) {
1889 			/*
1890 			 * We're done with data transfer, next
1891 			 * will be zero length OUT with data toggle of
1892 			 * 1. Setup data_toggle.
1893 			 */
1894 			epcfgreg = udc->read_fn(udc->addr + ep0->offset);
1895 			epcfgreg |= XUSB_EP_CFG_DATA_TOGGLE_MASK;
1896 			udc->write_fn(udc->addr, ep0->offset, epcfgreg);
1897 			udc->setupseqtx = STATUS_PHASE;
1898 		} else {
1899 			length = count = min_t(u32, bytes_to_tx,
1900 					       EP0_MAX_PACKET);
1901 			/* Copy the data to be transmitted into the DPRAM. */
1902 			ep0rambase = (u8 __force *) (udc->addr +
1903 				     (ep0->rambase << 2));
1904 			buffer = req->usb_req.buf + req->usb_req.actual;
1905 			req->usb_req.actual = req->usb_req.actual + length;
1906 			memcpy(ep0rambase, buffer, length);
1907 		}
1908 		udc->write_fn(udc->addr, XUSB_EP_BUF0COUNT_OFFSET, count);
1909 		udc->write_fn(udc->addr, XUSB_BUFFREADY_OFFSET, 1);
1910 		break;
1911 	default:
1912 		break;
1913 	}
1914 }
1915 
1916 /**
1917  * xudc_ctrl_ep_handler - Endpoint 0 interrupt handler.
1918  * @udc: pointer to the udc structure.
1919  * @intrstatus:	It's the mask value for the interrupt sources on endpoint 0.
1920  *
1921  * Processes the commands received during enumeration phase.
1922  */
1923 static void xudc_ctrl_ep_handler(struct xusb_udc *udc, u32 intrstatus)
1924 {
1925 
1926 	if (intrstatus & XUSB_STATUS_SETUP_PACKET_MASK) {
1927 		xudc_handle_setup(udc);
1928 	} else {
1929 		if (intrstatus & XUSB_STATUS_FIFO_BUFF_RDY_MASK)
1930 			xudc_ep0_out(udc);
1931 		else if (intrstatus & XUSB_STATUS_FIFO_BUFF_FREE_MASK)
1932 			xudc_ep0_in(udc);
1933 	}
1934 }
1935 
1936 /**
1937  * xudc_nonctrl_ep_handler - Non control endpoint interrupt handler.
1938  * @udc: pointer to the udc structure.
1939  * @epnum: End point number for which the interrupt is to be processed
1940  * @intrstatus:	mask value for interrupt sources of endpoints other
1941  *		than endpoint 0.
1942  *
1943  * Processes the buffer completion interrupts.
1944  */
1945 static void xudc_nonctrl_ep_handler(struct xusb_udc *udc, u8 epnum,
1946 				    u32 intrstatus)
1947 {
1948 
1949 	struct xusb_req *req;
1950 	struct xusb_ep *ep;
1951 
1952 	ep = &udc->ep[epnum];
1953 	/* Process the End point interrupts.*/
1954 	if (intrstatus & (XUSB_STATUS_EP0_BUFF1_COMP_MASK << epnum))
1955 		ep->buffer0ready = 0;
1956 	if (intrstatus & (XUSB_STATUS_EP0_BUFF2_COMP_MASK << epnum))
1957 		ep->buffer1ready = false;
1958 
1959 	if (list_empty(&ep->queue))
1960 		return;
1961 
1962 	req = list_first_entry(&ep->queue, struct xusb_req, queue);
1963 
1964 	if (ep->is_in)
1965 		xudc_write_fifo(ep, req);
1966 	else
1967 		xudc_read_fifo(ep, req);
1968 }
1969 
1970 /**
1971  * xudc_irq - The main interrupt handler.
1972  * @irq: The interrupt number.
1973  * @_udc: pointer to the usb device controller structure.
1974  *
1975  * Return: IRQ_HANDLED after the interrupt is handled.
1976  */
1977 static irqreturn_t xudc_irq(int irq, void *_udc)
1978 {
1979 	struct xusb_udc *udc = _udc;
1980 	u32 intrstatus;
1981 	u32 ier;
1982 	u8 index;
1983 	u32 bufintr;
1984 	unsigned long flags;
1985 
1986 	spin_lock_irqsave(&udc->lock, flags);
1987 
1988 	/*
1989 	 * Event interrupts are level sensitive hence first disable
1990 	 * IER, read ISR and figure out active interrupts.
1991 	 */
1992 	ier = udc->read_fn(udc->addr + XUSB_IER_OFFSET);
1993 	ier &= ~XUSB_STATUS_INTR_EVENT_MASK;
1994 	udc->write_fn(udc->addr, XUSB_IER_OFFSET, ier);
1995 
1996 	/* Read the Interrupt Status Register.*/
1997 	intrstatus = udc->read_fn(udc->addr + XUSB_STATUS_OFFSET);
1998 
1999 	/* Call the handler for the event interrupt.*/
2000 	if (intrstatus & XUSB_STATUS_INTR_EVENT_MASK) {
2001 		/*
2002 		 * Check if there is any action to be done for :
2003 		 * - USB Reset received {XUSB_STATUS_RESET_MASK}
2004 		 * - USB Suspend received {XUSB_STATUS_SUSPEND_MASK}
2005 		 * - USB Resume received {XUSB_STATUS_RESUME_MASK}
2006 		 * - USB Disconnect received {XUSB_STATUS_DISCONNECT_MASK}
2007 		 */
2008 		xudc_startup_handler(udc, intrstatus);
2009 	}
2010 
2011 	/* Check the buffer completion interrupts */
2012 	if (intrstatus & XUSB_STATUS_INTR_BUFF_COMP_ALL_MASK) {
2013 		/* Enable Reset, Suspend, Resume and Disconnect  */
2014 		ier = udc->read_fn(udc->addr + XUSB_IER_OFFSET);
2015 		ier |= XUSB_STATUS_INTR_EVENT_MASK;
2016 		udc->write_fn(udc->addr, XUSB_IER_OFFSET, ier);
2017 
2018 		if (intrstatus & XUSB_STATUS_EP0_BUFF1_COMP_MASK)
2019 			xudc_ctrl_ep_handler(udc, intrstatus);
2020 
2021 		for (index = 1; index < 8; index++) {
2022 			bufintr = ((intrstatus &
2023 				  (XUSB_STATUS_EP1_BUFF1_COMP_MASK <<
2024 				  (index - 1))) || (intrstatus &
2025 				  (XUSB_STATUS_EP1_BUFF2_COMP_MASK <<
2026 				  (index - 1))));
2027 			if (bufintr) {
2028 				xudc_nonctrl_ep_handler(udc, index,
2029 							intrstatus);
2030 			}
2031 		}
2032 	}
2033 
2034 	spin_unlock_irqrestore(&udc->lock, flags);
2035 	return IRQ_HANDLED;
2036 }
2037 
2038 /**
2039  * xudc_probe - The device probe function for driver initialization.
2040  * @pdev: pointer to the platform device structure.
2041  *
2042  * Return: 0 for success and error value on failure
2043  */
2044 static int xudc_probe(struct platform_device *pdev)
2045 {
2046 	struct device_node *np = pdev->dev.of_node;
2047 	struct resource *res;
2048 	struct xusb_udc *udc;
2049 	int irq;
2050 	int ret;
2051 	u32 ier;
2052 	u8 *buff;
2053 
2054 	udc = devm_kzalloc(&pdev->dev, sizeof(*udc), GFP_KERNEL);
2055 	if (!udc)
2056 		return -ENOMEM;
2057 
2058 	/* Create a dummy request for GET_STATUS, SET_ADDRESS */
2059 	udc->req = devm_kzalloc(&pdev->dev, sizeof(struct xusb_req),
2060 				GFP_KERNEL);
2061 	if (!udc->req)
2062 		return -ENOMEM;
2063 
2064 	buff = devm_kzalloc(&pdev->dev, STATUSBUFF_SIZE, GFP_KERNEL);
2065 	if (!buff)
2066 		return -ENOMEM;
2067 
2068 	udc->req->usb_req.buf = buff;
2069 
2070 	/* Map the registers */
2071 	res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
2072 	udc->addr = devm_ioremap_resource(&pdev->dev, res);
2073 	if (IS_ERR(udc->addr))
2074 		return PTR_ERR(udc->addr);
2075 
2076 	irq = platform_get_irq(pdev, 0);
2077 	if (irq < 0)
2078 		return irq;
2079 	ret = devm_request_irq(&pdev->dev, irq, xudc_irq, 0,
2080 			       dev_name(&pdev->dev), udc);
2081 	if (ret < 0) {
2082 		dev_dbg(&pdev->dev, "unable to request irq %d", irq);
2083 		goto fail;
2084 	}
2085 
2086 	udc->dma_enabled = of_property_read_bool(np, "xlnx,has-builtin-dma");
2087 
2088 	/* Setup gadget structure */
2089 	udc->gadget.ops = &xusb_udc_ops;
2090 	udc->gadget.max_speed = USB_SPEED_HIGH;
2091 	udc->gadget.speed = USB_SPEED_UNKNOWN;
2092 	udc->gadget.ep0 = &udc->ep[XUSB_EP_NUMBER_ZERO].ep_usb;
2093 	udc->gadget.name = driver_name;
2094 
2095 	spin_lock_init(&udc->lock);
2096 
2097 	/* Check for IP endianness */
2098 	udc->write_fn = xudc_write32_be;
2099 	udc->read_fn = xudc_read32_be;
2100 	udc->write_fn(udc->addr, XUSB_TESTMODE_OFFSET, USB_TEST_J);
2101 	if ((udc->read_fn(udc->addr + XUSB_TESTMODE_OFFSET))
2102 			!= USB_TEST_J) {
2103 		udc->write_fn = xudc_write32;
2104 		udc->read_fn = xudc_read32;
2105 	}
2106 	udc->write_fn(udc->addr, XUSB_TESTMODE_OFFSET, 0);
2107 
2108 	xudc_eps_init(udc);
2109 
2110 	/* Set device address to 0.*/
2111 	udc->write_fn(udc->addr, XUSB_ADDRESS_OFFSET, 0);
2112 
2113 	ret = usb_add_gadget_udc(&pdev->dev, &udc->gadget);
2114 	if (ret)
2115 		goto fail;
2116 
2117 	udc->dev = &udc->gadget.dev;
2118 
2119 	/* Enable the interrupts.*/
2120 	ier = XUSB_STATUS_GLOBAL_INTR_MASK | XUSB_STATUS_INTR_EVENT_MASK |
2121 	      XUSB_STATUS_FIFO_BUFF_RDY_MASK | XUSB_STATUS_FIFO_BUFF_FREE_MASK |
2122 	      XUSB_STATUS_SETUP_PACKET_MASK |
2123 	      XUSB_STATUS_INTR_BUFF_COMP_ALL_MASK;
2124 
2125 	udc->write_fn(udc->addr, XUSB_IER_OFFSET, ier);
2126 
2127 	platform_set_drvdata(pdev, udc);
2128 
2129 	dev_vdbg(&pdev->dev, "%s at 0x%08X mapped to %p %s\n",
2130 		 driver_name, (u32)res->start, udc->addr,
2131 		 udc->dma_enabled ? "with DMA" : "without DMA");
2132 
2133 	return 0;
2134 fail:
2135 	dev_err(&pdev->dev, "probe failed, %d\n", ret);
2136 	return ret;
2137 }
2138 
2139 /**
2140  * xudc_remove - Releases the resources allocated during the initialization.
2141  * @pdev: pointer to the platform device structure.
2142  *
2143  * Return: 0 always
2144  */
2145 static int xudc_remove(struct platform_device *pdev)
2146 {
2147 	struct xusb_udc *udc = platform_get_drvdata(pdev);
2148 
2149 	usb_del_gadget_udc(&udc->gadget);
2150 
2151 	return 0;
2152 }
2153 
2154 /* Match table for of_platform binding */
2155 static const struct of_device_id usb_of_match[] = {
2156 	{ .compatible = "xlnx,usb2-device-4.00.a", },
2157 	{ /* end of list */ },
2158 };
2159 MODULE_DEVICE_TABLE(of, usb_of_match);
2160 
2161 static struct platform_driver xudc_driver = {
2162 	.driver = {
2163 		.name = driver_name,
2164 		.of_match_table = usb_of_match,
2165 	},
2166 	.probe = xudc_probe,
2167 	.remove = xudc_remove,
2168 };
2169 
2170 module_platform_driver(xudc_driver);
2171 
2172 MODULE_DESCRIPTION("Xilinx udc driver");
2173 MODULE_AUTHOR("Xilinx, Inc");
2174 MODULE_LICENSE("GPL");
2175