1 // SPDX-License-Identifier: GPL-2.0+ 2 /* 3 * Xilinx USB peripheral controller driver 4 * 5 * Copyright (C) 2004 by Thomas Rathbone 6 * Copyright (C) 2005 by HP Labs 7 * Copyright (C) 2005 by David Brownell 8 * Copyright (C) 2010 - 2014 Xilinx, Inc. 9 * 10 * Some parts of this driver code is based on the driver for at91-series 11 * USB peripheral controller (at91_udc.c). 12 */ 13 14 #include <linux/delay.h> 15 #include <linux/device.h> 16 #include <linux/dma-mapping.h> 17 #include <linux/interrupt.h> 18 #include <linux/io.h> 19 #include <linux/module.h> 20 #include <linux/of_address.h> 21 #include <linux/of_device.h> 22 #include <linux/of_platform.h> 23 #include <linux/of_irq.h> 24 #include <linux/prefetch.h> 25 #include <linux/usb/ch9.h> 26 #include <linux/usb/gadget.h> 27 28 /* Register offsets for the USB device.*/ 29 #define XUSB_EP0_CONFIG_OFFSET 0x0000 /* EP0 Config Reg Offset */ 30 #define XUSB_SETUP_PKT_ADDR_OFFSET 0x0080 /* Setup Packet Address */ 31 #define XUSB_ADDRESS_OFFSET 0x0100 /* Address Register */ 32 #define XUSB_CONTROL_OFFSET 0x0104 /* Control Register */ 33 #define XUSB_STATUS_OFFSET 0x0108 /* Status Register */ 34 #define XUSB_FRAMENUM_OFFSET 0x010C /* Frame Number Register */ 35 #define XUSB_IER_OFFSET 0x0110 /* Interrupt Enable Register */ 36 #define XUSB_BUFFREADY_OFFSET 0x0114 /* Buffer Ready Register */ 37 #define XUSB_TESTMODE_OFFSET 0x0118 /* Test Mode Register */ 38 #define XUSB_DMA_RESET_OFFSET 0x0200 /* DMA Soft Reset Register */ 39 #define XUSB_DMA_CONTROL_OFFSET 0x0204 /* DMA Control Register */ 40 #define XUSB_DMA_DSAR_ADDR_OFFSET 0x0208 /* DMA source Address Reg */ 41 #define XUSB_DMA_DDAR_ADDR_OFFSET 0x020C /* DMA destination Addr Reg */ 42 #define XUSB_DMA_LENGTH_OFFSET 0x0210 /* DMA Length Register */ 43 #define XUSB_DMA_STATUS_OFFSET 0x0214 /* DMA Status Register */ 44 45 /* Endpoint Configuration Space offsets */ 46 #define XUSB_EP_CFGSTATUS_OFFSET 0x00 /* Endpoint Config Status */ 47 #define XUSB_EP_BUF0COUNT_OFFSET 0x08 /* Buffer 0 Count */ 48 #define XUSB_EP_BUF1COUNT_OFFSET 0x0C /* Buffer 1 Count */ 49 50 #define XUSB_CONTROL_USB_READY_MASK 0x80000000 /* USB ready Mask */ 51 #define XUSB_CONTROL_USB_RMTWAKE_MASK 0x40000000 /* Remote wake up mask */ 52 53 /* Interrupt register related masks.*/ 54 #define XUSB_STATUS_GLOBAL_INTR_MASK 0x80000000 /* Global Intr Enable */ 55 #define XUSB_STATUS_DMADONE_MASK 0x04000000 /* DMA done Mask */ 56 #define XUSB_STATUS_DMAERR_MASK 0x02000000 /* DMA Error Mask */ 57 #define XUSB_STATUS_DMABUSY_MASK 0x80000000 /* DMA Error Mask */ 58 #define XUSB_STATUS_RESUME_MASK 0x01000000 /* USB Resume Mask */ 59 #define XUSB_STATUS_RESET_MASK 0x00800000 /* USB Reset Mask */ 60 #define XUSB_STATUS_SUSPEND_MASK 0x00400000 /* USB Suspend Mask */ 61 #define XUSB_STATUS_DISCONNECT_MASK 0x00200000 /* USB Disconnect Mask */ 62 #define XUSB_STATUS_FIFO_BUFF_RDY_MASK 0x00100000 /* FIFO Buff Ready Mask */ 63 #define XUSB_STATUS_FIFO_BUFF_FREE_MASK 0x00080000 /* FIFO Buff Free Mask */ 64 #define XUSB_STATUS_SETUP_PACKET_MASK 0x00040000 /* Setup packet received */ 65 #define XUSB_STATUS_EP1_BUFF2_COMP_MASK 0x00000200 /* EP 1 Buff 2 Processed */ 66 #define XUSB_STATUS_EP1_BUFF1_COMP_MASK 0x00000002 /* EP 1 Buff 1 Processed */ 67 #define XUSB_STATUS_EP0_BUFF2_COMP_MASK 0x00000100 /* EP 0 Buff 2 Processed */ 68 #define XUSB_STATUS_EP0_BUFF1_COMP_MASK 0x00000001 /* EP 0 Buff 1 Processed */ 69 #define XUSB_STATUS_HIGH_SPEED_MASK 0x00010000 /* USB Speed Mask */ 70 /* Suspend,Reset,Suspend and Disconnect Mask */ 71 #define XUSB_STATUS_INTR_EVENT_MASK 0x01E00000 72 /* Buffers completion Mask */ 73 #define XUSB_STATUS_INTR_BUFF_COMP_ALL_MASK 0x0000FEFF 74 /* Mask for buffer 0 and buffer 1 completion for all Endpoints */ 75 #define XUSB_STATUS_INTR_BUFF_COMP_SHIFT_MASK 0x00000101 76 #define XUSB_STATUS_EP_BUFF2_SHIFT 8 /* EP buffer offset */ 77 78 /* Endpoint Configuration Status Register */ 79 #define XUSB_EP_CFG_VALID_MASK 0x80000000 /* Endpoint Valid bit */ 80 #define XUSB_EP_CFG_STALL_MASK 0x40000000 /* Endpoint Stall bit */ 81 #define XUSB_EP_CFG_DATA_TOGGLE_MASK 0x08000000 /* Endpoint Data toggle */ 82 83 /* USB device specific global configuration constants.*/ 84 #define XUSB_MAX_ENDPOINTS 8 /* Maximum End Points */ 85 #define XUSB_EP_NUMBER_ZERO 0 /* End point Zero */ 86 /* DPRAM is the source address for DMA transfer */ 87 #define XUSB_DMA_READ_FROM_DPRAM 0x80000000 88 #define XUSB_DMA_DMASR_BUSY 0x80000000 /* DMA busy */ 89 #define XUSB_DMA_DMASR_ERROR 0x40000000 /* DMA Error */ 90 /* 91 * When this bit is set, the DMA buffer ready bit is set by hardware upon 92 * DMA transfer completion. 93 */ 94 #define XUSB_DMA_BRR_CTRL 0x40000000 /* DMA bufready ctrl bit */ 95 /* Phase States */ 96 #define SETUP_PHASE 0x0000 /* Setup Phase */ 97 #define DATA_PHASE 0x0001 /* Data Phase */ 98 #define STATUS_PHASE 0x0002 /* Status Phase */ 99 100 #define EP0_MAX_PACKET 64 /* Endpoint 0 maximum packet length */ 101 #define STATUSBUFF_SIZE 2 /* Buffer size for GET_STATUS command */ 102 #define EPNAME_SIZE 4 /* Buffer size for endpoint name */ 103 104 /* container_of helper macros */ 105 #define to_udc(g) container_of((g), struct xusb_udc, gadget) 106 #define to_xusb_ep(ep) container_of((ep), struct xusb_ep, ep_usb) 107 #define to_xusb_req(req) container_of((req), struct xusb_req, usb_req) 108 109 /** 110 * struct xusb_req - Xilinx USB device request structure 111 * @usb_req: Linux usb request structure 112 * @queue: usb device request queue 113 * @ep: pointer to xusb_endpoint structure 114 */ 115 struct xusb_req { 116 struct usb_request usb_req; 117 struct list_head queue; 118 struct xusb_ep *ep; 119 }; 120 121 /** 122 * struct xusb_ep - USB end point structure. 123 * @ep_usb: usb endpoint instance 124 * @queue: endpoint message queue 125 * @udc: xilinx usb peripheral driver instance pointer 126 * @desc: pointer to the usb endpoint descriptor 127 * @rambase: the endpoint buffer address 128 * @offset: the endpoint register offset value 129 * @name: name of the endpoint 130 * @epnumber: endpoint number 131 * @maxpacket: maximum packet size the endpoint can store 132 * @buffer0count: the size of the packet recieved in the first buffer 133 * @buffer1count: the size of the packet received in the second buffer 134 * @curbufnum: current buffer of endpoint that will be processed next 135 * @buffer0ready: the busy state of first buffer 136 * @buffer1ready: the busy state of second buffer 137 * @is_in: endpoint direction (IN or OUT) 138 * @is_iso: endpoint type(isochronous or non isochronous) 139 */ 140 struct xusb_ep { 141 struct usb_ep ep_usb; 142 struct list_head queue; 143 struct xusb_udc *udc; 144 const struct usb_endpoint_descriptor *desc; 145 u32 rambase; 146 u32 offset; 147 char name[4]; 148 u16 epnumber; 149 u16 maxpacket; 150 u16 buffer0count; 151 u16 buffer1count; 152 u8 curbufnum; 153 bool buffer0ready; 154 bool buffer1ready; 155 bool is_in; 156 bool is_iso; 157 }; 158 159 /** 160 * struct xusb_udc - USB peripheral driver structure 161 * @gadget: USB gadget driver instance 162 * @ep: an array of endpoint structures 163 * @driver: pointer to the usb gadget driver instance 164 * @setup: usb_ctrlrequest structure for control requests 165 * @req: pointer to dummy request for get status command 166 * @dev: pointer to device structure in gadget 167 * @usb_state: device in suspended state or not 168 * @remote_wkp: remote wakeup enabled by host 169 * @setupseqtx: tx status 170 * @setupseqrx: rx status 171 * @addr: the usb device base address 172 * @lock: instance of spinlock 173 * @dma_enabled: flag indicating whether the dma is included in the system 174 * @read_fn: function pointer to read device registers 175 * @write_fn: function pointer to write to device registers 176 */ 177 struct xusb_udc { 178 struct usb_gadget gadget; 179 struct xusb_ep ep[8]; 180 struct usb_gadget_driver *driver; 181 struct usb_ctrlrequest setup; 182 struct xusb_req *req; 183 struct device *dev; 184 u32 usb_state; 185 u32 remote_wkp; 186 u32 setupseqtx; 187 u32 setupseqrx; 188 void __iomem *addr; 189 spinlock_t lock; 190 bool dma_enabled; 191 192 unsigned int (*read_fn)(void __iomem *); 193 void (*write_fn)(void __iomem *, u32, u32); 194 }; 195 196 /* Endpoint buffer start addresses in the core */ 197 static u32 rambase[8] = { 0x22, 0x1000, 0x1100, 0x1200, 0x1300, 0x1400, 0x1500, 198 0x1600 }; 199 200 static const char driver_name[] = "xilinx-udc"; 201 static const char ep0name[] = "ep0"; 202 203 /* Control endpoint configuration.*/ 204 static const struct usb_endpoint_descriptor config_bulk_out_desc = { 205 .bLength = USB_DT_ENDPOINT_SIZE, 206 .bDescriptorType = USB_DT_ENDPOINT, 207 .bEndpointAddress = USB_DIR_OUT, 208 .bmAttributes = USB_ENDPOINT_XFER_BULK, 209 .wMaxPacketSize = cpu_to_le16(EP0_MAX_PACKET), 210 }; 211 212 /** 213 * xudc_write32 - little endian write to device registers 214 * @addr: base addr of device registers 215 * @offset: register offset 216 * @val: data to be written 217 */ 218 static void xudc_write32(void __iomem *addr, u32 offset, u32 val) 219 { 220 iowrite32(val, addr + offset); 221 } 222 223 /** 224 * xudc_read32 - little endian read from device registers 225 * @addr: addr of device register 226 * Return: value at addr 227 */ 228 static unsigned int xudc_read32(void __iomem *addr) 229 { 230 return ioread32(addr); 231 } 232 233 /** 234 * xudc_write32_be - big endian write to device registers 235 * @addr: base addr of device registers 236 * @offset: register offset 237 * @val: data to be written 238 */ 239 static void xudc_write32_be(void __iomem *addr, u32 offset, u32 val) 240 { 241 iowrite32be(val, addr + offset); 242 } 243 244 /** 245 * xudc_read32_be - big endian read from device registers 246 * @addr: addr of device register 247 * Return: value at addr 248 */ 249 static unsigned int xudc_read32_be(void __iomem *addr) 250 { 251 return ioread32be(addr); 252 } 253 254 /** 255 * xudc_wrstatus - Sets up the usb device status stages. 256 * @udc: pointer to the usb device controller structure. 257 */ 258 static void xudc_wrstatus(struct xusb_udc *udc) 259 { 260 struct xusb_ep *ep0 = &udc->ep[XUSB_EP_NUMBER_ZERO]; 261 u32 epcfgreg; 262 263 epcfgreg = udc->read_fn(udc->addr + ep0->offset)| 264 XUSB_EP_CFG_DATA_TOGGLE_MASK; 265 udc->write_fn(udc->addr, ep0->offset, epcfgreg); 266 udc->write_fn(udc->addr, ep0->offset + XUSB_EP_BUF0COUNT_OFFSET, 0); 267 udc->write_fn(udc->addr, XUSB_BUFFREADY_OFFSET, 1); 268 } 269 270 /** 271 * xudc_epconfig - Configures the given endpoint. 272 * @ep: pointer to the usb device endpoint structure. 273 * @udc: pointer to the usb peripheral controller structure. 274 * 275 * This function configures a specific endpoint with the given configuration 276 * data. 277 */ 278 static void xudc_epconfig(struct xusb_ep *ep, struct xusb_udc *udc) 279 { 280 u32 epcfgreg; 281 282 /* 283 * Configure the end point direction, type, Max Packet Size and the 284 * EP buffer location. 285 */ 286 epcfgreg = ((ep->is_in << 29) | (ep->is_iso << 28) | 287 (ep->ep_usb.maxpacket << 15) | (ep->rambase)); 288 udc->write_fn(udc->addr, ep->offset, epcfgreg); 289 290 /* Set the Buffer count and the Buffer ready bits.*/ 291 udc->write_fn(udc->addr, ep->offset + XUSB_EP_BUF0COUNT_OFFSET, 292 ep->buffer0count); 293 udc->write_fn(udc->addr, ep->offset + XUSB_EP_BUF1COUNT_OFFSET, 294 ep->buffer1count); 295 if (ep->buffer0ready) 296 udc->write_fn(udc->addr, XUSB_BUFFREADY_OFFSET, 297 1 << ep->epnumber); 298 if (ep->buffer1ready) 299 udc->write_fn(udc->addr, XUSB_BUFFREADY_OFFSET, 300 1 << (ep->epnumber + XUSB_STATUS_EP_BUFF2_SHIFT)); 301 } 302 303 /** 304 * xudc_start_dma - Starts DMA transfer. 305 * @ep: pointer to the usb device endpoint structure. 306 * @src: DMA source address. 307 * @dst: DMA destination address. 308 * @length: number of bytes to transfer. 309 * 310 * Return: 0 on success, error code on failure 311 * 312 * This function starts DMA transfer by writing to DMA source, 313 * destination and lenth registers. 314 */ 315 static int xudc_start_dma(struct xusb_ep *ep, dma_addr_t src, 316 dma_addr_t dst, u32 length) 317 { 318 struct xusb_udc *udc = ep->udc; 319 int rc = 0; 320 u32 timeout = 500; 321 u32 reg; 322 323 /* 324 * Set the addresses in the DMA source and 325 * destination registers and then set the length 326 * into the DMA length register. 327 */ 328 udc->write_fn(udc->addr, XUSB_DMA_DSAR_ADDR_OFFSET, src); 329 udc->write_fn(udc->addr, XUSB_DMA_DDAR_ADDR_OFFSET, dst); 330 udc->write_fn(udc->addr, XUSB_DMA_LENGTH_OFFSET, length); 331 332 /* 333 * Wait till DMA transaction is complete and 334 * check whether the DMA transaction was 335 * successful. 336 */ 337 do { 338 reg = udc->read_fn(udc->addr + XUSB_DMA_STATUS_OFFSET); 339 if (!(reg & XUSB_DMA_DMASR_BUSY)) 340 break; 341 342 /* 343 * We can't sleep here, because it's also called from 344 * interrupt context. 345 */ 346 timeout--; 347 if (!timeout) { 348 dev_err(udc->dev, "DMA timeout\n"); 349 return -ETIMEDOUT; 350 } 351 udelay(1); 352 } while (1); 353 354 if ((udc->read_fn(udc->addr + XUSB_DMA_STATUS_OFFSET) & 355 XUSB_DMA_DMASR_ERROR) == XUSB_DMA_DMASR_ERROR){ 356 dev_err(udc->dev, "DMA Error\n"); 357 rc = -EINVAL; 358 } 359 360 return rc; 361 } 362 363 /** 364 * xudc_dma_send - Sends IN data using DMA. 365 * @ep: pointer to the usb device endpoint structure. 366 * @req: pointer to the usb request structure. 367 * @buffer: pointer to data to be sent. 368 * @length: number of bytes to send. 369 * 370 * Return: 0 on success, -EAGAIN if no buffer is free and error 371 * code on failure. 372 * 373 * This function sends data using DMA. 374 */ 375 static int xudc_dma_send(struct xusb_ep *ep, struct xusb_req *req, 376 u8 *buffer, u32 length) 377 { 378 u32 *eprambase; 379 dma_addr_t src; 380 dma_addr_t dst; 381 struct xusb_udc *udc = ep->udc; 382 383 src = req->usb_req.dma + req->usb_req.actual; 384 if (req->usb_req.length) 385 dma_sync_single_for_device(udc->dev, src, 386 length, DMA_TO_DEVICE); 387 if (!ep->curbufnum && !ep->buffer0ready) { 388 /* Get the Buffer address and copy the transmit data.*/ 389 eprambase = (u32 __force *)(udc->addr + ep->rambase); 390 dst = virt_to_phys(eprambase); 391 udc->write_fn(udc->addr, ep->offset + 392 XUSB_EP_BUF0COUNT_OFFSET, length); 393 udc->write_fn(udc->addr, XUSB_DMA_CONTROL_OFFSET, 394 XUSB_DMA_BRR_CTRL | (1 << ep->epnumber)); 395 ep->buffer0ready = 1; 396 ep->curbufnum = 1; 397 } else if (ep->curbufnum && !ep->buffer1ready) { 398 /* Get the Buffer address and copy the transmit data.*/ 399 eprambase = (u32 __force *)(udc->addr + ep->rambase + 400 ep->ep_usb.maxpacket); 401 dst = virt_to_phys(eprambase); 402 udc->write_fn(udc->addr, ep->offset + 403 XUSB_EP_BUF1COUNT_OFFSET, length); 404 udc->write_fn(udc->addr, XUSB_DMA_CONTROL_OFFSET, 405 XUSB_DMA_BRR_CTRL | (1 << (ep->epnumber + 406 XUSB_STATUS_EP_BUFF2_SHIFT))); 407 ep->buffer1ready = 1; 408 ep->curbufnum = 0; 409 } else { 410 /* None of ping pong buffers are ready currently .*/ 411 return -EAGAIN; 412 } 413 414 return xudc_start_dma(ep, src, dst, length); 415 } 416 417 /** 418 * xudc_dma_receive - Receives OUT data using DMA. 419 * @ep: pointer to the usb device endpoint structure. 420 * @req: pointer to the usb request structure. 421 * @buffer: pointer to storage buffer of received data. 422 * @length: number of bytes to receive. 423 * 424 * Return: 0 on success, -EAGAIN if no buffer is free and error 425 * code on failure. 426 * 427 * This function receives data using DMA. 428 */ 429 static int xudc_dma_receive(struct xusb_ep *ep, struct xusb_req *req, 430 u8 *buffer, u32 length) 431 { 432 u32 *eprambase; 433 dma_addr_t src; 434 dma_addr_t dst; 435 struct xusb_udc *udc = ep->udc; 436 437 dst = req->usb_req.dma + req->usb_req.actual; 438 if (!ep->curbufnum && !ep->buffer0ready) { 439 /* Get the Buffer address and copy the transmit data */ 440 eprambase = (u32 __force *)(udc->addr + ep->rambase); 441 src = virt_to_phys(eprambase); 442 udc->write_fn(udc->addr, XUSB_DMA_CONTROL_OFFSET, 443 XUSB_DMA_BRR_CTRL | XUSB_DMA_READ_FROM_DPRAM | 444 (1 << ep->epnumber)); 445 ep->buffer0ready = 1; 446 ep->curbufnum = 1; 447 } else if (ep->curbufnum && !ep->buffer1ready) { 448 /* Get the Buffer address and copy the transmit data */ 449 eprambase = (u32 __force *)(udc->addr + 450 ep->rambase + ep->ep_usb.maxpacket); 451 src = virt_to_phys(eprambase); 452 udc->write_fn(udc->addr, XUSB_DMA_CONTROL_OFFSET, 453 XUSB_DMA_BRR_CTRL | XUSB_DMA_READ_FROM_DPRAM | 454 (1 << (ep->epnumber + 455 XUSB_STATUS_EP_BUFF2_SHIFT))); 456 ep->buffer1ready = 1; 457 ep->curbufnum = 0; 458 } else { 459 /* None of the ping-pong buffers are ready currently */ 460 return -EAGAIN; 461 } 462 463 return xudc_start_dma(ep, src, dst, length); 464 } 465 466 /** 467 * xudc_eptxrx - Transmits or receives data to or from an endpoint. 468 * @ep: pointer to the usb endpoint configuration structure. 469 * @req: pointer to the usb request structure. 470 * @bufferptr: pointer to buffer containing the data to be sent. 471 * @bufferlen: The number of data bytes to be sent. 472 * 473 * Return: 0 on success, -EAGAIN if no buffer is free. 474 * 475 * This function copies the transmit/receive data to/from the end point buffer 476 * and enables the buffer for transmission/reception. 477 */ 478 static int xudc_eptxrx(struct xusb_ep *ep, struct xusb_req *req, 479 u8 *bufferptr, u32 bufferlen) 480 { 481 u32 *eprambase; 482 u32 bytestosend; 483 int rc = 0; 484 struct xusb_udc *udc = ep->udc; 485 486 bytestosend = bufferlen; 487 if (udc->dma_enabled) { 488 if (ep->is_in) 489 rc = xudc_dma_send(ep, req, bufferptr, bufferlen); 490 else 491 rc = xudc_dma_receive(ep, req, bufferptr, bufferlen); 492 return rc; 493 } 494 /* Put the transmit buffer into the correct ping-pong buffer.*/ 495 if (!ep->curbufnum && !ep->buffer0ready) { 496 /* Get the Buffer address and copy the transmit data.*/ 497 eprambase = (u32 __force *)(udc->addr + ep->rambase); 498 if (ep->is_in) { 499 memcpy(eprambase, bufferptr, bytestosend); 500 udc->write_fn(udc->addr, ep->offset + 501 XUSB_EP_BUF0COUNT_OFFSET, bufferlen); 502 } else { 503 memcpy(bufferptr, eprambase, bytestosend); 504 } 505 /* 506 * Enable the buffer for transmission. 507 */ 508 udc->write_fn(udc->addr, XUSB_BUFFREADY_OFFSET, 509 1 << ep->epnumber); 510 ep->buffer0ready = 1; 511 ep->curbufnum = 1; 512 } else if (ep->curbufnum && !ep->buffer1ready) { 513 /* Get the Buffer address and copy the transmit data.*/ 514 eprambase = (u32 __force *)(udc->addr + ep->rambase + 515 ep->ep_usb.maxpacket); 516 if (ep->is_in) { 517 memcpy(eprambase, bufferptr, bytestosend); 518 udc->write_fn(udc->addr, ep->offset + 519 XUSB_EP_BUF1COUNT_OFFSET, bufferlen); 520 } else { 521 memcpy(bufferptr, eprambase, bytestosend); 522 } 523 /* 524 * Enable the buffer for transmission. 525 */ 526 udc->write_fn(udc->addr, XUSB_BUFFREADY_OFFSET, 527 1 << (ep->epnumber + XUSB_STATUS_EP_BUFF2_SHIFT)); 528 ep->buffer1ready = 1; 529 ep->curbufnum = 0; 530 } else { 531 /* None of the ping-pong buffers are ready currently */ 532 return -EAGAIN; 533 } 534 return rc; 535 } 536 537 /** 538 * xudc_done - Exeutes the endpoint data transfer completion tasks. 539 * @ep: pointer to the usb device endpoint structure. 540 * @req: pointer to the usb request structure. 541 * @status: Status of the data transfer. 542 * 543 * Deletes the message from the queue and updates data transfer completion 544 * status. 545 */ 546 static void xudc_done(struct xusb_ep *ep, struct xusb_req *req, int status) 547 { 548 struct xusb_udc *udc = ep->udc; 549 550 list_del_init(&req->queue); 551 552 if (req->usb_req.status == -EINPROGRESS) 553 req->usb_req.status = status; 554 else 555 status = req->usb_req.status; 556 557 if (status && status != -ESHUTDOWN) 558 dev_dbg(udc->dev, "%s done %p, status %d\n", 559 ep->ep_usb.name, req, status); 560 /* unmap request if DMA is present*/ 561 if (udc->dma_enabled && ep->epnumber && req->usb_req.length) 562 usb_gadget_unmap_request(&udc->gadget, &req->usb_req, 563 ep->is_in); 564 565 if (req->usb_req.complete) { 566 spin_unlock(&udc->lock); 567 req->usb_req.complete(&ep->ep_usb, &req->usb_req); 568 spin_lock(&udc->lock); 569 } 570 } 571 572 /** 573 * xudc_read_fifo - Reads the data from the given endpoint buffer. 574 * @ep: pointer to the usb device endpoint structure. 575 * @req: pointer to the usb request structure. 576 * 577 * Return: 0 if request is completed and -EAGAIN if not completed. 578 * 579 * Pulls OUT packet data from the endpoint buffer. 580 */ 581 static int xudc_read_fifo(struct xusb_ep *ep, struct xusb_req *req) 582 { 583 u8 *buf; 584 u32 is_short, count, bufferspace; 585 u8 bufoffset; 586 u8 two_pkts = 0; 587 int ret; 588 int retval = -EAGAIN; 589 struct xusb_udc *udc = ep->udc; 590 591 if (ep->buffer0ready && ep->buffer1ready) { 592 dev_dbg(udc->dev, "Packet NOT ready!\n"); 593 return retval; 594 } 595 top: 596 if (ep->curbufnum) 597 bufoffset = XUSB_EP_BUF1COUNT_OFFSET; 598 else 599 bufoffset = XUSB_EP_BUF0COUNT_OFFSET; 600 601 count = udc->read_fn(udc->addr + ep->offset + bufoffset); 602 603 if (!ep->buffer0ready && !ep->buffer1ready) 604 two_pkts = 1; 605 606 buf = req->usb_req.buf + req->usb_req.actual; 607 prefetchw(buf); 608 bufferspace = req->usb_req.length - req->usb_req.actual; 609 is_short = count < ep->ep_usb.maxpacket; 610 611 if (unlikely(!bufferspace)) { 612 /* 613 * This happens when the driver's buffer 614 * is smaller than what the host sent. 615 * discard the extra data. 616 */ 617 if (req->usb_req.status != -EOVERFLOW) 618 dev_dbg(udc->dev, "%s overflow %d\n", 619 ep->ep_usb.name, count); 620 req->usb_req.status = -EOVERFLOW; 621 xudc_done(ep, req, -EOVERFLOW); 622 return 0; 623 } 624 625 ret = xudc_eptxrx(ep, req, buf, count); 626 switch (ret) { 627 case 0: 628 req->usb_req.actual += min(count, bufferspace); 629 dev_dbg(udc->dev, "read %s, %d bytes%s req %p %d/%d\n", 630 ep->ep_usb.name, count, is_short ? "/S" : "", req, 631 req->usb_req.actual, req->usb_req.length); 632 bufferspace -= count; 633 /* Completion */ 634 if ((req->usb_req.actual == req->usb_req.length) || is_short) { 635 if (udc->dma_enabled && req->usb_req.length) 636 dma_sync_single_for_cpu(udc->dev, 637 req->usb_req.dma, 638 req->usb_req.actual, 639 DMA_FROM_DEVICE); 640 xudc_done(ep, req, 0); 641 return 0; 642 } 643 if (two_pkts) { 644 two_pkts = 0; 645 goto top; 646 } 647 break; 648 case -EAGAIN: 649 dev_dbg(udc->dev, "receive busy\n"); 650 break; 651 case -EINVAL: 652 case -ETIMEDOUT: 653 /* DMA error, dequeue the request */ 654 xudc_done(ep, req, -ECONNRESET); 655 retval = 0; 656 break; 657 } 658 659 return retval; 660 } 661 662 /** 663 * xudc_write_fifo - Writes data into the given endpoint buffer. 664 * @ep: pointer to the usb device endpoint structure. 665 * @req: pointer to the usb request structure. 666 * 667 * Return: 0 if request is completed and -EAGAIN if not completed. 668 * 669 * Loads endpoint buffer for an IN packet. 670 */ 671 static int xudc_write_fifo(struct xusb_ep *ep, struct xusb_req *req) 672 { 673 u32 max; 674 u32 length; 675 int ret; 676 int retval = -EAGAIN; 677 struct xusb_udc *udc = ep->udc; 678 int is_last, is_short = 0; 679 u8 *buf; 680 681 max = le16_to_cpu(ep->desc->wMaxPacketSize); 682 buf = req->usb_req.buf + req->usb_req.actual; 683 prefetch(buf); 684 length = req->usb_req.length - req->usb_req.actual; 685 length = min(length, max); 686 687 ret = xudc_eptxrx(ep, req, buf, length); 688 switch (ret) { 689 case 0: 690 req->usb_req.actual += length; 691 if (unlikely(length != max)) { 692 is_last = is_short = 1; 693 } else { 694 if (likely(req->usb_req.length != 695 req->usb_req.actual) || req->usb_req.zero) 696 is_last = 0; 697 else 698 is_last = 1; 699 } 700 dev_dbg(udc->dev, "%s: wrote %s %d bytes%s%s %d left %p\n", 701 __func__, ep->ep_usb.name, length, is_last ? "/L" : "", 702 is_short ? "/S" : "", 703 req->usb_req.length - req->usb_req.actual, req); 704 /* completion */ 705 if (is_last) { 706 xudc_done(ep, req, 0); 707 retval = 0; 708 } 709 break; 710 case -EAGAIN: 711 dev_dbg(udc->dev, "Send busy\n"); 712 break; 713 case -EINVAL: 714 case -ETIMEDOUT: 715 /* DMA error, dequeue the request */ 716 xudc_done(ep, req, -ECONNRESET); 717 retval = 0; 718 break; 719 } 720 721 return retval; 722 } 723 724 /** 725 * xudc_nuke - Cleans up the data transfer message list. 726 * @ep: pointer to the usb device endpoint structure. 727 * @status: Status of the data transfer. 728 */ 729 static void xudc_nuke(struct xusb_ep *ep, int status) 730 { 731 struct xusb_req *req; 732 733 while (!list_empty(&ep->queue)) { 734 req = list_first_entry(&ep->queue, struct xusb_req, queue); 735 xudc_done(ep, req, status); 736 } 737 } 738 739 /** 740 * xudc_ep_set_halt - Stalls/unstalls the given endpoint. 741 * @_ep: pointer to the usb device endpoint structure. 742 * @value: value to indicate stall/unstall. 743 * 744 * Return: 0 for success and error value on failure 745 */ 746 static int xudc_ep_set_halt(struct usb_ep *_ep, int value) 747 { 748 struct xusb_ep *ep = to_xusb_ep(_ep); 749 struct xusb_udc *udc; 750 unsigned long flags; 751 u32 epcfgreg; 752 753 if (!_ep || (!ep->desc && ep->epnumber)) { 754 pr_debug("%s: bad ep or descriptor\n", __func__); 755 return -EINVAL; 756 } 757 udc = ep->udc; 758 759 if (ep->is_in && (!list_empty(&ep->queue)) && value) { 760 dev_dbg(udc->dev, "requests pending can't halt\n"); 761 return -EAGAIN; 762 } 763 764 if (ep->buffer0ready || ep->buffer1ready) { 765 dev_dbg(udc->dev, "HW buffers busy can't halt\n"); 766 return -EAGAIN; 767 } 768 769 spin_lock_irqsave(&udc->lock, flags); 770 771 if (value) { 772 /* Stall the device.*/ 773 epcfgreg = udc->read_fn(udc->addr + ep->offset); 774 epcfgreg |= XUSB_EP_CFG_STALL_MASK; 775 udc->write_fn(udc->addr, ep->offset, epcfgreg); 776 } else { 777 /* Unstall the device.*/ 778 epcfgreg = udc->read_fn(udc->addr + ep->offset); 779 epcfgreg &= ~XUSB_EP_CFG_STALL_MASK; 780 udc->write_fn(udc->addr, ep->offset, epcfgreg); 781 if (ep->epnumber) { 782 /* Reset the toggle bit.*/ 783 epcfgreg = udc->read_fn(ep->udc->addr + ep->offset); 784 epcfgreg &= ~XUSB_EP_CFG_DATA_TOGGLE_MASK; 785 udc->write_fn(udc->addr, ep->offset, epcfgreg); 786 } 787 } 788 789 spin_unlock_irqrestore(&udc->lock, flags); 790 return 0; 791 } 792 793 /** 794 * xudc_ep_enable - Enables the given endpoint. 795 * @ep: pointer to the xusb endpoint structure. 796 * @desc: pointer to usb endpoint descriptor. 797 * 798 * Return: 0 for success and error value on failure 799 */ 800 static int __xudc_ep_enable(struct xusb_ep *ep, 801 const struct usb_endpoint_descriptor *desc) 802 { 803 struct xusb_udc *udc = ep->udc; 804 u32 tmp; 805 u32 epcfg; 806 u32 ier; 807 u16 maxpacket; 808 809 ep->is_in = ((desc->bEndpointAddress & USB_DIR_IN) != 0); 810 /* Bit 3...0:endpoint number */ 811 ep->epnumber = (desc->bEndpointAddress & 0x0f); 812 ep->desc = desc; 813 ep->ep_usb.desc = desc; 814 tmp = desc->bmAttributes & USB_ENDPOINT_XFERTYPE_MASK; 815 ep->ep_usb.maxpacket = maxpacket = le16_to_cpu(desc->wMaxPacketSize); 816 817 switch (tmp) { 818 case USB_ENDPOINT_XFER_CONTROL: 819 dev_dbg(udc->dev, "only one control endpoint\n"); 820 /* NON- ISO */ 821 ep->is_iso = 0; 822 return -EINVAL; 823 case USB_ENDPOINT_XFER_INT: 824 /* NON- ISO */ 825 ep->is_iso = 0; 826 if (maxpacket > 64) { 827 dev_dbg(udc->dev, "bogus maxpacket %d\n", maxpacket); 828 return -EINVAL; 829 } 830 break; 831 case USB_ENDPOINT_XFER_BULK: 832 /* NON- ISO */ 833 ep->is_iso = 0; 834 if (!(is_power_of_2(maxpacket) && maxpacket >= 8 && 835 maxpacket <= 512)) { 836 dev_dbg(udc->dev, "bogus maxpacket %d\n", maxpacket); 837 return -EINVAL; 838 } 839 break; 840 case USB_ENDPOINT_XFER_ISOC: 841 /* ISO */ 842 ep->is_iso = 1; 843 break; 844 } 845 846 ep->buffer0ready = 0; 847 ep->buffer1ready = 0; 848 ep->curbufnum = 0; 849 ep->rambase = rambase[ep->epnumber]; 850 xudc_epconfig(ep, udc); 851 852 dev_dbg(udc->dev, "Enable Endpoint %d max pkt is %d\n", 853 ep->epnumber, maxpacket); 854 855 /* Enable the End point.*/ 856 epcfg = udc->read_fn(udc->addr + ep->offset); 857 epcfg |= XUSB_EP_CFG_VALID_MASK; 858 udc->write_fn(udc->addr, ep->offset, epcfg); 859 if (ep->epnumber) 860 ep->rambase <<= 2; 861 862 /* Enable buffer completion interrupts for endpoint */ 863 ier = udc->read_fn(udc->addr + XUSB_IER_OFFSET); 864 ier |= (XUSB_STATUS_INTR_BUFF_COMP_SHIFT_MASK << ep->epnumber); 865 udc->write_fn(udc->addr, XUSB_IER_OFFSET, ier); 866 867 /* for OUT endpoint set buffers ready to receive */ 868 if (ep->epnumber && !ep->is_in) { 869 udc->write_fn(udc->addr, XUSB_BUFFREADY_OFFSET, 870 1 << ep->epnumber); 871 ep->buffer0ready = 1; 872 udc->write_fn(udc->addr, XUSB_BUFFREADY_OFFSET, 873 (1 << (ep->epnumber + 874 XUSB_STATUS_EP_BUFF2_SHIFT))); 875 ep->buffer1ready = 1; 876 } 877 878 return 0; 879 } 880 881 /** 882 * xudc_ep_enable - Enables the given endpoint. 883 * @_ep: pointer to the usb endpoint structure. 884 * @desc: pointer to usb endpoint descriptor. 885 * 886 * Return: 0 for success and error value on failure 887 */ 888 static int xudc_ep_enable(struct usb_ep *_ep, 889 const struct usb_endpoint_descriptor *desc) 890 { 891 struct xusb_ep *ep; 892 struct xusb_udc *udc; 893 unsigned long flags; 894 int ret; 895 896 if (!_ep || !desc || desc->bDescriptorType != USB_DT_ENDPOINT) { 897 pr_debug("%s: bad ep or descriptor\n", __func__); 898 return -EINVAL; 899 } 900 901 ep = to_xusb_ep(_ep); 902 udc = ep->udc; 903 904 if (!udc->driver || udc->gadget.speed == USB_SPEED_UNKNOWN) { 905 dev_dbg(udc->dev, "bogus device state\n"); 906 return -ESHUTDOWN; 907 } 908 909 spin_lock_irqsave(&udc->lock, flags); 910 ret = __xudc_ep_enable(ep, desc); 911 spin_unlock_irqrestore(&udc->lock, flags); 912 913 return ret; 914 } 915 916 /** 917 * xudc_ep_disable - Disables the given endpoint. 918 * @_ep: pointer to the usb endpoint structure. 919 * 920 * Return: 0 for success and error value on failure 921 */ 922 static int xudc_ep_disable(struct usb_ep *_ep) 923 { 924 struct xusb_ep *ep; 925 unsigned long flags; 926 u32 epcfg; 927 struct xusb_udc *udc; 928 929 if (!_ep) { 930 pr_debug("%s: invalid ep\n", __func__); 931 return -EINVAL; 932 } 933 934 ep = to_xusb_ep(_ep); 935 udc = ep->udc; 936 937 spin_lock_irqsave(&udc->lock, flags); 938 939 xudc_nuke(ep, -ESHUTDOWN); 940 941 /* Restore the endpoint's pristine config */ 942 ep->desc = NULL; 943 ep->ep_usb.desc = NULL; 944 945 dev_dbg(udc->dev, "USB Ep %d disable\n ", ep->epnumber); 946 /* Disable the endpoint.*/ 947 epcfg = udc->read_fn(udc->addr + ep->offset); 948 epcfg &= ~XUSB_EP_CFG_VALID_MASK; 949 udc->write_fn(udc->addr, ep->offset, epcfg); 950 951 spin_unlock_irqrestore(&udc->lock, flags); 952 return 0; 953 } 954 955 /** 956 * xudc_ep_alloc_request - Initializes the request queue. 957 * @_ep: pointer to the usb endpoint structure. 958 * @gfp_flags: Flags related to the request call. 959 * 960 * Return: pointer to request structure on success and a NULL on failure. 961 */ 962 static struct usb_request *xudc_ep_alloc_request(struct usb_ep *_ep, 963 gfp_t gfp_flags) 964 { 965 struct xusb_ep *ep = to_xusb_ep(_ep); 966 struct xusb_udc *udc; 967 struct xusb_req *req; 968 969 udc = ep->udc; 970 req = kzalloc(sizeof(*req), gfp_flags); 971 if (!req) 972 return NULL; 973 974 req->ep = ep; 975 INIT_LIST_HEAD(&req->queue); 976 return &req->usb_req; 977 } 978 979 /** 980 * xudc_free_request - Releases the request from queue. 981 * @_ep: pointer to the usb device endpoint structure. 982 * @_req: pointer to the usb request structure. 983 */ 984 static void xudc_free_request(struct usb_ep *_ep, struct usb_request *_req) 985 { 986 struct xusb_req *req = to_xusb_req(_req); 987 988 kfree(req); 989 } 990 991 /** 992 * xudc_ep0_queue - Adds the request to endpoint 0 queue. 993 * @ep0: pointer to the xusb endpoint 0 structure. 994 * @req: pointer to the xusb request structure. 995 * 996 * Return: 0 for success and error value on failure 997 */ 998 static int __xudc_ep0_queue(struct xusb_ep *ep0, struct xusb_req *req) 999 { 1000 struct xusb_udc *udc = ep0->udc; 1001 u32 length; 1002 u8 *corebuf; 1003 1004 if (!udc->driver || udc->gadget.speed == USB_SPEED_UNKNOWN) { 1005 dev_dbg(udc->dev, "%s, bogus device state\n", __func__); 1006 return -EINVAL; 1007 } 1008 if (!list_empty(&ep0->queue)) { 1009 dev_dbg(udc->dev, "%s:ep0 busy\n", __func__); 1010 return -EBUSY; 1011 } 1012 1013 req->usb_req.status = -EINPROGRESS; 1014 req->usb_req.actual = 0; 1015 1016 list_add_tail(&req->queue, &ep0->queue); 1017 1018 if (udc->setup.bRequestType & USB_DIR_IN) { 1019 prefetch(req->usb_req.buf); 1020 length = req->usb_req.length; 1021 corebuf = (void __force *) ((ep0->rambase << 2) + 1022 udc->addr); 1023 length = req->usb_req.actual = min_t(u32, length, 1024 EP0_MAX_PACKET); 1025 memcpy(corebuf, req->usb_req.buf, length); 1026 udc->write_fn(udc->addr, XUSB_EP_BUF0COUNT_OFFSET, length); 1027 udc->write_fn(udc->addr, XUSB_BUFFREADY_OFFSET, 1); 1028 } else { 1029 if (udc->setup.wLength) { 1030 /* Enable EP0 buffer to receive data */ 1031 udc->write_fn(udc->addr, XUSB_EP_BUF0COUNT_OFFSET, 0); 1032 udc->write_fn(udc->addr, XUSB_BUFFREADY_OFFSET, 1); 1033 } else { 1034 xudc_wrstatus(udc); 1035 } 1036 } 1037 1038 return 0; 1039 } 1040 1041 /** 1042 * xudc_ep0_queue - Adds the request to endpoint 0 queue. 1043 * @_ep: pointer to the usb endpoint 0 structure. 1044 * @_req: pointer to the usb request structure. 1045 * @gfp_flags: Flags related to the request call. 1046 * 1047 * Return: 0 for success and error value on failure 1048 */ 1049 static int xudc_ep0_queue(struct usb_ep *_ep, struct usb_request *_req, 1050 gfp_t gfp_flags) 1051 { 1052 struct xusb_req *req = to_xusb_req(_req); 1053 struct xusb_ep *ep0 = to_xusb_ep(_ep); 1054 struct xusb_udc *udc = ep0->udc; 1055 unsigned long flags; 1056 int ret; 1057 1058 spin_lock_irqsave(&udc->lock, flags); 1059 ret = __xudc_ep0_queue(ep0, req); 1060 spin_unlock_irqrestore(&udc->lock, flags); 1061 1062 return ret; 1063 } 1064 1065 /** 1066 * xudc_ep_queue - Adds the request to endpoint queue. 1067 * @_ep: pointer to the usb endpoint structure. 1068 * @_req: pointer to the usb request structure. 1069 * @gfp_flags: Flags related to the request call. 1070 * 1071 * Return: 0 for success and error value on failure 1072 */ 1073 static int xudc_ep_queue(struct usb_ep *_ep, struct usb_request *_req, 1074 gfp_t gfp_flags) 1075 { 1076 struct xusb_req *req = to_xusb_req(_req); 1077 struct xusb_ep *ep = to_xusb_ep(_ep); 1078 struct xusb_udc *udc = ep->udc; 1079 int ret; 1080 unsigned long flags; 1081 1082 if (!ep->desc) { 1083 dev_dbg(udc->dev, "%s:queing request to disabled %s\n", 1084 __func__, ep->name); 1085 return -ESHUTDOWN; 1086 } 1087 1088 if (!udc->driver || udc->gadget.speed == USB_SPEED_UNKNOWN) { 1089 dev_dbg(udc->dev, "%s, bogus device state\n", __func__); 1090 return -EINVAL; 1091 } 1092 1093 spin_lock_irqsave(&udc->lock, flags); 1094 1095 _req->status = -EINPROGRESS; 1096 _req->actual = 0; 1097 1098 if (udc->dma_enabled) { 1099 ret = usb_gadget_map_request(&udc->gadget, &req->usb_req, 1100 ep->is_in); 1101 if (ret) { 1102 dev_dbg(udc->dev, "gadget_map failed ep%d\n", 1103 ep->epnumber); 1104 spin_unlock_irqrestore(&udc->lock, flags); 1105 return -EAGAIN; 1106 } 1107 } 1108 1109 if (list_empty(&ep->queue)) { 1110 if (ep->is_in) { 1111 dev_dbg(udc->dev, "xudc_write_fifo from ep_queue\n"); 1112 if (!xudc_write_fifo(ep, req)) 1113 req = NULL; 1114 } else { 1115 dev_dbg(udc->dev, "xudc_read_fifo from ep_queue\n"); 1116 if (!xudc_read_fifo(ep, req)) 1117 req = NULL; 1118 } 1119 } 1120 1121 if (req != NULL) 1122 list_add_tail(&req->queue, &ep->queue); 1123 1124 spin_unlock_irqrestore(&udc->lock, flags); 1125 return 0; 1126 } 1127 1128 /** 1129 * xudc_ep_dequeue - Removes the request from the queue. 1130 * @_ep: pointer to the usb device endpoint structure. 1131 * @_req: pointer to the usb request structure. 1132 * 1133 * Return: 0 for success and error value on failure 1134 */ 1135 static int xudc_ep_dequeue(struct usb_ep *_ep, struct usb_request *_req) 1136 { 1137 struct xusb_ep *ep = to_xusb_ep(_ep); 1138 struct xusb_req *req = to_xusb_req(_req); 1139 struct xusb_udc *udc = ep->udc; 1140 unsigned long flags; 1141 1142 spin_lock_irqsave(&udc->lock, flags); 1143 /* Make sure it's actually queued on this endpoint */ 1144 list_for_each_entry(req, &ep->queue, queue) { 1145 if (&req->usb_req == _req) 1146 break; 1147 } 1148 if (&req->usb_req != _req) { 1149 spin_unlock_irqrestore(&udc->lock, flags); 1150 return -EINVAL; 1151 } 1152 xudc_done(ep, req, -ECONNRESET); 1153 spin_unlock_irqrestore(&udc->lock, flags); 1154 1155 return 0; 1156 } 1157 1158 /** 1159 * xudc_ep0_enable - Enables the given endpoint. 1160 * @ep: pointer to the usb endpoint structure. 1161 * @desc: pointer to usb endpoint descriptor. 1162 * 1163 * Return: error always. 1164 * 1165 * endpoint 0 enable should not be called by gadget layer. 1166 */ 1167 static int xudc_ep0_enable(struct usb_ep *ep, 1168 const struct usb_endpoint_descriptor *desc) 1169 { 1170 return -EINVAL; 1171 } 1172 1173 /** 1174 * xudc_ep0_disable - Disables the given endpoint. 1175 * @ep: pointer to the usb endpoint structure. 1176 * 1177 * Return: error always. 1178 * 1179 * endpoint 0 disable should not be called by gadget layer. 1180 */ 1181 static int xudc_ep0_disable(struct usb_ep *ep) 1182 { 1183 return -EINVAL; 1184 } 1185 1186 static const struct usb_ep_ops xusb_ep0_ops = { 1187 .enable = xudc_ep0_enable, 1188 .disable = xudc_ep0_disable, 1189 .alloc_request = xudc_ep_alloc_request, 1190 .free_request = xudc_free_request, 1191 .queue = xudc_ep0_queue, 1192 .dequeue = xudc_ep_dequeue, 1193 .set_halt = xudc_ep_set_halt, 1194 }; 1195 1196 static const struct usb_ep_ops xusb_ep_ops = { 1197 .enable = xudc_ep_enable, 1198 .disable = xudc_ep_disable, 1199 .alloc_request = xudc_ep_alloc_request, 1200 .free_request = xudc_free_request, 1201 .queue = xudc_ep_queue, 1202 .dequeue = xudc_ep_dequeue, 1203 .set_halt = xudc_ep_set_halt, 1204 }; 1205 1206 /** 1207 * xudc_get_frame - Reads the current usb frame number. 1208 * @gadget: pointer to the usb gadget structure. 1209 * 1210 * Return: current frame number for success and error value on failure. 1211 */ 1212 static int xudc_get_frame(struct usb_gadget *gadget) 1213 { 1214 struct xusb_udc *udc; 1215 int frame; 1216 1217 if (!gadget) 1218 return -ENODEV; 1219 1220 udc = to_udc(gadget); 1221 frame = udc->read_fn(udc->addr + XUSB_FRAMENUM_OFFSET); 1222 return frame; 1223 } 1224 1225 /** 1226 * xudc_wakeup - Send remote wakeup signal to host 1227 * @gadget: pointer to the usb gadget structure. 1228 * 1229 * Return: 0 on success and error on failure 1230 */ 1231 static int xudc_wakeup(struct usb_gadget *gadget) 1232 { 1233 struct xusb_udc *udc = to_udc(gadget); 1234 u32 crtlreg; 1235 int status = -EINVAL; 1236 unsigned long flags; 1237 1238 spin_lock_irqsave(&udc->lock, flags); 1239 1240 /* Remote wake up not enabled by host */ 1241 if (!udc->remote_wkp) 1242 goto done; 1243 1244 crtlreg = udc->read_fn(udc->addr + XUSB_CONTROL_OFFSET); 1245 crtlreg |= XUSB_CONTROL_USB_RMTWAKE_MASK; 1246 /* set remote wake up bit */ 1247 udc->write_fn(udc->addr, XUSB_CONTROL_OFFSET, crtlreg); 1248 /* 1249 * wait for a while and reset remote wake up bit since this bit 1250 * is not cleared by HW after sending remote wakeup to host. 1251 */ 1252 mdelay(2); 1253 1254 crtlreg &= ~XUSB_CONTROL_USB_RMTWAKE_MASK; 1255 udc->write_fn(udc->addr, XUSB_CONTROL_OFFSET, crtlreg); 1256 status = 0; 1257 done: 1258 spin_unlock_irqrestore(&udc->lock, flags); 1259 return status; 1260 } 1261 1262 /** 1263 * xudc_pullup - start/stop USB traffic 1264 * @gadget: pointer to the usb gadget structure. 1265 * @is_on: flag to start or stop 1266 * 1267 * Return: 0 always 1268 * 1269 * This function starts/stops SIE engine of IP based on is_on. 1270 */ 1271 static int xudc_pullup(struct usb_gadget *gadget, int is_on) 1272 { 1273 struct xusb_udc *udc = to_udc(gadget); 1274 unsigned long flags; 1275 u32 crtlreg; 1276 1277 spin_lock_irqsave(&udc->lock, flags); 1278 1279 crtlreg = udc->read_fn(udc->addr + XUSB_CONTROL_OFFSET); 1280 if (is_on) 1281 crtlreg |= XUSB_CONTROL_USB_READY_MASK; 1282 else 1283 crtlreg &= ~XUSB_CONTROL_USB_READY_MASK; 1284 1285 udc->write_fn(udc->addr, XUSB_CONTROL_OFFSET, crtlreg); 1286 1287 spin_unlock_irqrestore(&udc->lock, flags); 1288 1289 return 0; 1290 } 1291 1292 /** 1293 * xudc_eps_init - initialize endpoints. 1294 * @udc: pointer to the usb device controller structure. 1295 */ 1296 static void xudc_eps_init(struct xusb_udc *udc) 1297 { 1298 u32 ep_number; 1299 1300 INIT_LIST_HEAD(&udc->gadget.ep_list); 1301 1302 for (ep_number = 0; ep_number < XUSB_MAX_ENDPOINTS; ep_number++) { 1303 struct xusb_ep *ep = &udc->ep[ep_number]; 1304 1305 if (ep_number) { 1306 list_add_tail(&ep->ep_usb.ep_list, 1307 &udc->gadget.ep_list); 1308 usb_ep_set_maxpacket_limit(&ep->ep_usb, 1309 (unsigned short) ~0); 1310 snprintf(ep->name, EPNAME_SIZE, "ep%d", ep_number); 1311 ep->ep_usb.name = ep->name; 1312 ep->ep_usb.ops = &xusb_ep_ops; 1313 1314 ep->ep_usb.caps.type_iso = true; 1315 ep->ep_usb.caps.type_bulk = true; 1316 ep->ep_usb.caps.type_int = true; 1317 } else { 1318 ep->ep_usb.name = ep0name; 1319 usb_ep_set_maxpacket_limit(&ep->ep_usb, EP0_MAX_PACKET); 1320 ep->ep_usb.ops = &xusb_ep0_ops; 1321 1322 ep->ep_usb.caps.type_control = true; 1323 } 1324 1325 ep->ep_usb.caps.dir_in = true; 1326 ep->ep_usb.caps.dir_out = true; 1327 1328 ep->udc = udc; 1329 ep->epnumber = ep_number; 1330 ep->desc = NULL; 1331 /* 1332 * The configuration register address offset between 1333 * each endpoint is 0x10. 1334 */ 1335 ep->offset = XUSB_EP0_CONFIG_OFFSET + (ep_number * 0x10); 1336 ep->is_in = 0; 1337 ep->is_iso = 0; 1338 ep->maxpacket = 0; 1339 xudc_epconfig(ep, udc); 1340 1341 /* Initialize one queue per endpoint */ 1342 INIT_LIST_HEAD(&ep->queue); 1343 } 1344 } 1345 1346 /** 1347 * xudc_stop_activity - Stops any further activity on the device. 1348 * @udc: pointer to the usb device controller structure. 1349 */ 1350 static void xudc_stop_activity(struct xusb_udc *udc) 1351 { 1352 int i; 1353 struct xusb_ep *ep; 1354 1355 for (i = 0; i < XUSB_MAX_ENDPOINTS; i++) { 1356 ep = &udc->ep[i]; 1357 xudc_nuke(ep, -ESHUTDOWN); 1358 } 1359 } 1360 1361 /** 1362 * xudc_start - Starts the device. 1363 * @gadget: pointer to the usb gadget structure 1364 * @driver: pointer to gadget driver structure 1365 * 1366 * Return: zero on success and error on failure 1367 */ 1368 static int xudc_start(struct usb_gadget *gadget, 1369 struct usb_gadget_driver *driver) 1370 { 1371 struct xusb_udc *udc = to_udc(gadget); 1372 struct xusb_ep *ep0 = &udc->ep[XUSB_EP_NUMBER_ZERO]; 1373 const struct usb_endpoint_descriptor *desc = &config_bulk_out_desc; 1374 unsigned long flags; 1375 int ret = 0; 1376 1377 spin_lock_irqsave(&udc->lock, flags); 1378 1379 if (udc->driver) { 1380 dev_err(udc->dev, "%s is already bound to %s\n", 1381 udc->gadget.name, udc->driver->driver.name); 1382 ret = -EBUSY; 1383 goto err; 1384 } 1385 1386 /* hook up the driver */ 1387 udc->driver = driver; 1388 udc->gadget.speed = driver->max_speed; 1389 1390 /* Enable the control endpoint. */ 1391 ret = __xudc_ep_enable(ep0, desc); 1392 1393 /* Set device address and remote wakeup to 0 */ 1394 udc->write_fn(udc->addr, XUSB_ADDRESS_OFFSET, 0); 1395 udc->remote_wkp = 0; 1396 err: 1397 spin_unlock_irqrestore(&udc->lock, flags); 1398 return ret; 1399 } 1400 1401 /** 1402 * xudc_stop - stops the device. 1403 * @gadget: pointer to the usb gadget structure 1404 * @driver: pointer to usb gadget driver structure 1405 * 1406 * Return: zero always 1407 */ 1408 static int xudc_stop(struct usb_gadget *gadget) 1409 { 1410 struct xusb_udc *udc = to_udc(gadget); 1411 unsigned long flags; 1412 1413 spin_lock_irqsave(&udc->lock, flags); 1414 1415 udc->gadget.speed = USB_SPEED_UNKNOWN; 1416 udc->driver = NULL; 1417 1418 /* Set device address and remote wakeup to 0 */ 1419 udc->write_fn(udc->addr, XUSB_ADDRESS_OFFSET, 0); 1420 udc->remote_wkp = 0; 1421 1422 xudc_stop_activity(udc); 1423 1424 spin_unlock_irqrestore(&udc->lock, flags); 1425 1426 return 0; 1427 } 1428 1429 static const struct usb_gadget_ops xusb_udc_ops = { 1430 .get_frame = xudc_get_frame, 1431 .wakeup = xudc_wakeup, 1432 .pullup = xudc_pullup, 1433 .udc_start = xudc_start, 1434 .udc_stop = xudc_stop, 1435 }; 1436 1437 /** 1438 * xudc_clear_stall_all_ep - clears stall of every endpoint. 1439 * @udc: pointer to the udc structure. 1440 */ 1441 static void xudc_clear_stall_all_ep(struct xusb_udc *udc) 1442 { 1443 struct xusb_ep *ep; 1444 u32 epcfgreg; 1445 int i; 1446 1447 for (i = 0; i < XUSB_MAX_ENDPOINTS; i++) { 1448 ep = &udc->ep[i]; 1449 epcfgreg = udc->read_fn(udc->addr + ep->offset); 1450 epcfgreg &= ~XUSB_EP_CFG_STALL_MASK; 1451 udc->write_fn(udc->addr, ep->offset, epcfgreg); 1452 if (ep->epnumber) { 1453 /* Reset the toggle bit.*/ 1454 epcfgreg = udc->read_fn(udc->addr + ep->offset); 1455 epcfgreg &= ~XUSB_EP_CFG_DATA_TOGGLE_MASK; 1456 udc->write_fn(udc->addr, ep->offset, epcfgreg); 1457 } 1458 } 1459 } 1460 1461 /** 1462 * xudc_startup_handler - The usb device controller interrupt handler. 1463 * @udc: pointer to the udc structure. 1464 * @intrstatus: The mask value containing the interrupt sources. 1465 * 1466 * This function handles the RESET,SUSPEND,RESUME and DISCONNECT interrupts. 1467 */ 1468 static void xudc_startup_handler(struct xusb_udc *udc, u32 intrstatus) 1469 { 1470 u32 intrreg; 1471 1472 if (intrstatus & XUSB_STATUS_RESET_MASK) { 1473 1474 dev_dbg(udc->dev, "Reset\n"); 1475 1476 if (intrstatus & XUSB_STATUS_HIGH_SPEED_MASK) 1477 udc->gadget.speed = USB_SPEED_HIGH; 1478 else 1479 udc->gadget.speed = USB_SPEED_FULL; 1480 1481 xudc_stop_activity(udc); 1482 xudc_clear_stall_all_ep(udc); 1483 udc->write_fn(udc->addr, XUSB_TESTMODE_OFFSET, 0); 1484 1485 /* Set device address and remote wakeup to 0 */ 1486 udc->write_fn(udc->addr, XUSB_ADDRESS_OFFSET, 0); 1487 udc->remote_wkp = 0; 1488 1489 /* Enable the suspend, resume and disconnect */ 1490 intrreg = udc->read_fn(udc->addr + XUSB_IER_OFFSET); 1491 intrreg |= XUSB_STATUS_SUSPEND_MASK | XUSB_STATUS_RESUME_MASK | 1492 XUSB_STATUS_DISCONNECT_MASK; 1493 udc->write_fn(udc->addr, XUSB_IER_OFFSET, intrreg); 1494 } 1495 if (intrstatus & XUSB_STATUS_SUSPEND_MASK) { 1496 1497 dev_dbg(udc->dev, "Suspend\n"); 1498 1499 /* Enable the reset, resume and disconnect */ 1500 intrreg = udc->read_fn(udc->addr + XUSB_IER_OFFSET); 1501 intrreg |= XUSB_STATUS_RESET_MASK | XUSB_STATUS_RESUME_MASK | 1502 XUSB_STATUS_DISCONNECT_MASK; 1503 udc->write_fn(udc->addr, XUSB_IER_OFFSET, intrreg); 1504 1505 udc->usb_state = USB_STATE_SUSPENDED; 1506 1507 if (udc->driver->suspend) { 1508 spin_unlock(&udc->lock); 1509 udc->driver->suspend(&udc->gadget); 1510 spin_lock(&udc->lock); 1511 } 1512 } 1513 if (intrstatus & XUSB_STATUS_RESUME_MASK) { 1514 bool condition = (udc->usb_state != USB_STATE_SUSPENDED); 1515 1516 dev_WARN_ONCE(udc->dev, condition, 1517 "Resume IRQ while not suspended\n"); 1518 1519 dev_dbg(udc->dev, "Resume\n"); 1520 1521 /* Enable the reset, suspend and disconnect */ 1522 intrreg = udc->read_fn(udc->addr + XUSB_IER_OFFSET); 1523 intrreg |= XUSB_STATUS_RESET_MASK | XUSB_STATUS_SUSPEND_MASK | 1524 XUSB_STATUS_DISCONNECT_MASK; 1525 udc->write_fn(udc->addr, XUSB_IER_OFFSET, intrreg); 1526 1527 udc->usb_state = 0; 1528 1529 if (udc->driver->resume) { 1530 spin_unlock(&udc->lock); 1531 udc->driver->resume(&udc->gadget); 1532 spin_lock(&udc->lock); 1533 } 1534 } 1535 if (intrstatus & XUSB_STATUS_DISCONNECT_MASK) { 1536 1537 dev_dbg(udc->dev, "Disconnect\n"); 1538 1539 /* Enable the reset, resume and suspend */ 1540 intrreg = udc->read_fn(udc->addr + XUSB_IER_OFFSET); 1541 intrreg |= XUSB_STATUS_RESET_MASK | XUSB_STATUS_RESUME_MASK | 1542 XUSB_STATUS_SUSPEND_MASK; 1543 udc->write_fn(udc->addr, XUSB_IER_OFFSET, intrreg); 1544 1545 if (udc->driver && udc->driver->disconnect) { 1546 spin_unlock(&udc->lock); 1547 udc->driver->disconnect(&udc->gadget); 1548 spin_lock(&udc->lock); 1549 } 1550 } 1551 } 1552 1553 /** 1554 * xudc_ep0_stall - Stall endpoint zero. 1555 * @udc: pointer to the udc structure. 1556 * 1557 * This function stalls endpoint zero. 1558 */ 1559 static void xudc_ep0_stall(struct xusb_udc *udc) 1560 { 1561 u32 epcfgreg; 1562 struct xusb_ep *ep0 = &udc->ep[XUSB_EP_NUMBER_ZERO]; 1563 1564 epcfgreg = udc->read_fn(udc->addr + ep0->offset); 1565 epcfgreg |= XUSB_EP_CFG_STALL_MASK; 1566 udc->write_fn(udc->addr, ep0->offset, epcfgreg); 1567 } 1568 1569 /** 1570 * xudc_setaddress - executes SET_ADDRESS command 1571 * @udc: pointer to the udc structure. 1572 * 1573 * This function executes USB SET_ADDRESS command 1574 */ 1575 static void xudc_setaddress(struct xusb_udc *udc) 1576 { 1577 struct xusb_ep *ep0 = &udc->ep[0]; 1578 struct xusb_req *req = udc->req; 1579 int ret; 1580 1581 req->usb_req.length = 0; 1582 ret = __xudc_ep0_queue(ep0, req); 1583 if (ret == 0) 1584 return; 1585 1586 dev_err(udc->dev, "Can't respond to SET ADDRESS request\n"); 1587 xudc_ep0_stall(udc); 1588 } 1589 1590 /** 1591 * xudc_getstatus - executes GET_STATUS command 1592 * @udc: pointer to the udc structure. 1593 * 1594 * This function executes USB GET_STATUS command 1595 */ 1596 static void xudc_getstatus(struct xusb_udc *udc) 1597 { 1598 struct xusb_ep *ep0 = &udc->ep[0]; 1599 struct xusb_req *req = udc->req; 1600 struct xusb_ep *target_ep; 1601 u16 status = 0; 1602 u32 epcfgreg; 1603 int epnum; 1604 u32 halt; 1605 int ret; 1606 1607 switch (udc->setup.bRequestType & USB_RECIP_MASK) { 1608 case USB_RECIP_DEVICE: 1609 /* Get device status */ 1610 status = 1 << USB_DEVICE_SELF_POWERED; 1611 if (udc->remote_wkp) 1612 status |= (1 << USB_DEVICE_REMOTE_WAKEUP); 1613 break; 1614 case USB_RECIP_INTERFACE: 1615 break; 1616 case USB_RECIP_ENDPOINT: 1617 epnum = udc->setup.wIndex & USB_ENDPOINT_NUMBER_MASK; 1618 target_ep = &udc->ep[epnum]; 1619 epcfgreg = udc->read_fn(udc->addr + target_ep->offset); 1620 halt = epcfgreg & XUSB_EP_CFG_STALL_MASK; 1621 if (udc->setup.wIndex & USB_DIR_IN) { 1622 if (!target_ep->is_in) 1623 goto stall; 1624 } else { 1625 if (target_ep->is_in) 1626 goto stall; 1627 } 1628 if (halt) 1629 status = 1 << USB_ENDPOINT_HALT; 1630 break; 1631 default: 1632 goto stall; 1633 } 1634 1635 req->usb_req.length = 2; 1636 *(u16 *)req->usb_req.buf = cpu_to_le16(status); 1637 ret = __xudc_ep0_queue(ep0, req); 1638 if (ret == 0) 1639 return; 1640 stall: 1641 dev_err(udc->dev, "Can't respond to getstatus request\n"); 1642 xudc_ep0_stall(udc); 1643 } 1644 1645 /** 1646 * xudc_set_clear_feature - Executes the set feature and clear feature commands. 1647 * @udc: pointer to the usb device controller structure. 1648 * 1649 * Processes the SET_FEATURE and CLEAR_FEATURE commands. 1650 */ 1651 static void xudc_set_clear_feature(struct xusb_udc *udc) 1652 { 1653 struct xusb_ep *ep0 = &udc->ep[0]; 1654 struct xusb_req *req = udc->req; 1655 struct xusb_ep *target_ep; 1656 u8 endpoint; 1657 u8 outinbit; 1658 u32 epcfgreg; 1659 int flag = (udc->setup.bRequest == USB_REQ_SET_FEATURE ? 1 : 0); 1660 int ret; 1661 1662 switch (udc->setup.bRequestType) { 1663 case USB_RECIP_DEVICE: 1664 switch (udc->setup.wValue) { 1665 case USB_DEVICE_TEST_MODE: 1666 /* 1667 * The Test Mode will be executed 1668 * after the status phase. 1669 */ 1670 break; 1671 case USB_DEVICE_REMOTE_WAKEUP: 1672 if (flag) 1673 udc->remote_wkp = 1; 1674 else 1675 udc->remote_wkp = 0; 1676 break; 1677 default: 1678 xudc_ep0_stall(udc); 1679 break; 1680 } 1681 break; 1682 case USB_RECIP_ENDPOINT: 1683 if (!udc->setup.wValue) { 1684 endpoint = udc->setup.wIndex & USB_ENDPOINT_NUMBER_MASK; 1685 target_ep = &udc->ep[endpoint]; 1686 outinbit = udc->setup.wIndex & USB_ENDPOINT_DIR_MASK; 1687 outinbit = outinbit >> 7; 1688 1689 /* Make sure direction matches.*/ 1690 if (outinbit != target_ep->is_in) { 1691 xudc_ep0_stall(udc); 1692 return; 1693 } 1694 epcfgreg = udc->read_fn(udc->addr + target_ep->offset); 1695 if (!endpoint) { 1696 /* Clear the stall.*/ 1697 epcfgreg &= ~XUSB_EP_CFG_STALL_MASK; 1698 udc->write_fn(udc->addr, 1699 target_ep->offset, epcfgreg); 1700 } else { 1701 if (flag) { 1702 epcfgreg |= XUSB_EP_CFG_STALL_MASK; 1703 udc->write_fn(udc->addr, 1704 target_ep->offset, 1705 epcfgreg); 1706 } else { 1707 /* Unstall the endpoint.*/ 1708 epcfgreg &= ~(XUSB_EP_CFG_STALL_MASK | 1709 XUSB_EP_CFG_DATA_TOGGLE_MASK); 1710 udc->write_fn(udc->addr, 1711 target_ep->offset, 1712 epcfgreg); 1713 } 1714 } 1715 } 1716 break; 1717 default: 1718 xudc_ep0_stall(udc); 1719 return; 1720 } 1721 1722 req->usb_req.length = 0; 1723 ret = __xudc_ep0_queue(ep0, req); 1724 if (ret == 0) 1725 return; 1726 1727 dev_err(udc->dev, "Can't respond to SET/CLEAR FEATURE\n"); 1728 xudc_ep0_stall(udc); 1729 } 1730 1731 /** 1732 * xudc_handle_setup - Processes the setup packet. 1733 * @udc: pointer to the usb device controller structure. 1734 * 1735 * Process setup packet and delegate to gadget layer. 1736 */ 1737 static void xudc_handle_setup(struct xusb_udc *udc) 1738 { 1739 struct xusb_ep *ep0 = &udc->ep[0]; 1740 struct usb_ctrlrequest setup; 1741 u32 *ep0rambase; 1742 1743 /* Load up the chapter 9 command buffer.*/ 1744 ep0rambase = (u32 __force *) (udc->addr + XUSB_SETUP_PKT_ADDR_OFFSET); 1745 memcpy(&setup, ep0rambase, 8); 1746 1747 udc->setup = setup; 1748 udc->setup.wValue = cpu_to_le16(setup.wValue); 1749 udc->setup.wIndex = cpu_to_le16(setup.wIndex); 1750 udc->setup.wLength = cpu_to_le16(setup.wLength); 1751 1752 /* Clear previous requests */ 1753 xudc_nuke(ep0, -ECONNRESET); 1754 1755 if (udc->setup.bRequestType & USB_DIR_IN) { 1756 /* Execute the get command.*/ 1757 udc->setupseqrx = STATUS_PHASE; 1758 udc->setupseqtx = DATA_PHASE; 1759 } else { 1760 /* Execute the put command.*/ 1761 udc->setupseqrx = DATA_PHASE; 1762 udc->setupseqtx = STATUS_PHASE; 1763 } 1764 1765 switch (udc->setup.bRequest) { 1766 case USB_REQ_GET_STATUS: 1767 /* Data+Status phase form udc */ 1768 if ((udc->setup.bRequestType & 1769 (USB_DIR_IN | USB_TYPE_MASK)) != 1770 (USB_DIR_IN | USB_TYPE_STANDARD)) 1771 break; 1772 xudc_getstatus(udc); 1773 return; 1774 case USB_REQ_SET_ADDRESS: 1775 /* Status phase from udc */ 1776 if (udc->setup.bRequestType != (USB_DIR_OUT | 1777 USB_TYPE_STANDARD | USB_RECIP_DEVICE)) 1778 break; 1779 xudc_setaddress(udc); 1780 return; 1781 case USB_REQ_CLEAR_FEATURE: 1782 case USB_REQ_SET_FEATURE: 1783 /* Requests with no data phase, status phase from udc */ 1784 if ((udc->setup.bRequestType & USB_TYPE_MASK) 1785 != USB_TYPE_STANDARD) 1786 break; 1787 xudc_set_clear_feature(udc); 1788 return; 1789 default: 1790 break; 1791 } 1792 1793 spin_unlock(&udc->lock); 1794 if (udc->driver->setup(&udc->gadget, &setup) < 0) 1795 xudc_ep0_stall(udc); 1796 spin_lock(&udc->lock); 1797 } 1798 1799 /** 1800 * xudc_ep0_out - Processes the endpoint 0 OUT token. 1801 * @udc: pointer to the usb device controller structure. 1802 */ 1803 static void xudc_ep0_out(struct xusb_udc *udc) 1804 { 1805 struct xusb_ep *ep0 = &udc->ep[0]; 1806 struct xusb_req *req; 1807 u8 *ep0rambase; 1808 unsigned int bytes_to_rx; 1809 void *buffer; 1810 1811 req = list_first_entry(&ep0->queue, struct xusb_req, queue); 1812 1813 switch (udc->setupseqrx) { 1814 case STATUS_PHASE: 1815 /* 1816 * This resets both state machines for the next 1817 * Setup packet. 1818 */ 1819 udc->setupseqrx = SETUP_PHASE; 1820 udc->setupseqtx = SETUP_PHASE; 1821 req->usb_req.actual = req->usb_req.length; 1822 xudc_done(ep0, req, 0); 1823 break; 1824 case DATA_PHASE: 1825 bytes_to_rx = udc->read_fn(udc->addr + 1826 XUSB_EP_BUF0COUNT_OFFSET); 1827 /* Copy the data to be received from the DPRAM. */ 1828 ep0rambase = (u8 __force *) (udc->addr + 1829 (ep0->rambase << 2)); 1830 buffer = req->usb_req.buf + req->usb_req.actual; 1831 req->usb_req.actual = req->usb_req.actual + bytes_to_rx; 1832 memcpy(buffer, ep0rambase, bytes_to_rx); 1833 1834 if (req->usb_req.length == req->usb_req.actual) { 1835 /* Data transfer completed get ready for Status stage */ 1836 xudc_wrstatus(udc); 1837 } else { 1838 /* Enable EP0 buffer to receive data */ 1839 udc->write_fn(udc->addr, XUSB_EP_BUF0COUNT_OFFSET, 0); 1840 udc->write_fn(udc->addr, XUSB_BUFFREADY_OFFSET, 1); 1841 } 1842 break; 1843 default: 1844 break; 1845 } 1846 } 1847 1848 /** 1849 * xudc_ep0_in - Processes the endpoint 0 IN token. 1850 * @udc: pointer to the usb device controller structure. 1851 */ 1852 static void xudc_ep0_in(struct xusb_udc *udc) 1853 { 1854 struct xusb_ep *ep0 = &udc->ep[0]; 1855 struct xusb_req *req; 1856 unsigned int bytes_to_tx; 1857 void *buffer; 1858 u32 epcfgreg; 1859 u16 count = 0; 1860 u16 length; 1861 u8 *ep0rambase; 1862 u8 test_mode = udc->setup.wIndex >> 8; 1863 1864 req = list_first_entry(&ep0->queue, struct xusb_req, queue); 1865 bytes_to_tx = req->usb_req.length - req->usb_req.actual; 1866 1867 switch (udc->setupseqtx) { 1868 case STATUS_PHASE: 1869 switch (udc->setup.bRequest) { 1870 case USB_REQ_SET_ADDRESS: 1871 /* Set the address of the device.*/ 1872 udc->write_fn(udc->addr, XUSB_ADDRESS_OFFSET, 1873 udc->setup.wValue); 1874 break; 1875 case USB_REQ_SET_FEATURE: 1876 if (udc->setup.bRequestType == 1877 USB_RECIP_DEVICE) { 1878 if (udc->setup.wValue == 1879 USB_DEVICE_TEST_MODE) 1880 udc->write_fn(udc->addr, 1881 XUSB_TESTMODE_OFFSET, 1882 test_mode); 1883 } 1884 break; 1885 } 1886 req->usb_req.actual = req->usb_req.length; 1887 xudc_done(ep0, req, 0); 1888 break; 1889 case DATA_PHASE: 1890 if (!bytes_to_tx) { 1891 /* 1892 * We're done with data transfer, next 1893 * will be zero length OUT with data toggle of 1894 * 1. Setup data_toggle. 1895 */ 1896 epcfgreg = udc->read_fn(udc->addr + ep0->offset); 1897 epcfgreg |= XUSB_EP_CFG_DATA_TOGGLE_MASK; 1898 udc->write_fn(udc->addr, ep0->offset, epcfgreg); 1899 udc->setupseqtx = STATUS_PHASE; 1900 } else { 1901 length = count = min_t(u32, bytes_to_tx, 1902 EP0_MAX_PACKET); 1903 /* Copy the data to be transmitted into the DPRAM. */ 1904 ep0rambase = (u8 __force *) (udc->addr + 1905 (ep0->rambase << 2)); 1906 buffer = req->usb_req.buf + req->usb_req.actual; 1907 req->usb_req.actual = req->usb_req.actual + length; 1908 memcpy(ep0rambase, buffer, length); 1909 } 1910 udc->write_fn(udc->addr, XUSB_EP_BUF0COUNT_OFFSET, count); 1911 udc->write_fn(udc->addr, XUSB_BUFFREADY_OFFSET, 1); 1912 break; 1913 default: 1914 break; 1915 } 1916 } 1917 1918 /** 1919 * xudc_ctrl_ep_handler - Endpoint 0 interrupt handler. 1920 * @udc: pointer to the udc structure. 1921 * @intrstatus: It's the mask value for the interrupt sources on endpoint 0. 1922 * 1923 * Processes the commands received during enumeration phase. 1924 */ 1925 static void xudc_ctrl_ep_handler(struct xusb_udc *udc, u32 intrstatus) 1926 { 1927 1928 if (intrstatus & XUSB_STATUS_SETUP_PACKET_MASK) { 1929 xudc_handle_setup(udc); 1930 } else { 1931 if (intrstatus & XUSB_STATUS_FIFO_BUFF_RDY_MASK) 1932 xudc_ep0_out(udc); 1933 else if (intrstatus & XUSB_STATUS_FIFO_BUFF_FREE_MASK) 1934 xudc_ep0_in(udc); 1935 } 1936 } 1937 1938 /** 1939 * xudc_nonctrl_ep_handler - Non control endpoint interrupt handler. 1940 * @udc: pointer to the udc structure. 1941 * @epnum: End point number for which the interrupt is to be processed 1942 * @intrstatus: mask value for interrupt sources of endpoints other 1943 * than endpoint 0. 1944 * 1945 * Processes the buffer completion interrupts. 1946 */ 1947 static void xudc_nonctrl_ep_handler(struct xusb_udc *udc, u8 epnum, 1948 u32 intrstatus) 1949 { 1950 1951 struct xusb_req *req; 1952 struct xusb_ep *ep; 1953 1954 ep = &udc->ep[epnum]; 1955 /* Process the End point interrupts.*/ 1956 if (intrstatus & (XUSB_STATUS_EP0_BUFF1_COMP_MASK << epnum)) 1957 ep->buffer0ready = 0; 1958 if (intrstatus & (XUSB_STATUS_EP0_BUFF2_COMP_MASK << epnum)) 1959 ep->buffer1ready = 0; 1960 1961 if (list_empty(&ep->queue)) 1962 return; 1963 1964 req = list_first_entry(&ep->queue, struct xusb_req, queue); 1965 1966 if (ep->is_in) 1967 xudc_write_fifo(ep, req); 1968 else 1969 xudc_read_fifo(ep, req); 1970 } 1971 1972 /** 1973 * xudc_irq - The main interrupt handler. 1974 * @irq: The interrupt number. 1975 * @_udc: pointer to the usb device controller structure. 1976 * 1977 * Return: IRQ_HANDLED after the interrupt is handled. 1978 */ 1979 static irqreturn_t xudc_irq(int irq, void *_udc) 1980 { 1981 struct xusb_udc *udc = _udc; 1982 u32 intrstatus; 1983 u32 ier; 1984 u8 index; 1985 u32 bufintr; 1986 unsigned long flags; 1987 1988 spin_lock_irqsave(&udc->lock, flags); 1989 1990 /* 1991 * Event interrupts are level sensitive hence first disable 1992 * IER, read ISR and figure out active interrupts. 1993 */ 1994 ier = udc->read_fn(udc->addr + XUSB_IER_OFFSET); 1995 ier &= ~XUSB_STATUS_INTR_EVENT_MASK; 1996 udc->write_fn(udc->addr, XUSB_IER_OFFSET, ier); 1997 1998 /* Read the Interrupt Status Register.*/ 1999 intrstatus = udc->read_fn(udc->addr + XUSB_STATUS_OFFSET); 2000 2001 /* Call the handler for the event interrupt.*/ 2002 if (intrstatus & XUSB_STATUS_INTR_EVENT_MASK) { 2003 /* 2004 * Check if there is any action to be done for : 2005 * - USB Reset received {XUSB_STATUS_RESET_MASK} 2006 * - USB Suspend received {XUSB_STATUS_SUSPEND_MASK} 2007 * - USB Resume received {XUSB_STATUS_RESUME_MASK} 2008 * - USB Disconnect received {XUSB_STATUS_DISCONNECT_MASK} 2009 */ 2010 xudc_startup_handler(udc, intrstatus); 2011 } 2012 2013 /* Check the buffer completion interrupts */ 2014 if (intrstatus & XUSB_STATUS_INTR_BUFF_COMP_ALL_MASK) { 2015 /* Enable Reset, Suspend, Resume and Disconnect */ 2016 ier = udc->read_fn(udc->addr + XUSB_IER_OFFSET); 2017 ier |= XUSB_STATUS_INTR_EVENT_MASK; 2018 udc->write_fn(udc->addr, XUSB_IER_OFFSET, ier); 2019 2020 if (intrstatus & XUSB_STATUS_EP0_BUFF1_COMP_MASK) 2021 xudc_ctrl_ep_handler(udc, intrstatus); 2022 2023 for (index = 1; index < 8; index++) { 2024 bufintr = ((intrstatus & 2025 (XUSB_STATUS_EP1_BUFF1_COMP_MASK << 2026 (index - 1))) || (intrstatus & 2027 (XUSB_STATUS_EP1_BUFF2_COMP_MASK << 2028 (index - 1)))); 2029 if (bufintr) { 2030 xudc_nonctrl_ep_handler(udc, index, 2031 intrstatus); 2032 } 2033 } 2034 } 2035 2036 spin_unlock_irqrestore(&udc->lock, flags); 2037 return IRQ_HANDLED; 2038 } 2039 2040 /** 2041 * xudc_probe - The device probe function for driver initialization. 2042 * @pdev: pointer to the platform device structure. 2043 * 2044 * Return: 0 for success and error value on failure 2045 */ 2046 static int xudc_probe(struct platform_device *pdev) 2047 { 2048 struct device_node *np = pdev->dev.of_node; 2049 struct resource *res; 2050 struct xusb_udc *udc; 2051 int irq; 2052 int ret; 2053 u32 ier; 2054 u8 *buff; 2055 2056 udc = devm_kzalloc(&pdev->dev, sizeof(*udc), GFP_KERNEL); 2057 if (!udc) 2058 return -ENOMEM; 2059 2060 /* Create a dummy request for GET_STATUS, SET_ADDRESS */ 2061 udc->req = devm_kzalloc(&pdev->dev, sizeof(struct xusb_req), 2062 GFP_KERNEL); 2063 if (!udc->req) 2064 return -ENOMEM; 2065 2066 buff = devm_kzalloc(&pdev->dev, STATUSBUFF_SIZE, GFP_KERNEL); 2067 if (!buff) 2068 return -ENOMEM; 2069 2070 udc->req->usb_req.buf = buff; 2071 2072 /* Map the registers */ 2073 res = platform_get_resource(pdev, IORESOURCE_MEM, 0); 2074 udc->addr = devm_ioremap_resource(&pdev->dev, res); 2075 if (IS_ERR(udc->addr)) 2076 return PTR_ERR(udc->addr); 2077 2078 irq = platform_get_irq(pdev, 0); 2079 if (irq < 0) { 2080 dev_err(&pdev->dev, "unable to get irq\n"); 2081 return irq; 2082 } 2083 ret = devm_request_irq(&pdev->dev, irq, xudc_irq, 0, 2084 dev_name(&pdev->dev), udc); 2085 if (ret < 0) { 2086 dev_dbg(&pdev->dev, "unable to request irq %d", irq); 2087 goto fail; 2088 } 2089 2090 udc->dma_enabled = of_property_read_bool(np, "xlnx,has-builtin-dma"); 2091 2092 /* Setup gadget structure */ 2093 udc->gadget.ops = &xusb_udc_ops; 2094 udc->gadget.max_speed = USB_SPEED_HIGH; 2095 udc->gadget.speed = USB_SPEED_UNKNOWN; 2096 udc->gadget.ep0 = &udc->ep[XUSB_EP_NUMBER_ZERO].ep_usb; 2097 udc->gadget.name = driver_name; 2098 2099 spin_lock_init(&udc->lock); 2100 2101 /* Check for IP endianness */ 2102 udc->write_fn = xudc_write32_be; 2103 udc->read_fn = xudc_read32_be; 2104 udc->write_fn(udc->addr, XUSB_TESTMODE_OFFSET, TEST_J); 2105 if ((udc->read_fn(udc->addr + XUSB_TESTMODE_OFFSET)) 2106 != TEST_J) { 2107 udc->write_fn = xudc_write32; 2108 udc->read_fn = xudc_read32; 2109 } 2110 udc->write_fn(udc->addr, XUSB_TESTMODE_OFFSET, 0); 2111 2112 xudc_eps_init(udc); 2113 2114 /* Set device address to 0.*/ 2115 udc->write_fn(udc->addr, XUSB_ADDRESS_OFFSET, 0); 2116 2117 ret = usb_add_gadget_udc(&pdev->dev, &udc->gadget); 2118 if (ret) 2119 goto fail; 2120 2121 udc->dev = &udc->gadget.dev; 2122 2123 /* Enable the interrupts.*/ 2124 ier = XUSB_STATUS_GLOBAL_INTR_MASK | XUSB_STATUS_INTR_EVENT_MASK | 2125 XUSB_STATUS_FIFO_BUFF_RDY_MASK | XUSB_STATUS_FIFO_BUFF_FREE_MASK | 2126 XUSB_STATUS_SETUP_PACKET_MASK | 2127 XUSB_STATUS_INTR_BUFF_COMP_ALL_MASK; 2128 2129 udc->write_fn(udc->addr, XUSB_IER_OFFSET, ier); 2130 2131 platform_set_drvdata(pdev, udc); 2132 2133 dev_vdbg(&pdev->dev, "%s at 0x%08X mapped to %p %s\n", 2134 driver_name, (u32)res->start, udc->addr, 2135 udc->dma_enabled ? "with DMA" : "without DMA"); 2136 2137 return 0; 2138 fail: 2139 dev_err(&pdev->dev, "probe failed, %d\n", ret); 2140 return ret; 2141 } 2142 2143 /** 2144 * xudc_remove - Releases the resources allocated during the initialization. 2145 * @pdev: pointer to the platform device structure. 2146 * 2147 * Return: 0 always 2148 */ 2149 static int xudc_remove(struct platform_device *pdev) 2150 { 2151 struct xusb_udc *udc = platform_get_drvdata(pdev); 2152 2153 usb_del_gadget_udc(&udc->gadget); 2154 2155 return 0; 2156 } 2157 2158 /* Match table for of_platform binding */ 2159 static const struct of_device_id usb_of_match[] = { 2160 { .compatible = "xlnx,usb2-device-4.00.a", }, 2161 { /* end of list */ }, 2162 }; 2163 MODULE_DEVICE_TABLE(of, usb_of_match); 2164 2165 static struct platform_driver xudc_driver = { 2166 .driver = { 2167 .name = driver_name, 2168 .of_match_table = usb_of_match, 2169 }, 2170 .probe = xudc_probe, 2171 .remove = xudc_remove, 2172 }; 2173 2174 module_platform_driver(xudc_driver); 2175 2176 MODULE_DESCRIPTION("Xilinx udc driver"); 2177 MODULE_AUTHOR("Xilinx, Inc"); 2178 MODULE_LICENSE("GPL"); 2179