1 // SPDX-License-Identifier: GPL-2.0+ 2 /* 3 * Xilinx USB peripheral controller driver 4 * 5 * Copyright (C) 2004 by Thomas Rathbone 6 * Copyright (C) 2005 by HP Labs 7 * Copyright (C) 2005 by David Brownell 8 * Copyright (C) 2010 - 2014 Xilinx, Inc. 9 * 10 * Some parts of this driver code is based on the driver for at91-series 11 * USB peripheral controller (at91_udc.c). 12 */ 13 14 #include <linux/clk.h> 15 #include <linux/delay.h> 16 #include <linux/device.h> 17 #include <linux/dma-mapping.h> 18 #include <linux/interrupt.h> 19 #include <linux/io.h> 20 #include <linux/module.h> 21 #include <linux/of.h> 22 #include <linux/platform_device.h> 23 #include <linux/prefetch.h> 24 #include <linux/usb/ch9.h> 25 #include <linux/usb/gadget.h> 26 27 /* Register offsets for the USB device.*/ 28 #define XUSB_EP0_CONFIG_OFFSET 0x0000 /* EP0 Config Reg Offset */ 29 #define XUSB_SETUP_PKT_ADDR_OFFSET 0x0080 /* Setup Packet Address */ 30 #define XUSB_ADDRESS_OFFSET 0x0100 /* Address Register */ 31 #define XUSB_CONTROL_OFFSET 0x0104 /* Control Register */ 32 #define XUSB_STATUS_OFFSET 0x0108 /* Status Register */ 33 #define XUSB_FRAMENUM_OFFSET 0x010C /* Frame Number Register */ 34 #define XUSB_IER_OFFSET 0x0110 /* Interrupt Enable Register */ 35 #define XUSB_BUFFREADY_OFFSET 0x0114 /* Buffer Ready Register */ 36 #define XUSB_TESTMODE_OFFSET 0x0118 /* Test Mode Register */ 37 #define XUSB_DMA_RESET_OFFSET 0x0200 /* DMA Soft Reset Register */ 38 #define XUSB_DMA_CONTROL_OFFSET 0x0204 /* DMA Control Register */ 39 #define XUSB_DMA_DSAR_ADDR_OFFSET 0x0208 /* DMA source Address Reg */ 40 #define XUSB_DMA_DDAR_ADDR_OFFSET 0x020C /* DMA destination Addr Reg */ 41 #define XUSB_DMA_LENGTH_OFFSET 0x0210 /* DMA Length Register */ 42 #define XUSB_DMA_STATUS_OFFSET 0x0214 /* DMA Status Register */ 43 44 /* Endpoint Configuration Space offsets */ 45 #define XUSB_EP_CFGSTATUS_OFFSET 0x00 /* Endpoint Config Status */ 46 #define XUSB_EP_BUF0COUNT_OFFSET 0x08 /* Buffer 0 Count */ 47 #define XUSB_EP_BUF1COUNT_OFFSET 0x0C /* Buffer 1 Count */ 48 49 #define XUSB_CONTROL_USB_READY_MASK 0x80000000 /* USB ready Mask */ 50 #define XUSB_CONTROL_USB_RMTWAKE_MASK 0x40000000 /* Remote wake up mask */ 51 52 /* Interrupt register related masks.*/ 53 #define XUSB_STATUS_GLOBAL_INTR_MASK 0x80000000 /* Global Intr Enable */ 54 #define XUSB_STATUS_DMADONE_MASK 0x04000000 /* DMA done Mask */ 55 #define XUSB_STATUS_DMAERR_MASK 0x02000000 /* DMA Error Mask */ 56 #define XUSB_STATUS_DMABUSY_MASK 0x80000000 /* DMA Error Mask */ 57 #define XUSB_STATUS_RESUME_MASK 0x01000000 /* USB Resume Mask */ 58 #define XUSB_STATUS_RESET_MASK 0x00800000 /* USB Reset Mask */ 59 #define XUSB_STATUS_SUSPEND_MASK 0x00400000 /* USB Suspend Mask */ 60 #define XUSB_STATUS_DISCONNECT_MASK 0x00200000 /* USB Disconnect Mask */ 61 #define XUSB_STATUS_FIFO_BUFF_RDY_MASK 0x00100000 /* FIFO Buff Ready Mask */ 62 #define XUSB_STATUS_FIFO_BUFF_FREE_MASK 0x00080000 /* FIFO Buff Free Mask */ 63 #define XUSB_STATUS_SETUP_PACKET_MASK 0x00040000 /* Setup packet received */ 64 #define XUSB_STATUS_EP1_BUFF2_COMP_MASK 0x00000200 /* EP 1 Buff 2 Processed */ 65 #define XUSB_STATUS_EP1_BUFF1_COMP_MASK 0x00000002 /* EP 1 Buff 1 Processed */ 66 #define XUSB_STATUS_EP0_BUFF2_COMP_MASK 0x00000100 /* EP 0 Buff 2 Processed */ 67 #define XUSB_STATUS_EP0_BUFF1_COMP_MASK 0x00000001 /* EP 0 Buff 1 Processed */ 68 #define XUSB_STATUS_HIGH_SPEED_MASK 0x00010000 /* USB Speed Mask */ 69 /* Suspend,Reset,Suspend and Disconnect Mask */ 70 #define XUSB_STATUS_INTR_EVENT_MASK 0x01E00000 71 /* Buffers completion Mask */ 72 #define XUSB_STATUS_INTR_BUFF_COMP_ALL_MASK 0x0000FEFF 73 /* Mask for buffer 0 and buffer 1 completion for all Endpoints */ 74 #define XUSB_STATUS_INTR_BUFF_COMP_SHIFT_MASK 0x00000101 75 #define XUSB_STATUS_EP_BUFF2_SHIFT 8 /* EP buffer offset */ 76 77 /* Endpoint Configuration Status Register */ 78 #define XUSB_EP_CFG_VALID_MASK 0x80000000 /* Endpoint Valid bit */ 79 #define XUSB_EP_CFG_STALL_MASK 0x40000000 /* Endpoint Stall bit */ 80 #define XUSB_EP_CFG_DATA_TOGGLE_MASK 0x08000000 /* Endpoint Data toggle */ 81 82 /* USB device specific global configuration constants.*/ 83 #define XUSB_MAX_ENDPOINTS 8 /* Maximum End Points */ 84 #define XUSB_EP_NUMBER_ZERO 0 /* End point Zero */ 85 /* DPRAM is the source address for DMA transfer */ 86 #define XUSB_DMA_READ_FROM_DPRAM 0x80000000 87 #define XUSB_DMA_DMASR_BUSY 0x80000000 /* DMA busy */ 88 #define XUSB_DMA_DMASR_ERROR 0x40000000 /* DMA Error */ 89 /* 90 * When this bit is set, the DMA buffer ready bit is set by hardware upon 91 * DMA transfer completion. 92 */ 93 #define XUSB_DMA_BRR_CTRL 0x40000000 /* DMA bufready ctrl bit */ 94 /* Phase States */ 95 #define SETUP_PHASE 0x0000 /* Setup Phase */ 96 #define DATA_PHASE 0x0001 /* Data Phase */ 97 #define STATUS_PHASE 0x0002 /* Status Phase */ 98 99 #define EP0_MAX_PACKET 64 /* Endpoint 0 maximum packet length */ 100 #define STATUSBUFF_SIZE 2 /* Buffer size for GET_STATUS command */ 101 #define EPNAME_SIZE 4 /* Buffer size for endpoint name */ 102 103 /* container_of helper macros */ 104 #define to_udc(g) container_of((g), struct xusb_udc, gadget) 105 #define to_xusb_ep(ep) container_of((ep), struct xusb_ep, ep_usb) 106 #define to_xusb_req(req) container_of((req), struct xusb_req, usb_req) 107 108 /** 109 * struct xusb_req - Xilinx USB device request structure 110 * @usb_req: Linux usb request structure 111 * @queue: usb device request queue 112 * @ep: pointer to xusb_endpoint structure 113 */ 114 struct xusb_req { 115 struct usb_request usb_req; 116 struct list_head queue; 117 struct xusb_ep *ep; 118 }; 119 120 /** 121 * struct xusb_ep - USB end point structure. 122 * @ep_usb: usb endpoint instance 123 * @queue: endpoint message queue 124 * @udc: xilinx usb peripheral driver instance pointer 125 * @desc: pointer to the usb endpoint descriptor 126 * @rambase: the endpoint buffer address 127 * @offset: the endpoint register offset value 128 * @name: name of the endpoint 129 * @epnumber: endpoint number 130 * @maxpacket: maximum packet size the endpoint can store 131 * @buffer0count: the size of the packet recieved in the first buffer 132 * @buffer1count: the size of the packet received in the second buffer 133 * @curbufnum: current buffer of endpoint that will be processed next 134 * @buffer0ready: the busy state of first buffer 135 * @buffer1ready: the busy state of second buffer 136 * @is_in: endpoint direction (IN or OUT) 137 * @is_iso: endpoint type(isochronous or non isochronous) 138 */ 139 struct xusb_ep { 140 struct usb_ep ep_usb; 141 struct list_head queue; 142 struct xusb_udc *udc; 143 const struct usb_endpoint_descriptor *desc; 144 u32 rambase; 145 u32 offset; 146 char name[4]; 147 u16 epnumber; 148 u16 maxpacket; 149 u16 buffer0count; 150 u16 buffer1count; 151 u8 curbufnum; 152 bool buffer0ready; 153 bool buffer1ready; 154 bool is_in; 155 bool is_iso; 156 }; 157 158 /** 159 * struct xusb_udc - USB peripheral driver structure 160 * @gadget: USB gadget driver instance 161 * @ep: an array of endpoint structures 162 * @driver: pointer to the usb gadget driver instance 163 * @setup: usb_ctrlrequest structure for control requests 164 * @req: pointer to dummy request for get status command 165 * @dev: pointer to device structure in gadget 166 * @usb_state: device in suspended state or not 167 * @remote_wkp: remote wakeup enabled by host 168 * @setupseqtx: tx status 169 * @setupseqrx: rx status 170 * @addr: the usb device base address 171 * @lock: instance of spinlock 172 * @dma_enabled: flag indicating whether the dma is included in the system 173 * @clk: pointer to struct clk 174 * @read_fn: function pointer to read device registers 175 * @write_fn: function pointer to write to device registers 176 */ 177 struct xusb_udc { 178 struct usb_gadget gadget; 179 struct xusb_ep ep[8]; 180 struct usb_gadget_driver *driver; 181 struct usb_ctrlrequest setup; 182 struct xusb_req *req; 183 struct device *dev; 184 u32 usb_state; 185 u32 remote_wkp; 186 u32 setupseqtx; 187 u32 setupseqrx; 188 void __iomem *addr; 189 spinlock_t lock; 190 bool dma_enabled; 191 struct clk *clk; 192 193 unsigned int (*read_fn)(void __iomem *reg); 194 void (*write_fn)(void __iomem *, u32, u32); 195 }; 196 197 /* Endpoint buffer start addresses in the core */ 198 static u32 rambase[8] = { 0x22, 0x1000, 0x1100, 0x1200, 0x1300, 0x1400, 0x1500, 199 0x1600 }; 200 201 static const char driver_name[] = "xilinx-udc"; 202 static const char ep0name[] = "ep0"; 203 204 /* Control endpoint configuration.*/ 205 static const struct usb_endpoint_descriptor config_bulk_out_desc = { 206 .bLength = USB_DT_ENDPOINT_SIZE, 207 .bDescriptorType = USB_DT_ENDPOINT, 208 .bEndpointAddress = USB_DIR_OUT, 209 .bmAttributes = USB_ENDPOINT_XFER_BULK, 210 .wMaxPacketSize = cpu_to_le16(EP0_MAX_PACKET), 211 }; 212 213 /** 214 * xudc_write32 - little endian write to device registers 215 * @addr: base addr of device registers 216 * @offset: register offset 217 * @val: data to be written 218 */ 219 static void xudc_write32(void __iomem *addr, u32 offset, u32 val) 220 { 221 iowrite32(val, addr + offset); 222 } 223 224 /** 225 * xudc_read32 - little endian read from device registers 226 * @addr: addr of device register 227 * Return: value at addr 228 */ 229 static unsigned int xudc_read32(void __iomem *addr) 230 { 231 return ioread32(addr); 232 } 233 234 /** 235 * xudc_write32_be - big endian write to device registers 236 * @addr: base addr of device registers 237 * @offset: register offset 238 * @val: data to be written 239 */ 240 static void xudc_write32_be(void __iomem *addr, u32 offset, u32 val) 241 { 242 iowrite32be(val, addr + offset); 243 } 244 245 /** 246 * xudc_read32_be - big endian read from device registers 247 * @addr: addr of device register 248 * Return: value at addr 249 */ 250 static unsigned int xudc_read32_be(void __iomem *addr) 251 { 252 return ioread32be(addr); 253 } 254 255 /** 256 * xudc_wrstatus - Sets up the usb device status stages. 257 * @udc: pointer to the usb device controller structure. 258 */ 259 static void xudc_wrstatus(struct xusb_udc *udc) 260 { 261 struct xusb_ep *ep0 = &udc->ep[XUSB_EP_NUMBER_ZERO]; 262 u32 epcfgreg; 263 264 epcfgreg = udc->read_fn(udc->addr + ep0->offset)| 265 XUSB_EP_CFG_DATA_TOGGLE_MASK; 266 udc->write_fn(udc->addr, ep0->offset, epcfgreg); 267 udc->write_fn(udc->addr, ep0->offset + XUSB_EP_BUF0COUNT_OFFSET, 0); 268 udc->write_fn(udc->addr, XUSB_BUFFREADY_OFFSET, 1); 269 } 270 271 /** 272 * xudc_epconfig - Configures the given endpoint. 273 * @ep: pointer to the usb device endpoint structure. 274 * @udc: pointer to the usb peripheral controller structure. 275 * 276 * This function configures a specific endpoint with the given configuration 277 * data. 278 */ 279 static void xudc_epconfig(struct xusb_ep *ep, struct xusb_udc *udc) 280 { 281 u32 epcfgreg; 282 283 /* 284 * Configure the end point direction, type, Max Packet Size and the 285 * EP buffer location. 286 */ 287 epcfgreg = ((ep->is_in << 29) | (ep->is_iso << 28) | 288 (ep->ep_usb.maxpacket << 15) | (ep->rambase)); 289 udc->write_fn(udc->addr, ep->offset, epcfgreg); 290 291 /* Set the Buffer count and the Buffer ready bits.*/ 292 udc->write_fn(udc->addr, ep->offset + XUSB_EP_BUF0COUNT_OFFSET, 293 ep->buffer0count); 294 udc->write_fn(udc->addr, ep->offset + XUSB_EP_BUF1COUNT_OFFSET, 295 ep->buffer1count); 296 if (ep->buffer0ready) 297 udc->write_fn(udc->addr, XUSB_BUFFREADY_OFFSET, 298 1 << ep->epnumber); 299 if (ep->buffer1ready) 300 udc->write_fn(udc->addr, XUSB_BUFFREADY_OFFSET, 301 1 << (ep->epnumber + XUSB_STATUS_EP_BUFF2_SHIFT)); 302 } 303 304 /** 305 * xudc_start_dma - Starts DMA transfer. 306 * @ep: pointer to the usb device endpoint structure. 307 * @src: DMA source address. 308 * @dst: DMA destination address. 309 * @length: number of bytes to transfer. 310 * 311 * Return: 0 on success, error code on failure 312 * 313 * This function starts DMA transfer by writing to DMA source, 314 * destination and lenth registers. 315 */ 316 static int xudc_start_dma(struct xusb_ep *ep, dma_addr_t src, 317 dma_addr_t dst, u32 length) 318 { 319 struct xusb_udc *udc = ep->udc; 320 int rc = 0; 321 u32 timeout = 500; 322 u32 reg; 323 324 /* 325 * Set the addresses in the DMA source and 326 * destination registers and then set the length 327 * into the DMA length register. 328 */ 329 udc->write_fn(udc->addr, XUSB_DMA_DSAR_ADDR_OFFSET, src); 330 udc->write_fn(udc->addr, XUSB_DMA_DDAR_ADDR_OFFSET, dst); 331 udc->write_fn(udc->addr, XUSB_DMA_LENGTH_OFFSET, length); 332 333 /* 334 * Wait till DMA transaction is complete and 335 * check whether the DMA transaction was 336 * successful. 337 */ 338 do { 339 reg = udc->read_fn(udc->addr + XUSB_DMA_STATUS_OFFSET); 340 if (!(reg & XUSB_DMA_DMASR_BUSY)) 341 break; 342 343 /* 344 * We can't sleep here, because it's also called from 345 * interrupt context. 346 */ 347 timeout--; 348 if (!timeout) { 349 dev_err(udc->dev, "DMA timeout\n"); 350 return -ETIMEDOUT; 351 } 352 udelay(1); 353 } while (1); 354 355 if ((udc->read_fn(udc->addr + XUSB_DMA_STATUS_OFFSET) & 356 XUSB_DMA_DMASR_ERROR) == XUSB_DMA_DMASR_ERROR){ 357 dev_err(udc->dev, "DMA Error\n"); 358 rc = -EINVAL; 359 } 360 361 return rc; 362 } 363 364 /** 365 * xudc_dma_send - Sends IN data using DMA. 366 * @ep: pointer to the usb device endpoint structure. 367 * @req: pointer to the usb request structure. 368 * @buffer: pointer to data to be sent. 369 * @length: number of bytes to send. 370 * 371 * Return: 0 on success, -EAGAIN if no buffer is free and error 372 * code on failure. 373 * 374 * This function sends data using DMA. 375 */ 376 static int xudc_dma_send(struct xusb_ep *ep, struct xusb_req *req, 377 u8 *buffer, u32 length) 378 { 379 u32 *eprambase; 380 dma_addr_t src; 381 dma_addr_t dst; 382 struct xusb_udc *udc = ep->udc; 383 384 src = req->usb_req.dma + req->usb_req.actual; 385 if (req->usb_req.length) 386 dma_sync_single_for_device(udc->dev, src, 387 length, DMA_TO_DEVICE); 388 if (!ep->curbufnum && !ep->buffer0ready) { 389 /* Get the Buffer address and copy the transmit data.*/ 390 eprambase = (u32 __force *)(udc->addr + ep->rambase); 391 dst = virt_to_phys(eprambase); 392 udc->write_fn(udc->addr, ep->offset + 393 XUSB_EP_BUF0COUNT_OFFSET, length); 394 udc->write_fn(udc->addr, XUSB_DMA_CONTROL_OFFSET, 395 XUSB_DMA_BRR_CTRL | (1 << ep->epnumber)); 396 ep->buffer0ready = 1; 397 ep->curbufnum = 1; 398 } else if (ep->curbufnum && !ep->buffer1ready) { 399 /* Get the Buffer address and copy the transmit data.*/ 400 eprambase = (u32 __force *)(udc->addr + ep->rambase + 401 ep->ep_usb.maxpacket); 402 dst = virt_to_phys(eprambase); 403 udc->write_fn(udc->addr, ep->offset + 404 XUSB_EP_BUF1COUNT_OFFSET, length); 405 udc->write_fn(udc->addr, XUSB_DMA_CONTROL_OFFSET, 406 XUSB_DMA_BRR_CTRL | (1 << (ep->epnumber + 407 XUSB_STATUS_EP_BUFF2_SHIFT))); 408 ep->buffer1ready = 1; 409 ep->curbufnum = 0; 410 } else { 411 /* None of ping pong buffers are ready currently .*/ 412 return -EAGAIN; 413 } 414 415 return xudc_start_dma(ep, src, dst, length); 416 } 417 418 /** 419 * xudc_dma_receive - Receives OUT data using DMA. 420 * @ep: pointer to the usb device endpoint structure. 421 * @req: pointer to the usb request structure. 422 * @buffer: pointer to storage buffer of received data. 423 * @length: number of bytes to receive. 424 * 425 * Return: 0 on success, -EAGAIN if no buffer is free and error 426 * code on failure. 427 * 428 * This function receives data using DMA. 429 */ 430 static int xudc_dma_receive(struct xusb_ep *ep, struct xusb_req *req, 431 u8 *buffer, u32 length) 432 { 433 u32 *eprambase; 434 dma_addr_t src; 435 dma_addr_t dst; 436 struct xusb_udc *udc = ep->udc; 437 438 dst = req->usb_req.dma + req->usb_req.actual; 439 if (!ep->curbufnum && !ep->buffer0ready) { 440 /* Get the Buffer address and copy the transmit data */ 441 eprambase = (u32 __force *)(udc->addr + ep->rambase); 442 src = virt_to_phys(eprambase); 443 udc->write_fn(udc->addr, XUSB_DMA_CONTROL_OFFSET, 444 XUSB_DMA_BRR_CTRL | XUSB_DMA_READ_FROM_DPRAM | 445 (1 << ep->epnumber)); 446 ep->buffer0ready = 1; 447 ep->curbufnum = 1; 448 } else if (ep->curbufnum && !ep->buffer1ready) { 449 /* Get the Buffer address and copy the transmit data */ 450 eprambase = (u32 __force *)(udc->addr + 451 ep->rambase + ep->ep_usb.maxpacket); 452 src = virt_to_phys(eprambase); 453 udc->write_fn(udc->addr, XUSB_DMA_CONTROL_OFFSET, 454 XUSB_DMA_BRR_CTRL | XUSB_DMA_READ_FROM_DPRAM | 455 (1 << (ep->epnumber + 456 XUSB_STATUS_EP_BUFF2_SHIFT))); 457 ep->buffer1ready = 1; 458 ep->curbufnum = 0; 459 } else { 460 /* None of the ping-pong buffers are ready currently */ 461 return -EAGAIN; 462 } 463 464 return xudc_start_dma(ep, src, dst, length); 465 } 466 467 /** 468 * xudc_eptxrx - Transmits or receives data to or from an endpoint. 469 * @ep: pointer to the usb endpoint configuration structure. 470 * @req: pointer to the usb request structure. 471 * @bufferptr: pointer to buffer containing the data to be sent. 472 * @bufferlen: The number of data bytes to be sent. 473 * 474 * Return: 0 on success, -EAGAIN if no buffer is free. 475 * 476 * This function copies the transmit/receive data to/from the end point buffer 477 * and enables the buffer for transmission/reception. 478 */ 479 static int xudc_eptxrx(struct xusb_ep *ep, struct xusb_req *req, 480 u8 *bufferptr, u32 bufferlen) 481 { 482 u32 *eprambase; 483 u32 bytestosend; 484 int rc = 0; 485 struct xusb_udc *udc = ep->udc; 486 487 bytestosend = bufferlen; 488 if (udc->dma_enabled) { 489 if (ep->is_in) 490 rc = xudc_dma_send(ep, req, bufferptr, bufferlen); 491 else 492 rc = xudc_dma_receive(ep, req, bufferptr, bufferlen); 493 return rc; 494 } 495 /* Put the transmit buffer into the correct ping-pong buffer.*/ 496 if (!ep->curbufnum && !ep->buffer0ready) { 497 /* Get the Buffer address and copy the transmit data.*/ 498 eprambase = (u32 __force *)(udc->addr + ep->rambase); 499 if (ep->is_in) { 500 memcpy(eprambase, bufferptr, bytestosend); 501 udc->write_fn(udc->addr, ep->offset + 502 XUSB_EP_BUF0COUNT_OFFSET, bufferlen); 503 } else { 504 memcpy(bufferptr, eprambase, bytestosend); 505 } 506 /* 507 * Enable the buffer for transmission. 508 */ 509 udc->write_fn(udc->addr, XUSB_BUFFREADY_OFFSET, 510 1 << ep->epnumber); 511 ep->buffer0ready = 1; 512 ep->curbufnum = 1; 513 } else if (ep->curbufnum && !ep->buffer1ready) { 514 /* Get the Buffer address and copy the transmit data.*/ 515 eprambase = (u32 __force *)(udc->addr + ep->rambase + 516 ep->ep_usb.maxpacket); 517 if (ep->is_in) { 518 memcpy(eprambase, bufferptr, bytestosend); 519 udc->write_fn(udc->addr, ep->offset + 520 XUSB_EP_BUF1COUNT_OFFSET, bufferlen); 521 } else { 522 memcpy(bufferptr, eprambase, bytestosend); 523 } 524 /* 525 * Enable the buffer for transmission. 526 */ 527 udc->write_fn(udc->addr, XUSB_BUFFREADY_OFFSET, 528 1 << (ep->epnumber + XUSB_STATUS_EP_BUFF2_SHIFT)); 529 ep->buffer1ready = 1; 530 ep->curbufnum = 0; 531 } else { 532 /* None of the ping-pong buffers are ready currently */ 533 return -EAGAIN; 534 } 535 return rc; 536 } 537 538 /** 539 * xudc_done - Exeutes the endpoint data transfer completion tasks. 540 * @ep: pointer to the usb device endpoint structure. 541 * @req: pointer to the usb request structure. 542 * @status: Status of the data transfer. 543 * 544 * Deletes the message from the queue and updates data transfer completion 545 * status. 546 */ 547 static void xudc_done(struct xusb_ep *ep, struct xusb_req *req, int status) 548 { 549 struct xusb_udc *udc = ep->udc; 550 551 list_del_init(&req->queue); 552 553 if (req->usb_req.status == -EINPROGRESS) 554 req->usb_req.status = status; 555 else 556 status = req->usb_req.status; 557 558 if (status && status != -ESHUTDOWN) 559 dev_dbg(udc->dev, "%s done %p, status %d\n", 560 ep->ep_usb.name, req, status); 561 /* unmap request if DMA is present*/ 562 if (udc->dma_enabled && ep->epnumber && req->usb_req.length) 563 usb_gadget_unmap_request(&udc->gadget, &req->usb_req, 564 ep->is_in); 565 566 if (req->usb_req.complete) { 567 spin_unlock(&udc->lock); 568 req->usb_req.complete(&ep->ep_usb, &req->usb_req); 569 spin_lock(&udc->lock); 570 } 571 } 572 573 /** 574 * xudc_read_fifo - Reads the data from the given endpoint buffer. 575 * @ep: pointer to the usb device endpoint structure. 576 * @req: pointer to the usb request structure. 577 * 578 * Return: 0 if request is completed and -EAGAIN if not completed. 579 * 580 * Pulls OUT packet data from the endpoint buffer. 581 */ 582 static int xudc_read_fifo(struct xusb_ep *ep, struct xusb_req *req) 583 { 584 u8 *buf; 585 u32 is_short, count, bufferspace; 586 u8 bufoffset; 587 u8 two_pkts = 0; 588 int ret; 589 int retval = -EAGAIN; 590 struct xusb_udc *udc = ep->udc; 591 592 if (ep->buffer0ready && ep->buffer1ready) { 593 dev_dbg(udc->dev, "Packet NOT ready!\n"); 594 return retval; 595 } 596 top: 597 if (ep->curbufnum) 598 bufoffset = XUSB_EP_BUF1COUNT_OFFSET; 599 else 600 bufoffset = XUSB_EP_BUF0COUNT_OFFSET; 601 602 count = udc->read_fn(udc->addr + ep->offset + bufoffset); 603 604 if (!ep->buffer0ready && !ep->buffer1ready) 605 two_pkts = 1; 606 607 buf = req->usb_req.buf + req->usb_req.actual; 608 prefetchw(buf); 609 bufferspace = req->usb_req.length - req->usb_req.actual; 610 is_short = count < ep->ep_usb.maxpacket; 611 612 if (unlikely(!bufferspace)) { 613 /* 614 * This happens when the driver's buffer 615 * is smaller than what the host sent. 616 * discard the extra data. 617 */ 618 if (req->usb_req.status != -EOVERFLOW) 619 dev_dbg(udc->dev, "%s overflow %d\n", 620 ep->ep_usb.name, count); 621 req->usb_req.status = -EOVERFLOW; 622 xudc_done(ep, req, -EOVERFLOW); 623 return 0; 624 } 625 626 ret = xudc_eptxrx(ep, req, buf, count); 627 switch (ret) { 628 case 0: 629 req->usb_req.actual += min(count, bufferspace); 630 dev_dbg(udc->dev, "read %s, %d bytes%s req %p %d/%d\n", 631 ep->ep_usb.name, count, is_short ? "/S" : "", req, 632 req->usb_req.actual, req->usb_req.length); 633 634 /* Completion */ 635 if ((req->usb_req.actual == req->usb_req.length) || is_short) { 636 if (udc->dma_enabled && req->usb_req.length) 637 dma_sync_single_for_cpu(udc->dev, 638 req->usb_req.dma, 639 req->usb_req.actual, 640 DMA_FROM_DEVICE); 641 xudc_done(ep, req, 0); 642 return 0; 643 } 644 if (two_pkts) { 645 two_pkts = 0; 646 goto top; 647 } 648 break; 649 case -EAGAIN: 650 dev_dbg(udc->dev, "receive busy\n"); 651 break; 652 case -EINVAL: 653 case -ETIMEDOUT: 654 /* DMA error, dequeue the request */ 655 xudc_done(ep, req, -ECONNRESET); 656 retval = 0; 657 break; 658 } 659 660 return retval; 661 } 662 663 /** 664 * xudc_write_fifo - Writes data into the given endpoint buffer. 665 * @ep: pointer to the usb device endpoint structure. 666 * @req: pointer to the usb request structure. 667 * 668 * Return: 0 if request is completed and -EAGAIN if not completed. 669 * 670 * Loads endpoint buffer for an IN packet. 671 */ 672 static int xudc_write_fifo(struct xusb_ep *ep, struct xusb_req *req) 673 { 674 u32 max; 675 u32 length; 676 int ret; 677 int retval = -EAGAIN; 678 struct xusb_udc *udc = ep->udc; 679 int is_last, is_short = 0; 680 u8 *buf; 681 682 max = le16_to_cpu(ep->desc->wMaxPacketSize); 683 buf = req->usb_req.buf + req->usb_req.actual; 684 prefetch(buf); 685 length = req->usb_req.length - req->usb_req.actual; 686 length = min(length, max); 687 688 ret = xudc_eptxrx(ep, req, buf, length); 689 switch (ret) { 690 case 0: 691 req->usb_req.actual += length; 692 if (unlikely(length != max)) { 693 is_last = is_short = 1; 694 } else { 695 if (likely(req->usb_req.length != 696 req->usb_req.actual) || req->usb_req.zero) 697 is_last = 0; 698 else 699 is_last = 1; 700 } 701 dev_dbg(udc->dev, "%s: wrote %s %d bytes%s%s %d left %p\n", 702 __func__, ep->ep_usb.name, length, is_last ? "/L" : "", 703 is_short ? "/S" : "", 704 req->usb_req.length - req->usb_req.actual, req); 705 /* completion */ 706 if (is_last) { 707 xudc_done(ep, req, 0); 708 retval = 0; 709 } 710 break; 711 case -EAGAIN: 712 dev_dbg(udc->dev, "Send busy\n"); 713 break; 714 case -EINVAL: 715 case -ETIMEDOUT: 716 /* DMA error, dequeue the request */ 717 xudc_done(ep, req, -ECONNRESET); 718 retval = 0; 719 break; 720 } 721 722 return retval; 723 } 724 725 /** 726 * xudc_nuke - Cleans up the data transfer message list. 727 * @ep: pointer to the usb device endpoint structure. 728 * @status: Status of the data transfer. 729 */ 730 static void xudc_nuke(struct xusb_ep *ep, int status) 731 { 732 struct xusb_req *req; 733 734 while (!list_empty(&ep->queue)) { 735 req = list_first_entry(&ep->queue, struct xusb_req, queue); 736 xudc_done(ep, req, status); 737 } 738 } 739 740 /** 741 * xudc_ep_set_halt - Stalls/unstalls the given endpoint. 742 * @_ep: pointer to the usb device endpoint structure. 743 * @value: value to indicate stall/unstall. 744 * 745 * Return: 0 for success and error value on failure 746 */ 747 static int xudc_ep_set_halt(struct usb_ep *_ep, int value) 748 { 749 struct xusb_ep *ep = to_xusb_ep(_ep); 750 struct xusb_udc *udc; 751 unsigned long flags; 752 u32 epcfgreg; 753 754 if (!_ep || (!ep->desc && ep->epnumber)) { 755 pr_debug("%s: bad ep or descriptor\n", __func__); 756 return -EINVAL; 757 } 758 udc = ep->udc; 759 760 if (ep->is_in && (!list_empty(&ep->queue)) && value) { 761 dev_dbg(udc->dev, "requests pending can't halt\n"); 762 return -EAGAIN; 763 } 764 765 if (ep->buffer0ready || ep->buffer1ready) { 766 dev_dbg(udc->dev, "HW buffers busy can't halt\n"); 767 return -EAGAIN; 768 } 769 770 spin_lock_irqsave(&udc->lock, flags); 771 772 if (value) { 773 /* Stall the device.*/ 774 epcfgreg = udc->read_fn(udc->addr + ep->offset); 775 epcfgreg |= XUSB_EP_CFG_STALL_MASK; 776 udc->write_fn(udc->addr, ep->offset, epcfgreg); 777 } else { 778 /* Unstall the device.*/ 779 epcfgreg = udc->read_fn(udc->addr + ep->offset); 780 epcfgreg &= ~XUSB_EP_CFG_STALL_MASK; 781 udc->write_fn(udc->addr, ep->offset, epcfgreg); 782 if (ep->epnumber) { 783 /* Reset the toggle bit.*/ 784 epcfgreg = udc->read_fn(ep->udc->addr + ep->offset); 785 epcfgreg &= ~XUSB_EP_CFG_DATA_TOGGLE_MASK; 786 udc->write_fn(udc->addr, ep->offset, epcfgreg); 787 } 788 } 789 790 spin_unlock_irqrestore(&udc->lock, flags); 791 return 0; 792 } 793 794 /** 795 * __xudc_ep_enable - Enables the given endpoint. 796 * @ep: pointer to the xusb endpoint structure. 797 * @desc: pointer to usb endpoint descriptor. 798 * 799 * Return: 0 for success and error value on failure 800 */ 801 static int __xudc_ep_enable(struct xusb_ep *ep, 802 const struct usb_endpoint_descriptor *desc) 803 { 804 struct xusb_udc *udc = ep->udc; 805 u32 tmp; 806 u32 epcfg; 807 u32 ier; 808 u16 maxpacket; 809 810 ep->is_in = ((desc->bEndpointAddress & USB_DIR_IN) != 0); 811 /* Bit 3...0:endpoint number */ 812 ep->epnumber = (desc->bEndpointAddress & 0x0f); 813 ep->desc = desc; 814 ep->ep_usb.desc = desc; 815 tmp = desc->bmAttributes & USB_ENDPOINT_XFERTYPE_MASK; 816 ep->ep_usb.maxpacket = maxpacket = le16_to_cpu(desc->wMaxPacketSize); 817 818 switch (tmp) { 819 case USB_ENDPOINT_XFER_CONTROL: 820 dev_dbg(udc->dev, "only one control endpoint\n"); 821 /* NON- ISO */ 822 ep->is_iso = 0; 823 return -EINVAL; 824 case USB_ENDPOINT_XFER_INT: 825 /* NON- ISO */ 826 ep->is_iso = 0; 827 if (maxpacket > 64) { 828 dev_dbg(udc->dev, "bogus maxpacket %d\n", maxpacket); 829 return -EINVAL; 830 } 831 break; 832 case USB_ENDPOINT_XFER_BULK: 833 /* NON- ISO */ 834 ep->is_iso = 0; 835 if (!(is_power_of_2(maxpacket) && maxpacket >= 8 && 836 maxpacket <= 512)) { 837 dev_dbg(udc->dev, "bogus maxpacket %d\n", maxpacket); 838 return -EINVAL; 839 } 840 break; 841 case USB_ENDPOINT_XFER_ISOC: 842 /* ISO */ 843 ep->is_iso = 1; 844 break; 845 } 846 847 ep->buffer0ready = false; 848 ep->buffer1ready = false; 849 ep->curbufnum = 0; 850 ep->rambase = rambase[ep->epnumber]; 851 xudc_epconfig(ep, udc); 852 853 dev_dbg(udc->dev, "Enable Endpoint %d max pkt is %d\n", 854 ep->epnumber, maxpacket); 855 856 /* Enable the End point.*/ 857 epcfg = udc->read_fn(udc->addr + ep->offset); 858 epcfg |= XUSB_EP_CFG_VALID_MASK; 859 udc->write_fn(udc->addr, ep->offset, epcfg); 860 if (ep->epnumber) 861 ep->rambase <<= 2; 862 863 /* Enable buffer completion interrupts for endpoint */ 864 ier = udc->read_fn(udc->addr + XUSB_IER_OFFSET); 865 ier |= (XUSB_STATUS_INTR_BUFF_COMP_SHIFT_MASK << ep->epnumber); 866 udc->write_fn(udc->addr, XUSB_IER_OFFSET, ier); 867 868 /* for OUT endpoint set buffers ready to receive */ 869 if (ep->epnumber && !ep->is_in) { 870 udc->write_fn(udc->addr, XUSB_BUFFREADY_OFFSET, 871 1 << ep->epnumber); 872 ep->buffer0ready = true; 873 udc->write_fn(udc->addr, XUSB_BUFFREADY_OFFSET, 874 (1 << (ep->epnumber + 875 XUSB_STATUS_EP_BUFF2_SHIFT))); 876 ep->buffer1ready = true; 877 } 878 879 return 0; 880 } 881 882 /** 883 * xudc_ep_enable - Enables the given endpoint. 884 * @_ep: pointer to the usb endpoint structure. 885 * @desc: pointer to usb endpoint descriptor. 886 * 887 * Return: 0 for success and error value on failure 888 */ 889 static int xudc_ep_enable(struct usb_ep *_ep, 890 const struct usb_endpoint_descriptor *desc) 891 { 892 struct xusb_ep *ep; 893 struct xusb_udc *udc; 894 unsigned long flags; 895 int ret; 896 897 if (!_ep || !desc || desc->bDescriptorType != USB_DT_ENDPOINT) { 898 pr_debug("%s: bad ep or descriptor\n", __func__); 899 return -EINVAL; 900 } 901 902 ep = to_xusb_ep(_ep); 903 udc = ep->udc; 904 905 if (!udc->driver || udc->gadget.speed == USB_SPEED_UNKNOWN) { 906 dev_dbg(udc->dev, "bogus device state\n"); 907 return -ESHUTDOWN; 908 } 909 910 spin_lock_irqsave(&udc->lock, flags); 911 ret = __xudc_ep_enable(ep, desc); 912 spin_unlock_irqrestore(&udc->lock, flags); 913 914 return ret; 915 } 916 917 /** 918 * xudc_ep_disable - Disables the given endpoint. 919 * @_ep: pointer to the usb endpoint structure. 920 * 921 * Return: 0 for success and error value on failure 922 */ 923 static int xudc_ep_disable(struct usb_ep *_ep) 924 { 925 struct xusb_ep *ep; 926 unsigned long flags; 927 u32 epcfg; 928 struct xusb_udc *udc; 929 930 if (!_ep) { 931 pr_debug("%s: invalid ep\n", __func__); 932 return -EINVAL; 933 } 934 935 ep = to_xusb_ep(_ep); 936 udc = ep->udc; 937 938 spin_lock_irqsave(&udc->lock, flags); 939 940 xudc_nuke(ep, -ESHUTDOWN); 941 942 /* Restore the endpoint's pristine config */ 943 ep->desc = NULL; 944 ep->ep_usb.desc = NULL; 945 946 dev_dbg(udc->dev, "USB Ep %d disable\n ", ep->epnumber); 947 /* Disable the endpoint.*/ 948 epcfg = udc->read_fn(udc->addr + ep->offset); 949 epcfg &= ~XUSB_EP_CFG_VALID_MASK; 950 udc->write_fn(udc->addr, ep->offset, epcfg); 951 952 spin_unlock_irqrestore(&udc->lock, flags); 953 return 0; 954 } 955 956 /** 957 * xudc_ep_alloc_request - Initializes the request queue. 958 * @_ep: pointer to the usb endpoint structure. 959 * @gfp_flags: Flags related to the request call. 960 * 961 * Return: pointer to request structure on success and a NULL on failure. 962 */ 963 static struct usb_request *xudc_ep_alloc_request(struct usb_ep *_ep, 964 gfp_t gfp_flags) 965 { 966 struct xusb_ep *ep = to_xusb_ep(_ep); 967 struct xusb_req *req; 968 969 req = kzalloc(sizeof(*req), gfp_flags); 970 if (!req) 971 return NULL; 972 973 req->ep = ep; 974 INIT_LIST_HEAD(&req->queue); 975 return &req->usb_req; 976 } 977 978 /** 979 * xudc_free_request - Releases the request from queue. 980 * @_ep: pointer to the usb device endpoint structure. 981 * @_req: pointer to the usb request structure. 982 */ 983 static void xudc_free_request(struct usb_ep *_ep, struct usb_request *_req) 984 { 985 struct xusb_req *req = to_xusb_req(_req); 986 987 kfree(req); 988 } 989 990 /** 991 * __xudc_ep0_queue - Adds the request to endpoint 0 queue. 992 * @ep0: pointer to the xusb endpoint 0 structure. 993 * @req: pointer to the xusb request structure. 994 * 995 * Return: 0 for success and error value on failure 996 */ 997 static int __xudc_ep0_queue(struct xusb_ep *ep0, struct xusb_req *req) 998 { 999 struct xusb_udc *udc = ep0->udc; 1000 u32 length; 1001 u8 *corebuf; 1002 1003 if (!udc->driver || udc->gadget.speed == USB_SPEED_UNKNOWN) { 1004 dev_dbg(udc->dev, "%s, bogus device state\n", __func__); 1005 return -EINVAL; 1006 } 1007 if (!list_empty(&ep0->queue)) { 1008 dev_dbg(udc->dev, "%s:ep0 busy\n", __func__); 1009 return -EBUSY; 1010 } 1011 1012 req->usb_req.status = -EINPROGRESS; 1013 req->usb_req.actual = 0; 1014 1015 list_add_tail(&req->queue, &ep0->queue); 1016 1017 if (udc->setup.bRequestType & USB_DIR_IN) { 1018 prefetch(req->usb_req.buf); 1019 length = req->usb_req.length; 1020 corebuf = (void __force *) ((ep0->rambase << 2) + 1021 udc->addr); 1022 length = req->usb_req.actual = min_t(u32, length, 1023 EP0_MAX_PACKET); 1024 memcpy(corebuf, req->usb_req.buf, length); 1025 udc->write_fn(udc->addr, XUSB_EP_BUF0COUNT_OFFSET, length); 1026 udc->write_fn(udc->addr, XUSB_BUFFREADY_OFFSET, 1); 1027 } else { 1028 if (udc->setup.wLength) { 1029 /* Enable EP0 buffer to receive data */ 1030 udc->write_fn(udc->addr, XUSB_EP_BUF0COUNT_OFFSET, 0); 1031 udc->write_fn(udc->addr, XUSB_BUFFREADY_OFFSET, 1); 1032 } else { 1033 xudc_wrstatus(udc); 1034 } 1035 } 1036 1037 return 0; 1038 } 1039 1040 /** 1041 * xudc_ep0_queue - Adds the request to endpoint 0 queue. 1042 * @_ep: pointer to the usb endpoint 0 structure. 1043 * @_req: pointer to the usb request structure. 1044 * @gfp_flags: Flags related to the request call. 1045 * 1046 * Return: 0 for success and error value on failure 1047 */ 1048 static int xudc_ep0_queue(struct usb_ep *_ep, struct usb_request *_req, 1049 gfp_t gfp_flags) 1050 { 1051 struct xusb_req *req = to_xusb_req(_req); 1052 struct xusb_ep *ep0 = to_xusb_ep(_ep); 1053 struct xusb_udc *udc = ep0->udc; 1054 unsigned long flags; 1055 int ret; 1056 1057 spin_lock_irqsave(&udc->lock, flags); 1058 ret = __xudc_ep0_queue(ep0, req); 1059 spin_unlock_irqrestore(&udc->lock, flags); 1060 1061 return ret; 1062 } 1063 1064 /** 1065 * xudc_ep_queue - Adds the request to endpoint queue. 1066 * @_ep: pointer to the usb endpoint structure. 1067 * @_req: pointer to the usb request structure. 1068 * @gfp_flags: Flags related to the request call. 1069 * 1070 * Return: 0 for success and error value on failure 1071 */ 1072 static int xudc_ep_queue(struct usb_ep *_ep, struct usb_request *_req, 1073 gfp_t gfp_flags) 1074 { 1075 struct xusb_req *req = to_xusb_req(_req); 1076 struct xusb_ep *ep = to_xusb_ep(_ep); 1077 struct xusb_udc *udc = ep->udc; 1078 int ret; 1079 unsigned long flags; 1080 1081 if (!ep->desc) { 1082 dev_dbg(udc->dev, "%s: queuing request to disabled %s\n", 1083 __func__, ep->name); 1084 return -ESHUTDOWN; 1085 } 1086 1087 if (!udc->driver || udc->gadget.speed == USB_SPEED_UNKNOWN) { 1088 dev_dbg(udc->dev, "%s, bogus device state\n", __func__); 1089 return -EINVAL; 1090 } 1091 1092 spin_lock_irqsave(&udc->lock, flags); 1093 1094 _req->status = -EINPROGRESS; 1095 _req->actual = 0; 1096 1097 if (udc->dma_enabled) { 1098 ret = usb_gadget_map_request(&udc->gadget, &req->usb_req, 1099 ep->is_in); 1100 if (ret) { 1101 dev_dbg(udc->dev, "gadget_map failed ep%d\n", 1102 ep->epnumber); 1103 spin_unlock_irqrestore(&udc->lock, flags); 1104 return -EAGAIN; 1105 } 1106 } 1107 1108 if (list_empty(&ep->queue)) { 1109 if (ep->is_in) { 1110 dev_dbg(udc->dev, "xudc_write_fifo from ep_queue\n"); 1111 if (!xudc_write_fifo(ep, req)) 1112 req = NULL; 1113 } else { 1114 dev_dbg(udc->dev, "xudc_read_fifo from ep_queue\n"); 1115 if (!xudc_read_fifo(ep, req)) 1116 req = NULL; 1117 } 1118 } 1119 1120 if (req != NULL) 1121 list_add_tail(&req->queue, &ep->queue); 1122 1123 spin_unlock_irqrestore(&udc->lock, flags); 1124 return 0; 1125 } 1126 1127 /** 1128 * xudc_ep_dequeue - Removes the request from the queue. 1129 * @_ep: pointer to the usb device endpoint structure. 1130 * @_req: pointer to the usb request structure. 1131 * 1132 * Return: 0 for success and error value on failure 1133 */ 1134 static int xudc_ep_dequeue(struct usb_ep *_ep, struct usb_request *_req) 1135 { 1136 struct xusb_ep *ep = to_xusb_ep(_ep); 1137 struct xusb_req *req = NULL; 1138 struct xusb_req *iter; 1139 struct xusb_udc *udc = ep->udc; 1140 unsigned long flags; 1141 1142 spin_lock_irqsave(&udc->lock, flags); 1143 /* Make sure it's actually queued on this endpoint */ 1144 list_for_each_entry(iter, &ep->queue, queue) { 1145 if (&iter->usb_req != _req) 1146 continue; 1147 req = iter; 1148 break; 1149 } 1150 if (!req) { 1151 spin_unlock_irqrestore(&udc->lock, flags); 1152 return -EINVAL; 1153 } 1154 xudc_done(ep, req, -ECONNRESET); 1155 spin_unlock_irqrestore(&udc->lock, flags); 1156 1157 return 0; 1158 } 1159 1160 /** 1161 * xudc_ep0_enable - Enables the given endpoint. 1162 * @ep: pointer to the usb endpoint structure. 1163 * @desc: pointer to usb endpoint descriptor. 1164 * 1165 * Return: error always. 1166 * 1167 * endpoint 0 enable should not be called by gadget layer. 1168 */ 1169 static int xudc_ep0_enable(struct usb_ep *ep, 1170 const struct usb_endpoint_descriptor *desc) 1171 { 1172 return -EINVAL; 1173 } 1174 1175 /** 1176 * xudc_ep0_disable - Disables the given endpoint. 1177 * @ep: pointer to the usb endpoint structure. 1178 * 1179 * Return: error always. 1180 * 1181 * endpoint 0 disable should not be called by gadget layer. 1182 */ 1183 static int xudc_ep0_disable(struct usb_ep *ep) 1184 { 1185 return -EINVAL; 1186 } 1187 1188 static const struct usb_ep_ops xusb_ep0_ops = { 1189 .enable = xudc_ep0_enable, 1190 .disable = xudc_ep0_disable, 1191 .alloc_request = xudc_ep_alloc_request, 1192 .free_request = xudc_free_request, 1193 .queue = xudc_ep0_queue, 1194 .dequeue = xudc_ep_dequeue, 1195 .set_halt = xudc_ep_set_halt, 1196 }; 1197 1198 static const struct usb_ep_ops xusb_ep_ops = { 1199 .enable = xudc_ep_enable, 1200 .disable = xudc_ep_disable, 1201 .alloc_request = xudc_ep_alloc_request, 1202 .free_request = xudc_free_request, 1203 .queue = xudc_ep_queue, 1204 .dequeue = xudc_ep_dequeue, 1205 .set_halt = xudc_ep_set_halt, 1206 }; 1207 1208 /** 1209 * xudc_get_frame - Reads the current usb frame number. 1210 * @gadget: pointer to the usb gadget structure. 1211 * 1212 * Return: current frame number for success and error value on failure. 1213 */ 1214 static int xudc_get_frame(struct usb_gadget *gadget) 1215 { 1216 struct xusb_udc *udc; 1217 int frame; 1218 1219 if (!gadget) 1220 return -ENODEV; 1221 1222 udc = to_udc(gadget); 1223 frame = udc->read_fn(udc->addr + XUSB_FRAMENUM_OFFSET); 1224 return frame; 1225 } 1226 1227 /** 1228 * xudc_wakeup - Send remote wakeup signal to host 1229 * @gadget: pointer to the usb gadget structure. 1230 * 1231 * Return: 0 on success and error on failure 1232 */ 1233 static int xudc_wakeup(struct usb_gadget *gadget) 1234 { 1235 struct xusb_udc *udc = to_udc(gadget); 1236 u32 crtlreg; 1237 int status = -EINVAL; 1238 unsigned long flags; 1239 1240 spin_lock_irqsave(&udc->lock, flags); 1241 1242 /* Remote wake up not enabled by host */ 1243 if (!udc->remote_wkp) 1244 goto done; 1245 1246 crtlreg = udc->read_fn(udc->addr + XUSB_CONTROL_OFFSET); 1247 crtlreg |= XUSB_CONTROL_USB_RMTWAKE_MASK; 1248 /* set remote wake up bit */ 1249 udc->write_fn(udc->addr, XUSB_CONTROL_OFFSET, crtlreg); 1250 /* 1251 * wait for a while and reset remote wake up bit since this bit 1252 * is not cleared by HW after sending remote wakeup to host. 1253 */ 1254 mdelay(2); 1255 1256 crtlreg &= ~XUSB_CONTROL_USB_RMTWAKE_MASK; 1257 udc->write_fn(udc->addr, XUSB_CONTROL_OFFSET, crtlreg); 1258 status = 0; 1259 done: 1260 spin_unlock_irqrestore(&udc->lock, flags); 1261 return status; 1262 } 1263 1264 /** 1265 * xudc_pullup - start/stop USB traffic 1266 * @gadget: pointer to the usb gadget structure. 1267 * @is_on: flag to start or stop 1268 * 1269 * Return: 0 always 1270 * 1271 * This function starts/stops SIE engine of IP based on is_on. 1272 */ 1273 static int xudc_pullup(struct usb_gadget *gadget, int is_on) 1274 { 1275 struct xusb_udc *udc = to_udc(gadget); 1276 unsigned long flags; 1277 u32 crtlreg; 1278 1279 spin_lock_irqsave(&udc->lock, flags); 1280 1281 crtlreg = udc->read_fn(udc->addr + XUSB_CONTROL_OFFSET); 1282 if (is_on) 1283 crtlreg |= XUSB_CONTROL_USB_READY_MASK; 1284 else 1285 crtlreg &= ~XUSB_CONTROL_USB_READY_MASK; 1286 1287 udc->write_fn(udc->addr, XUSB_CONTROL_OFFSET, crtlreg); 1288 1289 spin_unlock_irqrestore(&udc->lock, flags); 1290 1291 return 0; 1292 } 1293 1294 /** 1295 * xudc_eps_init - initialize endpoints. 1296 * @udc: pointer to the usb device controller structure. 1297 */ 1298 static void xudc_eps_init(struct xusb_udc *udc) 1299 { 1300 u32 ep_number; 1301 1302 INIT_LIST_HEAD(&udc->gadget.ep_list); 1303 1304 for (ep_number = 0; ep_number < XUSB_MAX_ENDPOINTS; ep_number++) { 1305 struct xusb_ep *ep = &udc->ep[ep_number]; 1306 1307 if (ep_number) { 1308 list_add_tail(&ep->ep_usb.ep_list, 1309 &udc->gadget.ep_list); 1310 usb_ep_set_maxpacket_limit(&ep->ep_usb, 1311 (unsigned short) ~0); 1312 snprintf(ep->name, EPNAME_SIZE, "ep%d", ep_number); 1313 ep->ep_usb.name = ep->name; 1314 ep->ep_usb.ops = &xusb_ep_ops; 1315 1316 ep->ep_usb.caps.type_iso = true; 1317 ep->ep_usb.caps.type_bulk = true; 1318 ep->ep_usb.caps.type_int = true; 1319 } else { 1320 ep->ep_usb.name = ep0name; 1321 usb_ep_set_maxpacket_limit(&ep->ep_usb, EP0_MAX_PACKET); 1322 ep->ep_usb.ops = &xusb_ep0_ops; 1323 1324 ep->ep_usb.caps.type_control = true; 1325 } 1326 1327 ep->ep_usb.caps.dir_in = true; 1328 ep->ep_usb.caps.dir_out = true; 1329 1330 ep->udc = udc; 1331 ep->epnumber = ep_number; 1332 ep->desc = NULL; 1333 /* 1334 * The configuration register address offset between 1335 * each endpoint is 0x10. 1336 */ 1337 ep->offset = XUSB_EP0_CONFIG_OFFSET + (ep_number * 0x10); 1338 ep->is_in = 0; 1339 ep->is_iso = 0; 1340 ep->maxpacket = 0; 1341 xudc_epconfig(ep, udc); 1342 1343 /* Initialize one queue per endpoint */ 1344 INIT_LIST_HEAD(&ep->queue); 1345 } 1346 } 1347 1348 /** 1349 * xudc_stop_activity - Stops any further activity on the device. 1350 * @udc: pointer to the usb device controller structure. 1351 */ 1352 static void xudc_stop_activity(struct xusb_udc *udc) 1353 { 1354 int i; 1355 struct xusb_ep *ep; 1356 1357 for (i = 0; i < XUSB_MAX_ENDPOINTS; i++) { 1358 ep = &udc->ep[i]; 1359 xudc_nuke(ep, -ESHUTDOWN); 1360 } 1361 } 1362 1363 /** 1364 * xudc_start - Starts the device. 1365 * @gadget: pointer to the usb gadget structure 1366 * @driver: pointer to gadget driver structure 1367 * 1368 * Return: zero on success and error on failure 1369 */ 1370 static int xudc_start(struct usb_gadget *gadget, 1371 struct usb_gadget_driver *driver) 1372 { 1373 struct xusb_udc *udc = to_udc(gadget); 1374 struct xusb_ep *ep0 = &udc->ep[XUSB_EP_NUMBER_ZERO]; 1375 const struct usb_endpoint_descriptor *desc = &config_bulk_out_desc; 1376 unsigned long flags; 1377 int ret = 0; 1378 1379 spin_lock_irqsave(&udc->lock, flags); 1380 1381 if (udc->driver) { 1382 dev_err(udc->dev, "%s is already bound to %s\n", 1383 udc->gadget.name, udc->driver->driver.name); 1384 ret = -EBUSY; 1385 goto err; 1386 } 1387 1388 /* hook up the driver */ 1389 udc->driver = driver; 1390 udc->gadget.speed = driver->max_speed; 1391 1392 /* Enable the control endpoint. */ 1393 ret = __xudc_ep_enable(ep0, desc); 1394 1395 /* Set device address and remote wakeup to 0 */ 1396 udc->write_fn(udc->addr, XUSB_ADDRESS_OFFSET, 0); 1397 udc->remote_wkp = 0; 1398 err: 1399 spin_unlock_irqrestore(&udc->lock, flags); 1400 return ret; 1401 } 1402 1403 /** 1404 * xudc_stop - stops the device. 1405 * @gadget: pointer to the usb gadget structure 1406 * 1407 * Return: zero always 1408 */ 1409 static int xudc_stop(struct usb_gadget *gadget) 1410 { 1411 struct xusb_udc *udc = to_udc(gadget); 1412 unsigned long flags; 1413 1414 spin_lock_irqsave(&udc->lock, flags); 1415 1416 udc->gadget.speed = USB_SPEED_UNKNOWN; 1417 udc->driver = NULL; 1418 1419 /* Set device address and remote wakeup to 0 */ 1420 udc->write_fn(udc->addr, XUSB_ADDRESS_OFFSET, 0); 1421 udc->remote_wkp = 0; 1422 1423 xudc_stop_activity(udc); 1424 1425 spin_unlock_irqrestore(&udc->lock, flags); 1426 1427 return 0; 1428 } 1429 1430 static const struct usb_gadget_ops xusb_udc_ops = { 1431 .get_frame = xudc_get_frame, 1432 .wakeup = xudc_wakeup, 1433 .pullup = xudc_pullup, 1434 .udc_start = xudc_start, 1435 .udc_stop = xudc_stop, 1436 }; 1437 1438 /** 1439 * xudc_clear_stall_all_ep - clears stall of every endpoint. 1440 * @udc: pointer to the udc structure. 1441 */ 1442 static void xudc_clear_stall_all_ep(struct xusb_udc *udc) 1443 { 1444 struct xusb_ep *ep; 1445 u32 epcfgreg; 1446 int i; 1447 1448 for (i = 0; i < XUSB_MAX_ENDPOINTS; i++) { 1449 ep = &udc->ep[i]; 1450 epcfgreg = udc->read_fn(udc->addr + ep->offset); 1451 epcfgreg &= ~XUSB_EP_CFG_STALL_MASK; 1452 udc->write_fn(udc->addr, ep->offset, epcfgreg); 1453 if (ep->epnumber) { 1454 /* Reset the toggle bit.*/ 1455 epcfgreg = udc->read_fn(udc->addr + ep->offset); 1456 epcfgreg &= ~XUSB_EP_CFG_DATA_TOGGLE_MASK; 1457 udc->write_fn(udc->addr, ep->offset, epcfgreg); 1458 } 1459 } 1460 } 1461 1462 /** 1463 * xudc_startup_handler - The usb device controller interrupt handler. 1464 * @udc: pointer to the udc structure. 1465 * @intrstatus: The mask value containing the interrupt sources. 1466 * 1467 * This function handles the RESET,SUSPEND,RESUME and DISCONNECT interrupts. 1468 */ 1469 static void xudc_startup_handler(struct xusb_udc *udc, u32 intrstatus) 1470 { 1471 u32 intrreg; 1472 1473 if (intrstatus & XUSB_STATUS_RESET_MASK) { 1474 1475 dev_dbg(udc->dev, "Reset\n"); 1476 1477 if (intrstatus & XUSB_STATUS_HIGH_SPEED_MASK) 1478 udc->gadget.speed = USB_SPEED_HIGH; 1479 else 1480 udc->gadget.speed = USB_SPEED_FULL; 1481 1482 xudc_stop_activity(udc); 1483 xudc_clear_stall_all_ep(udc); 1484 udc->write_fn(udc->addr, XUSB_TESTMODE_OFFSET, 0); 1485 1486 /* Set device address and remote wakeup to 0 */ 1487 udc->write_fn(udc->addr, XUSB_ADDRESS_OFFSET, 0); 1488 udc->remote_wkp = 0; 1489 1490 /* Enable the suspend, resume and disconnect */ 1491 intrreg = udc->read_fn(udc->addr + XUSB_IER_OFFSET); 1492 intrreg |= XUSB_STATUS_SUSPEND_MASK | XUSB_STATUS_RESUME_MASK | 1493 XUSB_STATUS_DISCONNECT_MASK; 1494 udc->write_fn(udc->addr, XUSB_IER_OFFSET, intrreg); 1495 } 1496 if (intrstatus & XUSB_STATUS_SUSPEND_MASK) { 1497 1498 dev_dbg(udc->dev, "Suspend\n"); 1499 1500 /* Enable the reset, resume and disconnect */ 1501 intrreg = udc->read_fn(udc->addr + XUSB_IER_OFFSET); 1502 intrreg |= XUSB_STATUS_RESET_MASK | XUSB_STATUS_RESUME_MASK | 1503 XUSB_STATUS_DISCONNECT_MASK; 1504 udc->write_fn(udc->addr, XUSB_IER_OFFSET, intrreg); 1505 1506 udc->usb_state = USB_STATE_SUSPENDED; 1507 1508 if (udc->driver->suspend) { 1509 spin_unlock(&udc->lock); 1510 udc->driver->suspend(&udc->gadget); 1511 spin_lock(&udc->lock); 1512 } 1513 } 1514 if (intrstatus & XUSB_STATUS_RESUME_MASK) { 1515 bool condition = (udc->usb_state != USB_STATE_SUSPENDED); 1516 1517 dev_WARN_ONCE(udc->dev, condition, 1518 "Resume IRQ while not suspended\n"); 1519 1520 dev_dbg(udc->dev, "Resume\n"); 1521 1522 /* Enable the reset, suspend and disconnect */ 1523 intrreg = udc->read_fn(udc->addr + XUSB_IER_OFFSET); 1524 intrreg |= XUSB_STATUS_RESET_MASK | XUSB_STATUS_SUSPEND_MASK | 1525 XUSB_STATUS_DISCONNECT_MASK; 1526 udc->write_fn(udc->addr, XUSB_IER_OFFSET, intrreg); 1527 1528 udc->usb_state = 0; 1529 1530 if (udc->driver->resume) { 1531 spin_unlock(&udc->lock); 1532 udc->driver->resume(&udc->gadget); 1533 spin_lock(&udc->lock); 1534 } 1535 } 1536 if (intrstatus & XUSB_STATUS_DISCONNECT_MASK) { 1537 1538 dev_dbg(udc->dev, "Disconnect\n"); 1539 1540 /* Enable the reset, resume and suspend */ 1541 intrreg = udc->read_fn(udc->addr + XUSB_IER_OFFSET); 1542 intrreg |= XUSB_STATUS_RESET_MASK | XUSB_STATUS_RESUME_MASK | 1543 XUSB_STATUS_SUSPEND_MASK; 1544 udc->write_fn(udc->addr, XUSB_IER_OFFSET, intrreg); 1545 1546 if (udc->driver && udc->driver->disconnect) { 1547 spin_unlock(&udc->lock); 1548 udc->driver->disconnect(&udc->gadget); 1549 spin_lock(&udc->lock); 1550 } 1551 } 1552 } 1553 1554 /** 1555 * xudc_ep0_stall - Stall endpoint zero. 1556 * @udc: pointer to the udc structure. 1557 * 1558 * This function stalls endpoint zero. 1559 */ 1560 static void xudc_ep0_stall(struct xusb_udc *udc) 1561 { 1562 u32 epcfgreg; 1563 struct xusb_ep *ep0 = &udc->ep[XUSB_EP_NUMBER_ZERO]; 1564 1565 epcfgreg = udc->read_fn(udc->addr + ep0->offset); 1566 epcfgreg |= XUSB_EP_CFG_STALL_MASK; 1567 udc->write_fn(udc->addr, ep0->offset, epcfgreg); 1568 } 1569 1570 /** 1571 * xudc_setaddress - executes SET_ADDRESS command 1572 * @udc: pointer to the udc structure. 1573 * 1574 * This function executes USB SET_ADDRESS command 1575 */ 1576 static void xudc_setaddress(struct xusb_udc *udc) 1577 { 1578 struct xusb_ep *ep0 = &udc->ep[0]; 1579 struct xusb_req *req = udc->req; 1580 int ret; 1581 1582 req->usb_req.length = 0; 1583 ret = __xudc_ep0_queue(ep0, req); 1584 if (ret == 0) 1585 return; 1586 1587 dev_err(udc->dev, "Can't respond to SET ADDRESS request\n"); 1588 xudc_ep0_stall(udc); 1589 } 1590 1591 /** 1592 * xudc_getstatus - executes GET_STATUS command 1593 * @udc: pointer to the udc structure. 1594 * 1595 * This function executes USB GET_STATUS command 1596 */ 1597 static void xudc_getstatus(struct xusb_udc *udc) 1598 { 1599 struct xusb_ep *ep0 = &udc->ep[0]; 1600 struct xusb_req *req = udc->req; 1601 struct xusb_ep *target_ep; 1602 u16 status = 0; 1603 u32 epcfgreg; 1604 int epnum; 1605 u32 halt; 1606 int ret; 1607 1608 switch (udc->setup.bRequestType & USB_RECIP_MASK) { 1609 case USB_RECIP_DEVICE: 1610 /* Get device status */ 1611 status = 1 << USB_DEVICE_SELF_POWERED; 1612 if (udc->remote_wkp) 1613 status |= (1 << USB_DEVICE_REMOTE_WAKEUP); 1614 break; 1615 case USB_RECIP_INTERFACE: 1616 break; 1617 case USB_RECIP_ENDPOINT: 1618 epnum = le16_to_cpu(udc->setup.wIndex) & USB_ENDPOINT_NUMBER_MASK; 1619 if (epnum >= XUSB_MAX_ENDPOINTS) 1620 goto stall; 1621 target_ep = &udc->ep[epnum]; 1622 epcfgreg = udc->read_fn(udc->addr + target_ep->offset); 1623 halt = epcfgreg & XUSB_EP_CFG_STALL_MASK; 1624 if (le16_to_cpu(udc->setup.wIndex) & USB_DIR_IN) { 1625 if (!target_ep->is_in) 1626 goto stall; 1627 } else { 1628 if (target_ep->is_in) 1629 goto stall; 1630 } 1631 if (halt) 1632 status = 1 << USB_ENDPOINT_HALT; 1633 break; 1634 default: 1635 goto stall; 1636 } 1637 1638 req->usb_req.length = 2; 1639 *(__le16 *)req->usb_req.buf = cpu_to_le16(status); 1640 ret = __xudc_ep0_queue(ep0, req); 1641 if (ret == 0) 1642 return; 1643 stall: 1644 dev_err(udc->dev, "Can't respond to getstatus request\n"); 1645 xudc_ep0_stall(udc); 1646 } 1647 1648 /** 1649 * xudc_set_clear_feature - Executes the set feature and clear feature commands. 1650 * @udc: pointer to the usb device controller structure. 1651 * 1652 * Processes the SET_FEATURE and CLEAR_FEATURE commands. 1653 */ 1654 static void xudc_set_clear_feature(struct xusb_udc *udc) 1655 { 1656 struct xusb_ep *ep0 = &udc->ep[0]; 1657 struct xusb_req *req = udc->req; 1658 struct xusb_ep *target_ep; 1659 u8 endpoint; 1660 u8 outinbit; 1661 u32 epcfgreg; 1662 int flag = (udc->setup.bRequest == USB_REQ_SET_FEATURE ? 1 : 0); 1663 int ret; 1664 1665 switch (udc->setup.bRequestType) { 1666 case USB_RECIP_DEVICE: 1667 switch (le16_to_cpu(udc->setup.wValue)) { 1668 case USB_DEVICE_TEST_MODE: 1669 /* 1670 * The Test Mode will be executed 1671 * after the status phase. 1672 */ 1673 break; 1674 case USB_DEVICE_REMOTE_WAKEUP: 1675 if (flag) 1676 udc->remote_wkp = 1; 1677 else 1678 udc->remote_wkp = 0; 1679 break; 1680 default: 1681 xudc_ep0_stall(udc); 1682 break; 1683 } 1684 break; 1685 case USB_RECIP_ENDPOINT: 1686 if (!udc->setup.wValue) { 1687 endpoint = le16_to_cpu(udc->setup.wIndex) & 1688 USB_ENDPOINT_NUMBER_MASK; 1689 if (endpoint >= XUSB_MAX_ENDPOINTS) { 1690 xudc_ep0_stall(udc); 1691 return; 1692 } 1693 target_ep = &udc->ep[endpoint]; 1694 outinbit = le16_to_cpu(udc->setup.wIndex) & 1695 USB_ENDPOINT_DIR_MASK; 1696 outinbit = outinbit >> 7; 1697 1698 /* Make sure direction matches.*/ 1699 if (outinbit != target_ep->is_in) { 1700 xudc_ep0_stall(udc); 1701 return; 1702 } 1703 epcfgreg = udc->read_fn(udc->addr + target_ep->offset); 1704 if (!endpoint) { 1705 /* Clear the stall.*/ 1706 epcfgreg &= ~XUSB_EP_CFG_STALL_MASK; 1707 udc->write_fn(udc->addr, 1708 target_ep->offset, epcfgreg); 1709 } else { 1710 if (flag) { 1711 epcfgreg |= XUSB_EP_CFG_STALL_MASK; 1712 udc->write_fn(udc->addr, 1713 target_ep->offset, 1714 epcfgreg); 1715 } else { 1716 /* Unstall the endpoint.*/ 1717 epcfgreg &= ~(XUSB_EP_CFG_STALL_MASK | 1718 XUSB_EP_CFG_DATA_TOGGLE_MASK); 1719 udc->write_fn(udc->addr, 1720 target_ep->offset, 1721 epcfgreg); 1722 } 1723 } 1724 } 1725 break; 1726 default: 1727 xudc_ep0_stall(udc); 1728 return; 1729 } 1730 1731 req->usb_req.length = 0; 1732 ret = __xudc_ep0_queue(ep0, req); 1733 if (ret == 0) 1734 return; 1735 1736 dev_err(udc->dev, "Can't respond to SET/CLEAR FEATURE\n"); 1737 xudc_ep0_stall(udc); 1738 } 1739 1740 /** 1741 * xudc_handle_setup - Processes the setup packet. 1742 * @udc: pointer to the usb device controller structure. 1743 * 1744 * Process setup packet and delegate to gadget layer. 1745 */ 1746 static void xudc_handle_setup(struct xusb_udc *udc) 1747 __must_hold(&udc->lock) 1748 { 1749 struct xusb_ep *ep0 = &udc->ep[0]; 1750 struct usb_ctrlrequest setup; 1751 u32 *ep0rambase; 1752 1753 /* Load up the chapter 9 command buffer.*/ 1754 ep0rambase = (u32 __force *) (udc->addr + XUSB_SETUP_PKT_ADDR_OFFSET); 1755 memcpy(&setup, ep0rambase, 8); 1756 1757 udc->setup = setup; 1758 udc->setup.wValue = cpu_to_le16((u16 __force)setup.wValue); 1759 udc->setup.wIndex = cpu_to_le16((u16 __force)setup.wIndex); 1760 udc->setup.wLength = cpu_to_le16((u16 __force)setup.wLength); 1761 1762 /* Clear previous requests */ 1763 xudc_nuke(ep0, -ECONNRESET); 1764 1765 if (udc->setup.bRequestType & USB_DIR_IN) { 1766 /* Execute the get command.*/ 1767 udc->setupseqrx = STATUS_PHASE; 1768 udc->setupseqtx = DATA_PHASE; 1769 } else { 1770 /* Execute the put command.*/ 1771 udc->setupseqrx = DATA_PHASE; 1772 udc->setupseqtx = STATUS_PHASE; 1773 } 1774 1775 switch (udc->setup.bRequest) { 1776 case USB_REQ_GET_STATUS: 1777 /* Data+Status phase form udc */ 1778 if ((udc->setup.bRequestType & 1779 (USB_DIR_IN | USB_TYPE_MASK)) != 1780 (USB_DIR_IN | USB_TYPE_STANDARD)) 1781 break; 1782 xudc_getstatus(udc); 1783 return; 1784 case USB_REQ_SET_ADDRESS: 1785 /* Status phase from udc */ 1786 if (udc->setup.bRequestType != (USB_DIR_OUT | 1787 USB_TYPE_STANDARD | USB_RECIP_DEVICE)) 1788 break; 1789 xudc_setaddress(udc); 1790 return; 1791 case USB_REQ_CLEAR_FEATURE: 1792 case USB_REQ_SET_FEATURE: 1793 /* Requests with no data phase, status phase from udc */ 1794 if ((udc->setup.bRequestType & USB_TYPE_MASK) 1795 != USB_TYPE_STANDARD) 1796 break; 1797 xudc_set_clear_feature(udc); 1798 return; 1799 default: 1800 break; 1801 } 1802 1803 spin_unlock(&udc->lock); 1804 if (udc->driver->setup(&udc->gadget, &setup) < 0) 1805 xudc_ep0_stall(udc); 1806 spin_lock(&udc->lock); 1807 } 1808 1809 /** 1810 * xudc_ep0_out - Processes the endpoint 0 OUT token. 1811 * @udc: pointer to the usb device controller structure. 1812 */ 1813 static void xudc_ep0_out(struct xusb_udc *udc) 1814 { 1815 struct xusb_ep *ep0 = &udc->ep[0]; 1816 struct xusb_req *req; 1817 u8 *ep0rambase; 1818 unsigned int bytes_to_rx; 1819 void *buffer; 1820 1821 req = list_first_entry(&ep0->queue, struct xusb_req, queue); 1822 1823 switch (udc->setupseqrx) { 1824 case STATUS_PHASE: 1825 /* 1826 * This resets both state machines for the next 1827 * Setup packet. 1828 */ 1829 udc->setupseqrx = SETUP_PHASE; 1830 udc->setupseqtx = SETUP_PHASE; 1831 req->usb_req.actual = req->usb_req.length; 1832 xudc_done(ep0, req, 0); 1833 break; 1834 case DATA_PHASE: 1835 bytes_to_rx = udc->read_fn(udc->addr + 1836 XUSB_EP_BUF0COUNT_OFFSET); 1837 /* Copy the data to be received from the DPRAM. */ 1838 ep0rambase = (u8 __force *) (udc->addr + 1839 (ep0->rambase << 2)); 1840 buffer = req->usb_req.buf + req->usb_req.actual; 1841 req->usb_req.actual = req->usb_req.actual + bytes_to_rx; 1842 memcpy(buffer, ep0rambase, bytes_to_rx); 1843 1844 if (req->usb_req.length == req->usb_req.actual) { 1845 /* Data transfer completed get ready for Status stage */ 1846 xudc_wrstatus(udc); 1847 } else { 1848 /* Enable EP0 buffer to receive data */ 1849 udc->write_fn(udc->addr, XUSB_EP_BUF0COUNT_OFFSET, 0); 1850 udc->write_fn(udc->addr, XUSB_BUFFREADY_OFFSET, 1); 1851 } 1852 break; 1853 default: 1854 break; 1855 } 1856 } 1857 1858 /** 1859 * xudc_ep0_in - Processes the endpoint 0 IN token. 1860 * @udc: pointer to the usb device controller structure. 1861 */ 1862 static void xudc_ep0_in(struct xusb_udc *udc) 1863 { 1864 struct xusb_ep *ep0 = &udc->ep[0]; 1865 struct xusb_req *req; 1866 unsigned int bytes_to_tx; 1867 void *buffer; 1868 u32 epcfgreg; 1869 u16 count = 0; 1870 u16 length; 1871 u8 *ep0rambase; 1872 u8 test_mode = le16_to_cpu(udc->setup.wIndex) >> 8; 1873 1874 req = list_first_entry(&ep0->queue, struct xusb_req, queue); 1875 bytes_to_tx = req->usb_req.length - req->usb_req.actual; 1876 1877 switch (udc->setupseqtx) { 1878 case STATUS_PHASE: 1879 switch (udc->setup.bRequest) { 1880 case USB_REQ_SET_ADDRESS: 1881 /* Set the address of the device.*/ 1882 udc->write_fn(udc->addr, XUSB_ADDRESS_OFFSET, 1883 le16_to_cpu(udc->setup.wValue)); 1884 break; 1885 case USB_REQ_SET_FEATURE: 1886 if (udc->setup.bRequestType == 1887 USB_RECIP_DEVICE) { 1888 if (le16_to_cpu(udc->setup.wValue) == 1889 USB_DEVICE_TEST_MODE) 1890 udc->write_fn(udc->addr, 1891 XUSB_TESTMODE_OFFSET, 1892 test_mode); 1893 } 1894 break; 1895 } 1896 req->usb_req.actual = req->usb_req.length; 1897 xudc_done(ep0, req, 0); 1898 break; 1899 case DATA_PHASE: 1900 if (!bytes_to_tx) { 1901 /* 1902 * We're done with data transfer, next 1903 * will be zero length OUT with data toggle of 1904 * 1. Setup data_toggle. 1905 */ 1906 epcfgreg = udc->read_fn(udc->addr + ep0->offset); 1907 epcfgreg |= XUSB_EP_CFG_DATA_TOGGLE_MASK; 1908 udc->write_fn(udc->addr, ep0->offset, epcfgreg); 1909 udc->setupseqtx = STATUS_PHASE; 1910 } else { 1911 length = count = min_t(u32, bytes_to_tx, 1912 EP0_MAX_PACKET); 1913 /* Copy the data to be transmitted into the DPRAM. */ 1914 ep0rambase = (u8 __force *) (udc->addr + 1915 (ep0->rambase << 2)); 1916 buffer = req->usb_req.buf + req->usb_req.actual; 1917 req->usb_req.actual = req->usb_req.actual + length; 1918 memcpy(ep0rambase, buffer, length); 1919 } 1920 udc->write_fn(udc->addr, XUSB_EP_BUF0COUNT_OFFSET, count); 1921 udc->write_fn(udc->addr, XUSB_BUFFREADY_OFFSET, 1); 1922 break; 1923 default: 1924 break; 1925 } 1926 } 1927 1928 /** 1929 * xudc_ctrl_ep_handler - Endpoint 0 interrupt handler. 1930 * @udc: pointer to the udc structure. 1931 * @intrstatus: It's the mask value for the interrupt sources on endpoint 0. 1932 * 1933 * Processes the commands received during enumeration phase. 1934 */ 1935 static void xudc_ctrl_ep_handler(struct xusb_udc *udc, u32 intrstatus) 1936 { 1937 1938 if (intrstatus & XUSB_STATUS_SETUP_PACKET_MASK) { 1939 xudc_handle_setup(udc); 1940 } else { 1941 if (intrstatus & XUSB_STATUS_FIFO_BUFF_RDY_MASK) 1942 xudc_ep0_out(udc); 1943 else if (intrstatus & XUSB_STATUS_FIFO_BUFF_FREE_MASK) 1944 xudc_ep0_in(udc); 1945 } 1946 } 1947 1948 /** 1949 * xudc_nonctrl_ep_handler - Non control endpoint interrupt handler. 1950 * @udc: pointer to the udc structure. 1951 * @epnum: End point number for which the interrupt is to be processed 1952 * @intrstatus: mask value for interrupt sources of endpoints other 1953 * than endpoint 0. 1954 * 1955 * Processes the buffer completion interrupts. 1956 */ 1957 static void xudc_nonctrl_ep_handler(struct xusb_udc *udc, u8 epnum, 1958 u32 intrstatus) 1959 { 1960 1961 struct xusb_req *req; 1962 struct xusb_ep *ep; 1963 1964 ep = &udc->ep[epnum]; 1965 /* Process the End point interrupts.*/ 1966 if (intrstatus & (XUSB_STATUS_EP0_BUFF1_COMP_MASK << epnum)) 1967 ep->buffer0ready = 0; 1968 if (intrstatus & (XUSB_STATUS_EP0_BUFF2_COMP_MASK << epnum)) 1969 ep->buffer1ready = false; 1970 1971 if (list_empty(&ep->queue)) 1972 return; 1973 1974 req = list_first_entry(&ep->queue, struct xusb_req, queue); 1975 1976 if (ep->is_in) 1977 xudc_write_fifo(ep, req); 1978 else 1979 xudc_read_fifo(ep, req); 1980 } 1981 1982 /** 1983 * xudc_irq - The main interrupt handler. 1984 * @irq: The interrupt number. 1985 * @_udc: pointer to the usb device controller structure. 1986 * 1987 * Return: IRQ_HANDLED after the interrupt is handled. 1988 */ 1989 static irqreturn_t xudc_irq(int irq, void *_udc) 1990 { 1991 struct xusb_udc *udc = _udc; 1992 u32 intrstatus; 1993 u32 ier; 1994 u8 index; 1995 u32 bufintr; 1996 unsigned long flags; 1997 1998 spin_lock_irqsave(&udc->lock, flags); 1999 2000 /* 2001 * Event interrupts are level sensitive hence first disable 2002 * IER, read ISR and figure out active interrupts. 2003 */ 2004 ier = udc->read_fn(udc->addr + XUSB_IER_OFFSET); 2005 ier &= ~XUSB_STATUS_INTR_EVENT_MASK; 2006 udc->write_fn(udc->addr, XUSB_IER_OFFSET, ier); 2007 2008 /* Read the Interrupt Status Register.*/ 2009 intrstatus = udc->read_fn(udc->addr + XUSB_STATUS_OFFSET); 2010 2011 /* Call the handler for the event interrupt.*/ 2012 if (intrstatus & XUSB_STATUS_INTR_EVENT_MASK) { 2013 /* 2014 * Check if there is any action to be done for : 2015 * - USB Reset received {XUSB_STATUS_RESET_MASK} 2016 * - USB Suspend received {XUSB_STATUS_SUSPEND_MASK} 2017 * - USB Resume received {XUSB_STATUS_RESUME_MASK} 2018 * - USB Disconnect received {XUSB_STATUS_DISCONNECT_MASK} 2019 */ 2020 xudc_startup_handler(udc, intrstatus); 2021 } 2022 2023 /* Check the buffer completion interrupts */ 2024 if (intrstatus & XUSB_STATUS_INTR_BUFF_COMP_ALL_MASK) { 2025 /* Enable Reset, Suspend, Resume and Disconnect */ 2026 ier = udc->read_fn(udc->addr + XUSB_IER_OFFSET); 2027 ier |= XUSB_STATUS_INTR_EVENT_MASK; 2028 udc->write_fn(udc->addr, XUSB_IER_OFFSET, ier); 2029 2030 if (intrstatus & XUSB_STATUS_EP0_BUFF1_COMP_MASK) 2031 xudc_ctrl_ep_handler(udc, intrstatus); 2032 2033 for (index = 1; index < 8; index++) { 2034 bufintr = ((intrstatus & 2035 (XUSB_STATUS_EP1_BUFF1_COMP_MASK << 2036 (index - 1))) || (intrstatus & 2037 (XUSB_STATUS_EP1_BUFF2_COMP_MASK << 2038 (index - 1)))); 2039 if (bufintr) { 2040 xudc_nonctrl_ep_handler(udc, index, 2041 intrstatus); 2042 } 2043 } 2044 } 2045 2046 spin_unlock_irqrestore(&udc->lock, flags); 2047 return IRQ_HANDLED; 2048 } 2049 2050 /** 2051 * xudc_probe - The device probe function for driver initialization. 2052 * @pdev: pointer to the platform device structure. 2053 * 2054 * Return: 0 for success and error value on failure 2055 */ 2056 static int xudc_probe(struct platform_device *pdev) 2057 { 2058 struct device_node *np = pdev->dev.of_node; 2059 struct resource *res; 2060 struct xusb_udc *udc; 2061 int irq; 2062 int ret; 2063 u32 ier; 2064 u8 *buff; 2065 2066 udc = devm_kzalloc(&pdev->dev, sizeof(*udc), GFP_KERNEL); 2067 if (!udc) 2068 return -ENOMEM; 2069 2070 /* Create a dummy request for GET_STATUS, SET_ADDRESS */ 2071 udc->req = devm_kzalloc(&pdev->dev, sizeof(struct xusb_req), 2072 GFP_KERNEL); 2073 if (!udc->req) 2074 return -ENOMEM; 2075 2076 buff = devm_kzalloc(&pdev->dev, STATUSBUFF_SIZE, GFP_KERNEL); 2077 if (!buff) 2078 return -ENOMEM; 2079 2080 udc->req->usb_req.buf = buff; 2081 2082 /* Map the registers */ 2083 udc->addr = devm_platform_get_and_ioremap_resource(pdev, 0, &res); 2084 if (IS_ERR(udc->addr)) 2085 return PTR_ERR(udc->addr); 2086 2087 irq = platform_get_irq(pdev, 0); 2088 if (irq < 0) 2089 return irq; 2090 ret = devm_request_irq(&pdev->dev, irq, xudc_irq, 0, 2091 dev_name(&pdev->dev), udc); 2092 if (ret < 0) { 2093 dev_dbg(&pdev->dev, "unable to request irq %d", irq); 2094 goto fail; 2095 } 2096 2097 udc->dma_enabled = of_property_read_bool(np, "xlnx,has-builtin-dma"); 2098 2099 /* Setup gadget structure */ 2100 udc->gadget.ops = &xusb_udc_ops; 2101 udc->gadget.max_speed = USB_SPEED_HIGH; 2102 udc->gadget.speed = USB_SPEED_UNKNOWN; 2103 udc->gadget.ep0 = &udc->ep[XUSB_EP_NUMBER_ZERO].ep_usb; 2104 udc->gadget.name = driver_name; 2105 2106 udc->clk = devm_clk_get(&pdev->dev, "s_axi_aclk"); 2107 if (IS_ERR(udc->clk)) { 2108 if (PTR_ERR(udc->clk) != -ENOENT) { 2109 ret = PTR_ERR(udc->clk); 2110 goto fail; 2111 } 2112 2113 /* 2114 * Clock framework support is optional, continue on, 2115 * anyways if we don't find a matching clock 2116 */ 2117 dev_warn(&pdev->dev, "s_axi_aclk clock property is not found\n"); 2118 udc->clk = NULL; 2119 } 2120 2121 ret = clk_prepare_enable(udc->clk); 2122 if (ret) { 2123 dev_err(&pdev->dev, "Unable to enable clock.\n"); 2124 return ret; 2125 } 2126 2127 spin_lock_init(&udc->lock); 2128 2129 /* Check for IP endianness */ 2130 udc->write_fn = xudc_write32_be; 2131 udc->read_fn = xudc_read32_be; 2132 udc->write_fn(udc->addr, XUSB_TESTMODE_OFFSET, USB_TEST_J); 2133 if ((udc->read_fn(udc->addr + XUSB_TESTMODE_OFFSET)) 2134 != USB_TEST_J) { 2135 udc->write_fn = xudc_write32; 2136 udc->read_fn = xudc_read32; 2137 } 2138 udc->write_fn(udc->addr, XUSB_TESTMODE_OFFSET, 0); 2139 2140 xudc_eps_init(udc); 2141 2142 /* Set device address to 0.*/ 2143 udc->write_fn(udc->addr, XUSB_ADDRESS_OFFSET, 0); 2144 2145 ret = usb_add_gadget_udc(&pdev->dev, &udc->gadget); 2146 if (ret) 2147 goto err_disable_unprepare_clk; 2148 2149 udc->dev = &udc->gadget.dev; 2150 2151 /* Enable the interrupts.*/ 2152 ier = XUSB_STATUS_GLOBAL_INTR_MASK | XUSB_STATUS_INTR_EVENT_MASK | 2153 XUSB_STATUS_FIFO_BUFF_RDY_MASK | XUSB_STATUS_FIFO_BUFF_FREE_MASK | 2154 XUSB_STATUS_SETUP_PACKET_MASK | 2155 XUSB_STATUS_INTR_BUFF_COMP_ALL_MASK; 2156 2157 udc->write_fn(udc->addr, XUSB_IER_OFFSET, ier); 2158 2159 platform_set_drvdata(pdev, udc); 2160 2161 dev_vdbg(&pdev->dev, "%s at 0x%08X mapped to %p %s\n", 2162 driver_name, (u32)res->start, udc->addr, 2163 udc->dma_enabled ? "with DMA" : "without DMA"); 2164 2165 return 0; 2166 2167 err_disable_unprepare_clk: 2168 clk_disable_unprepare(udc->clk); 2169 fail: 2170 dev_err(&pdev->dev, "probe failed, %d\n", ret); 2171 return ret; 2172 } 2173 2174 /** 2175 * xudc_remove - Releases the resources allocated during the initialization. 2176 * @pdev: pointer to the platform device structure. 2177 * 2178 * Return: 0 always 2179 */ 2180 static void xudc_remove(struct platform_device *pdev) 2181 { 2182 struct xusb_udc *udc = platform_get_drvdata(pdev); 2183 2184 usb_del_gadget_udc(&udc->gadget); 2185 clk_disable_unprepare(udc->clk); 2186 } 2187 2188 #ifdef CONFIG_PM_SLEEP 2189 static int xudc_suspend(struct device *dev) 2190 { 2191 struct xusb_udc *udc; 2192 u32 crtlreg; 2193 unsigned long flags; 2194 2195 udc = dev_get_drvdata(dev); 2196 2197 spin_lock_irqsave(&udc->lock, flags); 2198 2199 crtlreg = udc->read_fn(udc->addr + XUSB_CONTROL_OFFSET); 2200 crtlreg &= ~XUSB_CONTROL_USB_READY_MASK; 2201 2202 udc->write_fn(udc->addr, XUSB_CONTROL_OFFSET, crtlreg); 2203 2204 spin_unlock_irqrestore(&udc->lock, flags); 2205 if (udc->driver && udc->driver->suspend) 2206 udc->driver->suspend(&udc->gadget); 2207 2208 clk_disable(udc->clk); 2209 2210 return 0; 2211 } 2212 2213 static int xudc_resume(struct device *dev) 2214 { 2215 struct xusb_udc *udc; 2216 u32 crtlreg; 2217 unsigned long flags; 2218 int ret; 2219 2220 udc = dev_get_drvdata(dev); 2221 2222 ret = clk_enable(udc->clk); 2223 if (ret < 0) 2224 return ret; 2225 2226 spin_lock_irqsave(&udc->lock, flags); 2227 2228 crtlreg = udc->read_fn(udc->addr + XUSB_CONTROL_OFFSET); 2229 crtlreg |= XUSB_CONTROL_USB_READY_MASK; 2230 2231 udc->write_fn(udc->addr, XUSB_CONTROL_OFFSET, crtlreg); 2232 2233 spin_unlock_irqrestore(&udc->lock, flags); 2234 2235 return 0; 2236 } 2237 #endif /* CONFIG_PM_SLEEP */ 2238 2239 static const struct dev_pm_ops xudc_pm_ops = { 2240 SET_SYSTEM_SLEEP_PM_OPS(xudc_suspend, xudc_resume) 2241 }; 2242 2243 /* Match table for of_platform binding */ 2244 static const struct of_device_id usb_of_match[] = { 2245 { .compatible = "xlnx,usb2-device-4.00.a", }, 2246 { /* end of list */ }, 2247 }; 2248 MODULE_DEVICE_TABLE(of, usb_of_match); 2249 2250 static struct platform_driver xudc_driver = { 2251 .driver = { 2252 .name = driver_name, 2253 .of_match_table = usb_of_match, 2254 .pm = &xudc_pm_ops, 2255 }, 2256 .probe = xudc_probe, 2257 .remove_new = xudc_remove, 2258 }; 2259 2260 module_platform_driver(xudc_driver); 2261 2262 MODULE_DESCRIPTION("Xilinx udc driver"); 2263 MODULE_AUTHOR("Xilinx, Inc"); 2264 MODULE_LICENSE("GPL"); 2265