1 /* 2 * Intel PXA25x on-chip full speed USB device controller 3 * 4 * Copyright (C) 2003 Robert Schwebel <r.schwebel@pengutronix.de>, Pengutronix 5 * Copyright (C) 2003 David Brownell 6 * 7 * 8 * This program is free software; you can redistribute it and/or modify 9 * it under the terms of the GNU General Public License as published by 10 * the Free Software Foundation; either version 2 of the License, or 11 * (at your option) any later version. 12 */ 13 14 #ifndef __LINUX_USB_GADGET_PXA25X_H 15 #define __LINUX_USB_GADGET_PXA25X_H 16 17 #include <linux/types.h> 18 19 /*-------------------------------------------------------------------------*/ 20 21 /* pxa25x has this (move to include/asm-arm/arch-pxa/pxa-regs.h) */ 22 #define UFNRH_SIR (1 << 7) /* SOF interrupt request */ 23 #define UFNRH_SIM (1 << 6) /* SOF interrupt mask */ 24 #define UFNRH_IPE14 (1 << 5) /* ISO packet error, ep14 */ 25 #define UFNRH_IPE9 (1 << 4) /* ISO packet error, ep9 */ 26 #define UFNRH_IPE4 (1 << 3) /* ISO packet error, ep4 */ 27 28 /* pxa255 has this (move to include/asm-arm/arch-pxa/pxa-regs.h) */ 29 #define UDCCFR UDC_RES2 /* UDC Control Function Register */ 30 #define UDCCFR_AREN (1 << 7) /* ACK response enable (now) */ 31 #define UDCCFR_ACM (1 << 2) /* ACK control mode (wait for AREN) */ 32 33 /* latest pxa255 errata define new "must be one" bits in UDCCFR */ 34 #define UDCCFR_MB1 (0xff & ~(UDCCFR_AREN|UDCCFR_ACM)) 35 36 /*-------------------------------------------------------------------------*/ 37 38 struct pxa25x_udc; 39 40 struct pxa25x_ep { 41 struct usb_ep ep; 42 struct pxa25x_udc *dev; 43 44 struct list_head queue; 45 unsigned long pio_irqs; 46 47 unsigned short fifo_size; 48 u8 bEndpointAddress; 49 u8 bmAttributes; 50 51 unsigned stopped : 1; 52 unsigned dma_fixup : 1; 53 54 /* UDCCS = UDC Control/Status for this EP 55 * UBCR = UDC Byte Count Remaining (contents of OUT fifo) 56 * UDDR = UDC Endpoint Data Register (the fifo) 57 * DRCM = DMA Request Channel Map 58 */ 59 u32 regoff_udccs; 60 u32 regoff_ubcr; 61 u32 regoff_uddr; 62 }; 63 64 struct pxa25x_request { 65 struct usb_request req; 66 struct list_head queue; 67 }; 68 69 enum ep0_state { 70 EP0_IDLE, 71 EP0_IN_DATA_PHASE, 72 EP0_OUT_DATA_PHASE, 73 EP0_END_XFER, 74 EP0_STALL, 75 }; 76 77 #define EP0_FIFO_SIZE ((unsigned)16) 78 #define BULK_FIFO_SIZE ((unsigned)64) 79 #define ISO_FIFO_SIZE ((unsigned)256) 80 #define INT_FIFO_SIZE ((unsigned)8) 81 82 struct udc_stats { 83 struct ep0stats { 84 unsigned long ops; 85 unsigned long bytes; 86 } read, write; 87 unsigned long irqs; 88 }; 89 90 #ifdef CONFIG_USB_PXA25X_SMALL 91 /* when memory's tight, SMALL config saves code+data. */ 92 #define PXA_UDC_NUM_ENDPOINTS 3 93 #endif 94 95 #ifndef PXA_UDC_NUM_ENDPOINTS 96 #define PXA_UDC_NUM_ENDPOINTS 16 97 #endif 98 99 struct pxa25x_udc { 100 struct usb_gadget gadget; 101 struct usb_gadget_driver *driver; 102 103 enum ep0_state ep0state; 104 struct udc_stats stats; 105 unsigned got_irq : 1, 106 vbus : 1, 107 pullup : 1, 108 has_cfr : 1, 109 req_pending : 1, 110 req_std : 1, 111 req_config : 1, 112 suspended : 1, 113 active : 1; 114 115 #define start_watchdog(dev) mod_timer(&dev->timer, jiffies + (HZ/200)) 116 struct timer_list timer; 117 118 struct device *dev; 119 struct clk *clk; 120 struct pxa2xx_udc_mach_info *mach; 121 struct usb_phy *transceiver; 122 u64 dma_mask; 123 struct pxa25x_ep ep [PXA_UDC_NUM_ENDPOINTS]; 124 125 #ifdef CONFIG_USB_GADGET_DEBUG_FS 126 struct dentry *debugfs_udc; 127 #endif 128 void __iomem *regs; 129 }; 130 #define to_pxa25x(g) (container_of((g), struct pxa25x_udc, gadget)) 131 132 /*-------------------------------------------------------------------------*/ 133 134 #ifdef CONFIG_ARCH_LUBBOCK 135 #include <mach/lubbock.h> 136 /* lubbock can also report usb connect/disconnect irqs */ 137 #endif 138 139 static struct pxa25x_udc *the_controller; 140 141 /*-------------------------------------------------------------------------*/ 142 143 /* 144 * Debugging support vanishes in non-debug builds. DBG_NORMAL should be 145 * mostly silent during normal use/testing, with no timing side-effects. 146 */ 147 #define DBG_NORMAL 1 /* error paths, device state transitions */ 148 #define DBG_VERBOSE 2 /* add some success path trace info */ 149 #define DBG_NOISY 3 /* ... even more: request level */ 150 #define DBG_VERY_NOISY 4 /* ... even more: packet level */ 151 152 #define DMSG(stuff...) pr_debug("udc: " stuff) 153 154 #ifdef DEBUG 155 156 static const char *state_name[] = { 157 "EP0_IDLE", 158 "EP0_IN_DATA_PHASE", "EP0_OUT_DATA_PHASE", 159 "EP0_END_XFER", "EP0_STALL" 160 }; 161 162 #ifdef VERBOSE_DEBUG 163 # define UDC_DEBUG DBG_VERBOSE 164 #else 165 # define UDC_DEBUG DBG_NORMAL 166 #endif 167 168 static void __maybe_unused 169 dump_udccr(const char *label) 170 { 171 u32 udccr = UDCCR; 172 DMSG("%s %02X =%s%s%s%s%s%s%s%s\n", 173 label, udccr, 174 (udccr & UDCCR_REM) ? " rem" : "", 175 (udccr & UDCCR_RSTIR) ? " rstir" : "", 176 (udccr & UDCCR_SRM) ? " srm" : "", 177 (udccr & UDCCR_SUSIR) ? " susir" : "", 178 (udccr & UDCCR_RESIR) ? " resir" : "", 179 (udccr & UDCCR_RSM) ? " rsm" : "", 180 (udccr & UDCCR_UDA) ? " uda" : "", 181 (udccr & UDCCR_UDE) ? " ude" : ""); 182 } 183 184 static void __maybe_unused 185 dump_udccs0(const char *label) 186 { 187 u32 udccs0 = UDCCS0; 188 189 DMSG("%s %s %02X =%s%s%s%s%s%s%s%s\n", 190 label, state_name[the_controller->ep0state], udccs0, 191 (udccs0 & UDCCS0_SA) ? " sa" : "", 192 (udccs0 & UDCCS0_RNE) ? " rne" : "", 193 (udccs0 & UDCCS0_FST) ? " fst" : "", 194 (udccs0 & UDCCS0_SST) ? " sst" : "", 195 (udccs0 & UDCCS0_DRWF) ? " dwrf" : "", 196 (udccs0 & UDCCS0_FTF) ? " ftf" : "", 197 (udccs0 & UDCCS0_IPR) ? " ipr" : "", 198 (udccs0 & UDCCS0_OPR) ? " opr" : ""); 199 } 200 201 static inline u32 udc_ep_get_UDCCS(struct pxa25x_ep *); 202 203 static void __maybe_unused 204 dump_state(struct pxa25x_udc *dev) 205 { 206 u32 tmp; 207 unsigned i; 208 209 DMSG("%s, uicr %02X.%02X, usir %02X.%02x, ufnr %02X.%02X\n", 210 state_name[dev->ep0state], 211 UICR1, UICR0, USIR1, USIR0, UFNRH, UFNRL); 212 dump_udccr("udccr"); 213 if (dev->has_cfr) { 214 tmp = UDCCFR; 215 DMSG("udccfr %02X =%s%s\n", tmp, 216 (tmp & UDCCFR_AREN) ? " aren" : "", 217 (tmp & UDCCFR_ACM) ? " acm" : ""); 218 } 219 220 if (!dev->driver) { 221 DMSG("no gadget driver bound\n"); 222 return; 223 } else 224 DMSG("ep0 driver '%s'\n", dev->driver->driver.name); 225 226 dump_udccs0 ("udccs0"); 227 DMSG("ep0 IN %lu/%lu, OUT %lu/%lu\n", 228 dev->stats.write.bytes, dev->stats.write.ops, 229 dev->stats.read.bytes, dev->stats.read.ops); 230 231 for (i = 1; i < PXA_UDC_NUM_ENDPOINTS; i++) { 232 if (dev->ep[i].ep.desc == NULL) 233 continue; 234 DMSG ("udccs%d = %02x\n", i, udc_ep_get_UDCCS(&dev->ep[i])); 235 } 236 } 237 238 #else 239 240 #define dump_udccr(x) do{}while(0) 241 #define dump_udccs0(x) do{}while(0) 242 #define dump_state(x) do{}while(0) 243 244 #define UDC_DEBUG ((unsigned)0) 245 246 #endif 247 248 #define DBG(lvl, stuff...) do{if ((lvl) <= UDC_DEBUG) DMSG(stuff);}while(0) 249 250 #define ERR(stuff...) pr_err("udc: " stuff) 251 #define WARNING(stuff...) pr_warning("udc: " stuff) 252 #define INFO(stuff...) pr_info("udc: " stuff) 253 254 255 #endif /* __LINUX_USB_GADGET_PXA25X_H */ 256