1 // SPDX-License-Identifier: GPL-2.0+
2 /*
3  * Intel PXA25x and IXP4xx on-chip full speed USB device controllers
4  *
5  * Copyright (C) 2002 Intrinsyc, Inc. (Frank Becker)
6  * Copyright (C) 2003 Robert Schwebel, Pengutronix
7  * Copyright (C) 2003 Benedikt Spranger, Pengutronix
8  * Copyright (C) 2003 David Brownell
9  * Copyright (C) 2003 Joshua Wise
10  */
11 
12 /* #define VERBOSE_DEBUG */
13 
14 #include <linux/device.h>
15 #include <linux/gpio.h>
16 #include <linux/module.h>
17 #include <linux/kernel.h>
18 #include <linux/ioport.h>
19 #include <linux/types.h>
20 #include <linux/errno.h>
21 #include <linux/err.h>
22 #include <linux/delay.h>
23 #include <linux/slab.h>
24 #include <linux/timer.h>
25 #include <linux/list.h>
26 #include <linux/interrupt.h>
27 #include <linux/mm.h>
28 #include <linux/platform_data/pxa2xx_udc.h>
29 #include <linux/platform_device.h>
30 #include <linux/dma-mapping.h>
31 #include <linux/irq.h>
32 #include <linux/clk.h>
33 #include <linux/seq_file.h>
34 #include <linux/debugfs.h>
35 #include <linux/io.h>
36 #include <linux/prefetch.h>
37 
38 #include <asm/byteorder.h>
39 #include <asm/dma.h>
40 #include <asm/mach-types.h>
41 #include <asm/unaligned.h>
42 
43 #include <linux/usb/ch9.h>
44 #include <linux/usb/gadget.h>
45 #include <linux/usb/otg.h>
46 
47 #define UDCCR	 0x0000 /* UDC Control Register */
48 #define UDC_RES1 0x0004 /* UDC Undocumented - Reserved1 */
49 #define UDC_RES2 0x0008 /* UDC Undocumented - Reserved2 */
50 #define UDC_RES3 0x000C /* UDC Undocumented - Reserved3 */
51 #define UDCCS0	 0x0010 /* UDC Endpoint 0 Control/Status Register */
52 #define UDCCS1	 0x0014 /* UDC Endpoint 1 (IN) Control/Status Register */
53 #define UDCCS2	 0x0018 /* UDC Endpoint 2 (OUT) Control/Status Register */
54 #define UDCCS3	 0x001C /* UDC Endpoint 3 (IN) Control/Status Register */
55 #define UDCCS4	 0x0020 /* UDC Endpoint 4 (OUT) Control/Status Register */
56 #define UDCCS5	 0x0024 /* UDC Endpoint 5 (Interrupt) Control/Status Register */
57 #define UDCCS6	 0x0028 /* UDC Endpoint 6 (IN) Control/Status Register */
58 #define UDCCS7	 0x002C /* UDC Endpoint 7 (OUT) Control/Status Register */
59 #define UDCCS8	 0x0030 /* UDC Endpoint 8 (IN) Control/Status Register */
60 #define UDCCS9	 0x0034 /* UDC Endpoint 9 (OUT) Control/Status Register */
61 #define UDCCS10	 0x0038 /* UDC Endpoint 10 (Interrupt) Control/Status Register */
62 #define UDCCS11	 0x003C /* UDC Endpoint 11 (IN) Control/Status Register */
63 #define UDCCS12	 0x0040 /* UDC Endpoint 12 (OUT) Control/Status Register */
64 #define UDCCS13	 0x0044 /* UDC Endpoint 13 (IN) Control/Status Register */
65 #define UDCCS14	 0x0048 /* UDC Endpoint 14 (OUT) Control/Status Register */
66 #define UDCCS15	 0x004C /* UDC Endpoint 15 (Interrupt) Control/Status Register */
67 #define UFNRH	 0x0060 /* UDC Frame Number Register High */
68 #define UFNRL	 0x0064 /* UDC Frame Number Register Low */
69 #define UBCR2	 0x0068 /* UDC Byte Count Reg 2 */
70 #define UBCR4	 0x006c /* UDC Byte Count Reg 4 */
71 #define UBCR7	 0x0070 /* UDC Byte Count Reg 7 */
72 #define UBCR9	 0x0074 /* UDC Byte Count Reg 9 */
73 #define UBCR12	 0x0078 /* UDC Byte Count Reg 12 */
74 #define UBCR14	 0x007c /* UDC Byte Count Reg 14 */
75 #define UDDR0	 0x0080 /* UDC Endpoint 0 Data Register */
76 #define UDDR1	 0x0100 /* UDC Endpoint 1 Data Register */
77 #define UDDR2	 0x0180 /* UDC Endpoint 2 Data Register */
78 #define UDDR3	 0x0200 /* UDC Endpoint 3 Data Register */
79 #define UDDR4	 0x0400 /* UDC Endpoint 4 Data Register */
80 #define UDDR5	 0x00A0 /* UDC Endpoint 5 Data Register */
81 #define UDDR6	 0x0600 /* UDC Endpoint 6 Data Register */
82 #define UDDR7	 0x0680 /* UDC Endpoint 7 Data Register */
83 #define UDDR8	 0x0700 /* UDC Endpoint 8 Data Register */
84 #define UDDR9	 0x0900 /* UDC Endpoint 9 Data Register */
85 #define UDDR10	 0x00C0 /* UDC Endpoint 10 Data Register */
86 #define UDDR11	 0x0B00 /* UDC Endpoint 11 Data Register */
87 #define UDDR12	 0x0B80 /* UDC Endpoint 12 Data Register */
88 #define UDDR13	 0x0C00 /* UDC Endpoint 13 Data Register */
89 #define UDDR14	 0x0E00 /* UDC Endpoint 14 Data Register */
90 #define UDDR15	 0x00E0 /* UDC Endpoint 15 Data Register */
91 
92 #define UICR0	 0x0050 /* UDC Interrupt Control Register 0 */
93 #define UICR1	 0x0054 /* UDC Interrupt Control Register 1 */
94 
95 #define USIR0	 0x0058 /* UDC Status Interrupt Register 0 */
96 #define USIR1	 0x005C /* UDC Status Interrupt Register 1 */
97 
98 #define UDCCR_UDE	(1 << 0)	/* UDC enable */
99 #define UDCCR_UDA	(1 << 1)	/* UDC active */
100 #define UDCCR_RSM	(1 << 2)	/* Device resume */
101 #define UDCCR_RESIR	(1 << 3)	/* Resume interrupt request */
102 #define UDCCR_SUSIR	(1 << 4)	/* Suspend interrupt request */
103 #define UDCCR_SRM	(1 << 5)	/* Suspend/resume interrupt mask */
104 #define UDCCR_RSTIR	(1 << 6)	/* Reset interrupt request */
105 #define UDCCR_REM	(1 << 7)	/* Reset interrupt mask */
106 
107 #define UDCCS0_OPR	(1 << 0)	/* OUT packet ready */
108 #define UDCCS0_IPR	(1 << 1)	/* IN packet ready */
109 #define UDCCS0_FTF	(1 << 2)	/* Flush Tx FIFO */
110 #define UDCCS0_DRWF	(1 << 3)	/* Device remote wakeup feature */
111 #define UDCCS0_SST	(1 << 4)	/* Sent stall */
112 #define UDCCS0_FST	(1 << 5)	/* Force stall */
113 #define UDCCS0_RNE	(1 << 6)	/* Receive FIFO no empty */
114 #define UDCCS0_SA	(1 << 7)	/* Setup active */
115 
116 #define UDCCS_BI_TFS	(1 << 0)	/* Transmit FIFO service */
117 #define UDCCS_BI_TPC	(1 << 1)	/* Transmit packet complete */
118 #define UDCCS_BI_FTF	(1 << 2)	/* Flush Tx FIFO */
119 #define UDCCS_BI_TUR	(1 << 3)	/* Transmit FIFO underrun */
120 #define UDCCS_BI_SST	(1 << 4)	/* Sent stall */
121 #define UDCCS_BI_FST	(1 << 5)	/* Force stall */
122 #define UDCCS_BI_TSP	(1 << 7)	/* Transmit short packet */
123 
124 #define UDCCS_BO_RFS	(1 << 0)	/* Receive FIFO service */
125 #define UDCCS_BO_RPC	(1 << 1)	/* Receive packet complete */
126 #define UDCCS_BO_DME	(1 << 3)	/* DMA enable */
127 #define UDCCS_BO_SST	(1 << 4)	/* Sent stall */
128 #define UDCCS_BO_FST	(1 << 5)	/* Force stall */
129 #define UDCCS_BO_RNE	(1 << 6)	/* Receive FIFO not empty */
130 #define UDCCS_BO_RSP	(1 << 7)	/* Receive short packet */
131 
132 #define UDCCS_II_TFS	(1 << 0)	/* Transmit FIFO service */
133 #define UDCCS_II_TPC	(1 << 1)	/* Transmit packet complete */
134 #define UDCCS_II_FTF	(1 << 2)	/* Flush Tx FIFO */
135 #define UDCCS_II_TUR	(1 << 3)	/* Transmit FIFO underrun */
136 #define UDCCS_II_TSP	(1 << 7)	/* Transmit short packet */
137 
138 #define UDCCS_IO_RFS	(1 << 0)	/* Receive FIFO service */
139 #define UDCCS_IO_RPC	(1 << 1)	/* Receive packet complete */
140 #ifdef CONFIG_ARCH_IXP4XX /* FIXME: is this right?, datasheed says '2' */
141 #define UDCCS_IO_ROF	(1 << 3)	/* Receive overflow */
142 #endif
143 #ifdef CONFIG_ARCH_PXA
144 #define UDCCS_IO_ROF	(1 << 2)	/* Receive overflow */
145 #endif
146 #define UDCCS_IO_DME	(1 << 3)	/* DMA enable */
147 #define UDCCS_IO_RNE	(1 << 6)	/* Receive FIFO not empty */
148 #define UDCCS_IO_RSP	(1 << 7)	/* Receive short packet */
149 
150 #define UDCCS_INT_TFS	(1 << 0)	/* Transmit FIFO service */
151 #define UDCCS_INT_TPC	(1 << 1)	/* Transmit packet complete */
152 #define UDCCS_INT_FTF	(1 << 2)	/* Flush Tx FIFO */
153 #define UDCCS_INT_TUR	(1 << 3)	/* Transmit FIFO underrun */
154 #define UDCCS_INT_SST	(1 << 4)	/* Sent stall */
155 #define UDCCS_INT_FST	(1 << 5)	/* Force stall */
156 #define UDCCS_INT_TSP	(1 << 7)	/* Transmit short packet */
157 
158 #define UICR0_IM0	(1 << 0)	/* Interrupt mask ep 0 */
159 #define UICR0_IM1	(1 << 1)	/* Interrupt mask ep 1 */
160 #define UICR0_IM2	(1 << 2)	/* Interrupt mask ep 2 */
161 #define UICR0_IM3	(1 << 3)	/* Interrupt mask ep 3 */
162 #define UICR0_IM4	(1 << 4)	/* Interrupt mask ep 4 */
163 #define UICR0_IM5	(1 << 5)	/* Interrupt mask ep 5 */
164 #define UICR0_IM6	(1 << 6)	/* Interrupt mask ep 6 */
165 #define UICR0_IM7	(1 << 7)	/* Interrupt mask ep 7 */
166 
167 #define UICR1_IM8	(1 << 0)	/* Interrupt mask ep 8 */
168 #define UICR1_IM9	(1 << 1)	/* Interrupt mask ep 9 */
169 #define UICR1_IM10	(1 << 2)	/* Interrupt mask ep 10 */
170 #define UICR1_IM11	(1 << 3)	/* Interrupt mask ep 11 */
171 #define UICR1_IM12	(1 << 4)	/* Interrupt mask ep 12 */
172 #define UICR1_IM13	(1 << 5)	/* Interrupt mask ep 13 */
173 #define UICR1_IM14	(1 << 6)	/* Interrupt mask ep 14 */
174 #define UICR1_IM15	(1 << 7)	/* Interrupt mask ep 15 */
175 
176 #define USIR0_IR0	(1 << 0)	/* Interrupt request ep 0 */
177 #define USIR0_IR1	(1 << 1)	/* Interrupt request ep 1 */
178 #define USIR0_IR2	(1 << 2)	/* Interrupt request ep 2 */
179 #define USIR0_IR3	(1 << 3)	/* Interrupt request ep 3 */
180 #define USIR0_IR4	(1 << 4)	/* Interrupt request ep 4 */
181 #define USIR0_IR5	(1 << 5)	/* Interrupt request ep 5 */
182 #define USIR0_IR6	(1 << 6)	/* Interrupt request ep 6 */
183 #define USIR0_IR7	(1 << 7)	/* Interrupt request ep 7 */
184 
185 #define USIR1_IR8	(1 << 0)	/* Interrupt request ep 8 */
186 #define USIR1_IR9	(1 << 1)	/* Interrupt request ep 9 */
187 #define USIR1_IR10	(1 << 2)	/* Interrupt request ep 10 */
188 #define USIR1_IR11	(1 << 3)	/* Interrupt request ep 11 */
189 #define USIR1_IR12	(1 << 4)	/* Interrupt request ep 12 */
190 #define USIR1_IR13	(1 << 5)	/* Interrupt request ep 13 */
191 #define USIR1_IR14	(1 << 6)	/* Interrupt request ep 14 */
192 #define USIR1_IR15	(1 << 7)	/* Interrupt request ep 15 */
193 
194 /*
195  * This driver handles the USB Device Controller (UDC) in Intel's PXA 25x
196  * series processors.  The UDC for the IXP 4xx series is very similar.
197  * There are fifteen endpoints, in addition to ep0.
198  *
199  * Such controller drivers work with a gadget driver.  The gadget driver
200  * returns descriptors, implements configuration and data protocols used
201  * by the host to interact with this device, and allocates endpoints to
202  * the different protocol interfaces.  The controller driver virtualizes
203  * usb hardware so that the gadget drivers will be more portable.
204  *
205  * This UDC hardware wants to implement a bit too much USB protocol, so
206  * it constrains the sorts of USB configuration change events that work.
207  * The errata for these chips are misleading; some "fixed" bugs from
208  * pxa250 a0/a1 b0/b1/b2 sure act like they're still there.
209  *
210  * Note that the UDC hardware supports DMA (except on IXP) but that's
211  * not used here.  IN-DMA (to host) is simple enough, when the data is
212  * suitably aligned (16 bytes) ... the network stack doesn't do that,
213  * other software can.  OUT-DMA is buggy in most chip versions, as well
214  * as poorly designed (data toggle not automatic).  So this driver won't
215  * bother using DMA.  (Mostly-working IN-DMA support was available in
216  * kernels before 2.6.23, but was never enabled or well tested.)
217  */
218 
219 #define	DRIVER_VERSION	"30-June-2007"
220 #define	DRIVER_DESC	"PXA 25x USB Device Controller driver"
221 
222 
223 static const char driver_name [] = "pxa25x_udc";
224 
225 static const char ep0name [] = "ep0";
226 
227 
228 #ifdef CONFIG_ARCH_IXP4XX
229 
230 /* cpu-specific register addresses are compiled in to this code */
231 #ifdef CONFIG_ARCH_PXA
232 #error "Can't configure both IXP and PXA"
233 #endif
234 
235 /* IXP doesn't yet support <linux/clk.h> */
236 #define clk_get(dev,name)	NULL
237 #define clk_enable(clk)		do { } while (0)
238 #define clk_disable(clk)	do { } while (0)
239 #define clk_put(clk)		do { } while (0)
240 
241 #endif
242 
243 #include "pxa25x_udc.h"
244 
245 
246 #ifdef	CONFIG_USB_PXA25X_SMALL
247 #define SIZE_STR	" (small)"
248 #else
249 #define SIZE_STR	""
250 #endif
251 
252 /* ---------------------------------------------------------------------------
253  *	endpoint related parts of the api to the usb controller hardware,
254  *	used by gadget driver; and the inner talker-to-hardware core.
255  * ---------------------------------------------------------------------------
256  */
257 
258 static void pxa25x_ep_fifo_flush (struct usb_ep *ep);
259 static void nuke (struct pxa25x_ep *, int status);
260 
261 /* one GPIO should control a D+ pullup, so host sees this device (or not) */
262 static void pullup_off(void)
263 {
264 	struct pxa2xx_udc_mach_info		*mach = the_controller->mach;
265 	int off_level = mach->gpio_pullup_inverted;
266 
267 	if (gpio_is_valid(mach->gpio_pullup))
268 		gpio_set_value(mach->gpio_pullup, off_level);
269 	else if (mach->udc_command)
270 		mach->udc_command(PXA2XX_UDC_CMD_DISCONNECT);
271 }
272 
273 static void pullup_on(void)
274 {
275 	struct pxa2xx_udc_mach_info		*mach = the_controller->mach;
276 	int on_level = !mach->gpio_pullup_inverted;
277 
278 	if (gpio_is_valid(mach->gpio_pullup))
279 		gpio_set_value(mach->gpio_pullup, on_level);
280 	else if (mach->udc_command)
281 		mach->udc_command(PXA2XX_UDC_CMD_CONNECT);
282 }
283 
284 #if defined(CONFIG_CPU_BIG_ENDIAN)
285 /*
286  * IXP4xx has its buses wired up in a way that relies on never doing any
287  * byte swaps, independent of whether it runs in big-endian or little-endian
288  * mode, as explained by Krzysztof Hałasa.
289  *
290  * We only support pxa25x in little-endian mode, but it is very likely
291  * that it works the same way.
292  */
293 static inline void udc_set_reg(struct pxa25x_udc *dev, u32 reg, u32 val)
294 {
295 	iowrite32be(val, dev->regs + reg);
296 }
297 
298 static inline u32 udc_get_reg(struct pxa25x_udc *dev, u32 reg)
299 {
300 	return ioread32be(dev->regs + reg);
301 }
302 #else
303 static inline void udc_set_reg(struct pxa25x_udc *dev, u32 reg, u32 val)
304 {
305 	writel(val, dev->regs + reg);
306 }
307 
308 static inline u32 udc_get_reg(struct pxa25x_udc *dev, u32 reg)
309 {
310 	return readl(dev->regs + reg);
311 }
312 #endif
313 
314 static void pio_irq_enable(struct pxa25x_ep *ep)
315 {
316 	u32 bEndpointAddress = ep->bEndpointAddress & 0xf;
317 
318         if (bEndpointAddress < 8)
319 		udc_set_reg(ep->dev, UICR0, udc_get_reg(ep->dev, UICR0) &
320 						~(1 << bEndpointAddress));
321         else {
322                 bEndpointAddress -= 8;
323 		udc_set_reg(ep->dev, UICR1, udc_get_reg(ep->dev, UICR1) &
324 						~(1 << bEndpointAddress));
325 	}
326 }
327 
328 static void pio_irq_disable(struct pxa25x_ep *ep)
329 {
330 	u32 bEndpointAddress = ep->bEndpointAddress & 0xf;
331 
332         if (bEndpointAddress < 8)
333                 udc_set_reg(ep->dev, UICR0, udc_get_reg(ep->dev, UICR0) |
334 						(1 << bEndpointAddress));
335         else {
336                 bEndpointAddress -= 8;
337                 udc_set_reg(ep->dev, UICR1, udc_get_reg(ep->dev, UICR1) |
338 						(1 << bEndpointAddress));
339         }
340 }
341 
342 /* The UDCCR reg contains mask and interrupt status bits,
343  * so using '|=' isn't safe as it may ack an interrupt.
344  */
345 #define UDCCR_MASK_BITS         (UDCCR_REM | UDCCR_SRM | UDCCR_UDE)
346 
347 static inline void udc_set_mask_UDCCR(struct pxa25x_udc *dev, int mask)
348 {
349 	u32 udccr = udc_get_reg(dev, UDCCR);
350 
351 	udc_set_reg(dev, (udccr & UDCCR_MASK_BITS) | (mask & UDCCR_MASK_BITS), UDCCR);
352 }
353 
354 static inline void udc_clear_mask_UDCCR(struct pxa25x_udc *dev, int mask)
355 {
356 	u32 udccr = udc_get_reg(dev, UDCCR);
357 
358 	udc_set_reg(dev, (udccr & UDCCR_MASK_BITS) & ~(mask & UDCCR_MASK_BITS), UDCCR);
359 }
360 
361 static inline void udc_ack_int_UDCCR(struct pxa25x_udc *dev, int mask)
362 {
363 	/* udccr contains the bits we dont want to change */
364 	u32 udccr = udc_get_reg(dev, UDCCR) & UDCCR_MASK_BITS;
365 
366 	udc_set_reg(dev, udccr | (mask & ~UDCCR_MASK_BITS), UDCCR);
367 }
368 
369 static inline u32 udc_ep_get_UDCCS(struct pxa25x_ep *ep)
370 {
371 	return udc_get_reg(ep->dev, ep->regoff_udccs);
372 }
373 
374 static inline void udc_ep_set_UDCCS(struct pxa25x_ep *ep, u32 data)
375 {
376 	udc_set_reg(ep->dev, data, ep->regoff_udccs);
377 }
378 
379 static inline u32 udc_ep0_get_UDCCS(struct pxa25x_udc *dev)
380 {
381 	return udc_get_reg(dev, UDCCS0);
382 }
383 
384 static inline void udc_ep0_set_UDCCS(struct pxa25x_udc *dev, u32 data)
385 {
386 	udc_set_reg(dev, data, UDCCS0);
387 }
388 
389 static inline u32 udc_ep_get_UDDR(struct pxa25x_ep *ep)
390 {
391 	return udc_get_reg(ep->dev, ep->regoff_uddr);
392 }
393 
394 static inline void udc_ep_set_UDDR(struct pxa25x_ep *ep, u32 data)
395 {
396 	udc_set_reg(ep->dev, data, ep->regoff_uddr);
397 }
398 
399 static inline u32 udc_ep_get_UBCR(struct pxa25x_ep *ep)
400 {
401 	return udc_get_reg(ep->dev, ep->regoff_ubcr);
402 }
403 
404 /*
405  * endpoint enable/disable
406  *
407  * we need to verify the descriptors used to enable endpoints.  since pxa25x
408  * endpoint configurations are fixed, and are pretty much always enabled,
409  * there's not a lot to manage here.
410  *
411  * because pxa25x can't selectively initialize bulk (or interrupt) endpoints,
412  * (resetting endpoint halt and toggle), SET_INTERFACE is unusable except
413  * for a single interface (with only the default altsetting) and for gadget
414  * drivers that don't halt endpoints (not reset by set_interface).  that also
415  * means that if you use ISO, you must violate the USB spec rule that all
416  * iso endpoints must be in non-default altsettings.
417  */
418 static int pxa25x_ep_enable (struct usb_ep *_ep,
419 		const struct usb_endpoint_descriptor *desc)
420 {
421 	struct pxa25x_ep        *ep;
422 	struct pxa25x_udc       *dev;
423 
424 	ep = container_of (_ep, struct pxa25x_ep, ep);
425 	if (!_ep || !desc || _ep->name == ep0name
426 			|| desc->bDescriptorType != USB_DT_ENDPOINT
427 			|| ep->bEndpointAddress != desc->bEndpointAddress
428 			|| ep->fifo_size < usb_endpoint_maxp (desc)) {
429 		DMSG("%s, bad ep or descriptor\n", __func__);
430 		return -EINVAL;
431 	}
432 
433 	/* xfer types must match, except that interrupt ~= bulk */
434 	if (ep->bmAttributes != desc->bmAttributes
435 			&& ep->bmAttributes != USB_ENDPOINT_XFER_BULK
436 			&& desc->bmAttributes != USB_ENDPOINT_XFER_INT) {
437 		DMSG("%s, %s type mismatch\n", __func__, _ep->name);
438 		return -EINVAL;
439 	}
440 
441 	/* hardware _could_ do smaller, but driver doesn't */
442 	if ((desc->bmAttributes == USB_ENDPOINT_XFER_BULK
443 				&& usb_endpoint_maxp (desc)
444 						!= BULK_FIFO_SIZE)
445 			|| !desc->wMaxPacketSize) {
446 		DMSG("%s, bad %s maxpacket\n", __func__, _ep->name);
447 		return -ERANGE;
448 	}
449 
450 	dev = ep->dev;
451 	if (!dev->driver || dev->gadget.speed == USB_SPEED_UNKNOWN) {
452 		DMSG("%s, bogus device state\n", __func__);
453 		return -ESHUTDOWN;
454 	}
455 
456 	ep->ep.desc = desc;
457 	ep->stopped = 0;
458 	ep->pio_irqs = 0;
459 	ep->ep.maxpacket = usb_endpoint_maxp (desc);
460 
461 	/* flush fifo (mostly for OUT buffers) */
462 	pxa25x_ep_fifo_flush (_ep);
463 
464 	/* ... reset halt state too, if we could ... */
465 
466 	DBG(DBG_VERBOSE, "enabled %s\n", _ep->name);
467 	return 0;
468 }
469 
470 static int pxa25x_ep_disable (struct usb_ep *_ep)
471 {
472 	struct pxa25x_ep	*ep;
473 	unsigned long		flags;
474 
475 	ep = container_of (_ep, struct pxa25x_ep, ep);
476 	if (!_ep || !ep->ep.desc) {
477 		DMSG("%s, %s not enabled\n", __func__,
478 			_ep ? ep->ep.name : NULL);
479 		return -EINVAL;
480 	}
481 	local_irq_save(flags);
482 
483 	nuke (ep, -ESHUTDOWN);
484 
485 	/* flush fifo (mostly for IN buffers) */
486 	pxa25x_ep_fifo_flush (_ep);
487 
488 	ep->ep.desc = NULL;
489 	ep->stopped = 1;
490 
491 	local_irq_restore(flags);
492 	DBG(DBG_VERBOSE, "%s disabled\n", _ep->name);
493 	return 0;
494 }
495 
496 /*-------------------------------------------------------------------------*/
497 
498 /* for the pxa25x, these can just wrap kmalloc/kfree.  gadget drivers
499  * must still pass correctly initialized endpoints, since other controller
500  * drivers may care about how it's currently set up (dma issues etc).
501  */
502 
503 /*
504  *	pxa25x_ep_alloc_request - allocate a request data structure
505  */
506 static struct usb_request *
507 pxa25x_ep_alloc_request (struct usb_ep *_ep, gfp_t gfp_flags)
508 {
509 	struct pxa25x_request *req;
510 
511 	req = kzalloc(sizeof(*req), gfp_flags);
512 	if (!req)
513 		return NULL;
514 
515 	INIT_LIST_HEAD (&req->queue);
516 	return &req->req;
517 }
518 
519 
520 /*
521  *	pxa25x_ep_free_request - deallocate a request data structure
522  */
523 static void
524 pxa25x_ep_free_request (struct usb_ep *_ep, struct usb_request *_req)
525 {
526 	struct pxa25x_request	*req;
527 
528 	req = container_of (_req, struct pxa25x_request, req);
529 	WARN_ON(!list_empty (&req->queue));
530 	kfree(req);
531 }
532 
533 /*-------------------------------------------------------------------------*/
534 
535 /*
536  *	done - retire a request; caller blocked irqs
537  */
538 static void done(struct pxa25x_ep *ep, struct pxa25x_request *req, int status)
539 {
540 	unsigned		stopped = ep->stopped;
541 
542 	list_del_init(&req->queue);
543 
544 	if (likely (req->req.status == -EINPROGRESS))
545 		req->req.status = status;
546 	else
547 		status = req->req.status;
548 
549 	if (status && status != -ESHUTDOWN)
550 		DBG(DBG_VERBOSE, "complete %s req %p stat %d len %u/%u\n",
551 			ep->ep.name, &req->req, status,
552 			req->req.actual, req->req.length);
553 
554 	/* don't modify queue heads during completion callback */
555 	ep->stopped = 1;
556 	usb_gadget_giveback_request(&ep->ep, &req->req);
557 	ep->stopped = stopped;
558 }
559 
560 
561 static inline void ep0_idle (struct pxa25x_udc *dev)
562 {
563 	dev->ep0state = EP0_IDLE;
564 }
565 
566 static int
567 write_packet(struct pxa25x_ep *ep, struct pxa25x_request *req, unsigned max)
568 {
569 	u8		*buf;
570 	unsigned	length, count;
571 
572 	buf = req->req.buf + req->req.actual;
573 	prefetch(buf);
574 
575 	/* how big will this packet be? */
576 	length = min(req->req.length - req->req.actual, max);
577 	req->req.actual += length;
578 
579 	count = length;
580 	while (likely(count--))
581 		udc_ep_set_UDDR(ep, *buf++);
582 
583 	return length;
584 }
585 
586 /*
587  * write to an IN endpoint fifo, as many packets as possible.
588  * irqs will use this to write the rest later.
589  * caller guarantees at least one packet buffer is ready (or a zlp).
590  */
591 static int
592 write_fifo (struct pxa25x_ep *ep, struct pxa25x_request *req)
593 {
594 	unsigned		max;
595 
596 	max = usb_endpoint_maxp(ep->ep.desc);
597 	do {
598 		unsigned	count;
599 		int		is_last, is_short;
600 
601 		count = write_packet(ep, req, max);
602 
603 		/* last packet is usually short (or a zlp) */
604 		if (unlikely (count != max))
605 			is_last = is_short = 1;
606 		else {
607 			if (likely(req->req.length != req->req.actual)
608 					|| req->req.zero)
609 				is_last = 0;
610 			else
611 				is_last = 1;
612 			/* interrupt/iso maxpacket may not fill the fifo */
613 			is_short = unlikely (max < ep->fifo_size);
614 		}
615 
616 		DBG(DBG_VERY_NOISY, "wrote %s %d bytes%s%s %d left %p\n",
617 			ep->ep.name, count,
618 			is_last ? "/L" : "", is_short ? "/S" : "",
619 			req->req.length - req->req.actual, req);
620 
621 		/* let loose that packet. maybe try writing another one,
622 		 * double buffering might work.  TSP, TPC, and TFS
623 		 * bit values are the same for all normal IN endpoints.
624 		 */
625 		udc_ep_set_UDCCS(ep, UDCCS_BI_TPC);
626 		if (is_short)
627 			udc_ep_set_UDCCS(ep, UDCCS_BI_TSP);
628 
629 		/* requests complete when all IN data is in the FIFO */
630 		if (is_last) {
631 			done (ep, req, 0);
632 			if (list_empty(&ep->queue))
633 				pio_irq_disable(ep);
634 			return 1;
635 		}
636 
637 		// TODO experiment: how robust can fifo mode tweaking be?
638 		// double buffering is off in the default fifo mode, which
639 		// prevents TFS from being set here.
640 
641 	} while (udc_ep_get_UDCCS(ep) & UDCCS_BI_TFS);
642 	return 0;
643 }
644 
645 /* caller asserts req->pending (ep0 irq status nyet cleared); starts
646  * ep0 data stage.  these chips want very simple state transitions.
647  */
648 static inline
649 void ep0start(struct pxa25x_udc *dev, u32 flags, const char *tag)
650 {
651 	udc_ep0_set_UDCCS(dev, flags|UDCCS0_SA|UDCCS0_OPR);
652 	udc_set_reg(dev, USIR0, USIR0_IR0);
653 	dev->req_pending = 0;
654 	DBG(DBG_VERY_NOISY, "%s %s, %02x/%02x\n",
655 		__func__, tag, udc_ep0_get_UDCCS(dev), flags);
656 }
657 
658 static int
659 write_ep0_fifo (struct pxa25x_ep *ep, struct pxa25x_request *req)
660 {
661 	struct pxa25x_udc *dev = ep->dev;
662 	unsigned	count;
663 	int		is_short;
664 
665 	count = write_packet(&dev->ep[0], req, EP0_FIFO_SIZE);
666 	ep->dev->stats.write.bytes += count;
667 
668 	/* last packet "must be" short (or a zlp) */
669 	is_short = (count != EP0_FIFO_SIZE);
670 
671 	DBG(DBG_VERY_NOISY, "ep0in %d bytes %d left %p\n", count,
672 		req->req.length - req->req.actual, req);
673 
674 	if (unlikely (is_short)) {
675 		if (ep->dev->req_pending)
676 			ep0start(ep->dev, UDCCS0_IPR, "short IN");
677 		else
678 			udc_ep0_set_UDCCS(dev, UDCCS0_IPR);
679 
680 		count = req->req.length;
681 		done (ep, req, 0);
682 		ep0_idle(ep->dev);
683 #ifndef CONFIG_ARCH_IXP4XX
684 #if 1
685 		/* This seems to get rid of lost status irqs in some cases:
686 		 * host responds quickly, or next request involves config
687 		 * change automagic, or should have been hidden, or ...
688 		 *
689 		 * FIXME get rid of all udelays possible...
690 		 */
691 		if (count >= EP0_FIFO_SIZE) {
692 			count = 100;
693 			do {
694 				if ((udc_ep0_get_UDCCS(dev) & UDCCS0_OPR) != 0) {
695 					/* clear OPR, generate ack */
696 					udc_ep0_set_UDCCS(dev, UDCCS0_OPR);
697 					break;
698 				}
699 				count--;
700 				udelay(1);
701 			} while (count);
702 		}
703 #endif
704 #endif
705 	} else if (ep->dev->req_pending)
706 		ep0start(ep->dev, 0, "IN");
707 	return is_short;
708 }
709 
710 
711 /*
712  * read_fifo -  unload packet(s) from the fifo we use for usb OUT
713  * transfers and put them into the request.  caller should have made
714  * sure there's at least one packet ready.
715  *
716  * returns true if the request completed because of short packet or the
717  * request buffer having filled (and maybe overran till end-of-packet).
718  */
719 static int
720 read_fifo (struct pxa25x_ep *ep, struct pxa25x_request *req)
721 {
722 	for (;;) {
723 		u32		udccs;
724 		u8		*buf;
725 		unsigned	bufferspace, count, is_short;
726 
727 		/* make sure there's a packet in the FIFO.
728 		 * UDCCS_{BO,IO}_RPC are all the same bit value.
729 		 * UDCCS_{BO,IO}_RNE are all the same bit value.
730 		 */
731 		udccs = udc_ep_get_UDCCS(ep);
732 		if (unlikely ((udccs & UDCCS_BO_RPC) == 0))
733 			break;
734 		buf = req->req.buf + req->req.actual;
735 		prefetchw(buf);
736 		bufferspace = req->req.length - req->req.actual;
737 
738 		/* read all bytes from this packet */
739 		if (likely (udccs & UDCCS_BO_RNE)) {
740 			count = 1 + (0x0ff & udc_ep_get_UBCR(ep));
741 			req->req.actual += min (count, bufferspace);
742 		} else /* zlp */
743 			count = 0;
744 		is_short = (count < ep->ep.maxpacket);
745 		DBG(DBG_VERY_NOISY, "read %s %02x, %d bytes%s req %p %d/%d\n",
746 			ep->ep.name, udccs, count,
747 			is_short ? "/S" : "",
748 			req, req->req.actual, req->req.length);
749 		while (likely (count-- != 0)) {
750 			u8	byte = (u8) udc_ep_get_UDDR(ep);
751 
752 			if (unlikely (bufferspace == 0)) {
753 				/* this happens when the driver's buffer
754 				 * is smaller than what the host sent.
755 				 * discard the extra data.
756 				 */
757 				if (req->req.status != -EOVERFLOW)
758 					DMSG("%s overflow %d\n",
759 						ep->ep.name, count);
760 				req->req.status = -EOVERFLOW;
761 			} else {
762 				*buf++ = byte;
763 				bufferspace--;
764 			}
765 		}
766 		udc_ep_set_UDCCS(ep, UDCCS_BO_RPC);
767 		/* RPC/RSP/RNE could now reflect the other packet buffer */
768 
769 		/* iso is one request per packet */
770 		if (ep->bmAttributes == USB_ENDPOINT_XFER_ISOC) {
771 			if (udccs & UDCCS_IO_ROF)
772 				req->req.status = -EHOSTUNREACH;
773 			/* more like "is_done" */
774 			is_short = 1;
775 		}
776 
777 		/* completion */
778 		if (is_short || req->req.actual == req->req.length) {
779 			done (ep, req, 0);
780 			if (list_empty(&ep->queue))
781 				pio_irq_disable(ep);
782 			return 1;
783 		}
784 
785 		/* finished that packet.  the next one may be waiting... */
786 	}
787 	return 0;
788 }
789 
790 /*
791  * special ep0 version of the above.  no UBCR0 or double buffering; status
792  * handshaking is magic.  most device protocols don't need control-OUT.
793  * CDC vendor commands (and RNDIS), mass storage CB/CBI, and some other
794  * protocols do use them.
795  */
796 static int
797 read_ep0_fifo (struct pxa25x_ep *ep, struct pxa25x_request *req)
798 {
799 	u8		*buf, byte;
800 	unsigned	bufferspace;
801 
802 	buf = req->req.buf + req->req.actual;
803 	bufferspace = req->req.length - req->req.actual;
804 
805 	while (udc_ep_get_UDCCS(ep) & UDCCS0_RNE) {
806 		byte = (u8) UDDR0;
807 
808 		if (unlikely (bufferspace == 0)) {
809 			/* this happens when the driver's buffer
810 			 * is smaller than what the host sent.
811 			 * discard the extra data.
812 			 */
813 			if (req->req.status != -EOVERFLOW)
814 				DMSG("%s overflow\n", ep->ep.name);
815 			req->req.status = -EOVERFLOW;
816 		} else {
817 			*buf++ = byte;
818 			req->req.actual++;
819 			bufferspace--;
820 		}
821 	}
822 
823 	udc_ep_set_UDCCS(ep, UDCCS0_OPR | UDCCS0_IPR);
824 
825 	/* completion */
826 	if (req->req.actual >= req->req.length)
827 		return 1;
828 
829 	/* finished that packet.  the next one may be waiting... */
830 	return 0;
831 }
832 
833 /*-------------------------------------------------------------------------*/
834 
835 static int
836 pxa25x_ep_queue(struct usb_ep *_ep, struct usb_request *_req, gfp_t gfp_flags)
837 {
838 	struct pxa25x_request	*req;
839 	struct pxa25x_ep	*ep;
840 	struct pxa25x_udc	*dev;
841 	unsigned long		flags;
842 
843 	req = container_of(_req, struct pxa25x_request, req);
844 	if (unlikely (!_req || !_req->complete || !_req->buf
845 			|| !list_empty(&req->queue))) {
846 		DMSG("%s, bad params\n", __func__);
847 		return -EINVAL;
848 	}
849 
850 	ep = container_of(_ep, struct pxa25x_ep, ep);
851 	if (unlikely(!_ep || (!ep->ep.desc && ep->ep.name != ep0name))) {
852 		DMSG("%s, bad ep\n", __func__);
853 		return -EINVAL;
854 	}
855 
856 	dev = ep->dev;
857 	if (unlikely (!dev->driver
858 			|| dev->gadget.speed == USB_SPEED_UNKNOWN)) {
859 		DMSG("%s, bogus device state\n", __func__);
860 		return -ESHUTDOWN;
861 	}
862 
863 	/* iso is always one packet per request, that's the only way
864 	 * we can report per-packet status.  that also helps with dma.
865 	 */
866 	if (unlikely (ep->bmAttributes == USB_ENDPOINT_XFER_ISOC
867 			&& req->req.length > usb_endpoint_maxp(ep->ep.desc)))
868 		return -EMSGSIZE;
869 
870 	DBG(DBG_NOISY, "%s queue req %p, len %d buf %p\n",
871 		_ep->name, _req, _req->length, _req->buf);
872 
873 	local_irq_save(flags);
874 
875 	_req->status = -EINPROGRESS;
876 	_req->actual = 0;
877 
878 	/* kickstart this i/o queue? */
879 	if (list_empty(&ep->queue) && !ep->stopped) {
880 		if (ep->ep.desc == NULL/* ep0 */) {
881 			unsigned	length = _req->length;
882 
883 			switch (dev->ep0state) {
884 			case EP0_IN_DATA_PHASE:
885 				dev->stats.write.ops++;
886 				if (write_ep0_fifo(ep, req))
887 					req = NULL;
888 				break;
889 
890 			case EP0_OUT_DATA_PHASE:
891 				dev->stats.read.ops++;
892 				/* messy ... */
893 				if (dev->req_config) {
894 					DBG(DBG_VERBOSE, "ep0 config ack%s\n",
895 						dev->has_cfr ?  "" : " raced");
896 					if (dev->has_cfr)
897 						udc_set_reg(dev, UDCCFR, UDCCFR_AREN |
898 							    UDCCFR_ACM | UDCCFR_MB1);
899 					done(ep, req, 0);
900 					dev->ep0state = EP0_END_XFER;
901 					local_irq_restore (flags);
902 					return 0;
903 				}
904 				if (dev->req_pending)
905 					ep0start(dev, UDCCS0_IPR, "OUT");
906 				if (length == 0 || ((udc_ep0_get_UDCCS(dev) & UDCCS0_RNE) != 0
907 						&& read_ep0_fifo(ep, req))) {
908 					ep0_idle(dev);
909 					done(ep, req, 0);
910 					req = NULL;
911 				}
912 				break;
913 
914 			default:
915 				DMSG("ep0 i/o, odd state %d\n", dev->ep0state);
916 				local_irq_restore (flags);
917 				return -EL2HLT;
918 			}
919 		/* can the FIFO can satisfy the request immediately? */
920 		} else if ((ep->bEndpointAddress & USB_DIR_IN) != 0) {
921 			if ((udc_ep_get_UDCCS(ep) & UDCCS_BI_TFS) != 0
922 					&& write_fifo(ep, req))
923 				req = NULL;
924 		} else if ((udc_ep_get_UDCCS(ep) & UDCCS_BO_RFS) != 0
925 				&& read_fifo(ep, req)) {
926 			req = NULL;
927 		}
928 
929 		if (likely(req && ep->ep.desc))
930 			pio_irq_enable(ep);
931 	}
932 
933 	/* pio or dma irq handler advances the queue. */
934 	if (likely(req != NULL))
935 		list_add_tail(&req->queue, &ep->queue);
936 	local_irq_restore(flags);
937 
938 	return 0;
939 }
940 
941 
942 /*
943  *	nuke - dequeue ALL requests
944  */
945 static void nuke(struct pxa25x_ep *ep, int status)
946 {
947 	struct pxa25x_request *req;
948 
949 	/* called with irqs blocked */
950 	while (!list_empty(&ep->queue)) {
951 		req = list_entry(ep->queue.next,
952 				struct pxa25x_request,
953 				queue);
954 		done(ep, req, status);
955 	}
956 	if (ep->ep.desc)
957 		pio_irq_disable(ep);
958 }
959 
960 
961 /* dequeue JUST ONE request */
962 static int pxa25x_ep_dequeue(struct usb_ep *_ep, struct usb_request *_req)
963 {
964 	struct pxa25x_ep	*ep;
965 	struct pxa25x_request	*req = NULL;
966 	struct pxa25x_request	*iter;
967 	unsigned long		flags;
968 
969 	ep = container_of(_ep, struct pxa25x_ep, ep);
970 	if (!_ep || ep->ep.name == ep0name)
971 		return -EINVAL;
972 
973 	local_irq_save(flags);
974 
975 	/* make sure it's actually queued on this endpoint */
976 	list_for_each_entry(iter, &ep->queue, queue) {
977 		if (&iter->req != _req)
978 			continue;
979 		req = iter;
980 		break;
981 	}
982 	if (!req) {
983 		local_irq_restore(flags);
984 		return -EINVAL;
985 	}
986 
987 	done(ep, req, -ECONNRESET);
988 
989 	local_irq_restore(flags);
990 	return 0;
991 }
992 
993 /*-------------------------------------------------------------------------*/
994 
995 static int pxa25x_ep_set_halt(struct usb_ep *_ep, int value)
996 {
997 	struct pxa25x_ep	*ep;
998 	unsigned long		flags;
999 
1000 	ep = container_of(_ep, struct pxa25x_ep, ep);
1001 	if (unlikely (!_ep
1002 			|| (!ep->ep.desc && ep->ep.name != ep0name))
1003 			|| ep->bmAttributes == USB_ENDPOINT_XFER_ISOC) {
1004 		DMSG("%s, bad ep\n", __func__);
1005 		return -EINVAL;
1006 	}
1007 	if (value == 0) {
1008 		/* this path (reset toggle+halt) is needed to implement
1009 		 * SET_INTERFACE on normal hardware.  but it can't be
1010 		 * done from software on the PXA UDC, and the hardware
1011 		 * forgets to do it as part of SET_INTERFACE automagic.
1012 		 */
1013 		DMSG("only host can clear %s halt\n", _ep->name);
1014 		return -EROFS;
1015 	}
1016 
1017 	local_irq_save(flags);
1018 
1019 	if ((ep->bEndpointAddress & USB_DIR_IN) != 0
1020 			&& ((udc_ep_get_UDCCS(ep) & UDCCS_BI_TFS) == 0
1021 			   || !list_empty(&ep->queue))) {
1022 		local_irq_restore(flags);
1023 		return -EAGAIN;
1024 	}
1025 
1026 	/* FST bit is the same for control, bulk in, bulk out, interrupt in */
1027 	udc_ep_set_UDCCS(ep, UDCCS_BI_FST|UDCCS_BI_FTF);
1028 
1029 	/* ep0 needs special care */
1030 	if (!ep->ep.desc) {
1031 		start_watchdog(ep->dev);
1032 		ep->dev->req_pending = 0;
1033 		ep->dev->ep0state = EP0_STALL;
1034 
1035 	/* and bulk/intr endpoints like dropping stalls too */
1036 	} else {
1037 		unsigned i;
1038 		for (i = 0; i < 1000; i += 20) {
1039 			if (udc_ep_get_UDCCS(ep) & UDCCS_BI_SST)
1040 				break;
1041 			udelay(20);
1042 		}
1043 	}
1044 	local_irq_restore(flags);
1045 
1046 	DBG(DBG_VERBOSE, "%s halt\n", _ep->name);
1047 	return 0;
1048 }
1049 
1050 static int pxa25x_ep_fifo_status(struct usb_ep *_ep)
1051 {
1052 	struct pxa25x_ep        *ep;
1053 
1054 	ep = container_of(_ep, struct pxa25x_ep, ep);
1055 	if (!_ep) {
1056 		DMSG("%s, bad ep\n", __func__);
1057 		return -ENODEV;
1058 	}
1059 	/* pxa can't report unclaimed bytes from IN fifos */
1060 	if ((ep->bEndpointAddress & USB_DIR_IN) != 0)
1061 		return -EOPNOTSUPP;
1062 	if (ep->dev->gadget.speed == USB_SPEED_UNKNOWN
1063 			|| (udc_ep_get_UDCCS(ep) & UDCCS_BO_RFS) == 0)
1064 		return 0;
1065 	else
1066 		return (udc_ep_get_UBCR(ep) & 0xfff) + 1;
1067 }
1068 
1069 static void pxa25x_ep_fifo_flush(struct usb_ep *_ep)
1070 {
1071 	struct pxa25x_ep        *ep;
1072 
1073 	ep = container_of(_ep, struct pxa25x_ep, ep);
1074 	if (!_ep || ep->ep.name == ep0name || !list_empty(&ep->queue)) {
1075 		DMSG("%s, bad ep\n", __func__);
1076 		return;
1077 	}
1078 
1079 	/* toggle and halt bits stay unchanged */
1080 
1081 	/* for OUT, just read and discard the FIFO contents. */
1082 	if ((ep->bEndpointAddress & USB_DIR_IN) == 0) {
1083 		while (((udc_ep_get_UDCCS(ep)) & UDCCS_BO_RNE) != 0)
1084 			(void)udc_ep_get_UDDR(ep);
1085 		return;
1086 	}
1087 
1088 	/* most IN status is the same, but ISO can't stall */
1089 	udc_ep_set_UDCCS(ep, UDCCS_BI_TPC|UDCCS_BI_FTF|UDCCS_BI_TUR
1090 		| (ep->bmAttributes == USB_ENDPOINT_XFER_ISOC
1091 			? 0 : UDCCS_BI_SST));
1092 }
1093 
1094 
1095 static const struct usb_ep_ops pxa25x_ep_ops = {
1096 	.enable		= pxa25x_ep_enable,
1097 	.disable	= pxa25x_ep_disable,
1098 
1099 	.alloc_request	= pxa25x_ep_alloc_request,
1100 	.free_request	= pxa25x_ep_free_request,
1101 
1102 	.queue		= pxa25x_ep_queue,
1103 	.dequeue	= pxa25x_ep_dequeue,
1104 
1105 	.set_halt	= pxa25x_ep_set_halt,
1106 	.fifo_status	= pxa25x_ep_fifo_status,
1107 	.fifo_flush	= pxa25x_ep_fifo_flush,
1108 };
1109 
1110 
1111 /* ---------------------------------------------------------------------------
1112  *	device-scoped parts of the api to the usb controller hardware
1113  * ---------------------------------------------------------------------------
1114  */
1115 
1116 static int pxa25x_udc_get_frame(struct usb_gadget *_gadget)
1117 {
1118 	struct pxa25x_udc	*dev;
1119 
1120 	dev = container_of(_gadget, struct pxa25x_udc, gadget);
1121 	return ((udc_get_reg(dev, UFNRH) & 0x07) << 8) |
1122 		(udc_get_reg(dev, UFNRL) & 0xff);
1123 }
1124 
1125 static int pxa25x_udc_wakeup(struct usb_gadget *_gadget)
1126 {
1127 	struct pxa25x_udc	*udc;
1128 
1129 	udc = container_of(_gadget, struct pxa25x_udc, gadget);
1130 
1131 	/* host may not have enabled remote wakeup */
1132 	if ((udc_ep0_get_UDCCS(udc) & UDCCS0_DRWF) == 0)
1133 		return -EHOSTUNREACH;
1134 	udc_set_mask_UDCCR(udc, UDCCR_RSM);
1135 	return 0;
1136 }
1137 
1138 static void stop_activity(struct pxa25x_udc *, struct usb_gadget_driver *);
1139 static void udc_enable (struct pxa25x_udc *);
1140 static void udc_disable(struct pxa25x_udc *);
1141 
1142 /* We disable the UDC -- and its 48 MHz clock -- whenever it's not
1143  * in active use.
1144  */
1145 static int pullup(struct pxa25x_udc *udc)
1146 {
1147 	int is_active = udc->vbus && udc->pullup && !udc->suspended;
1148 	DMSG("%s\n", is_active ? "active" : "inactive");
1149 	if (is_active) {
1150 		if (!udc->active) {
1151 			udc->active = 1;
1152 			/* Enable clock for USB device */
1153 			clk_enable(udc->clk);
1154 			udc_enable(udc);
1155 		}
1156 	} else {
1157 		if (udc->active) {
1158 			if (udc->gadget.speed != USB_SPEED_UNKNOWN) {
1159 				DMSG("disconnect %s\n", udc->driver
1160 					? udc->driver->driver.name
1161 					: "(no driver)");
1162 				stop_activity(udc, udc->driver);
1163 			}
1164 			udc_disable(udc);
1165 			/* Disable clock for USB device */
1166 			clk_disable(udc->clk);
1167 			udc->active = 0;
1168 		}
1169 
1170 	}
1171 	return 0;
1172 }
1173 
1174 /* VBUS reporting logically comes from a transceiver */
1175 static int pxa25x_udc_vbus_session(struct usb_gadget *_gadget, int is_active)
1176 {
1177 	struct pxa25x_udc	*udc;
1178 
1179 	udc = container_of(_gadget, struct pxa25x_udc, gadget);
1180 	udc->vbus = is_active;
1181 	DMSG("vbus %s\n", is_active ? "supplied" : "inactive");
1182 	pullup(udc);
1183 	return 0;
1184 }
1185 
1186 /* drivers may have software control over D+ pullup */
1187 static int pxa25x_udc_pullup(struct usb_gadget *_gadget, int is_active)
1188 {
1189 	struct pxa25x_udc	*udc;
1190 
1191 	udc = container_of(_gadget, struct pxa25x_udc, gadget);
1192 
1193 	/* not all boards support pullup control */
1194 	if (!gpio_is_valid(udc->mach->gpio_pullup) && !udc->mach->udc_command)
1195 		return -EOPNOTSUPP;
1196 
1197 	udc->pullup = (is_active != 0);
1198 	pullup(udc);
1199 	return 0;
1200 }
1201 
1202 /* boards may consume current from VBUS, up to 100-500mA based on config.
1203  * the 500uA suspend ceiling means that exclusively vbus-powered PXA designs
1204  * violate USB specs.
1205  */
1206 static int pxa25x_udc_vbus_draw(struct usb_gadget *_gadget, unsigned mA)
1207 {
1208 	struct pxa25x_udc	*udc;
1209 
1210 	udc = container_of(_gadget, struct pxa25x_udc, gadget);
1211 
1212 	if (!IS_ERR_OR_NULL(udc->transceiver))
1213 		return usb_phy_set_power(udc->transceiver, mA);
1214 	return -EOPNOTSUPP;
1215 }
1216 
1217 static int pxa25x_udc_start(struct usb_gadget *g,
1218 		struct usb_gadget_driver *driver);
1219 static int pxa25x_udc_stop(struct usb_gadget *g);
1220 
1221 static const struct usb_gadget_ops pxa25x_udc_ops = {
1222 	.get_frame	= pxa25x_udc_get_frame,
1223 	.wakeup		= pxa25x_udc_wakeup,
1224 	.vbus_session	= pxa25x_udc_vbus_session,
1225 	.pullup		= pxa25x_udc_pullup,
1226 	.vbus_draw	= pxa25x_udc_vbus_draw,
1227 	.udc_start	= pxa25x_udc_start,
1228 	.udc_stop	= pxa25x_udc_stop,
1229 };
1230 
1231 /*-------------------------------------------------------------------------*/
1232 
1233 #ifdef CONFIG_USB_GADGET_DEBUG_FS
1234 
1235 static int udc_debug_show(struct seq_file *m, void *_d)
1236 {
1237 	struct pxa25x_udc	*dev = m->private;
1238 	unsigned long		flags;
1239 	int			i;
1240 	u32			tmp;
1241 
1242 	local_irq_save(flags);
1243 
1244 	/* basic device status */
1245 	seq_printf(m, DRIVER_DESC "\n"
1246 		"%s version: %s\nGadget driver: %s\nHost %s\n\n",
1247 		driver_name, DRIVER_VERSION SIZE_STR "(pio)",
1248 		dev->driver ? dev->driver->driver.name : "(none)",
1249 		dev->gadget.speed == USB_SPEED_FULL ? "full speed" : "disconnected");
1250 
1251 	/* registers for device and ep0 */
1252 	seq_printf(m,
1253 		"uicr %02X.%02X, usir %02X.%02x, ufnr %02X.%02X\n",
1254 		udc_get_reg(dev, UICR1), udc_get_reg(dev, UICR0),
1255 		udc_get_reg(dev, USIR1), udc_get_reg(dev, USIR0),
1256 		udc_get_reg(dev, UFNRH), udc_get_reg(dev, UFNRL));
1257 
1258 	tmp = udc_get_reg(dev, UDCCR);
1259 	seq_printf(m,
1260 		"udccr %02X =%s%s%s%s%s%s%s%s\n", tmp,
1261 		(tmp & UDCCR_REM) ? " rem" : "",
1262 		(tmp & UDCCR_RSTIR) ? " rstir" : "",
1263 		(tmp & UDCCR_SRM) ? " srm" : "",
1264 		(tmp & UDCCR_SUSIR) ? " susir" : "",
1265 		(tmp & UDCCR_RESIR) ? " resir" : "",
1266 		(tmp & UDCCR_RSM) ? " rsm" : "",
1267 		(tmp & UDCCR_UDA) ? " uda" : "",
1268 		(tmp & UDCCR_UDE) ? " ude" : "");
1269 
1270 	tmp = udc_ep0_get_UDCCS(dev);
1271 	seq_printf(m,
1272 		"udccs0 %02X =%s%s%s%s%s%s%s%s\n", tmp,
1273 		(tmp & UDCCS0_SA) ? " sa" : "",
1274 		(tmp & UDCCS0_RNE) ? " rne" : "",
1275 		(tmp & UDCCS0_FST) ? " fst" : "",
1276 		(tmp & UDCCS0_SST) ? " sst" : "",
1277 		(tmp & UDCCS0_DRWF) ? " dwrf" : "",
1278 		(tmp & UDCCS0_FTF) ? " ftf" : "",
1279 		(tmp & UDCCS0_IPR) ? " ipr" : "",
1280 		(tmp & UDCCS0_OPR) ? " opr" : "");
1281 
1282 	if (dev->has_cfr) {
1283 		tmp = udc_get_reg(dev, UDCCFR);
1284 		seq_printf(m,
1285 			"udccfr %02X =%s%s\n", tmp,
1286 			(tmp & UDCCFR_AREN) ? " aren" : "",
1287 			(tmp & UDCCFR_ACM) ? " acm" : "");
1288 	}
1289 
1290 	if (dev->gadget.speed != USB_SPEED_FULL || !dev->driver)
1291 		goto done;
1292 
1293 	seq_printf(m, "ep0 IN %lu/%lu, OUT %lu/%lu\nirqs %lu\n\n",
1294 		dev->stats.write.bytes, dev->stats.write.ops,
1295 		dev->stats.read.bytes, dev->stats.read.ops,
1296 		dev->stats.irqs);
1297 
1298 	/* dump endpoint queues */
1299 	for (i = 0; i < PXA_UDC_NUM_ENDPOINTS; i++) {
1300 		struct pxa25x_ep	*ep = &dev->ep [i];
1301 		struct pxa25x_request	*req;
1302 
1303 		if (i != 0) {
1304 			const struct usb_endpoint_descriptor	*desc;
1305 
1306 			desc = ep->ep.desc;
1307 			if (!desc)
1308 				continue;
1309 			tmp = udc_ep_get_UDCCS(&dev->ep[i]);
1310 			seq_printf(m,
1311 				"%s max %d %s udccs %02x irqs %lu\n",
1312 				ep->ep.name, usb_endpoint_maxp(desc),
1313 				"pio", tmp, ep->pio_irqs);
1314 			/* TODO translate all five groups of udccs bits! */
1315 
1316 		} else /* ep0 should only have one transfer queued */
1317 			seq_printf(m, "ep0 max 16 pio irqs %lu\n",
1318 				ep->pio_irqs);
1319 
1320 		if (list_empty(&ep->queue)) {
1321 			seq_printf(m, "\t(nothing queued)\n");
1322 			continue;
1323 		}
1324 		list_for_each_entry(req, &ep->queue, queue) {
1325 			seq_printf(m,
1326 					"\treq %p len %d/%d buf %p\n",
1327 					&req->req, req->req.actual,
1328 					req->req.length, req->req.buf);
1329 		}
1330 	}
1331 
1332 done:
1333 	local_irq_restore(flags);
1334 	return 0;
1335 }
1336 DEFINE_SHOW_ATTRIBUTE(udc_debug);
1337 
1338 #define create_debug_files(dev) \
1339 	do { \
1340 		debugfs_create_file(dev->gadget.name, \
1341 			S_IRUGO, NULL, dev, &udc_debug_fops); \
1342 	} while (0)
1343 #define remove_debug_files(dev) debugfs_remove(debugfs_lookup(dev->gadget.name, NULL))
1344 
1345 #else	/* !CONFIG_USB_GADGET_DEBUG_FILES */
1346 
1347 #define create_debug_files(dev) do {} while (0)
1348 #define remove_debug_files(dev) do {} while (0)
1349 
1350 #endif	/* CONFIG_USB_GADGET_DEBUG_FILES */
1351 
1352 /*-------------------------------------------------------------------------*/
1353 
1354 /*
1355  *	udc_disable - disable USB device controller
1356  */
1357 static void udc_disable(struct pxa25x_udc *dev)
1358 {
1359 	/* block all irqs */
1360 	udc_set_mask_UDCCR(dev, UDCCR_SRM|UDCCR_REM);
1361 	udc_set_reg(dev, UICR0, 0xff);
1362 	udc_set_reg(dev, UICR1, 0xff);
1363 	udc_set_reg(dev, UFNRH, UFNRH_SIM);
1364 
1365 	/* if hardware supports it, disconnect from usb */
1366 	pullup_off();
1367 
1368 	udc_clear_mask_UDCCR(dev, UDCCR_UDE);
1369 
1370 	ep0_idle (dev);
1371 	dev->gadget.speed = USB_SPEED_UNKNOWN;
1372 }
1373 
1374 
1375 /*
1376  *	udc_reinit - initialize software state
1377  */
1378 static void udc_reinit(struct pxa25x_udc *dev)
1379 {
1380 	u32	i;
1381 
1382 	/* device/ep0 records init */
1383 	INIT_LIST_HEAD (&dev->gadget.ep_list);
1384 	INIT_LIST_HEAD (&dev->gadget.ep0->ep_list);
1385 	dev->ep0state = EP0_IDLE;
1386 	dev->gadget.quirk_altset_not_supp = 1;
1387 
1388 	/* basic endpoint records init */
1389 	for (i = 0; i < PXA_UDC_NUM_ENDPOINTS; i++) {
1390 		struct pxa25x_ep *ep = &dev->ep[i];
1391 
1392 		if (i != 0)
1393 			list_add_tail (&ep->ep.ep_list, &dev->gadget.ep_list);
1394 
1395 		ep->ep.desc = NULL;
1396 		ep->stopped = 0;
1397 		INIT_LIST_HEAD (&ep->queue);
1398 		ep->pio_irqs = 0;
1399 		usb_ep_set_maxpacket_limit(&ep->ep, ep->ep.maxpacket);
1400 	}
1401 
1402 	/* the rest was statically initialized, and is read-only */
1403 }
1404 
1405 /* until it's enabled, this UDC should be completely invisible
1406  * to any USB host.
1407  */
1408 static void udc_enable (struct pxa25x_udc *dev)
1409 {
1410 	udc_clear_mask_UDCCR(dev, UDCCR_UDE);
1411 
1412 	/* try to clear these bits before we enable the udc */
1413 	udc_ack_int_UDCCR(dev, UDCCR_SUSIR|/*UDCCR_RSTIR|*/UDCCR_RESIR);
1414 
1415 	ep0_idle(dev);
1416 	dev->gadget.speed = USB_SPEED_UNKNOWN;
1417 	dev->stats.irqs = 0;
1418 
1419 	/*
1420 	 * sequence taken from chapter 12.5.10, PXA250 AppProcDevManual:
1421 	 * - enable UDC
1422 	 * - if RESET is already in progress, ack interrupt
1423 	 * - unmask reset interrupt
1424 	 */
1425 	udc_set_mask_UDCCR(dev, UDCCR_UDE);
1426 	if (!(udc_get_reg(dev, UDCCR) & UDCCR_UDA))
1427 		udc_ack_int_UDCCR(dev, UDCCR_RSTIR);
1428 
1429 	if (dev->has_cfr /* UDC_RES2 is defined */) {
1430 		/* pxa255 (a0+) can avoid a set_config race that could
1431 		 * prevent gadget drivers from configuring correctly
1432 		 */
1433 		udc_set_reg(dev, UDCCFR, UDCCFR_ACM | UDCCFR_MB1);
1434 	} else {
1435 		/* "USB test mode" for pxa250 errata 40-42 (stepping a0, a1)
1436 		 * which could result in missing packets and interrupts.
1437 		 * supposedly one bit per endpoint, controlling whether it
1438 		 * double buffers or not; ACM/AREN bits fit into the holes.
1439 		 * zero bits (like USIR0_IRx) disable double buffering.
1440 		 */
1441 		udc_set_reg(dev, UDC_RES1, 0x00);
1442 		udc_set_reg(dev, UDC_RES2, 0x00);
1443 	}
1444 
1445 	/* enable suspend/resume and reset irqs */
1446 	udc_clear_mask_UDCCR(dev, UDCCR_SRM | UDCCR_REM);
1447 
1448 	/* enable ep0 irqs */
1449 	udc_set_reg(dev, UICR0, udc_get_reg(dev, UICR0) & ~UICR0_IM0);
1450 
1451 	/* if hardware supports it, pullup D+ and wait for reset */
1452 	pullup_on();
1453 }
1454 
1455 
1456 /* when a driver is successfully registered, it will receive
1457  * control requests including set_configuration(), which enables
1458  * non-control requests.  then usb traffic follows until a
1459  * disconnect is reported.  then a host may connect again, or
1460  * the driver might get unbound.
1461  */
1462 static int pxa25x_udc_start(struct usb_gadget *g,
1463 		struct usb_gadget_driver *driver)
1464 {
1465 	struct pxa25x_udc	*dev = to_pxa25x(g);
1466 	int			retval;
1467 
1468 	/* first hook up the driver ... */
1469 	dev->driver = driver;
1470 	dev->pullup = 1;
1471 
1472 	/* ... then enable host detection and ep0; and we're ready
1473 	 * for set_configuration as well as eventual disconnect.
1474 	 */
1475 	/* connect to bus through transceiver */
1476 	if (!IS_ERR_OR_NULL(dev->transceiver)) {
1477 		retval = otg_set_peripheral(dev->transceiver->otg,
1478 						&dev->gadget);
1479 		if (retval)
1480 			goto bind_fail;
1481 	}
1482 
1483 	dump_state(dev);
1484 	return 0;
1485 bind_fail:
1486 	return retval;
1487 }
1488 
1489 static void
1490 reset_gadget(struct pxa25x_udc *dev, struct usb_gadget_driver *driver)
1491 {
1492 	int i;
1493 
1494 	/* don't disconnect drivers more than once */
1495 	if (dev->gadget.speed == USB_SPEED_UNKNOWN)
1496 		driver = NULL;
1497 	dev->gadget.speed = USB_SPEED_UNKNOWN;
1498 
1499 	/* prevent new request submissions, kill any outstanding requests  */
1500 	for (i = 0; i < PXA_UDC_NUM_ENDPOINTS; i++) {
1501 		struct pxa25x_ep *ep = &dev->ep[i];
1502 
1503 		ep->stopped = 1;
1504 		nuke(ep, -ESHUTDOWN);
1505 	}
1506 	del_timer_sync(&dev->timer);
1507 
1508 	/* report reset; the driver is already quiesced */
1509 	if (driver)
1510 		usb_gadget_udc_reset(&dev->gadget, driver);
1511 
1512 	/* re-init driver-visible data structures */
1513 	udc_reinit(dev);
1514 }
1515 
1516 static void
1517 stop_activity(struct pxa25x_udc *dev, struct usb_gadget_driver *driver)
1518 {
1519 	int i;
1520 
1521 	/* don't disconnect drivers more than once */
1522 	if (dev->gadget.speed == USB_SPEED_UNKNOWN)
1523 		driver = NULL;
1524 	dev->gadget.speed = USB_SPEED_UNKNOWN;
1525 
1526 	/* prevent new request submissions, kill any outstanding requests  */
1527 	for (i = 0; i < PXA_UDC_NUM_ENDPOINTS; i++) {
1528 		struct pxa25x_ep *ep = &dev->ep[i];
1529 
1530 		ep->stopped = 1;
1531 		nuke(ep, -ESHUTDOWN);
1532 	}
1533 	del_timer_sync(&dev->timer);
1534 
1535 	/* report disconnect; the driver is already quiesced */
1536 	if (driver)
1537 		driver->disconnect(&dev->gadget);
1538 
1539 	/* re-init driver-visible data structures */
1540 	udc_reinit(dev);
1541 }
1542 
1543 static int pxa25x_udc_stop(struct usb_gadget*g)
1544 {
1545 	struct pxa25x_udc	*dev = to_pxa25x(g);
1546 
1547 	local_irq_disable();
1548 	dev->pullup = 0;
1549 	stop_activity(dev, NULL);
1550 	local_irq_enable();
1551 
1552 	if (!IS_ERR_OR_NULL(dev->transceiver))
1553 		(void) otg_set_peripheral(dev->transceiver->otg, NULL);
1554 
1555 	dev->driver = NULL;
1556 
1557 	dump_state(dev);
1558 
1559 	return 0;
1560 }
1561 
1562 /*-------------------------------------------------------------------------*/
1563 
1564 #ifdef CONFIG_ARCH_LUBBOCK
1565 
1566 /* Lubbock has separate connect and disconnect irqs.  More typical designs
1567  * use one GPIO as the VBUS IRQ, and another to control the D+ pullup.
1568  */
1569 
1570 static irqreturn_t
1571 lubbock_vbus_irq(int irq, void *_dev)
1572 {
1573 	struct pxa25x_udc	*dev = _dev;
1574 	int			vbus;
1575 
1576 	dev->stats.irqs++;
1577 	if (irq == dev->usb_irq) {
1578 		vbus = 1;
1579 		disable_irq(dev->usb_irq);
1580 		enable_irq(dev->usb_disc_irq);
1581 	} else if (irq == dev->usb_disc_irq) {
1582 		vbus = 0;
1583 		disable_irq(dev->usb_disc_irq);
1584 		enable_irq(dev->usb_irq);
1585 	} else {
1586 		return IRQ_NONE;
1587 	}
1588 
1589 	pxa25x_udc_vbus_session(&dev->gadget, vbus);
1590 	return IRQ_HANDLED;
1591 }
1592 
1593 #endif
1594 
1595 
1596 /*-------------------------------------------------------------------------*/
1597 
1598 static inline void clear_ep_state (struct pxa25x_udc *dev)
1599 {
1600 	unsigned i;
1601 
1602 	/* hardware SET_{CONFIGURATION,INTERFACE} automagic resets endpoint
1603 	 * fifos, and pending transactions mustn't be continued in any case.
1604 	 */
1605 	for (i = 1; i < PXA_UDC_NUM_ENDPOINTS; i++)
1606 		nuke(&dev->ep[i], -ECONNABORTED);
1607 }
1608 
1609 static void udc_watchdog(struct timer_list *t)
1610 {
1611 	struct pxa25x_udc	*dev = from_timer(dev, t, timer);
1612 
1613 	local_irq_disable();
1614 	if (dev->ep0state == EP0_STALL
1615 			&& (udc_ep0_get_UDCCS(dev) & UDCCS0_FST) == 0
1616 			&& (udc_ep0_get_UDCCS(dev) & UDCCS0_SST) == 0) {
1617 		udc_ep0_set_UDCCS(dev, UDCCS0_FST|UDCCS0_FTF);
1618 		DBG(DBG_VERBOSE, "ep0 re-stall\n");
1619 		start_watchdog(dev);
1620 	}
1621 	local_irq_enable();
1622 }
1623 
1624 static void handle_ep0 (struct pxa25x_udc *dev)
1625 {
1626 	u32			udccs0 = udc_ep0_get_UDCCS(dev);
1627 	struct pxa25x_ep	*ep = &dev->ep [0];
1628 	struct pxa25x_request	*req;
1629 	union {
1630 		struct usb_ctrlrequest	r;
1631 		u8			raw [8];
1632 		u32			word [2];
1633 	} u;
1634 
1635 	if (list_empty(&ep->queue))
1636 		req = NULL;
1637 	else
1638 		req = list_entry(ep->queue.next, struct pxa25x_request, queue);
1639 
1640 	/* clear stall status */
1641 	if (udccs0 & UDCCS0_SST) {
1642 		nuke(ep, -EPIPE);
1643 		udc_ep0_set_UDCCS(dev, UDCCS0_SST);
1644 		del_timer(&dev->timer);
1645 		ep0_idle(dev);
1646 	}
1647 
1648 	/* previous request unfinished?  non-error iff back-to-back ... */
1649 	if ((udccs0 & UDCCS0_SA) != 0 && dev->ep0state != EP0_IDLE) {
1650 		nuke(ep, 0);
1651 		del_timer(&dev->timer);
1652 		ep0_idle(dev);
1653 	}
1654 
1655 	switch (dev->ep0state) {
1656 	case EP0_IDLE:
1657 		/* late-breaking status? */
1658 		udccs0 = udc_ep0_get_UDCCS(dev);
1659 
1660 		/* start control request? */
1661 		if (likely((udccs0 & (UDCCS0_OPR|UDCCS0_SA|UDCCS0_RNE))
1662 				== (UDCCS0_OPR|UDCCS0_SA|UDCCS0_RNE))) {
1663 			int i;
1664 
1665 			nuke (ep, -EPROTO);
1666 
1667 			/* read SETUP packet */
1668 			for (i = 0; i < 8; i++) {
1669 				if (unlikely(!(udc_ep0_get_UDCCS(dev) & UDCCS0_RNE))) {
1670 bad_setup:
1671 					DMSG("SETUP %d!\n", i);
1672 					goto stall;
1673 				}
1674 				u.raw [i] = (u8) UDDR0;
1675 			}
1676 			if (unlikely((udc_ep0_get_UDCCS(dev) & UDCCS0_RNE) != 0))
1677 				goto bad_setup;
1678 
1679 got_setup:
1680 			DBG(DBG_VERBOSE, "SETUP %02x.%02x v%04x i%04x l%04x\n",
1681 				u.r.bRequestType, u.r.bRequest,
1682 				le16_to_cpu(u.r.wValue),
1683 				le16_to_cpu(u.r.wIndex),
1684 				le16_to_cpu(u.r.wLength));
1685 
1686 			/* cope with automagic for some standard requests. */
1687 			dev->req_std = (u.r.bRequestType & USB_TYPE_MASK)
1688 						== USB_TYPE_STANDARD;
1689 			dev->req_config = 0;
1690 			dev->req_pending = 1;
1691 			switch (u.r.bRequest) {
1692 			/* hardware restricts gadget drivers here! */
1693 			case USB_REQ_SET_CONFIGURATION:
1694 				if (u.r.bRequestType == USB_RECIP_DEVICE) {
1695 					/* reflect hardware's automagic
1696 					 * up to the gadget driver.
1697 					 */
1698 config_change:
1699 					dev->req_config = 1;
1700 					clear_ep_state(dev);
1701 					/* if !has_cfr, there's no synch
1702 					 * else use AREN (later) not SA|OPR
1703 					 * USIR0_IR0 acts edge sensitive
1704 					 */
1705 				}
1706 				break;
1707 			/* ... and here, even more ... */
1708 			case USB_REQ_SET_INTERFACE:
1709 				if (u.r.bRequestType == USB_RECIP_INTERFACE) {
1710 					/* udc hardware is broken by design:
1711 					 *  - altsetting may only be zero;
1712 					 *  - hw resets all interfaces' eps;
1713 					 *  - ep reset doesn't include halt(?).
1714 					 */
1715 					DMSG("broken set_interface (%d/%d)\n",
1716 						le16_to_cpu(u.r.wIndex),
1717 						le16_to_cpu(u.r.wValue));
1718 					goto config_change;
1719 				}
1720 				break;
1721 			/* hardware was supposed to hide this */
1722 			case USB_REQ_SET_ADDRESS:
1723 				if (u.r.bRequestType == USB_RECIP_DEVICE) {
1724 					ep0start(dev, 0, "address");
1725 					return;
1726 				}
1727 				break;
1728 			}
1729 
1730 			if (u.r.bRequestType & USB_DIR_IN)
1731 				dev->ep0state = EP0_IN_DATA_PHASE;
1732 			else
1733 				dev->ep0state = EP0_OUT_DATA_PHASE;
1734 
1735 			i = dev->driver->setup(&dev->gadget, &u.r);
1736 			if (i < 0) {
1737 				/* hardware automagic preventing STALL... */
1738 				if (dev->req_config) {
1739 					/* hardware sometimes neglects to tell
1740 					 * tell us about config change events,
1741 					 * so later ones may fail...
1742 					 */
1743 					WARNING("config change %02x fail %d?\n",
1744 						u.r.bRequest, i);
1745 					return;
1746 					/* TODO experiment:  if has_cfr,
1747 					 * hardware didn't ACK; maybe we
1748 					 * could actually STALL!
1749 					 */
1750 				}
1751 				DBG(DBG_VERBOSE, "protocol STALL, "
1752 					"%02x err %d\n", udc_ep0_get_UDCCS(dev), i);
1753 stall:
1754 				/* the watchdog timer helps deal with cases
1755 				 * where udc seems to clear FST wrongly, and
1756 				 * then NAKs instead of STALLing.
1757 				 */
1758 				ep0start(dev, UDCCS0_FST|UDCCS0_FTF, "stall");
1759 				start_watchdog(dev);
1760 				dev->ep0state = EP0_STALL;
1761 
1762 			/* deferred i/o == no response yet */
1763 			} else if (dev->req_pending) {
1764 				if (likely(dev->ep0state == EP0_IN_DATA_PHASE
1765 						|| dev->req_std || u.r.wLength))
1766 					ep0start(dev, 0, "defer");
1767 				else
1768 					ep0start(dev, UDCCS0_IPR, "defer/IPR");
1769 			}
1770 
1771 			/* expect at least one data or status stage irq */
1772 			return;
1773 
1774 		} else if (likely((udccs0 & (UDCCS0_OPR|UDCCS0_SA))
1775 				== (UDCCS0_OPR|UDCCS0_SA))) {
1776 			unsigned i;
1777 
1778 			/* pxa210/250 erratum 131 for B0/B1 says RNE lies.
1779 			 * still observed on a pxa255 a0.
1780 			 */
1781 			DBG(DBG_VERBOSE, "e131\n");
1782 			nuke(ep, -EPROTO);
1783 
1784 			/* read SETUP data, but don't trust it too much */
1785 			for (i = 0; i < 8; i++)
1786 				u.raw [i] = (u8) UDDR0;
1787 			if ((u.r.bRequestType & USB_RECIP_MASK)
1788 					> USB_RECIP_OTHER)
1789 				goto stall;
1790 			if (u.word [0] == 0 && u.word [1] == 0)
1791 				goto stall;
1792 			goto got_setup;
1793 		} else {
1794 			/* some random early IRQ:
1795 			 * - we acked FST
1796 			 * - IPR cleared
1797 			 * - OPR got set, without SA (likely status stage)
1798 			 */
1799 			udc_ep0_set_UDCCS(dev, udccs0 & (UDCCS0_SA|UDCCS0_OPR));
1800 		}
1801 		break;
1802 	case EP0_IN_DATA_PHASE:			/* GET_DESCRIPTOR etc */
1803 		if (udccs0 & UDCCS0_OPR) {
1804 			udc_ep0_set_UDCCS(dev, UDCCS0_OPR|UDCCS0_FTF);
1805 			DBG(DBG_VERBOSE, "ep0in premature status\n");
1806 			if (req)
1807 				done(ep, req, 0);
1808 			ep0_idle(dev);
1809 		} else /* irq was IPR clearing */ {
1810 			if (req) {
1811 				/* this IN packet might finish the request */
1812 				(void) write_ep0_fifo(ep, req);
1813 			} /* else IN token before response was written */
1814 		}
1815 		break;
1816 	case EP0_OUT_DATA_PHASE:		/* SET_DESCRIPTOR etc */
1817 		if (udccs0 & UDCCS0_OPR) {
1818 			if (req) {
1819 				/* this OUT packet might finish the request */
1820 				if (read_ep0_fifo(ep, req))
1821 					done(ep, req, 0);
1822 				/* else more OUT packets expected */
1823 			} /* else OUT token before read was issued */
1824 		} else /* irq was IPR clearing */ {
1825 			DBG(DBG_VERBOSE, "ep0out premature status\n");
1826 			if (req)
1827 				done(ep, req, 0);
1828 			ep0_idle(dev);
1829 		}
1830 		break;
1831 	case EP0_END_XFER:
1832 		if (req)
1833 			done(ep, req, 0);
1834 		/* ack control-IN status (maybe in-zlp was skipped)
1835 		 * also appears after some config change events.
1836 		 */
1837 		if (udccs0 & UDCCS0_OPR)
1838 			udc_ep0_set_UDCCS(dev, UDCCS0_OPR);
1839 		ep0_idle(dev);
1840 		break;
1841 	case EP0_STALL:
1842 		udc_ep0_set_UDCCS(dev, UDCCS0_FST);
1843 		break;
1844 	}
1845 	udc_set_reg(dev, USIR0, USIR0_IR0);
1846 }
1847 
1848 static void handle_ep(struct pxa25x_ep *ep)
1849 {
1850 	struct pxa25x_request	*req;
1851 	int			is_in = ep->bEndpointAddress & USB_DIR_IN;
1852 	int			completed;
1853 	u32			udccs, tmp;
1854 
1855 	do {
1856 		completed = 0;
1857 		if (likely (!list_empty(&ep->queue)))
1858 			req = list_entry(ep->queue.next,
1859 					struct pxa25x_request, queue);
1860 		else
1861 			req = NULL;
1862 
1863 		// TODO check FST handling
1864 
1865 		udccs = udc_ep_get_UDCCS(ep);
1866 		if (unlikely(is_in)) {	/* irq from TPC, SST, or (ISO) TUR */
1867 			tmp = UDCCS_BI_TUR;
1868 			if (likely(ep->bmAttributes == USB_ENDPOINT_XFER_BULK))
1869 				tmp |= UDCCS_BI_SST;
1870 			tmp &= udccs;
1871 			if (likely (tmp))
1872 				udc_ep_set_UDCCS(ep, tmp);
1873 			if (req && likely ((udccs & UDCCS_BI_TFS) != 0))
1874 				completed = write_fifo(ep, req);
1875 
1876 		} else {	/* irq from RPC (or for ISO, ROF) */
1877 			if (likely(ep->bmAttributes == USB_ENDPOINT_XFER_BULK))
1878 				tmp = UDCCS_BO_SST | UDCCS_BO_DME;
1879 			else
1880 				tmp = UDCCS_IO_ROF | UDCCS_IO_DME;
1881 			tmp &= udccs;
1882 			if (likely(tmp))
1883 				udc_ep_set_UDCCS(ep, tmp);
1884 
1885 			/* fifos can hold packets, ready for reading... */
1886 			if (likely(req)) {
1887 				completed = read_fifo(ep, req);
1888 			} else
1889 				pio_irq_disable(ep);
1890 		}
1891 		ep->pio_irqs++;
1892 	} while (completed);
1893 }
1894 
1895 /*
1896  *	pxa25x_udc_irq - interrupt handler
1897  *
1898  * avoid delays in ep0 processing. the control handshaking isn't always
1899  * under software control (pxa250c0 and the pxa255 are better), and delays
1900  * could cause usb protocol errors.
1901  */
1902 static irqreturn_t
1903 pxa25x_udc_irq(int irq, void *_dev)
1904 {
1905 	struct pxa25x_udc	*dev = _dev;
1906 	int			handled;
1907 
1908 	dev->stats.irqs++;
1909 	do {
1910 		u32		udccr = udc_get_reg(dev, UDCCR);
1911 
1912 		handled = 0;
1913 
1914 		/* SUSpend Interrupt Request */
1915 		if (unlikely(udccr & UDCCR_SUSIR)) {
1916 			udc_ack_int_UDCCR(dev, UDCCR_SUSIR);
1917 			handled = 1;
1918 			DBG(DBG_VERBOSE, "USB suspend\n");
1919 
1920 			if (dev->gadget.speed != USB_SPEED_UNKNOWN
1921 					&& dev->driver
1922 					&& dev->driver->suspend)
1923 				dev->driver->suspend(&dev->gadget);
1924 			ep0_idle (dev);
1925 		}
1926 
1927 		/* RESume Interrupt Request */
1928 		if (unlikely(udccr & UDCCR_RESIR)) {
1929 			udc_ack_int_UDCCR(dev, UDCCR_RESIR);
1930 			handled = 1;
1931 			DBG(DBG_VERBOSE, "USB resume\n");
1932 
1933 			if (dev->gadget.speed != USB_SPEED_UNKNOWN
1934 					&& dev->driver
1935 					&& dev->driver->resume)
1936 				dev->driver->resume(&dev->gadget);
1937 		}
1938 
1939 		/* ReSeT Interrupt Request - USB reset */
1940 		if (unlikely(udccr & UDCCR_RSTIR)) {
1941 			udc_ack_int_UDCCR(dev, UDCCR_RSTIR);
1942 			handled = 1;
1943 
1944 			if ((udc_get_reg(dev, UDCCR) & UDCCR_UDA) == 0) {
1945 				DBG(DBG_VERBOSE, "USB reset start\n");
1946 
1947 				/* reset driver and endpoints,
1948 				 * in case that's not yet done
1949 				 */
1950 				reset_gadget(dev, dev->driver);
1951 
1952 			} else {
1953 				DBG(DBG_VERBOSE, "USB reset end\n");
1954 				dev->gadget.speed = USB_SPEED_FULL;
1955 				memset(&dev->stats, 0, sizeof dev->stats);
1956 				/* driver and endpoints are still reset */
1957 			}
1958 
1959 		} else {
1960 			u32	usir0 = udc_get_reg(dev, USIR0) &
1961 					~udc_get_reg(dev, UICR0);
1962 			u32	usir1 = udc_get_reg(dev, USIR1) &
1963 					~udc_get_reg(dev, UICR1);
1964 			int	i;
1965 
1966 			if (unlikely (!usir0 && !usir1))
1967 				continue;
1968 
1969 			DBG(DBG_VERY_NOISY, "irq %02x.%02x\n", usir1, usir0);
1970 
1971 			/* control traffic */
1972 			if (usir0 & USIR0_IR0) {
1973 				dev->ep[0].pio_irqs++;
1974 				handle_ep0(dev);
1975 				handled = 1;
1976 			}
1977 
1978 			/* endpoint data transfers */
1979 			for (i = 0; i < 8; i++) {
1980 				u32	tmp = 1 << i;
1981 
1982 				if (i && (usir0 & tmp)) {
1983 					handle_ep(&dev->ep[i]);
1984 					udc_set_reg(dev, USIR0,
1985 						udc_get_reg(dev, USIR0) | tmp);
1986 					handled = 1;
1987 				}
1988 #ifndef	CONFIG_USB_PXA25X_SMALL
1989 				if (usir1 & tmp) {
1990 					handle_ep(&dev->ep[i+8]);
1991 					udc_set_reg(dev, USIR1,
1992 						udc_get_reg(dev, USIR1) | tmp);
1993 					handled = 1;
1994 				}
1995 #endif
1996 			}
1997 		}
1998 
1999 		/* we could also ask for 1 msec SOF (SIR) interrupts */
2000 
2001 	} while (handled);
2002 	return IRQ_HANDLED;
2003 }
2004 
2005 /*-------------------------------------------------------------------------*/
2006 
2007 static void nop_release (struct device *dev)
2008 {
2009 	DMSG("%s %s\n", __func__, dev_name(dev));
2010 }
2011 
2012 /* this uses load-time allocation and initialization (instead of
2013  * doing it at run-time) to save code, eliminate fault paths, and
2014  * be more obviously correct.
2015  */
2016 static struct pxa25x_udc memory = {
2017 	.gadget = {
2018 		.ops		= &pxa25x_udc_ops,
2019 		.ep0		= &memory.ep[0].ep,
2020 		.name		= driver_name,
2021 		.dev = {
2022 			.init_name	= "gadget",
2023 			.release	= nop_release,
2024 		},
2025 	},
2026 
2027 	/* control endpoint */
2028 	.ep[0] = {
2029 		.ep = {
2030 			.name		= ep0name,
2031 			.ops		= &pxa25x_ep_ops,
2032 			.maxpacket	= EP0_FIFO_SIZE,
2033 			.caps		= USB_EP_CAPS(USB_EP_CAPS_TYPE_CONTROL,
2034 						USB_EP_CAPS_DIR_ALL),
2035 		},
2036 		.dev		= &memory,
2037 		.regoff_udccs	= UDCCS0,
2038 		.regoff_uddr	= UDDR0,
2039 	},
2040 
2041 	/* first group of endpoints */
2042 	.ep[1] = {
2043 		.ep = {
2044 			.name		= "ep1in-bulk",
2045 			.ops		= &pxa25x_ep_ops,
2046 			.maxpacket	= BULK_FIFO_SIZE,
2047 			.caps		= USB_EP_CAPS(USB_EP_CAPS_TYPE_BULK,
2048 						USB_EP_CAPS_DIR_IN),
2049 		},
2050 		.dev		= &memory,
2051 		.fifo_size	= BULK_FIFO_SIZE,
2052 		.bEndpointAddress = USB_DIR_IN | 1,
2053 		.bmAttributes	= USB_ENDPOINT_XFER_BULK,
2054 		.regoff_udccs	= UDCCS1,
2055 		.regoff_uddr	= UDDR1,
2056 	},
2057 	.ep[2] = {
2058 		.ep = {
2059 			.name		= "ep2out-bulk",
2060 			.ops		= &pxa25x_ep_ops,
2061 			.maxpacket	= BULK_FIFO_SIZE,
2062 			.caps		= USB_EP_CAPS(USB_EP_CAPS_TYPE_BULK,
2063 						USB_EP_CAPS_DIR_OUT),
2064 		},
2065 		.dev		= &memory,
2066 		.fifo_size	= BULK_FIFO_SIZE,
2067 		.bEndpointAddress = 2,
2068 		.bmAttributes	= USB_ENDPOINT_XFER_BULK,
2069 		.regoff_udccs	= UDCCS2,
2070 		.regoff_ubcr	= UBCR2,
2071 		.regoff_uddr	= UDDR2,
2072 	},
2073 #ifndef CONFIG_USB_PXA25X_SMALL
2074 	.ep[3] = {
2075 		.ep = {
2076 			.name		= "ep3in-iso",
2077 			.ops		= &pxa25x_ep_ops,
2078 			.maxpacket	= ISO_FIFO_SIZE,
2079 			.caps		= USB_EP_CAPS(USB_EP_CAPS_TYPE_ISO,
2080 						USB_EP_CAPS_DIR_IN),
2081 		},
2082 		.dev		= &memory,
2083 		.fifo_size	= ISO_FIFO_SIZE,
2084 		.bEndpointAddress = USB_DIR_IN | 3,
2085 		.bmAttributes	= USB_ENDPOINT_XFER_ISOC,
2086 		.regoff_udccs	= UDCCS3,
2087 		.regoff_uddr	= UDDR3,
2088 	},
2089 	.ep[4] = {
2090 		.ep = {
2091 			.name		= "ep4out-iso",
2092 			.ops		= &pxa25x_ep_ops,
2093 			.maxpacket	= ISO_FIFO_SIZE,
2094 			.caps		= USB_EP_CAPS(USB_EP_CAPS_TYPE_ISO,
2095 						USB_EP_CAPS_DIR_OUT),
2096 		},
2097 		.dev		= &memory,
2098 		.fifo_size	= ISO_FIFO_SIZE,
2099 		.bEndpointAddress = 4,
2100 		.bmAttributes	= USB_ENDPOINT_XFER_ISOC,
2101 		.regoff_udccs	= UDCCS4,
2102 		.regoff_ubcr	= UBCR4,
2103 		.regoff_uddr	= UDDR4,
2104 	},
2105 	.ep[5] = {
2106 		.ep = {
2107 			.name		= "ep5in-int",
2108 			.ops		= &pxa25x_ep_ops,
2109 			.maxpacket	= INT_FIFO_SIZE,
2110 			.caps		= USB_EP_CAPS(0, 0),
2111 		},
2112 		.dev		= &memory,
2113 		.fifo_size	= INT_FIFO_SIZE,
2114 		.bEndpointAddress = USB_DIR_IN | 5,
2115 		.bmAttributes	= USB_ENDPOINT_XFER_INT,
2116 		.regoff_udccs	= UDCCS5,
2117 		.regoff_uddr	= UDDR5,
2118 	},
2119 
2120 	/* second group of endpoints */
2121 	.ep[6] = {
2122 		.ep = {
2123 			.name		= "ep6in-bulk",
2124 			.ops		= &pxa25x_ep_ops,
2125 			.maxpacket	= BULK_FIFO_SIZE,
2126 			.caps		= USB_EP_CAPS(USB_EP_CAPS_TYPE_BULK,
2127 						USB_EP_CAPS_DIR_IN),
2128 		},
2129 		.dev		= &memory,
2130 		.fifo_size	= BULK_FIFO_SIZE,
2131 		.bEndpointAddress = USB_DIR_IN | 6,
2132 		.bmAttributes	= USB_ENDPOINT_XFER_BULK,
2133 		.regoff_udccs	= UDCCS6,
2134 		.regoff_uddr	= UDDR6,
2135 	},
2136 	.ep[7] = {
2137 		.ep = {
2138 			.name		= "ep7out-bulk",
2139 			.ops		= &pxa25x_ep_ops,
2140 			.maxpacket	= BULK_FIFO_SIZE,
2141 			.caps		= USB_EP_CAPS(USB_EP_CAPS_TYPE_BULK,
2142 						USB_EP_CAPS_DIR_OUT),
2143 		},
2144 		.dev		= &memory,
2145 		.fifo_size	= BULK_FIFO_SIZE,
2146 		.bEndpointAddress = 7,
2147 		.bmAttributes	= USB_ENDPOINT_XFER_BULK,
2148 		.regoff_udccs	= UDCCS7,
2149 		.regoff_ubcr	= UBCR7,
2150 		.regoff_uddr	= UDDR7,
2151 	},
2152 	.ep[8] = {
2153 		.ep = {
2154 			.name		= "ep8in-iso",
2155 			.ops		= &pxa25x_ep_ops,
2156 			.maxpacket	= ISO_FIFO_SIZE,
2157 			.caps		= USB_EP_CAPS(USB_EP_CAPS_TYPE_ISO,
2158 						USB_EP_CAPS_DIR_IN),
2159 		},
2160 		.dev		= &memory,
2161 		.fifo_size	= ISO_FIFO_SIZE,
2162 		.bEndpointAddress = USB_DIR_IN | 8,
2163 		.bmAttributes	= USB_ENDPOINT_XFER_ISOC,
2164 		.regoff_udccs	= UDCCS8,
2165 		.regoff_uddr	= UDDR8,
2166 	},
2167 	.ep[9] = {
2168 		.ep = {
2169 			.name		= "ep9out-iso",
2170 			.ops		= &pxa25x_ep_ops,
2171 			.maxpacket	= ISO_FIFO_SIZE,
2172 			.caps		= USB_EP_CAPS(USB_EP_CAPS_TYPE_ISO,
2173 						USB_EP_CAPS_DIR_OUT),
2174 		},
2175 		.dev		= &memory,
2176 		.fifo_size	= ISO_FIFO_SIZE,
2177 		.bEndpointAddress = 9,
2178 		.bmAttributes	= USB_ENDPOINT_XFER_ISOC,
2179 		.regoff_udccs	= UDCCS9,
2180 		.regoff_ubcr	= UBCR9,
2181 		.regoff_uddr	= UDDR9,
2182 	},
2183 	.ep[10] = {
2184 		.ep = {
2185 			.name		= "ep10in-int",
2186 			.ops		= &pxa25x_ep_ops,
2187 			.maxpacket	= INT_FIFO_SIZE,
2188 			.caps		= USB_EP_CAPS(0, 0),
2189 		},
2190 		.dev		= &memory,
2191 		.fifo_size	= INT_FIFO_SIZE,
2192 		.bEndpointAddress = USB_DIR_IN | 10,
2193 		.bmAttributes	= USB_ENDPOINT_XFER_INT,
2194 		.regoff_udccs	= UDCCS10,
2195 		.regoff_uddr	= UDDR10,
2196 	},
2197 
2198 	/* third group of endpoints */
2199 	.ep[11] = {
2200 		.ep = {
2201 			.name		= "ep11in-bulk",
2202 			.ops		= &pxa25x_ep_ops,
2203 			.maxpacket	= BULK_FIFO_SIZE,
2204 			.caps		= USB_EP_CAPS(USB_EP_CAPS_TYPE_BULK,
2205 						USB_EP_CAPS_DIR_IN),
2206 		},
2207 		.dev		= &memory,
2208 		.fifo_size	= BULK_FIFO_SIZE,
2209 		.bEndpointAddress = USB_DIR_IN | 11,
2210 		.bmAttributes	= USB_ENDPOINT_XFER_BULK,
2211 		.regoff_udccs	= UDCCS11,
2212 		.regoff_uddr	= UDDR11,
2213 	},
2214 	.ep[12] = {
2215 		.ep = {
2216 			.name		= "ep12out-bulk",
2217 			.ops		= &pxa25x_ep_ops,
2218 			.maxpacket	= BULK_FIFO_SIZE,
2219 			.caps		= USB_EP_CAPS(USB_EP_CAPS_TYPE_BULK,
2220 						USB_EP_CAPS_DIR_OUT),
2221 		},
2222 		.dev		= &memory,
2223 		.fifo_size	= BULK_FIFO_SIZE,
2224 		.bEndpointAddress = 12,
2225 		.bmAttributes	= USB_ENDPOINT_XFER_BULK,
2226 		.regoff_udccs	= UDCCS12,
2227 		.regoff_ubcr	= UBCR12,
2228 		.regoff_uddr	= UDDR12,
2229 	},
2230 	.ep[13] = {
2231 		.ep = {
2232 			.name		= "ep13in-iso",
2233 			.ops		= &pxa25x_ep_ops,
2234 			.maxpacket	= ISO_FIFO_SIZE,
2235 			.caps		= USB_EP_CAPS(USB_EP_CAPS_TYPE_ISO,
2236 						USB_EP_CAPS_DIR_IN),
2237 		},
2238 		.dev		= &memory,
2239 		.fifo_size	= ISO_FIFO_SIZE,
2240 		.bEndpointAddress = USB_DIR_IN | 13,
2241 		.bmAttributes	= USB_ENDPOINT_XFER_ISOC,
2242 		.regoff_udccs	= UDCCS13,
2243 		.regoff_uddr	= UDDR13,
2244 	},
2245 	.ep[14] = {
2246 		.ep = {
2247 			.name		= "ep14out-iso",
2248 			.ops		= &pxa25x_ep_ops,
2249 			.maxpacket	= ISO_FIFO_SIZE,
2250 			.caps		= USB_EP_CAPS(USB_EP_CAPS_TYPE_ISO,
2251 						USB_EP_CAPS_DIR_OUT),
2252 		},
2253 		.dev		= &memory,
2254 		.fifo_size	= ISO_FIFO_SIZE,
2255 		.bEndpointAddress = 14,
2256 		.bmAttributes	= USB_ENDPOINT_XFER_ISOC,
2257 		.regoff_udccs	= UDCCS14,
2258 		.regoff_ubcr	= UBCR14,
2259 		.regoff_uddr	= UDDR14,
2260 	},
2261 	.ep[15] = {
2262 		.ep = {
2263 			.name		= "ep15in-int",
2264 			.ops		= &pxa25x_ep_ops,
2265 			.maxpacket	= INT_FIFO_SIZE,
2266 			.caps		= USB_EP_CAPS(0, 0),
2267 		},
2268 		.dev		= &memory,
2269 		.fifo_size	= INT_FIFO_SIZE,
2270 		.bEndpointAddress = USB_DIR_IN | 15,
2271 		.bmAttributes	= USB_ENDPOINT_XFER_INT,
2272 		.regoff_udccs	= UDCCS15,
2273 		.regoff_uddr	= UDDR15,
2274 	},
2275 #endif /* !CONFIG_USB_PXA25X_SMALL */
2276 };
2277 
2278 #define CP15R0_VENDOR_MASK	0xffffe000
2279 
2280 #if	defined(CONFIG_ARCH_PXA)
2281 #define CP15R0_XSCALE_VALUE	0x69052000	/* intel/arm/xscale */
2282 
2283 #elif	defined(CONFIG_ARCH_IXP4XX)
2284 #define CP15R0_XSCALE_VALUE	0x69054000	/* intel/arm/ixp4xx */
2285 
2286 #endif
2287 
2288 #define CP15R0_PROD_MASK	0x000003f0
2289 #define PXA25x			0x00000100	/* and PXA26x */
2290 #define PXA210			0x00000120
2291 
2292 #define CP15R0_REV_MASK		0x0000000f
2293 
2294 #define CP15R0_PRODREV_MASK	(CP15R0_PROD_MASK | CP15R0_REV_MASK)
2295 
2296 #define PXA255_A0		0x00000106	/* or PXA260_B1 */
2297 #define PXA250_C0		0x00000105	/* or PXA26x_B0 */
2298 #define PXA250_B2		0x00000104
2299 #define PXA250_B1		0x00000103	/* or PXA260_A0 */
2300 #define PXA250_B0		0x00000102
2301 #define PXA250_A1		0x00000101
2302 #define PXA250_A0		0x00000100
2303 
2304 #define PXA210_C0		0x00000125
2305 #define PXA210_B2		0x00000124
2306 #define PXA210_B1		0x00000123
2307 #define PXA210_B0		0x00000122
2308 #define IXP425_A0		0x000001c1
2309 #define IXP425_B0		0x000001f1
2310 #define IXP465_AD		0x00000200
2311 
2312 /*
2313  *	probe - binds to the platform device
2314  */
2315 static int pxa25x_udc_probe(struct platform_device *pdev)
2316 {
2317 	struct pxa25x_udc *dev = &memory;
2318 	int retval, irq;
2319 	u32 chiprev;
2320 
2321 	pr_info("%s: version %s\n", driver_name, DRIVER_VERSION);
2322 
2323 	/* insist on Intel/ARM/XScale */
2324 	asm("mrc p15, 0, %0, c0, c0" : "=r" (chiprev));
2325 	if ((chiprev & CP15R0_VENDOR_MASK) != CP15R0_XSCALE_VALUE) {
2326 		pr_err("%s: not XScale!\n", driver_name);
2327 		return -ENODEV;
2328 	}
2329 
2330 	/* trigger chiprev-specific logic */
2331 	switch (chiprev & CP15R0_PRODREV_MASK) {
2332 #if	defined(CONFIG_ARCH_PXA)
2333 	case PXA255_A0:
2334 		dev->has_cfr = 1;
2335 		break;
2336 	case PXA250_A0:
2337 	case PXA250_A1:
2338 		/* A0/A1 "not released"; ep 13, 15 unusable */
2339 		fallthrough;
2340 	case PXA250_B2: case PXA210_B2:
2341 	case PXA250_B1: case PXA210_B1:
2342 	case PXA250_B0: case PXA210_B0:
2343 		/* OUT-DMA is broken ... */
2344 		fallthrough;
2345 	case PXA250_C0: case PXA210_C0:
2346 		break;
2347 #elif	defined(CONFIG_ARCH_IXP4XX)
2348 	case IXP425_A0:
2349 	case IXP425_B0:
2350 	case IXP465_AD:
2351 		dev->has_cfr = 1;
2352 		break;
2353 #endif
2354 	default:
2355 		pr_err("%s: unrecognized processor: %08x\n",
2356 			driver_name, chiprev);
2357 		/* iop3xx, ixp4xx, ... */
2358 		return -ENODEV;
2359 	}
2360 
2361 	irq = platform_get_irq(pdev, 0);
2362 	if (irq < 0)
2363 		return irq;
2364 
2365 	dev->regs = devm_platform_ioremap_resource(pdev, 0);
2366 	if (IS_ERR(dev->regs))
2367 		return PTR_ERR(dev->regs);
2368 
2369 	dev->clk = devm_clk_get(&pdev->dev, NULL);
2370 	if (IS_ERR(dev->clk))
2371 		return PTR_ERR(dev->clk);
2372 
2373 	pr_debug("%s: IRQ %d%s%s\n", driver_name, irq,
2374 		dev->has_cfr ? "" : " (!cfr)",
2375 		SIZE_STR "(pio)"
2376 		);
2377 
2378 	/* other non-static parts of init */
2379 	dev->dev = &pdev->dev;
2380 	dev->mach = dev_get_platdata(&pdev->dev);
2381 
2382 	dev->transceiver = devm_usb_get_phy(&pdev->dev, USB_PHY_TYPE_USB2);
2383 
2384 	if (gpio_is_valid(dev->mach->gpio_pullup)) {
2385 		retval = devm_gpio_request(&pdev->dev, dev->mach->gpio_pullup,
2386 					   "pca25x_udc GPIO PULLUP");
2387 		if (retval) {
2388 			dev_dbg(&pdev->dev,
2389 				"can't get pullup gpio %d, err: %d\n",
2390 				dev->mach->gpio_pullup, retval);
2391 			goto err;
2392 		}
2393 		gpio_direction_output(dev->mach->gpio_pullup, 0);
2394 	}
2395 
2396 	timer_setup(&dev->timer, udc_watchdog, 0);
2397 
2398 	the_controller = dev;
2399 	platform_set_drvdata(pdev, dev);
2400 
2401 	udc_disable(dev);
2402 	udc_reinit(dev);
2403 
2404 	dev->vbus = 0;
2405 
2406 	/* irq setup after old hardware state is cleaned up */
2407 	retval = devm_request_irq(&pdev->dev, irq, pxa25x_udc_irq, 0,
2408 				  driver_name, dev);
2409 	if (retval != 0) {
2410 		pr_err("%s: can't get irq %d, err %d\n",
2411 			driver_name, irq, retval);
2412 		goto err;
2413 	}
2414 	dev->got_irq = 1;
2415 
2416 #ifdef CONFIG_ARCH_LUBBOCK
2417 	if (machine_is_lubbock()) {
2418 		dev->usb_irq = platform_get_irq(pdev, 1);
2419 		if (dev->usb_irq < 0)
2420 			return dev->usb_irq;
2421 
2422 		dev->usb_disc_irq = platform_get_irq(pdev, 2);
2423 		if (dev->usb_disc_irq < 0)
2424 			return dev->usb_disc_irq;
2425 
2426 		retval = devm_request_irq(&pdev->dev, dev->usb_disc_irq,
2427 					  lubbock_vbus_irq, 0, driver_name,
2428 					  dev);
2429 		if (retval != 0) {
2430 			pr_err("%s: can't get irq %i, err %d\n",
2431 				driver_name, dev->usb_disc_irq, retval);
2432 			goto err;
2433 		}
2434 		retval = devm_request_irq(&pdev->dev, dev->usb_irq,
2435 					  lubbock_vbus_irq, 0, driver_name,
2436 					  dev);
2437 		if (retval != 0) {
2438 			pr_err("%s: can't get irq %i, err %d\n",
2439 				driver_name, dev->usb_irq, retval);
2440 			goto err;
2441 		}
2442 	} else
2443 #endif
2444 	create_debug_files(dev);
2445 
2446 	retval = usb_add_gadget_udc(&pdev->dev, &dev->gadget);
2447 	if (!retval)
2448 		return retval;
2449 
2450 	remove_debug_files(dev);
2451  err:
2452 	if (!IS_ERR_OR_NULL(dev->transceiver))
2453 		dev->transceiver = NULL;
2454 	return retval;
2455 }
2456 
2457 static void pxa25x_udc_shutdown(struct platform_device *_dev)
2458 {
2459 	pullup_off();
2460 }
2461 
2462 static int pxa25x_udc_remove(struct platform_device *pdev)
2463 {
2464 	struct pxa25x_udc *dev = platform_get_drvdata(pdev);
2465 
2466 	if (dev->driver)
2467 		return -EBUSY;
2468 
2469 	usb_del_gadget_udc(&dev->gadget);
2470 	dev->pullup = 0;
2471 	pullup(dev);
2472 
2473 	remove_debug_files(dev);
2474 
2475 	if (!IS_ERR_OR_NULL(dev->transceiver))
2476 		dev->transceiver = NULL;
2477 
2478 	the_controller = NULL;
2479 	return 0;
2480 }
2481 
2482 /*-------------------------------------------------------------------------*/
2483 
2484 #ifdef	CONFIG_PM
2485 
2486 /* USB suspend (controlled by the host) and system suspend (controlled
2487  * by the PXA) don't necessarily work well together.  If USB is active,
2488  * the 48 MHz clock is required; so the system can't enter 33 MHz idle
2489  * mode, or any deeper PM saving state.
2490  *
2491  * For now, we punt and forcibly disconnect from the USB host when PXA
2492  * enters any suspend state.  While we're disconnected, we always disable
2493  * the 48MHz USB clock ... allowing PXA sleep and/or 33 MHz idle states.
2494  * Boards without software pullup control shouldn't use those states.
2495  * VBUS IRQs should probably be ignored so that the PXA device just acts
2496  * "dead" to USB hosts until system resume.
2497  */
2498 static int pxa25x_udc_suspend(struct platform_device *dev, pm_message_t state)
2499 {
2500 	struct pxa25x_udc	*udc = platform_get_drvdata(dev);
2501 	unsigned long flags;
2502 
2503 	if (!gpio_is_valid(udc->mach->gpio_pullup) && !udc->mach->udc_command)
2504 		WARNING("USB host won't detect disconnect!\n");
2505 	udc->suspended = 1;
2506 
2507 	local_irq_save(flags);
2508 	pullup(udc);
2509 	local_irq_restore(flags);
2510 
2511 	return 0;
2512 }
2513 
2514 static int pxa25x_udc_resume(struct platform_device *dev)
2515 {
2516 	struct pxa25x_udc	*udc = platform_get_drvdata(dev);
2517 	unsigned long flags;
2518 
2519 	udc->suspended = 0;
2520 	local_irq_save(flags);
2521 	pullup(udc);
2522 	local_irq_restore(flags);
2523 
2524 	return 0;
2525 }
2526 
2527 #else
2528 #define	pxa25x_udc_suspend	NULL
2529 #define	pxa25x_udc_resume	NULL
2530 #endif
2531 
2532 /*-------------------------------------------------------------------------*/
2533 
2534 static struct platform_driver udc_driver = {
2535 	.shutdown	= pxa25x_udc_shutdown,
2536 	.probe		= pxa25x_udc_probe,
2537 	.remove		= pxa25x_udc_remove,
2538 	.suspend	= pxa25x_udc_suspend,
2539 	.resume		= pxa25x_udc_resume,
2540 	.driver		= {
2541 		.name	= "pxa25x-udc",
2542 	},
2543 };
2544 
2545 module_platform_driver(udc_driver);
2546 
2547 MODULE_DESCRIPTION(DRIVER_DESC);
2548 MODULE_AUTHOR("Frank Becker, Robert Schwebel, David Brownell");
2549 MODULE_LICENSE("GPL");
2550 MODULE_ALIAS("platform:pxa25x-udc");
2551