1 // SPDX-License-Identifier: GPL-2.0+
2 /*
3  * Intel PXA25x and IXP4xx on-chip full speed USB device controllers
4  *
5  * Copyright (C) 2002 Intrinsyc, Inc. (Frank Becker)
6  * Copyright (C) 2003 Robert Schwebel, Pengutronix
7  * Copyright (C) 2003 Benedikt Spranger, Pengutronix
8  * Copyright (C) 2003 David Brownell
9  * Copyright (C) 2003 Joshua Wise
10  */
11 
12 /* #define VERBOSE_DEBUG */
13 
14 #include <linux/device.h>
15 #include <linux/gpio.h>
16 #include <linux/module.h>
17 #include <linux/kernel.h>
18 #include <linux/ioport.h>
19 #include <linux/types.h>
20 #include <linux/errno.h>
21 #include <linux/err.h>
22 #include <linux/delay.h>
23 #include <linux/slab.h>
24 #include <linux/timer.h>
25 #include <linux/list.h>
26 #include <linux/interrupt.h>
27 #include <linux/mm.h>
28 #include <linux/platform_data/pxa2xx_udc.h>
29 #include <linux/platform_device.h>
30 #include <linux/dma-mapping.h>
31 #include <linux/irq.h>
32 #include <linux/clk.h>
33 #include <linux/seq_file.h>
34 #include <linux/debugfs.h>
35 #include <linux/io.h>
36 #include <linux/prefetch.h>
37 
38 #include <asm/byteorder.h>
39 #include <asm/dma.h>
40 #include <asm/mach-types.h>
41 #include <asm/unaligned.h>
42 
43 #include <linux/usb/ch9.h>
44 #include <linux/usb/gadget.h>
45 #include <linux/usb/otg.h>
46 
47 #ifdef CONFIG_ARCH_LUBBOCK
48 #include <mach/lubbock.h>
49 #endif
50 
51 #define UDCCR	 0x0000 /* UDC Control Register */
52 #define UDC_RES1 0x0004 /* UDC Undocumented - Reserved1 */
53 #define UDC_RES2 0x0008 /* UDC Undocumented - Reserved2 */
54 #define UDC_RES3 0x000C /* UDC Undocumented - Reserved3 */
55 #define UDCCS0	 0x0010 /* UDC Endpoint 0 Control/Status Register */
56 #define UDCCS1	 0x0014 /* UDC Endpoint 1 (IN) Control/Status Register */
57 #define UDCCS2	 0x0018 /* UDC Endpoint 2 (OUT) Control/Status Register */
58 #define UDCCS3	 0x001C /* UDC Endpoint 3 (IN) Control/Status Register */
59 #define UDCCS4	 0x0020 /* UDC Endpoint 4 (OUT) Control/Status Register */
60 #define UDCCS5	 0x0024 /* UDC Endpoint 5 (Interrupt) Control/Status Register */
61 #define UDCCS6	 0x0028 /* UDC Endpoint 6 (IN) Control/Status Register */
62 #define UDCCS7	 0x002C /* UDC Endpoint 7 (OUT) Control/Status Register */
63 #define UDCCS8	 0x0030 /* UDC Endpoint 8 (IN) Control/Status Register */
64 #define UDCCS9	 0x0034 /* UDC Endpoint 9 (OUT) Control/Status Register */
65 #define UDCCS10	 0x0038 /* UDC Endpoint 10 (Interrupt) Control/Status Register */
66 #define UDCCS11	 0x003C /* UDC Endpoint 11 (IN) Control/Status Register */
67 #define UDCCS12	 0x0040 /* UDC Endpoint 12 (OUT) Control/Status Register */
68 #define UDCCS13	 0x0044 /* UDC Endpoint 13 (IN) Control/Status Register */
69 #define UDCCS14	 0x0048 /* UDC Endpoint 14 (OUT) Control/Status Register */
70 #define UDCCS15	 0x004C /* UDC Endpoint 15 (Interrupt) Control/Status Register */
71 #define UFNRH	 0x0060 /* UDC Frame Number Register High */
72 #define UFNRL	 0x0064 /* UDC Frame Number Register Low */
73 #define UBCR2	 0x0068 /* UDC Byte Count Reg 2 */
74 #define UBCR4	 0x006c /* UDC Byte Count Reg 4 */
75 #define UBCR7	 0x0070 /* UDC Byte Count Reg 7 */
76 #define UBCR9	 0x0074 /* UDC Byte Count Reg 9 */
77 #define UBCR12	 0x0078 /* UDC Byte Count Reg 12 */
78 #define UBCR14	 0x007c /* UDC Byte Count Reg 14 */
79 #define UDDR0	 0x0080 /* UDC Endpoint 0 Data Register */
80 #define UDDR1	 0x0100 /* UDC Endpoint 1 Data Register */
81 #define UDDR2	 0x0180 /* UDC Endpoint 2 Data Register */
82 #define UDDR3	 0x0200 /* UDC Endpoint 3 Data Register */
83 #define UDDR4	 0x0400 /* UDC Endpoint 4 Data Register */
84 #define UDDR5	 0x00A0 /* UDC Endpoint 5 Data Register */
85 #define UDDR6	 0x0600 /* UDC Endpoint 6 Data Register */
86 #define UDDR7	 0x0680 /* UDC Endpoint 7 Data Register */
87 #define UDDR8	 0x0700 /* UDC Endpoint 8 Data Register */
88 #define UDDR9	 0x0900 /* UDC Endpoint 9 Data Register */
89 #define UDDR10	 0x00C0 /* UDC Endpoint 10 Data Register */
90 #define UDDR11	 0x0B00 /* UDC Endpoint 11 Data Register */
91 #define UDDR12	 0x0B80 /* UDC Endpoint 12 Data Register */
92 #define UDDR13	 0x0C00 /* UDC Endpoint 13 Data Register */
93 #define UDDR14	 0x0E00 /* UDC Endpoint 14 Data Register */
94 #define UDDR15	 0x00E0 /* UDC Endpoint 15 Data Register */
95 
96 #define UICR0	 0x0050 /* UDC Interrupt Control Register 0 */
97 #define UICR1	 0x0054 /* UDC Interrupt Control Register 1 */
98 
99 #define USIR0	 0x0058 /* UDC Status Interrupt Register 0 */
100 #define USIR1	 0x005C /* UDC Status Interrupt Register 1 */
101 
102 #define UDCCR_UDE	(1 << 0)	/* UDC enable */
103 #define UDCCR_UDA	(1 << 1)	/* UDC active */
104 #define UDCCR_RSM	(1 << 2)	/* Device resume */
105 #define UDCCR_RESIR	(1 << 3)	/* Resume interrupt request */
106 #define UDCCR_SUSIR	(1 << 4)	/* Suspend interrupt request */
107 #define UDCCR_SRM	(1 << 5)	/* Suspend/resume interrupt mask */
108 #define UDCCR_RSTIR	(1 << 6)	/* Reset interrupt request */
109 #define UDCCR_REM	(1 << 7)	/* Reset interrupt mask */
110 
111 #define UDCCS0_OPR	(1 << 0)	/* OUT packet ready */
112 #define UDCCS0_IPR	(1 << 1)	/* IN packet ready */
113 #define UDCCS0_FTF	(1 << 2)	/* Flush Tx FIFO */
114 #define UDCCS0_DRWF	(1 << 3)	/* Device remote wakeup feature */
115 #define UDCCS0_SST	(1 << 4)	/* Sent stall */
116 #define UDCCS0_FST	(1 << 5)	/* Force stall */
117 #define UDCCS0_RNE	(1 << 6)	/* Receive FIFO no empty */
118 #define UDCCS0_SA	(1 << 7)	/* Setup active */
119 
120 #define UDCCS_BI_TFS	(1 << 0)	/* Transmit FIFO service */
121 #define UDCCS_BI_TPC	(1 << 1)	/* Transmit packet complete */
122 #define UDCCS_BI_FTF	(1 << 2)	/* Flush Tx FIFO */
123 #define UDCCS_BI_TUR	(1 << 3)	/* Transmit FIFO underrun */
124 #define UDCCS_BI_SST	(1 << 4)	/* Sent stall */
125 #define UDCCS_BI_FST	(1 << 5)	/* Force stall */
126 #define UDCCS_BI_TSP	(1 << 7)	/* Transmit short packet */
127 
128 #define UDCCS_BO_RFS	(1 << 0)	/* Receive FIFO service */
129 #define UDCCS_BO_RPC	(1 << 1)	/* Receive packet complete */
130 #define UDCCS_BO_DME	(1 << 3)	/* DMA enable */
131 #define UDCCS_BO_SST	(1 << 4)	/* Sent stall */
132 #define UDCCS_BO_FST	(1 << 5)	/* Force stall */
133 #define UDCCS_BO_RNE	(1 << 6)	/* Receive FIFO not empty */
134 #define UDCCS_BO_RSP	(1 << 7)	/* Receive short packet */
135 
136 #define UDCCS_II_TFS	(1 << 0)	/* Transmit FIFO service */
137 #define UDCCS_II_TPC	(1 << 1)	/* Transmit packet complete */
138 #define UDCCS_II_FTF	(1 << 2)	/* Flush Tx FIFO */
139 #define UDCCS_II_TUR	(1 << 3)	/* Transmit FIFO underrun */
140 #define UDCCS_II_TSP	(1 << 7)	/* Transmit short packet */
141 
142 #define UDCCS_IO_RFS	(1 << 0)	/* Receive FIFO service */
143 #define UDCCS_IO_RPC	(1 << 1)	/* Receive packet complete */
144 #ifdef CONFIG_ARCH_IXP4XX /* FIXME: is this right?, datasheed says '2' */
145 #define UDCCS_IO_ROF	(1 << 3)	/* Receive overflow */
146 #endif
147 #ifdef CONFIG_ARCH_PXA
148 #define UDCCS_IO_ROF	(1 << 2)	/* Receive overflow */
149 #endif
150 #define UDCCS_IO_DME	(1 << 3)	/* DMA enable */
151 #define UDCCS_IO_RNE	(1 << 6)	/* Receive FIFO not empty */
152 #define UDCCS_IO_RSP	(1 << 7)	/* Receive short packet */
153 
154 #define UDCCS_INT_TFS	(1 << 0)	/* Transmit FIFO service */
155 #define UDCCS_INT_TPC	(1 << 1)	/* Transmit packet complete */
156 #define UDCCS_INT_FTF	(1 << 2)	/* Flush Tx FIFO */
157 #define UDCCS_INT_TUR	(1 << 3)	/* Transmit FIFO underrun */
158 #define UDCCS_INT_SST	(1 << 4)	/* Sent stall */
159 #define UDCCS_INT_FST	(1 << 5)	/* Force stall */
160 #define UDCCS_INT_TSP	(1 << 7)	/* Transmit short packet */
161 
162 #define UICR0_IM0	(1 << 0)	/* Interrupt mask ep 0 */
163 #define UICR0_IM1	(1 << 1)	/* Interrupt mask ep 1 */
164 #define UICR0_IM2	(1 << 2)	/* Interrupt mask ep 2 */
165 #define UICR0_IM3	(1 << 3)	/* Interrupt mask ep 3 */
166 #define UICR0_IM4	(1 << 4)	/* Interrupt mask ep 4 */
167 #define UICR0_IM5	(1 << 5)	/* Interrupt mask ep 5 */
168 #define UICR0_IM6	(1 << 6)	/* Interrupt mask ep 6 */
169 #define UICR0_IM7	(1 << 7)	/* Interrupt mask ep 7 */
170 
171 #define UICR1_IM8	(1 << 0)	/* Interrupt mask ep 8 */
172 #define UICR1_IM9	(1 << 1)	/* Interrupt mask ep 9 */
173 #define UICR1_IM10	(1 << 2)	/* Interrupt mask ep 10 */
174 #define UICR1_IM11	(1 << 3)	/* Interrupt mask ep 11 */
175 #define UICR1_IM12	(1 << 4)	/* Interrupt mask ep 12 */
176 #define UICR1_IM13	(1 << 5)	/* Interrupt mask ep 13 */
177 #define UICR1_IM14	(1 << 6)	/* Interrupt mask ep 14 */
178 #define UICR1_IM15	(1 << 7)	/* Interrupt mask ep 15 */
179 
180 #define USIR0_IR0	(1 << 0)	/* Interrupt request ep 0 */
181 #define USIR0_IR1	(1 << 1)	/* Interrupt request ep 1 */
182 #define USIR0_IR2	(1 << 2)	/* Interrupt request ep 2 */
183 #define USIR0_IR3	(1 << 3)	/* Interrupt request ep 3 */
184 #define USIR0_IR4	(1 << 4)	/* Interrupt request ep 4 */
185 #define USIR0_IR5	(1 << 5)	/* Interrupt request ep 5 */
186 #define USIR0_IR6	(1 << 6)	/* Interrupt request ep 6 */
187 #define USIR0_IR7	(1 << 7)	/* Interrupt request ep 7 */
188 
189 #define USIR1_IR8	(1 << 0)	/* Interrupt request ep 8 */
190 #define USIR1_IR9	(1 << 1)	/* Interrupt request ep 9 */
191 #define USIR1_IR10	(1 << 2)	/* Interrupt request ep 10 */
192 #define USIR1_IR11	(1 << 3)	/* Interrupt request ep 11 */
193 #define USIR1_IR12	(1 << 4)	/* Interrupt request ep 12 */
194 #define USIR1_IR13	(1 << 5)	/* Interrupt request ep 13 */
195 #define USIR1_IR14	(1 << 6)	/* Interrupt request ep 14 */
196 #define USIR1_IR15	(1 << 7)	/* Interrupt request ep 15 */
197 
198 /*
199  * This driver handles the USB Device Controller (UDC) in Intel's PXA 25x
200  * series processors.  The UDC for the IXP 4xx series is very similar.
201  * There are fifteen endpoints, in addition to ep0.
202  *
203  * Such controller drivers work with a gadget driver.  The gadget driver
204  * returns descriptors, implements configuration and data protocols used
205  * by the host to interact with this device, and allocates endpoints to
206  * the different protocol interfaces.  The controller driver virtualizes
207  * usb hardware so that the gadget drivers will be more portable.
208  *
209  * This UDC hardware wants to implement a bit too much USB protocol, so
210  * it constrains the sorts of USB configuration change events that work.
211  * The errata for these chips are misleading; some "fixed" bugs from
212  * pxa250 a0/a1 b0/b1/b2 sure act like they're still there.
213  *
214  * Note that the UDC hardware supports DMA (except on IXP) but that's
215  * not used here.  IN-DMA (to host) is simple enough, when the data is
216  * suitably aligned (16 bytes) ... the network stack doesn't do that,
217  * other software can.  OUT-DMA is buggy in most chip versions, as well
218  * as poorly designed (data toggle not automatic).  So this driver won't
219  * bother using DMA.  (Mostly-working IN-DMA support was available in
220  * kernels before 2.6.23, but was never enabled or well tested.)
221  */
222 
223 #define	DRIVER_VERSION	"30-June-2007"
224 #define	DRIVER_DESC	"PXA 25x USB Device Controller driver"
225 
226 
227 static const char driver_name [] = "pxa25x_udc";
228 
229 static const char ep0name [] = "ep0";
230 
231 
232 #ifdef CONFIG_ARCH_IXP4XX
233 
234 /* cpu-specific register addresses are compiled in to this code */
235 #ifdef CONFIG_ARCH_PXA
236 #error "Can't configure both IXP and PXA"
237 #endif
238 
239 /* IXP doesn't yet support <linux/clk.h> */
240 #define clk_get(dev,name)	NULL
241 #define clk_enable(clk)		do { } while (0)
242 #define clk_disable(clk)	do { } while (0)
243 #define clk_put(clk)		do { } while (0)
244 
245 #endif
246 
247 #include "pxa25x_udc.h"
248 
249 
250 #ifdef	CONFIG_USB_PXA25X_SMALL
251 #define SIZE_STR	" (small)"
252 #else
253 #define SIZE_STR	""
254 #endif
255 
256 /* ---------------------------------------------------------------------------
257  *	endpoint related parts of the api to the usb controller hardware,
258  *	used by gadget driver; and the inner talker-to-hardware core.
259  * ---------------------------------------------------------------------------
260  */
261 
262 static void pxa25x_ep_fifo_flush (struct usb_ep *ep);
263 static void nuke (struct pxa25x_ep *, int status);
264 
265 /* one GPIO should control a D+ pullup, so host sees this device (or not) */
266 static void pullup_off(void)
267 {
268 	struct pxa2xx_udc_mach_info		*mach = the_controller->mach;
269 	int off_level = mach->gpio_pullup_inverted;
270 
271 	if (gpio_is_valid(mach->gpio_pullup))
272 		gpio_set_value(mach->gpio_pullup, off_level);
273 	else if (mach->udc_command)
274 		mach->udc_command(PXA2XX_UDC_CMD_DISCONNECT);
275 }
276 
277 static void pullup_on(void)
278 {
279 	struct pxa2xx_udc_mach_info		*mach = the_controller->mach;
280 	int on_level = !mach->gpio_pullup_inverted;
281 
282 	if (gpio_is_valid(mach->gpio_pullup))
283 		gpio_set_value(mach->gpio_pullup, on_level);
284 	else if (mach->udc_command)
285 		mach->udc_command(PXA2XX_UDC_CMD_CONNECT);
286 }
287 
288 #if defined(CONFIG_CPU_BIG_ENDIAN)
289 /*
290  * IXP4xx has its buses wired up in a way that relies on never doing any
291  * byte swaps, independent of whether it runs in big-endian or little-endian
292  * mode, as explained by Krzysztof Hałasa.
293  *
294  * We only support pxa25x in little-endian mode, but it is very likely
295  * that it works the same way.
296  */
297 static inline void udc_set_reg(struct pxa25x_udc *dev, u32 reg, u32 val)
298 {
299 	iowrite32be(val, dev->regs + reg);
300 }
301 
302 static inline u32 udc_get_reg(struct pxa25x_udc *dev, u32 reg)
303 {
304 	return ioread32be(dev->regs + reg);
305 }
306 #else
307 static inline void udc_set_reg(struct pxa25x_udc *dev, u32 reg, u32 val)
308 {
309 	writel(val, dev->regs + reg);
310 }
311 
312 static inline u32 udc_get_reg(struct pxa25x_udc *dev, u32 reg)
313 {
314 	return readl(dev->regs + reg);
315 }
316 #endif
317 
318 static void pio_irq_enable(struct pxa25x_ep *ep)
319 {
320 	u32 bEndpointAddress = ep->bEndpointAddress & 0xf;
321 
322         if (bEndpointAddress < 8)
323 		udc_set_reg(ep->dev, UICR0, udc_get_reg(ep->dev, UICR0) &
324 						~(1 << bEndpointAddress));
325         else {
326                 bEndpointAddress -= 8;
327 		udc_set_reg(ep->dev, UICR1, udc_get_reg(ep->dev, UICR1) &
328 						~(1 << bEndpointAddress));
329 	}
330 }
331 
332 static void pio_irq_disable(struct pxa25x_ep *ep)
333 {
334 	u32 bEndpointAddress = ep->bEndpointAddress & 0xf;
335 
336         if (bEndpointAddress < 8)
337                 udc_set_reg(ep->dev, UICR0, udc_get_reg(ep->dev, UICR0) |
338 						(1 << bEndpointAddress));
339         else {
340                 bEndpointAddress -= 8;
341                 udc_set_reg(ep->dev, UICR1, udc_get_reg(ep->dev, UICR1) |
342 						(1 << bEndpointAddress));
343         }
344 }
345 
346 /* The UDCCR reg contains mask and interrupt status bits,
347  * so using '|=' isn't safe as it may ack an interrupt.
348  */
349 #define UDCCR_MASK_BITS         (UDCCR_REM | UDCCR_SRM | UDCCR_UDE)
350 
351 static inline void udc_set_mask_UDCCR(struct pxa25x_udc *dev, int mask)
352 {
353 	u32 udccr = udc_get_reg(dev, UDCCR);
354 
355 	udc_set_reg(dev, (udccr & UDCCR_MASK_BITS) | (mask & UDCCR_MASK_BITS), UDCCR);
356 }
357 
358 static inline void udc_clear_mask_UDCCR(struct pxa25x_udc *dev, int mask)
359 {
360 	u32 udccr = udc_get_reg(dev, UDCCR);
361 
362 	udc_set_reg(dev, (udccr & UDCCR_MASK_BITS) & ~(mask & UDCCR_MASK_BITS), UDCCR);
363 }
364 
365 static inline void udc_ack_int_UDCCR(struct pxa25x_udc *dev, int mask)
366 {
367 	/* udccr contains the bits we dont want to change */
368 	u32 udccr = udc_get_reg(dev, UDCCR) & UDCCR_MASK_BITS;
369 
370 	udc_set_reg(dev, udccr | (mask & ~UDCCR_MASK_BITS), UDCCR);
371 }
372 
373 static inline u32 udc_ep_get_UDCCS(struct pxa25x_ep *ep)
374 {
375 	return udc_get_reg(ep->dev, ep->regoff_udccs);
376 }
377 
378 static inline void udc_ep_set_UDCCS(struct pxa25x_ep *ep, u32 data)
379 {
380 	udc_set_reg(ep->dev, data, ep->regoff_udccs);
381 }
382 
383 static inline u32 udc_ep0_get_UDCCS(struct pxa25x_udc *dev)
384 {
385 	return udc_get_reg(dev, UDCCS0);
386 }
387 
388 static inline void udc_ep0_set_UDCCS(struct pxa25x_udc *dev, u32 data)
389 {
390 	udc_set_reg(dev, data, UDCCS0);
391 }
392 
393 static inline u32 udc_ep_get_UDDR(struct pxa25x_ep *ep)
394 {
395 	return udc_get_reg(ep->dev, ep->regoff_uddr);
396 }
397 
398 static inline void udc_ep_set_UDDR(struct pxa25x_ep *ep, u32 data)
399 {
400 	udc_set_reg(ep->dev, data, ep->regoff_uddr);
401 }
402 
403 static inline u32 udc_ep_get_UBCR(struct pxa25x_ep *ep)
404 {
405 	return udc_get_reg(ep->dev, ep->regoff_ubcr);
406 }
407 
408 /*
409  * endpoint enable/disable
410  *
411  * we need to verify the descriptors used to enable endpoints.  since pxa25x
412  * endpoint configurations are fixed, and are pretty much always enabled,
413  * there's not a lot to manage here.
414  *
415  * because pxa25x can't selectively initialize bulk (or interrupt) endpoints,
416  * (resetting endpoint halt and toggle), SET_INTERFACE is unusable except
417  * for a single interface (with only the default altsetting) and for gadget
418  * drivers that don't halt endpoints (not reset by set_interface).  that also
419  * means that if you use ISO, you must violate the USB spec rule that all
420  * iso endpoints must be in non-default altsettings.
421  */
422 static int pxa25x_ep_enable (struct usb_ep *_ep,
423 		const struct usb_endpoint_descriptor *desc)
424 {
425 	struct pxa25x_ep        *ep;
426 	struct pxa25x_udc       *dev;
427 
428 	ep = container_of (_ep, struct pxa25x_ep, ep);
429 	if (!_ep || !desc || _ep->name == ep0name
430 			|| desc->bDescriptorType != USB_DT_ENDPOINT
431 			|| ep->bEndpointAddress != desc->bEndpointAddress
432 			|| ep->fifo_size < usb_endpoint_maxp (desc)) {
433 		DMSG("%s, bad ep or descriptor\n", __func__);
434 		return -EINVAL;
435 	}
436 
437 	/* xfer types must match, except that interrupt ~= bulk */
438 	if (ep->bmAttributes != desc->bmAttributes
439 			&& ep->bmAttributes != USB_ENDPOINT_XFER_BULK
440 			&& desc->bmAttributes != USB_ENDPOINT_XFER_INT) {
441 		DMSG("%s, %s type mismatch\n", __func__, _ep->name);
442 		return -EINVAL;
443 	}
444 
445 	/* hardware _could_ do smaller, but driver doesn't */
446 	if ((desc->bmAttributes == USB_ENDPOINT_XFER_BULK
447 				&& usb_endpoint_maxp (desc)
448 						!= BULK_FIFO_SIZE)
449 			|| !desc->wMaxPacketSize) {
450 		DMSG("%s, bad %s maxpacket\n", __func__, _ep->name);
451 		return -ERANGE;
452 	}
453 
454 	dev = ep->dev;
455 	if (!dev->driver || dev->gadget.speed == USB_SPEED_UNKNOWN) {
456 		DMSG("%s, bogus device state\n", __func__);
457 		return -ESHUTDOWN;
458 	}
459 
460 	ep->ep.desc = desc;
461 	ep->stopped = 0;
462 	ep->pio_irqs = 0;
463 	ep->ep.maxpacket = usb_endpoint_maxp (desc);
464 
465 	/* flush fifo (mostly for OUT buffers) */
466 	pxa25x_ep_fifo_flush (_ep);
467 
468 	/* ... reset halt state too, if we could ... */
469 
470 	DBG(DBG_VERBOSE, "enabled %s\n", _ep->name);
471 	return 0;
472 }
473 
474 static int pxa25x_ep_disable (struct usb_ep *_ep)
475 {
476 	struct pxa25x_ep	*ep;
477 	unsigned long		flags;
478 
479 	ep = container_of (_ep, struct pxa25x_ep, ep);
480 	if (!_ep || !ep->ep.desc) {
481 		DMSG("%s, %s not enabled\n", __func__,
482 			_ep ? ep->ep.name : NULL);
483 		return -EINVAL;
484 	}
485 	local_irq_save(flags);
486 
487 	nuke (ep, -ESHUTDOWN);
488 
489 	/* flush fifo (mostly for IN buffers) */
490 	pxa25x_ep_fifo_flush (_ep);
491 
492 	ep->ep.desc = NULL;
493 	ep->stopped = 1;
494 
495 	local_irq_restore(flags);
496 	DBG(DBG_VERBOSE, "%s disabled\n", _ep->name);
497 	return 0;
498 }
499 
500 /*-------------------------------------------------------------------------*/
501 
502 /* for the pxa25x, these can just wrap kmalloc/kfree.  gadget drivers
503  * must still pass correctly initialized endpoints, since other controller
504  * drivers may care about how it's currently set up (dma issues etc).
505  */
506 
507 /*
508  *	pxa25x_ep_alloc_request - allocate a request data structure
509  */
510 static struct usb_request *
511 pxa25x_ep_alloc_request (struct usb_ep *_ep, gfp_t gfp_flags)
512 {
513 	struct pxa25x_request *req;
514 
515 	req = kzalloc(sizeof(*req), gfp_flags);
516 	if (!req)
517 		return NULL;
518 
519 	INIT_LIST_HEAD (&req->queue);
520 	return &req->req;
521 }
522 
523 
524 /*
525  *	pxa25x_ep_free_request - deallocate a request data structure
526  */
527 static void
528 pxa25x_ep_free_request (struct usb_ep *_ep, struct usb_request *_req)
529 {
530 	struct pxa25x_request	*req;
531 
532 	req = container_of (_req, struct pxa25x_request, req);
533 	WARN_ON(!list_empty (&req->queue));
534 	kfree(req);
535 }
536 
537 /*-------------------------------------------------------------------------*/
538 
539 /*
540  *	done - retire a request; caller blocked irqs
541  */
542 static void done(struct pxa25x_ep *ep, struct pxa25x_request *req, int status)
543 {
544 	unsigned		stopped = ep->stopped;
545 
546 	list_del_init(&req->queue);
547 
548 	if (likely (req->req.status == -EINPROGRESS))
549 		req->req.status = status;
550 	else
551 		status = req->req.status;
552 
553 	if (status && status != -ESHUTDOWN)
554 		DBG(DBG_VERBOSE, "complete %s req %p stat %d len %u/%u\n",
555 			ep->ep.name, &req->req, status,
556 			req->req.actual, req->req.length);
557 
558 	/* don't modify queue heads during completion callback */
559 	ep->stopped = 1;
560 	usb_gadget_giveback_request(&ep->ep, &req->req);
561 	ep->stopped = stopped;
562 }
563 
564 
565 static inline void ep0_idle (struct pxa25x_udc *dev)
566 {
567 	dev->ep0state = EP0_IDLE;
568 }
569 
570 static int
571 write_packet(struct pxa25x_ep *ep, struct pxa25x_request *req, unsigned max)
572 {
573 	u8		*buf;
574 	unsigned	length, count;
575 
576 	buf = req->req.buf + req->req.actual;
577 	prefetch(buf);
578 
579 	/* how big will this packet be? */
580 	length = min(req->req.length - req->req.actual, max);
581 	req->req.actual += length;
582 
583 	count = length;
584 	while (likely(count--))
585 		udc_ep_set_UDDR(ep, *buf++);
586 
587 	return length;
588 }
589 
590 /*
591  * write to an IN endpoint fifo, as many packets as possible.
592  * irqs will use this to write the rest later.
593  * caller guarantees at least one packet buffer is ready (or a zlp).
594  */
595 static int
596 write_fifo (struct pxa25x_ep *ep, struct pxa25x_request *req)
597 {
598 	unsigned		max;
599 
600 	max = usb_endpoint_maxp(ep->ep.desc);
601 	do {
602 		unsigned	count;
603 		int		is_last, is_short;
604 
605 		count = write_packet(ep, req, max);
606 
607 		/* last packet is usually short (or a zlp) */
608 		if (unlikely (count != max))
609 			is_last = is_short = 1;
610 		else {
611 			if (likely(req->req.length != req->req.actual)
612 					|| req->req.zero)
613 				is_last = 0;
614 			else
615 				is_last = 1;
616 			/* interrupt/iso maxpacket may not fill the fifo */
617 			is_short = unlikely (max < ep->fifo_size);
618 		}
619 
620 		DBG(DBG_VERY_NOISY, "wrote %s %d bytes%s%s %d left %p\n",
621 			ep->ep.name, count,
622 			is_last ? "/L" : "", is_short ? "/S" : "",
623 			req->req.length - req->req.actual, req);
624 
625 		/* let loose that packet. maybe try writing another one,
626 		 * double buffering might work.  TSP, TPC, and TFS
627 		 * bit values are the same for all normal IN endpoints.
628 		 */
629 		udc_ep_set_UDCCS(ep, UDCCS_BI_TPC);
630 		if (is_short)
631 			udc_ep_set_UDCCS(ep, UDCCS_BI_TSP);
632 
633 		/* requests complete when all IN data is in the FIFO */
634 		if (is_last) {
635 			done (ep, req, 0);
636 			if (list_empty(&ep->queue))
637 				pio_irq_disable(ep);
638 			return 1;
639 		}
640 
641 		// TODO experiment: how robust can fifo mode tweaking be?
642 		// double buffering is off in the default fifo mode, which
643 		// prevents TFS from being set here.
644 
645 	} while (udc_ep_get_UDCCS(ep) & UDCCS_BI_TFS);
646 	return 0;
647 }
648 
649 /* caller asserts req->pending (ep0 irq status nyet cleared); starts
650  * ep0 data stage.  these chips want very simple state transitions.
651  */
652 static inline
653 void ep0start(struct pxa25x_udc *dev, u32 flags, const char *tag)
654 {
655 	udc_ep0_set_UDCCS(dev, flags|UDCCS0_SA|UDCCS0_OPR);
656 	udc_set_reg(dev, USIR0, USIR0_IR0);
657 	dev->req_pending = 0;
658 	DBG(DBG_VERY_NOISY, "%s %s, %02x/%02x\n",
659 		__func__, tag, udc_ep0_get_UDCCS(dev), flags);
660 }
661 
662 static int
663 write_ep0_fifo (struct pxa25x_ep *ep, struct pxa25x_request *req)
664 {
665 	struct pxa25x_udc *dev = ep->dev;
666 	unsigned	count;
667 	int		is_short;
668 
669 	count = write_packet(&dev->ep[0], req, EP0_FIFO_SIZE);
670 	ep->dev->stats.write.bytes += count;
671 
672 	/* last packet "must be" short (or a zlp) */
673 	is_short = (count != EP0_FIFO_SIZE);
674 
675 	DBG(DBG_VERY_NOISY, "ep0in %d bytes %d left %p\n", count,
676 		req->req.length - req->req.actual, req);
677 
678 	if (unlikely (is_short)) {
679 		if (ep->dev->req_pending)
680 			ep0start(ep->dev, UDCCS0_IPR, "short IN");
681 		else
682 			udc_ep0_set_UDCCS(dev, UDCCS0_IPR);
683 
684 		count = req->req.length;
685 		done (ep, req, 0);
686 		ep0_idle(ep->dev);
687 #ifndef CONFIG_ARCH_IXP4XX
688 #if 1
689 		/* This seems to get rid of lost status irqs in some cases:
690 		 * host responds quickly, or next request involves config
691 		 * change automagic, or should have been hidden, or ...
692 		 *
693 		 * FIXME get rid of all udelays possible...
694 		 */
695 		if (count >= EP0_FIFO_SIZE) {
696 			count = 100;
697 			do {
698 				if ((udc_ep0_get_UDCCS(dev) & UDCCS0_OPR) != 0) {
699 					/* clear OPR, generate ack */
700 					udc_ep0_set_UDCCS(dev, UDCCS0_OPR);
701 					break;
702 				}
703 				count--;
704 				udelay(1);
705 			} while (count);
706 		}
707 #endif
708 #endif
709 	} else if (ep->dev->req_pending)
710 		ep0start(ep->dev, 0, "IN");
711 	return is_short;
712 }
713 
714 
715 /*
716  * read_fifo -  unload packet(s) from the fifo we use for usb OUT
717  * transfers and put them into the request.  caller should have made
718  * sure there's at least one packet ready.
719  *
720  * returns true if the request completed because of short packet or the
721  * request buffer having filled (and maybe overran till end-of-packet).
722  */
723 static int
724 read_fifo (struct pxa25x_ep *ep, struct pxa25x_request *req)
725 {
726 	for (;;) {
727 		u32		udccs;
728 		u8		*buf;
729 		unsigned	bufferspace, count, is_short;
730 
731 		/* make sure there's a packet in the FIFO.
732 		 * UDCCS_{BO,IO}_RPC are all the same bit value.
733 		 * UDCCS_{BO,IO}_RNE are all the same bit value.
734 		 */
735 		udccs = udc_ep_get_UDCCS(ep);
736 		if (unlikely ((udccs & UDCCS_BO_RPC) == 0))
737 			break;
738 		buf = req->req.buf + req->req.actual;
739 		prefetchw(buf);
740 		bufferspace = req->req.length - req->req.actual;
741 
742 		/* read all bytes from this packet */
743 		if (likely (udccs & UDCCS_BO_RNE)) {
744 			count = 1 + (0x0ff & udc_ep_get_UBCR(ep));
745 			req->req.actual += min (count, bufferspace);
746 		} else /* zlp */
747 			count = 0;
748 		is_short = (count < ep->ep.maxpacket);
749 		DBG(DBG_VERY_NOISY, "read %s %02x, %d bytes%s req %p %d/%d\n",
750 			ep->ep.name, udccs, count,
751 			is_short ? "/S" : "",
752 			req, req->req.actual, req->req.length);
753 		while (likely (count-- != 0)) {
754 			u8	byte = (u8) udc_ep_get_UDDR(ep);
755 
756 			if (unlikely (bufferspace == 0)) {
757 				/* this happens when the driver's buffer
758 				 * is smaller than what the host sent.
759 				 * discard the extra data.
760 				 */
761 				if (req->req.status != -EOVERFLOW)
762 					DMSG("%s overflow %d\n",
763 						ep->ep.name, count);
764 				req->req.status = -EOVERFLOW;
765 			} else {
766 				*buf++ = byte;
767 				bufferspace--;
768 			}
769 		}
770 		udc_ep_set_UDCCS(ep, UDCCS_BO_RPC);
771 		/* RPC/RSP/RNE could now reflect the other packet buffer */
772 
773 		/* iso is one request per packet */
774 		if (ep->bmAttributes == USB_ENDPOINT_XFER_ISOC) {
775 			if (udccs & UDCCS_IO_ROF)
776 				req->req.status = -EHOSTUNREACH;
777 			/* more like "is_done" */
778 			is_short = 1;
779 		}
780 
781 		/* completion */
782 		if (is_short || req->req.actual == req->req.length) {
783 			done (ep, req, 0);
784 			if (list_empty(&ep->queue))
785 				pio_irq_disable(ep);
786 			return 1;
787 		}
788 
789 		/* finished that packet.  the next one may be waiting... */
790 	}
791 	return 0;
792 }
793 
794 /*
795  * special ep0 version of the above.  no UBCR0 or double buffering; status
796  * handshaking is magic.  most device protocols don't need control-OUT.
797  * CDC vendor commands (and RNDIS), mass storage CB/CBI, and some other
798  * protocols do use them.
799  */
800 static int
801 read_ep0_fifo (struct pxa25x_ep *ep, struct pxa25x_request *req)
802 {
803 	u8		*buf, byte;
804 	unsigned	bufferspace;
805 
806 	buf = req->req.buf + req->req.actual;
807 	bufferspace = req->req.length - req->req.actual;
808 
809 	while (udc_ep_get_UDCCS(ep) & UDCCS0_RNE) {
810 		byte = (u8) UDDR0;
811 
812 		if (unlikely (bufferspace == 0)) {
813 			/* this happens when the driver's buffer
814 			 * is smaller than what the host sent.
815 			 * discard the extra data.
816 			 */
817 			if (req->req.status != -EOVERFLOW)
818 				DMSG("%s overflow\n", ep->ep.name);
819 			req->req.status = -EOVERFLOW;
820 		} else {
821 			*buf++ = byte;
822 			req->req.actual++;
823 			bufferspace--;
824 		}
825 	}
826 
827 	udc_ep_set_UDCCS(ep, UDCCS0_OPR | UDCCS0_IPR);
828 
829 	/* completion */
830 	if (req->req.actual >= req->req.length)
831 		return 1;
832 
833 	/* finished that packet.  the next one may be waiting... */
834 	return 0;
835 }
836 
837 /*-------------------------------------------------------------------------*/
838 
839 static int
840 pxa25x_ep_queue(struct usb_ep *_ep, struct usb_request *_req, gfp_t gfp_flags)
841 {
842 	struct pxa25x_request	*req;
843 	struct pxa25x_ep	*ep;
844 	struct pxa25x_udc	*dev;
845 	unsigned long		flags;
846 
847 	req = container_of(_req, struct pxa25x_request, req);
848 	if (unlikely (!_req || !_req->complete || !_req->buf
849 			|| !list_empty(&req->queue))) {
850 		DMSG("%s, bad params\n", __func__);
851 		return -EINVAL;
852 	}
853 
854 	ep = container_of(_ep, struct pxa25x_ep, ep);
855 	if (unlikely(!_ep || (!ep->ep.desc && ep->ep.name != ep0name))) {
856 		DMSG("%s, bad ep\n", __func__);
857 		return -EINVAL;
858 	}
859 
860 	dev = ep->dev;
861 	if (unlikely (!dev->driver
862 			|| dev->gadget.speed == USB_SPEED_UNKNOWN)) {
863 		DMSG("%s, bogus device state\n", __func__);
864 		return -ESHUTDOWN;
865 	}
866 
867 	/* iso is always one packet per request, that's the only way
868 	 * we can report per-packet status.  that also helps with dma.
869 	 */
870 	if (unlikely (ep->bmAttributes == USB_ENDPOINT_XFER_ISOC
871 			&& req->req.length > usb_endpoint_maxp(ep->ep.desc)))
872 		return -EMSGSIZE;
873 
874 	DBG(DBG_NOISY, "%s queue req %p, len %d buf %p\n",
875 		_ep->name, _req, _req->length, _req->buf);
876 
877 	local_irq_save(flags);
878 
879 	_req->status = -EINPROGRESS;
880 	_req->actual = 0;
881 
882 	/* kickstart this i/o queue? */
883 	if (list_empty(&ep->queue) && !ep->stopped) {
884 		if (ep->ep.desc == NULL/* ep0 */) {
885 			unsigned	length = _req->length;
886 
887 			switch (dev->ep0state) {
888 			case EP0_IN_DATA_PHASE:
889 				dev->stats.write.ops++;
890 				if (write_ep0_fifo(ep, req))
891 					req = NULL;
892 				break;
893 
894 			case EP0_OUT_DATA_PHASE:
895 				dev->stats.read.ops++;
896 				/* messy ... */
897 				if (dev->req_config) {
898 					DBG(DBG_VERBOSE, "ep0 config ack%s\n",
899 						dev->has_cfr ?  "" : " raced");
900 					if (dev->has_cfr)
901 						udc_set_reg(dev, UDCCFR, UDCCFR_AREN |
902 							    UDCCFR_ACM | UDCCFR_MB1);
903 					done(ep, req, 0);
904 					dev->ep0state = EP0_END_XFER;
905 					local_irq_restore (flags);
906 					return 0;
907 				}
908 				if (dev->req_pending)
909 					ep0start(dev, UDCCS0_IPR, "OUT");
910 				if (length == 0 || ((udc_ep0_get_UDCCS(dev) & UDCCS0_RNE) != 0
911 						&& read_ep0_fifo(ep, req))) {
912 					ep0_idle(dev);
913 					done(ep, req, 0);
914 					req = NULL;
915 				}
916 				break;
917 
918 			default:
919 				DMSG("ep0 i/o, odd state %d\n", dev->ep0state);
920 				local_irq_restore (flags);
921 				return -EL2HLT;
922 			}
923 		/* can the FIFO can satisfy the request immediately? */
924 		} else if ((ep->bEndpointAddress & USB_DIR_IN) != 0) {
925 			if ((udc_ep_get_UDCCS(ep) & UDCCS_BI_TFS) != 0
926 					&& write_fifo(ep, req))
927 				req = NULL;
928 		} else if ((udc_ep_get_UDCCS(ep) & UDCCS_BO_RFS) != 0
929 				&& read_fifo(ep, req)) {
930 			req = NULL;
931 		}
932 
933 		if (likely(req && ep->ep.desc))
934 			pio_irq_enable(ep);
935 	}
936 
937 	/* pio or dma irq handler advances the queue. */
938 	if (likely(req != NULL))
939 		list_add_tail(&req->queue, &ep->queue);
940 	local_irq_restore(flags);
941 
942 	return 0;
943 }
944 
945 
946 /*
947  *	nuke - dequeue ALL requests
948  */
949 static void nuke(struct pxa25x_ep *ep, int status)
950 {
951 	struct pxa25x_request *req;
952 
953 	/* called with irqs blocked */
954 	while (!list_empty(&ep->queue)) {
955 		req = list_entry(ep->queue.next,
956 				struct pxa25x_request,
957 				queue);
958 		done(ep, req, status);
959 	}
960 	if (ep->ep.desc)
961 		pio_irq_disable(ep);
962 }
963 
964 
965 /* dequeue JUST ONE request */
966 static int pxa25x_ep_dequeue(struct usb_ep *_ep, struct usb_request *_req)
967 {
968 	struct pxa25x_ep	*ep;
969 	struct pxa25x_request	*req = NULL;
970 	struct pxa25x_request	*iter;
971 	unsigned long		flags;
972 
973 	ep = container_of(_ep, struct pxa25x_ep, ep);
974 	if (!_ep || ep->ep.name == ep0name)
975 		return -EINVAL;
976 
977 	local_irq_save(flags);
978 
979 	/* make sure it's actually queued on this endpoint */
980 	list_for_each_entry(iter, &ep->queue, queue) {
981 		if (&iter->req != _req)
982 			continue;
983 		req = iter;
984 		break;
985 	}
986 	if (!req) {
987 		local_irq_restore(flags);
988 		return -EINVAL;
989 	}
990 
991 	done(ep, req, -ECONNRESET);
992 
993 	local_irq_restore(flags);
994 	return 0;
995 }
996 
997 /*-------------------------------------------------------------------------*/
998 
999 static int pxa25x_ep_set_halt(struct usb_ep *_ep, int value)
1000 {
1001 	struct pxa25x_ep	*ep;
1002 	unsigned long		flags;
1003 
1004 	ep = container_of(_ep, struct pxa25x_ep, ep);
1005 	if (unlikely (!_ep
1006 			|| (!ep->ep.desc && ep->ep.name != ep0name))
1007 			|| ep->bmAttributes == USB_ENDPOINT_XFER_ISOC) {
1008 		DMSG("%s, bad ep\n", __func__);
1009 		return -EINVAL;
1010 	}
1011 	if (value == 0) {
1012 		/* this path (reset toggle+halt) is needed to implement
1013 		 * SET_INTERFACE on normal hardware.  but it can't be
1014 		 * done from software on the PXA UDC, and the hardware
1015 		 * forgets to do it as part of SET_INTERFACE automagic.
1016 		 */
1017 		DMSG("only host can clear %s halt\n", _ep->name);
1018 		return -EROFS;
1019 	}
1020 
1021 	local_irq_save(flags);
1022 
1023 	if ((ep->bEndpointAddress & USB_DIR_IN) != 0
1024 			&& ((udc_ep_get_UDCCS(ep) & UDCCS_BI_TFS) == 0
1025 			   || !list_empty(&ep->queue))) {
1026 		local_irq_restore(flags);
1027 		return -EAGAIN;
1028 	}
1029 
1030 	/* FST bit is the same for control, bulk in, bulk out, interrupt in */
1031 	udc_ep_set_UDCCS(ep, UDCCS_BI_FST|UDCCS_BI_FTF);
1032 
1033 	/* ep0 needs special care */
1034 	if (!ep->ep.desc) {
1035 		start_watchdog(ep->dev);
1036 		ep->dev->req_pending = 0;
1037 		ep->dev->ep0state = EP0_STALL;
1038 
1039 	/* and bulk/intr endpoints like dropping stalls too */
1040 	} else {
1041 		unsigned i;
1042 		for (i = 0; i < 1000; i += 20) {
1043 			if (udc_ep_get_UDCCS(ep) & UDCCS_BI_SST)
1044 				break;
1045 			udelay(20);
1046 		}
1047 	}
1048 	local_irq_restore(flags);
1049 
1050 	DBG(DBG_VERBOSE, "%s halt\n", _ep->name);
1051 	return 0;
1052 }
1053 
1054 static int pxa25x_ep_fifo_status(struct usb_ep *_ep)
1055 {
1056 	struct pxa25x_ep        *ep;
1057 
1058 	ep = container_of(_ep, struct pxa25x_ep, ep);
1059 	if (!_ep) {
1060 		DMSG("%s, bad ep\n", __func__);
1061 		return -ENODEV;
1062 	}
1063 	/* pxa can't report unclaimed bytes from IN fifos */
1064 	if ((ep->bEndpointAddress & USB_DIR_IN) != 0)
1065 		return -EOPNOTSUPP;
1066 	if (ep->dev->gadget.speed == USB_SPEED_UNKNOWN
1067 			|| (udc_ep_get_UDCCS(ep) & UDCCS_BO_RFS) == 0)
1068 		return 0;
1069 	else
1070 		return (udc_ep_get_UBCR(ep) & 0xfff) + 1;
1071 }
1072 
1073 static void pxa25x_ep_fifo_flush(struct usb_ep *_ep)
1074 {
1075 	struct pxa25x_ep        *ep;
1076 
1077 	ep = container_of(_ep, struct pxa25x_ep, ep);
1078 	if (!_ep || ep->ep.name == ep0name || !list_empty(&ep->queue)) {
1079 		DMSG("%s, bad ep\n", __func__);
1080 		return;
1081 	}
1082 
1083 	/* toggle and halt bits stay unchanged */
1084 
1085 	/* for OUT, just read and discard the FIFO contents. */
1086 	if ((ep->bEndpointAddress & USB_DIR_IN) == 0) {
1087 		while (((udc_ep_get_UDCCS(ep)) & UDCCS_BO_RNE) != 0)
1088 			(void)udc_ep_get_UDDR(ep);
1089 		return;
1090 	}
1091 
1092 	/* most IN status is the same, but ISO can't stall */
1093 	udc_ep_set_UDCCS(ep, UDCCS_BI_TPC|UDCCS_BI_FTF|UDCCS_BI_TUR
1094 		| (ep->bmAttributes == USB_ENDPOINT_XFER_ISOC
1095 			? 0 : UDCCS_BI_SST));
1096 }
1097 
1098 
1099 static const struct usb_ep_ops pxa25x_ep_ops = {
1100 	.enable		= pxa25x_ep_enable,
1101 	.disable	= pxa25x_ep_disable,
1102 
1103 	.alloc_request	= pxa25x_ep_alloc_request,
1104 	.free_request	= pxa25x_ep_free_request,
1105 
1106 	.queue		= pxa25x_ep_queue,
1107 	.dequeue	= pxa25x_ep_dequeue,
1108 
1109 	.set_halt	= pxa25x_ep_set_halt,
1110 	.fifo_status	= pxa25x_ep_fifo_status,
1111 	.fifo_flush	= pxa25x_ep_fifo_flush,
1112 };
1113 
1114 
1115 /* ---------------------------------------------------------------------------
1116  *	device-scoped parts of the api to the usb controller hardware
1117  * ---------------------------------------------------------------------------
1118  */
1119 
1120 static int pxa25x_udc_get_frame(struct usb_gadget *_gadget)
1121 {
1122 	struct pxa25x_udc	*dev;
1123 
1124 	dev = container_of(_gadget, struct pxa25x_udc, gadget);
1125 	return ((udc_get_reg(dev, UFNRH) & 0x07) << 8) |
1126 		(udc_get_reg(dev, UFNRL) & 0xff);
1127 }
1128 
1129 static int pxa25x_udc_wakeup(struct usb_gadget *_gadget)
1130 {
1131 	struct pxa25x_udc	*udc;
1132 
1133 	udc = container_of(_gadget, struct pxa25x_udc, gadget);
1134 
1135 	/* host may not have enabled remote wakeup */
1136 	if ((udc_ep0_get_UDCCS(udc) & UDCCS0_DRWF) == 0)
1137 		return -EHOSTUNREACH;
1138 	udc_set_mask_UDCCR(udc, UDCCR_RSM);
1139 	return 0;
1140 }
1141 
1142 static void stop_activity(struct pxa25x_udc *, struct usb_gadget_driver *);
1143 static void udc_enable (struct pxa25x_udc *);
1144 static void udc_disable(struct pxa25x_udc *);
1145 
1146 /* We disable the UDC -- and its 48 MHz clock -- whenever it's not
1147  * in active use.
1148  */
1149 static int pullup(struct pxa25x_udc *udc)
1150 {
1151 	int is_active = udc->vbus && udc->pullup && !udc->suspended;
1152 	DMSG("%s\n", is_active ? "active" : "inactive");
1153 	if (is_active) {
1154 		if (!udc->active) {
1155 			udc->active = 1;
1156 			/* Enable clock for USB device */
1157 			clk_enable(udc->clk);
1158 			udc_enable(udc);
1159 		}
1160 	} else {
1161 		if (udc->active) {
1162 			if (udc->gadget.speed != USB_SPEED_UNKNOWN) {
1163 				DMSG("disconnect %s\n", udc->driver
1164 					? udc->driver->driver.name
1165 					: "(no driver)");
1166 				stop_activity(udc, udc->driver);
1167 			}
1168 			udc_disable(udc);
1169 			/* Disable clock for USB device */
1170 			clk_disable(udc->clk);
1171 			udc->active = 0;
1172 		}
1173 
1174 	}
1175 	return 0;
1176 }
1177 
1178 /* VBUS reporting logically comes from a transceiver */
1179 static int pxa25x_udc_vbus_session(struct usb_gadget *_gadget, int is_active)
1180 {
1181 	struct pxa25x_udc	*udc;
1182 
1183 	udc = container_of(_gadget, struct pxa25x_udc, gadget);
1184 	udc->vbus = is_active;
1185 	DMSG("vbus %s\n", is_active ? "supplied" : "inactive");
1186 	pullup(udc);
1187 	return 0;
1188 }
1189 
1190 /* drivers may have software control over D+ pullup */
1191 static int pxa25x_udc_pullup(struct usb_gadget *_gadget, int is_active)
1192 {
1193 	struct pxa25x_udc	*udc;
1194 
1195 	udc = container_of(_gadget, struct pxa25x_udc, gadget);
1196 
1197 	/* not all boards support pullup control */
1198 	if (!gpio_is_valid(udc->mach->gpio_pullup) && !udc->mach->udc_command)
1199 		return -EOPNOTSUPP;
1200 
1201 	udc->pullup = (is_active != 0);
1202 	pullup(udc);
1203 	return 0;
1204 }
1205 
1206 /* boards may consume current from VBUS, up to 100-500mA based on config.
1207  * the 500uA suspend ceiling means that exclusively vbus-powered PXA designs
1208  * violate USB specs.
1209  */
1210 static int pxa25x_udc_vbus_draw(struct usb_gadget *_gadget, unsigned mA)
1211 {
1212 	struct pxa25x_udc	*udc;
1213 
1214 	udc = container_of(_gadget, struct pxa25x_udc, gadget);
1215 
1216 	if (!IS_ERR_OR_NULL(udc->transceiver))
1217 		return usb_phy_set_power(udc->transceiver, mA);
1218 	return -EOPNOTSUPP;
1219 }
1220 
1221 static int pxa25x_udc_start(struct usb_gadget *g,
1222 		struct usb_gadget_driver *driver);
1223 static int pxa25x_udc_stop(struct usb_gadget *g);
1224 
1225 static const struct usb_gadget_ops pxa25x_udc_ops = {
1226 	.get_frame	= pxa25x_udc_get_frame,
1227 	.wakeup		= pxa25x_udc_wakeup,
1228 	.vbus_session	= pxa25x_udc_vbus_session,
1229 	.pullup		= pxa25x_udc_pullup,
1230 	.vbus_draw	= pxa25x_udc_vbus_draw,
1231 	.udc_start	= pxa25x_udc_start,
1232 	.udc_stop	= pxa25x_udc_stop,
1233 };
1234 
1235 /*-------------------------------------------------------------------------*/
1236 
1237 #ifdef CONFIG_USB_GADGET_DEBUG_FS
1238 
1239 static int udc_debug_show(struct seq_file *m, void *_d)
1240 {
1241 	struct pxa25x_udc	*dev = m->private;
1242 	unsigned long		flags;
1243 	int			i;
1244 	u32			tmp;
1245 
1246 	local_irq_save(flags);
1247 
1248 	/* basic device status */
1249 	seq_printf(m, DRIVER_DESC "\n"
1250 		"%s version: %s\nGadget driver: %s\nHost %s\n\n",
1251 		driver_name, DRIVER_VERSION SIZE_STR "(pio)",
1252 		dev->driver ? dev->driver->driver.name : "(none)",
1253 		dev->gadget.speed == USB_SPEED_FULL ? "full speed" : "disconnected");
1254 
1255 	/* registers for device and ep0 */
1256 	seq_printf(m,
1257 		"uicr %02X.%02X, usir %02X.%02x, ufnr %02X.%02X\n",
1258 		udc_get_reg(dev, UICR1), udc_get_reg(dev, UICR0),
1259 		udc_get_reg(dev, USIR1), udc_get_reg(dev, USIR0),
1260 		udc_get_reg(dev, UFNRH), udc_get_reg(dev, UFNRL));
1261 
1262 	tmp = udc_get_reg(dev, UDCCR);
1263 	seq_printf(m,
1264 		"udccr %02X =%s%s%s%s%s%s%s%s\n", tmp,
1265 		(tmp & UDCCR_REM) ? " rem" : "",
1266 		(tmp & UDCCR_RSTIR) ? " rstir" : "",
1267 		(tmp & UDCCR_SRM) ? " srm" : "",
1268 		(tmp & UDCCR_SUSIR) ? " susir" : "",
1269 		(tmp & UDCCR_RESIR) ? " resir" : "",
1270 		(tmp & UDCCR_RSM) ? " rsm" : "",
1271 		(tmp & UDCCR_UDA) ? " uda" : "",
1272 		(tmp & UDCCR_UDE) ? " ude" : "");
1273 
1274 	tmp = udc_ep0_get_UDCCS(dev);
1275 	seq_printf(m,
1276 		"udccs0 %02X =%s%s%s%s%s%s%s%s\n", tmp,
1277 		(tmp & UDCCS0_SA) ? " sa" : "",
1278 		(tmp & UDCCS0_RNE) ? " rne" : "",
1279 		(tmp & UDCCS0_FST) ? " fst" : "",
1280 		(tmp & UDCCS0_SST) ? " sst" : "",
1281 		(tmp & UDCCS0_DRWF) ? " dwrf" : "",
1282 		(tmp & UDCCS0_FTF) ? " ftf" : "",
1283 		(tmp & UDCCS0_IPR) ? " ipr" : "",
1284 		(tmp & UDCCS0_OPR) ? " opr" : "");
1285 
1286 	if (dev->has_cfr) {
1287 		tmp = udc_get_reg(dev, UDCCFR);
1288 		seq_printf(m,
1289 			"udccfr %02X =%s%s\n", tmp,
1290 			(tmp & UDCCFR_AREN) ? " aren" : "",
1291 			(tmp & UDCCFR_ACM) ? " acm" : "");
1292 	}
1293 
1294 	if (dev->gadget.speed != USB_SPEED_FULL || !dev->driver)
1295 		goto done;
1296 
1297 	seq_printf(m, "ep0 IN %lu/%lu, OUT %lu/%lu\nirqs %lu\n\n",
1298 		dev->stats.write.bytes, dev->stats.write.ops,
1299 		dev->stats.read.bytes, dev->stats.read.ops,
1300 		dev->stats.irqs);
1301 
1302 	/* dump endpoint queues */
1303 	for (i = 0; i < PXA_UDC_NUM_ENDPOINTS; i++) {
1304 		struct pxa25x_ep	*ep = &dev->ep [i];
1305 		struct pxa25x_request	*req;
1306 
1307 		if (i != 0) {
1308 			const struct usb_endpoint_descriptor	*desc;
1309 
1310 			desc = ep->ep.desc;
1311 			if (!desc)
1312 				continue;
1313 			tmp = udc_ep_get_UDCCS(&dev->ep[i]);
1314 			seq_printf(m,
1315 				"%s max %d %s udccs %02x irqs %lu\n",
1316 				ep->ep.name, usb_endpoint_maxp(desc),
1317 				"pio", tmp, ep->pio_irqs);
1318 			/* TODO translate all five groups of udccs bits! */
1319 
1320 		} else /* ep0 should only have one transfer queued */
1321 			seq_printf(m, "ep0 max 16 pio irqs %lu\n",
1322 				ep->pio_irqs);
1323 
1324 		if (list_empty(&ep->queue)) {
1325 			seq_printf(m, "\t(nothing queued)\n");
1326 			continue;
1327 		}
1328 		list_for_each_entry(req, &ep->queue, queue) {
1329 			seq_printf(m,
1330 					"\treq %p len %d/%d buf %p\n",
1331 					&req->req, req->req.actual,
1332 					req->req.length, req->req.buf);
1333 		}
1334 	}
1335 
1336 done:
1337 	local_irq_restore(flags);
1338 	return 0;
1339 }
1340 DEFINE_SHOW_ATTRIBUTE(udc_debug);
1341 
1342 #define create_debug_files(dev) \
1343 	do { \
1344 		debugfs_create_file(dev->gadget.name, \
1345 			S_IRUGO, NULL, dev, &udc_debug_fops); \
1346 	} while (0)
1347 #define remove_debug_files(dev) debugfs_remove(debugfs_lookup(dev->gadget.name, NULL))
1348 
1349 #else	/* !CONFIG_USB_GADGET_DEBUG_FILES */
1350 
1351 #define create_debug_files(dev) do {} while (0)
1352 #define remove_debug_files(dev) do {} while (0)
1353 
1354 #endif	/* CONFIG_USB_GADGET_DEBUG_FILES */
1355 
1356 /*-------------------------------------------------------------------------*/
1357 
1358 /*
1359  *	udc_disable - disable USB device controller
1360  */
1361 static void udc_disable(struct pxa25x_udc *dev)
1362 {
1363 	/* block all irqs */
1364 	udc_set_mask_UDCCR(dev, UDCCR_SRM|UDCCR_REM);
1365 	udc_set_reg(dev, UICR0, 0xff);
1366 	udc_set_reg(dev, UICR1, 0xff);
1367 	udc_set_reg(dev, UFNRH, UFNRH_SIM);
1368 
1369 	/* if hardware supports it, disconnect from usb */
1370 	pullup_off();
1371 
1372 	udc_clear_mask_UDCCR(dev, UDCCR_UDE);
1373 
1374 	ep0_idle (dev);
1375 	dev->gadget.speed = USB_SPEED_UNKNOWN;
1376 }
1377 
1378 
1379 /*
1380  *	udc_reinit - initialize software state
1381  */
1382 static void udc_reinit(struct pxa25x_udc *dev)
1383 {
1384 	u32	i;
1385 
1386 	/* device/ep0 records init */
1387 	INIT_LIST_HEAD (&dev->gadget.ep_list);
1388 	INIT_LIST_HEAD (&dev->gadget.ep0->ep_list);
1389 	dev->ep0state = EP0_IDLE;
1390 	dev->gadget.quirk_altset_not_supp = 1;
1391 
1392 	/* basic endpoint records init */
1393 	for (i = 0; i < PXA_UDC_NUM_ENDPOINTS; i++) {
1394 		struct pxa25x_ep *ep = &dev->ep[i];
1395 
1396 		if (i != 0)
1397 			list_add_tail (&ep->ep.ep_list, &dev->gadget.ep_list);
1398 
1399 		ep->ep.desc = NULL;
1400 		ep->stopped = 0;
1401 		INIT_LIST_HEAD (&ep->queue);
1402 		ep->pio_irqs = 0;
1403 		usb_ep_set_maxpacket_limit(&ep->ep, ep->ep.maxpacket);
1404 	}
1405 
1406 	/* the rest was statically initialized, and is read-only */
1407 }
1408 
1409 /* until it's enabled, this UDC should be completely invisible
1410  * to any USB host.
1411  */
1412 static void udc_enable (struct pxa25x_udc *dev)
1413 {
1414 	udc_clear_mask_UDCCR(dev, UDCCR_UDE);
1415 
1416 	/* try to clear these bits before we enable the udc */
1417 	udc_ack_int_UDCCR(dev, UDCCR_SUSIR|/*UDCCR_RSTIR|*/UDCCR_RESIR);
1418 
1419 	ep0_idle(dev);
1420 	dev->gadget.speed = USB_SPEED_UNKNOWN;
1421 	dev->stats.irqs = 0;
1422 
1423 	/*
1424 	 * sequence taken from chapter 12.5.10, PXA250 AppProcDevManual:
1425 	 * - enable UDC
1426 	 * - if RESET is already in progress, ack interrupt
1427 	 * - unmask reset interrupt
1428 	 */
1429 	udc_set_mask_UDCCR(dev, UDCCR_UDE);
1430 	if (!(udc_get_reg(dev, UDCCR) & UDCCR_UDA))
1431 		udc_ack_int_UDCCR(dev, UDCCR_RSTIR);
1432 
1433 	if (dev->has_cfr /* UDC_RES2 is defined */) {
1434 		/* pxa255 (a0+) can avoid a set_config race that could
1435 		 * prevent gadget drivers from configuring correctly
1436 		 */
1437 		udc_set_reg(dev, UDCCFR, UDCCFR_ACM | UDCCFR_MB1);
1438 	} else {
1439 		/* "USB test mode" for pxa250 errata 40-42 (stepping a0, a1)
1440 		 * which could result in missing packets and interrupts.
1441 		 * supposedly one bit per endpoint, controlling whether it
1442 		 * double buffers or not; ACM/AREN bits fit into the holes.
1443 		 * zero bits (like USIR0_IRx) disable double buffering.
1444 		 */
1445 		udc_set_reg(dev, UDC_RES1, 0x00);
1446 		udc_set_reg(dev, UDC_RES2, 0x00);
1447 	}
1448 
1449 	/* enable suspend/resume and reset irqs */
1450 	udc_clear_mask_UDCCR(dev, UDCCR_SRM | UDCCR_REM);
1451 
1452 	/* enable ep0 irqs */
1453 	udc_set_reg(dev, UICR0, udc_get_reg(dev, UICR0) & ~UICR0_IM0);
1454 
1455 	/* if hardware supports it, pullup D+ and wait for reset */
1456 	pullup_on();
1457 }
1458 
1459 
1460 /* when a driver is successfully registered, it will receive
1461  * control requests including set_configuration(), which enables
1462  * non-control requests.  then usb traffic follows until a
1463  * disconnect is reported.  then a host may connect again, or
1464  * the driver might get unbound.
1465  */
1466 static int pxa25x_udc_start(struct usb_gadget *g,
1467 		struct usb_gadget_driver *driver)
1468 {
1469 	struct pxa25x_udc	*dev = to_pxa25x(g);
1470 	int			retval;
1471 
1472 	/* first hook up the driver ... */
1473 	dev->driver = driver;
1474 	dev->pullup = 1;
1475 
1476 	/* ... then enable host detection and ep0; and we're ready
1477 	 * for set_configuration as well as eventual disconnect.
1478 	 */
1479 	/* connect to bus through transceiver */
1480 	if (!IS_ERR_OR_NULL(dev->transceiver)) {
1481 		retval = otg_set_peripheral(dev->transceiver->otg,
1482 						&dev->gadget);
1483 		if (retval)
1484 			goto bind_fail;
1485 	}
1486 
1487 	dump_state(dev);
1488 	return 0;
1489 bind_fail:
1490 	return retval;
1491 }
1492 
1493 static void
1494 reset_gadget(struct pxa25x_udc *dev, struct usb_gadget_driver *driver)
1495 {
1496 	int i;
1497 
1498 	/* don't disconnect drivers more than once */
1499 	if (dev->gadget.speed == USB_SPEED_UNKNOWN)
1500 		driver = NULL;
1501 	dev->gadget.speed = USB_SPEED_UNKNOWN;
1502 
1503 	/* prevent new request submissions, kill any outstanding requests  */
1504 	for (i = 0; i < PXA_UDC_NUM_ENDPOINTS; i++) {
1505 		struct pxa25x_ep *ep = &dev->ep[i];
1506 
1507 		ep->stopped = 1;
1508 		nuke(ep, -ESHUTDOWN);
1509 	}
1510 	del_timer_sync(&dev->timer);
1511 
1512 	/* report reset; the driver is already quiesced */
1513 	if (driver)
1514 		usb_gadget_udc_reset(&dev->gadget, driver);
1515 
1516 	/* re-init driver-visible data structures */
1517 	udc_reinit(dev);
1518 }
1519 
1520 static void
1521 stop_activity(struct pxa25x_udc *dev, struct usb_gadget_driver *driver)
1522 {
1523 	int i;
1524 
1525 	/* don't disconnect drivers more than once */
1526 	if (dev->gadget.speed == USB_SPEED_UNKNOWN)
1527 		driver = NULL;
1528 	dev->gadget.speed = USB_SPEED_UNKNOWN;
1529 
1530 	/* prevent new request submissions, kill any outstanding requests  */
1531 	for (i = 0; i < PXA_UDC_NUM_ENDPOINTS; i++) {
1532 		struct pxa25x_ep *ep = &dev->ep[i];
1533 
1534 		ep->stopped = 1;
1535 		nuke(ep, -ESHUTDOWN);
1536 	}
1537 	del_timer_sync(&dev->timer);
1538 
1539 	/* report disconnect; the driver is already quiesced */
1540 	if (driver)
1541 		driver->disconnect(&dev->gadget);
1542 
1543 	/* re-init driver-visible data structures */
1544 	udc_reinit(dev);
1545 }
1546 
1547 static int pxa25x_udc_stop(struct usb_gadget*g)
1548 {
1549 	struct pxa25x_udc	*dev = to_pxa25x(g);
1550 
1551 	local_irq_disable();
1552 	dev->pullup = 0;
1553 	stop_activity(dev, NULL);
1554 	local_irq_enable();
1555 
1556 	if (!IS_ERR_OR_NULL(dev->transceiver))
1557 		(void) otg_set_peripheral(dev->transceiver->otg, NULL);
1558 
1559 	dev->driver = NULL;
1560 
1561 	dump_state(dev);
1562 
1563 	return 0;
1564 }
1565 
1566 /*-------------------------------------------------------------------------*/
1567 
1568 #ifdef CONFIG_ARCH_LUBBOCK
1569 
1570 /* Lubbock has separate connect and disconnect irqs.  More typical designs
1571  * use one GPIO as the VBUS IRQ, and another to control the D+ pullup.
1572  */
1573 
1574 static irqreturn_t
1575 lubbock_vbus_irq(int irq, void *_dev)
1576 {
1577 	struct pxa25x_udc	*dev = _dev;
1578 	int			vbus;
1579 
1580 	dev->stats.irqs++;
1581 	switch (irq) {
1582 	case LUBBOCK_USB_IRQ:
1583 		vbus = 1;
1584 		disable_irq(LUBBOCK_USB_IRQ);
1585 		enable_irq(LUBBOCK_USB_DISC_IRQ);
1586 		break;
1587 	case LUBBOCK_USB_DISC_IRQ:
1588 		vbus = 0;
1589 		disable_irq(LUBBOCK_USB_DISC_IRQ);
1590 		enable_irq(LUBBOCK_USB_IRQ);
1591 		break;
1592 	default:
1593 		return IRQ_NONE;
1594 	}
1595 
1596 	pxa25x_udc_vbus_session(&dev->gadget, vbus);
1597 	return IRQ_HANDLED;
1598 }
1599 
1600 #endif
1601 
1602 
1603 /*-------------------------------------------------------------------------*/
1604 
1605 static inline void clear_ep_state (struct pxa25x_udc *dev)
1606 {
1607 	unsigned i;
1608 
1609 	/* hardware SET_{CONFIGURATION,INTERFACE} automagic resets endpoint
1610 	 * fifos, and pending transactions mustn't be continued in any case.
1611 	 */
1612 	for (i = 1; i < PXA_UDC_NUM_ENDPOINTS; i++)
1613 		nuke(&dev->ep[i], -ECONNABORTED);
1614 }
1615 
1616 static void udc_watchdog(struct timer_list *t)
1617 {
1618 	struct pxa25x_udc	*dev = from_timer(dev, t, timer);
1619 
1620 	local_irq_disable();
1621 	if (dev->ep0state == EP0_STALL
1622 			&& (udc_ep0_get_UDCCS(dev) & UDCCS0_FST) == 0
1623 			&& (udc_ep0_get_UDCCS(dev) & UDCCS0_SST) == 0) {
1624 		udc_ep0_set_UDCCS(dev, UDCCS0_FST|UDCCS0_FTF);
1625 		DBG(DBG_VERBOSE, "ep0 re-stall\n");
1626 		start_watchdog(dev);
1627 	}
1628 	local_irq_enable();
1629 }
1630 
1631 static void handle_ep0 (struct pxa25x_udc *dev)
1632 {
1633 	u32			udccs0 = udc_ep0_get_UDCCS(dev);
1634 	struct pxa25x_ep	*ep = &dev->ep [0];
1635 	struct pxa25x_request	*req;
1636 	union {
1637 		struct usb_ctrlrequest	r;
1638 		u8			raw [8];
1639 		u32			word [2];
1640 	} u;
1641 
1642 	if (list_empty(&ep->queue))
1643 		req = NULL;
1644 	else
1645 		req = list_entry(ep->queue.next, struct pxa25x_request, queue);
1646 
1647 	/* clear stall status */
1648 	if (udccs0 & UDCCS0_SST) {
1649 		nuke(ep, -EPIPE);
1650 		udc_ep0_set_UDCCS(dev, UDCCS0_SST);
1651 		del_timer(&dev->timer);
1652 		ep0_idle(dev);
1653 	}
1654 
1655 	/* previous request unfinished?  non-error iff back-to-back ... */
1656 	if ((udccs0 & UDCCS0_SA) != 0 && dev->ep0state != EP0_IDLE) {
1657 		nuke(ep, 0);
1658 		del_timer(&dev->timer);
1659 		ep0_idle(dev);
1660 	}
1661 
1662 	switch (dev->ep0state) {
1663 	case EP0_IDLE:
1664 		/* late-breaking status? */
1665 		udccs0 = udc_ep0_get_UDCCS(dev);
1666 
1667 		/* start control request? */
1668 		if (likely((udccs0 & (UDCCS0_OPR|UDCCS0_SA|UDCCS0_RNE))
1669 				== (UDCCS0_OPR|UDCCS0_SA|UDCCS0_RNE))) {
1670 			int i;
1671 
1672 			nuke (ep, -EPROTO);
1673 
1674 			/* read SETUP packet */
1675 			for (i = 0; i < 8; i++) {
1676 				if (unlikely(!(udc_ep0_get_UDCCS(dev) & UDCCS0_RNE))) {
1677 bad_setup:
1678 					DMSG("SETUP %d!\n", i);
1679 					goto stall;
1680 				}
1681 				u.raw [i] = (u8) UDDR0;
1682 			}
1683 			if (unlikely((udc_ep0_get_UDCCS(dev) & UDCCS0_RNE) != 0))
1684 				goto bad_setup;
1685 
1686 got_setup:
1687 			DBG(DBG_VERBOSE, "SETUP %02x.%02x v%04x i%04x l%04x\n",
1688 				u.r.bRequestType, u.r.bRequest,
1689 				le16_to_cpu(u.r.wValue),
1690 				le16_to_cpu(u.r.wIndex),
1691 				le16_to_cpu(u.r.wLength));
1692 
1693 			/* cope with automagic for some standard requests. */
1694 			dev->req_std = (u.r.bRequestType & USB_TYPE_MASK)
1695 						== USB_TYPE_STANDARD;
1696 			dev->req_config = 0;
1697 			dev->req_pending = 1;
1698 			switch (u.r.bRequest) {
1699 			/* hardware restricts gadget drivers here! */
1700 			case USB_REQ_SET_CONFIGURATION:
1701 				if (u.r.bRequestType == USB_RECIP_DEVICE) {
1702 					/* reflect hardware's automagic
1703 					 * up to the gadget driver.
1704 					 */
1705 config_change:
1706 					dev->req_config = 1;
1707 					clear_ep_state(dev);
1708 					/* if !has_cfr, there's no synch
1709 					 * else use AREN (later) not SA|OPR
1710 					 * USIR0_IR0 acts edge sensitive
1711 					 */
1712 				}
1713 				break;
1714 			/* ... and here, even more ... */
1715 			case USB_REQ_SET_INTERFACE:
1716 				if (u.r.bRequestType == USB_RECIP_INTERFACE) {
1717 					/* udc hardware is broken by design:
1718 					 *  - altsetting may only be zero;
1719 					 *  - hw resets all interfaces' eps;
1720 					 *  - ep reset doesn't include halt(?).
1721 					 */
1722 					DMSG("broken set_interface (%d/%d)\n",
1723 						le16_to_cpu(u.r.wIndex),
1724 						le16_to_cpu(u.r.wValue));
1725 					goto config_change;
1726 				}
1727 				break;
1728 			/* hardware was supposed to hide this */
1729 			case USB_REQ_SET_ADDRESS:
1730 				if (u.r.bRequestType == USB_RECIP_DEVICE) {
1731 					ep0start(dev, 0, "address");
1732 					return;
1733 				}
1734 				break;
1735 			}
1736 
1737 			if (u.r.bRequestType & USB_DIR_IN)
1738 				dev->ep0state = EP0_IN_DATA_PHASE;
1739 			else
1740 				dev->ep0state = EP0_OUT_DATA_PHASE;
1741 
1742 			i = dev->driver->setup(&dev->gadget, &u.r);
1743 			if (i < 0) {
1744 				/* hardware automagic preventing STALL... */
1745 				if (dev->req_config) {
1746 					/* hardware sometimes neglects to tell
1747 					 * tell us about config change events,
1748 					 * so later ones may fail...
1749 					 */
1750 					WARNING("config change %02x fail %d?\n",
1751 						u.r.bRequest, i);
1752 					return;
1753 					/* TODO experiment:  if has_cfr,
1754 					 * hardware didn't ACK; maybe we
1755 					 * could actually STALL!
1756 					 */
1757 				}
1758 				DBG(DBG_VERBOSE, "protocol STALL, "
1759 					"%02x err %d\n", udc_ep0_get_UDCCS(dev), i);
1760 stall:
1761 				/* the watchdog timer helps deal with cases
1762 				 * where udc seems to clear FST wrongly, and
1763 				 * then NAKs instead of STALLing.
1764 				 */
1765 				ep0start(dev, UDCCS0_FST|UDCCS0_FTF, "stall");
1766 				start_watchdog(dev);
1767 				dev->ep0state = EP0_STALL;
1768 
1769 			/* deferred i/o == no response yet */
1770 			} else if (dev->req_pending) {
1771 				if (likely(dev->ep0state == EP0_IN_DATA_PHASE
1772 						|| dev->req_std || u.r.wLength))
1773 					ep0start(dev, 0, "defer");
1774 				else
1775 					ep0start(dev, UDCCS0_IPR, "defer/IPR");
1776 			}
1777 
1778 			/* expect at least one data or status stage irq */
1779 			return;
1780 
1781 		} else if (likely((udccs0 & (UDCCS0_OPR|UDCCS0_SA))
1782 				== (UDCCS0_OPR|UDCCS0_SA))) {
1783 			unsigned i;
1784 
1785 			/* pxa210/250 erratum 131 for B0/B1 says RNE lies.
1786 			 * still observed on a pxa255 a0.
1787 			 */
1788 			DBG(DBG_VERBOSE, "e131\n");
1789 			nuke(ep, -EPROTO);
1790 
1791 			/* read SETUP data, but don't trust it too much */
1792 			for (i = 0; i < 8; i++)
1793 				u.raw [i] = (u8) UDDR0;
1794 			if ((u.r.bRequestType & USB_RECIP_MASK)
1795 					> USB_RECIP_OTHER)
1796 				goto stall;
1797 			if (u.word [0] == 0 && u.word [1] == 0)
1798 				goto stall;
1799 			goto got_setup;
1800 		} else {
1801 			/* some random early IRQ:
1802 			 * - we acked FST
1803 			 * - IPR cleared
1804 			 * - OPR got set, without SA (likely status stage)
1805 			 */
1806 			udc_ep0_set_UDCCS(dev, udccs0 & (UDCCS0_SA|UDCCS0_OPR));
1807 		}
1808 		break;
1809 	case EP0_IN_DATA_PHASE:			/* GET_DESCRIPTOR etc */
1810 		if (udccs0 & UDCCS0_OPR) {
1811 			udc_ep0_set_UDCCS(dev, UDCCS0_OPR|UDCCS0_FTF);
1812 			DBG(DBG_VERBOSE, "ep0in premature status\n");
1813 			if (req)
1814 				done(ep, req, 0);
1815 			ep0_idle(dev);
1816 		} else /* irq was IPR clearing */ {
1817 			if (req) {
1818 				/* this IN packet might finish the request */
1819 				(void) write_ep0_fifo(ep, req);
1820 			} /* else IN token before response was written */
1821 		}
1822 		break;
1823 	case EP0_OUT_DATA_PHASE:		/* SET_DESCRIPTOR etc */
1824 		if (udccs0 & UDCCS0_OPR) {
1825 			if (req) {
1826 				/* this OUT packet might finish the request */
1827 				if (read_ep0_fifo(ep, req))
1828 					done(ep, req, 0);
1829 				/* else more OUT packets expected */
1830 			} /* else OUT token before read was issued */
1831 		} else /* irq was IPR clearing */ {
1832 			DBG(DBG_VERBOSE, "ep0out premature status\n");
1833 			if (req)
1834 				done(ep, req, 0);
1835 			ep0_idle(dev);
1836 		}
1837 		break;
1838 	case EP0_END_XFER:
1839 		if (req)
1840 			done(ep, req, 0);
1841 		/* ack control-IN status (maybe in-zlp was skipped)
1842 		 * also appears after some config change events.
1843 		 */
1844 		if (udccs0 & UDCCS0_OPR)
1845 			udc_ep0_set_UDCCS(dev, UDCCS0_OPR);
1846 		ep0_idle(dev);
1847 		break;
1848 	case EP0_STALL:
1849 		udc_ep0_set_UDCCS(dev, UDCCS0_FST);
1850 		break;
1851 	}
1852 	udc_set_reg(dev, USIR0, USIR0_IR0);
1853 }
1854 
1855 static void handle_ep(struct pxa25x_ep *ep)
1856 {
1857 	struct pxa25x_request	*req;
1858 	int			is_in = ep->bEndpointAddress & USB_DIR_IN;
1859 	int			completed;
1860 	u32			udccs, tmp;
1861 
1862 	do {
1863 		completed = 0;
1864 		if (likely (!list_empty(&ep->queue)))
1865 			req = list_entry(ep->queue.next,
1866 					struct pxa25x_request, queue);
1867 		else
1868 			req = NULL;
1869 
1870 		// TODO check FST handling
1871 
1872 		udccs = udc_ep_get_UDCCS(ep);
1873 		if (unlikely(is_in)) {	/* irq from TPC, SST, or (ISO) TUR */
1874 			tmp = UDCCS_BI_TUR;
1875 			if (likely(ep->bmAttributes == USB_ENDPOINT_XFER_BULK))
1876 				tmp |= UDCCS_BI_SST;
1877 			tmp &= udccs;
1878 			if (likely (tmp))
1879 				udc_ep_set_UDCCS(ep, tmp);
1880 			if (req && likely ((udccs & UDCCS_BI_TFS) != 0))
1881 				completed = write_fifo(ep, req);
1882 
1883 		} else {	/* irq from RPC (or for ISO, ROF) */
1884 			if (likely(ep->bmAttributes == USB_ENDPOINT_XFER_BULK))
1885 				tmp = UDCCS_BO_SST | UDCCS_BO_DME;
1886 			else
1887 				tmp = UDCCS_IO_ROF | UDCCS_IO_DME;
1888 			tmp &= udccs;
1889 			if (likely(tmp))
1890 				udc_ep_set_UDCCS(ep, tmp);
1891 
1892 			/* fifos can hold packets, ready for reading... */
1893 			if (likely(req)) {
1894 				completed = read_fifo(ep, req);
1895 			} else
1896 				pio_irq_disable(ep);
1897 		}
1898 		ep->pio_irqs++;
1899 	} while (completed);
1900 }
1901 
1902 /*
1903  *	pxa25x_udc_irq - interrupt handler
1904  *
1905  * avoid delays in ep0 processing. the control handshaking isn't always
1906  * under software control (pxa250c0 and the pxa255 are better), and delays
1907  * could cause usb protocol errors.
1908  */
1909 static irqreturn_t
1910 pxa25x_udc_irq(int irq, void *_dev)
1911 {
1912 	struct pxa25x_udc	*dev = _dev;
1913 	int			handled;
1914 
1915 	dev->stats.irqs++;
1916 	do {
1917 		u32		udccr = udc_get_reg(dev, UDCCR);
1918 
1919 		handled = 0;
1920 
1921 		/* SUSpend Interrupt Request */
1922 		if (unlikely(udccr & UDCCR_SUSIR)) {
1923 			udc_ack_int_UDCCR(dev, UDCCR_SUSIR);
1924 			handled = 1;
1925 			DBG(DBG_VERBOSE, "USB suspend\n");
1926 
1927 			if (dev->gadget.speed != USB_SPEED_UNKNOWN
1928 					&& dev->driver
1929 					&& dev->driver->suspend)
1930 				dev->driver->suspend(&dev->gadget);
1931 			ep0_idle (dev);
1932 		}
1933 
1934 		/* RESume Interrupt Request */
1935 		if (unlikely(udccr & UDCCR_RESIR)) {
1936 			udc_ack_int_UDCCR(dev, UDCCR_RESIR);
1937 			handled = 1;
1938 			DBG(DBG_VERBOSE, "USB resume\n");
1939 
1940 			if (dev->gadget.speed != USB_SPEED_UNKNOWN
1941 					&& dev->driver
1942 					&& dev->driver->resume)
1943 				dev->driver->resume(&dev->gadget);
1944 		}
1945 
1946 		/* ReSeT Interrupt Request - USB reset */
1947 		if (unlikely(udccr & UDCCR_RSTIR)) {
1948 			udc_ack_int_UDCCR(dev, UDCCR_RSTIR);
1949 			handled = 1;
1950 
1951 			if ((udc_get_reg(dev, UDCCR) & UDCCR_UDA) == 0) {
1952 				DBG(DBG_VERBOSE, "USB reset start\n");
1953 
1954 				/* reset driver and endpoints,
1955 				 * in case that's not yet done
1956 				 */
1957 				reset_gadget(dev, dev->driver);
1958 
1959 			} else {
1960 				DBG(DBG_VERBOSE, "USB reset end\n");
1961 				dev->gadget.speed = USB_SPEED_FULL;
1962 				memset(&dev->stats, 0, sizeof dev->stats);
1963 				/* driver and endpoints are still reset */
1964 			}
1965 
1966 		} else {
1967 			u32	usir0 = udc_get_reg(dev, USIR0) &
1968 					~udc_get_reg(dev, UICR0);
1969 			u32	usir1 = udc_get_reg(dev, USIR1) &
1970 					~udc_get_reg(dev, UICR1);
1971 			int	i;
1972 
1973 			if (unlikely (!usir0 && !usir1))
1974 				continue;
1975 
1976 			DBG(DBG_VERY_NOISY, "irq %02x.%02x\n", usir1, usir0);
1977 
1978 			/* control traffic */
1979 			if (usir0 & USIR0_IR0) {
1980 				dev->ep[0].pio_irqs++;
1981 				handle_ep0(dev);
1982 				handled = 1;
1983 			}
1984 
1985 			/* endpoint data transfers */
1986 			for (i = 0; i < 8; i++) {
1987 				u32	tmp = 1 << i;
1988 
1989 				if (i && (usir0 & tmp)) {
1990 					handle_ep(&dev->ep[i]);
1991 					udc_set_reg(dev, USIR0,
1992 						udc_get_reg(dev, USIR0) | tmp);
1993 					handled = 1;
1994 				}
1995 #ifndef	CONFIG_USB_PXA25X_SMALL
1996 				if (usir1 & tmp) {
1997 					handle_ep(&dev->ep[i+8]);
1998 					udc_set_reg(dev, USIR1,
1999 						udc_get_reg(dev, USIR1) | tmp);
2000 					handled = 1;
2001 				}
2002 #endif
2003 			}
2004 		}
2005 
2006 		/* we could also ask for 1 msec SOF (SIR) interrupts */
2007 
2008 	} while (handled);
2009 	return IRQ_HANDLED;
2010 }
2011 
2012 /*-------------------------------------------------------------------------*/
2013 
2014 static void nop_release (struct device *dev)
2015 {
2016 	DMSG("%s %s\n", __func__, dev_name(dev));
2017 }
2018 
2019 /* this uses load-time allocation and initialization (instead of
2020  * doing it at run-time) to save code, eliminate fault paths, and
2021  * be more obviously correct.
2022  */
2023 static struct pxa25x_udc memory = {
2024 	.gadget = {
2025 		.ops		= &pxa25x_udc_ops,
2026 		.ep0		= &memory.ep[0].ep,
2027 		.name		= driver_name,
2028 		.dev = {
2029 			.init_name	= "gadget",
2030 			.release	= nop_release,
2031 		},
2032 	},
2033 
2034 	/* control endpoint */
2035 	.ep[0] = {
2036 		.ep = {
2037 			.name		= ep0name,
2038 			.ops		= &pxa25x_ep_ops,
2039 			.maxpacket	= EP0_FIFO_SIZE,
2040 			.caps		= USB_EP_CAPS(USB_EP_CAPS_TYPE_CONTROL,
2041 						USB_EP_CAPS_DIR_ALL),
2042 		},
2043 		.dev		= &memory,
2044 		.regoff_udccs	= UDCCS0,
2045 		.regoff_uddr	= UDDR0,
2046 	},
2047 
2048 	/* first group of endpoints */
2049 	.ep[1] = {
2050 		.ep = {
2051 			.name		= "ep1in-bulk",
2052 			.ops		= &pxa25x_ep_ops,
2053 			.maxpacket	= BULK_FIFO_SIZE,
2054 			.caps		= USB_EP_CAPS(USB_EP_CAPS_TYPE_BULK,
2055 						USB_EP_CAPS_DIR_IN),
2056 		},
2057 		.dev		= &memory,
2058 		.fifo_size	= BULK_FIFO_SIZE,
2059 		.bEndpointAddress = USB_DIR_IN | 1,
2060 		.bmAttributes	= USB_ENDPOINT_XFER_BULK,
2061 		.regoff_udccs	= UDCCS1,
2062 		.regoff_uddr	= UDDR1,
2063 	},
2064 	.ep[2] = {
2065 		.ep = {
2066 			.name		= "ep2out-bulk",
2067 			.ops		= &pxa25x_ep_ops,
2068 			.maxpacket	= BULK_FIFO_SIZE,
2069 			.caps		= USB_EP_CAPS(USB_EP_CAPS_TYPE_BULK,
2070 						USB_EP_CAPS_DIR_OUT),
2071 		},
2072 		.dev		= &memory,
2073 		.fifo_size	= BULK_FIFO_SIZE,
2074 		.bEndpointAddress = 2,
2075 		.bmAttributes	= USB_ENDPOINT_XFER_BULK,
2076 		.regoff_udccs	= UDCCS2,
2077 		.regoff_ubcr	= UBCR2,
2078 		.regoff_uddr	= UDDR2,
2079 	},
2080 #ifndef CONFIG_USB_PXA25X_SMALL
2081 	.ep[3] = {
2082 		.ep = {
2083 			.name		= "ep3in-iso",
2084 			.ops		= &pxa25x_ep_ops,
2085 			.maxpacket	= ISO_FIFO_SIZE,
2086 			.caps		= USB_EP_CAPS(USB_EP_CAPS_TYPE_ISO,
2087 						USB_EP_CAPS_DIR_IN),
2088 		},
2089 		.dev		= &memory,
2090 		.fifo_size	= ISO_FIFO_SIZE,
2091 		.bEndpointAddress = USB_DIR_IN | 3,
2092 		.bmAttributes	= USB_ENDPOINT_XFER_ISOC,
2093 		.regoff_udccs	= UDCCS3,
2094 		.regoff_uddr	= UDDR3,
2095 	},
2096 	.ep[4] = {
2097 		.ep = {
2098 			.name		= "ep4out-iso",
2099 			.ops		= &pxa25x_ep_ops,
2100 			.maxpacket	= ISO_FIFO_SIZE,
2101 			.caps		= USB_EP_CAPS(USB_EP_CAPS_TYPE_ISO,
2102 						USB_EP_CAPS_DIR_OUT),
2103 		},
2104 		.dev		= &memory,
2105 		.fifo_size	= ISO_FIFO_SIZE,
2106 		.bEndpointAddress = 4,
2107 		.bmAttributes	= USB_ENDPOINT_XFER_ISOC,
2108 		.regoff_udccs	= UDCCS4,
2109 		.regoff_ubcr	= UBCR4,
2110 		.regoff_uddr	= UDDR4,
2111 	},
2112 	.ep[5] = {
2113 		.ep = {
2114 			.name		= "ep5in-int",
2115 			.ops		= &pxa25x_ep_ops,
2116 			.maxpacket	= INT_FIFO_SIZE,
2117 			.caps		= USB_EP_CAPS(0, 0),
2118 		},
2119 		.dev		= &memory,
2120 		.fifo_size	= INT_FIFO_SIZE,
2121 		.bEndpointAddress = USB_DIR_IN | 5,
2122 		.bmAttributes	= USB_ENDPOINT_XFER_INT,
2123 		.regoff_udccs	= UDCCS5,
2124 		.regoff_uddr	= UDDR5,
2125 	},
2126 
2127 	/* second group of endpoints */
2128 	.ep[6] = {
2129 		.ep = {
2130 			.name		= "ep6in-bulk",
2131 			.ops		= &pxa25x_ep_ops,
2132 			.maxpacket	= BULK_FIFO_SIZE,
2133 			.caps		= USB_EP_CAPS(USB_EP_CAPS_TYPE_BULK,
2134 						USB_EP_CAPS_DIR_IN),
2135 		},
2136 		.dev		= &memory,
2137 		.fifo_size	= BULK_FIFO_SIZE,
2138 		.bEndpointAddress = USB_DIR_IN | 6,
2139 		.bmAttributes	= USB_ENDPOINT_XFER_BULK,
2140 		.regoff_udccs	= UDCCS6,
2141 		.regoff_uddr	= UDDR6,
2142 	},
2143 	.ep[7] = {
2144 		.ep = {
2145 			.name		= "ep7out-bulk",
2146 			.ops		= &pxa25x_ep_ops,
2147 			.maxpacket	= BULK_FIFO_SIZE,
2148 			.caps		= USB_EP_CAPS(USB_EP_CAPS_TYPE_BULK,
2149 						USB_EP_CAPS_DIR_OUT),
2150 		},
2151 		.dev		= &memory,
2152 		.fifo_size	= BULK_FIFO_SIZE,
2153 		.bEndpointAddress = 7,
2154 		.bmAttributes	= USB_ENDPOINT_XFER_BULK,
2155 		.regoff_udccs	= UDCCS7,
2156 		.regoff_ubcr	= UBCR7,
2157 		.regoff_uddr	= UDDR7,
2158 	},
2159 	.ep[8] = {
2160 		.ep = {
2161 			.name		= "ep8in-iso",
2162 			.ops		= &pxa25x_ep_ops,
2163 			.maxpacket	= ISO_FIFO_SIZE,
2164 			.caps		= USB_EP_CAPS(USB_EP_CAPS_TYPE_ISO,
2165 						USB_EP_CAPS_DIR_IN),
2166 		},
2167 		.dev		= &memory,
2168 		.fifo_size	= ISO_FIFO_SIZE,
2169 		.bEndpointAddress = USB_DIR_IN | 8,
2170 		.bmAttributes	= USB_ENDPOINT_XFER_ISOC,
2171 		.regoff_udccs	= UDCCS8,
2172 		.regoff_uddr	= UDDR8,
2173 	},
2174 	.ep[9] = {
2175 		.ep = {
2176 			.name		= "ep9out-iso",
2177 			.ops		= &pxa25x_ep_ops,
2178 			.maxpacket	= ISO_FIFO_SIZE,
2179 			.caps		= USB_EP_CAPS(USB_EP_CAPS_TYPE_ISO,
2180 						USB_EP_CAPS_DIR_OUT),
2181 		},
2182 		.dev		= &memory,
2183 		.fifo_size	= ISO_FIFO_SIZE,
2184 		.bEndpointAddress = 9,
2185 		.bmAttributes	= USB_ENDPOINT_XFER_ISOC,
2186 		.regoff_udccs	= UDCCS9,
2187 		.regoff_ubcr	= UBCR9,
2188 		.regoff_uddr	= UDDR9,
2189 	},
2190 	.ep[10] = {
2191 		.ep = {
2192 			.name		= "ep10in-int",
2193 			.ops		= &pxa25x_ep_ops,
2194 			.maxpacket	= INT_FIFO_SIZE,
2195 			.caps		= USB_EP_CAPS(0, 0),
2196 		},
2197 		.dev		= &memory,
2198 		.fifo_size	= INT_FIFO_SIZE,
2199 		.bEndpointAddress = USB_DIR_IN | 10,
2200 		.bmAttributes	= USB_ENDPOINT_XFER_INT,
2201 		.regoff_udccs	= UDCCS10,
2202 		.regoff_uddr	= UDDR10,
2203 	},
2204 
2205 	/* third group of endpoints */
2206 	.ep[11] = {
2207 		.ep = {
2208 			.name		= "ep11in-bulk",
2209 			.ops		= &pxa25x_ep_ops,
2210 			.maxpacket	= BULK_FIFO_SIZE,
2211 			.caps		= USB_EP_CAPS(USB_EP_CAPS_TYPE_BULK,
2212 						USB_EP_CAPS_DIR_IN),
2213 		},
2214 		.dev		= &memory,
2215 		.fifo_size	= BULK_FIFO_SIZE,
2216 		.bEndpointAddress = USB_DIR_IN | 11,
2217 		.bmAttributes	= USB_ENDPOINT_XFER_BULK,
2218 		.regoff_udccs	= UDCCS11,
2219 		.regoff_uddr	= UDDR11,
2220 	},
2221 	.ep[12] = {
2222 		.ep = {
2223 			.name		= "ep12out-bulk",
2224 			.ops		= &pxa25x_ep_ops,
2225 			.maxpacket	= BULK_FIFO_SIZE,
2226 			.caps		= USB_EP_CAPS(USB_EP_CAPS_TYPE_BULK,
2227 						USB_EP_CAPS_DIR_OUT),
2228 		},
2229 		.dev		= &memory,
2230 		.fifo_size	= BULK_FIFO_SIZE,
2231 		.bEndpointAddress = 12,
2232 		.bmAttributes	= USB_ENDPOINT_XFER_BULK,
2233 		.regoff_udccs	= UDCCS12,
2234 		.regoff_ubcr	= UBCR12,
2235 		.regoff_uddr	= UDDR12,
2236 	},
2237 	.ep[13] = {
2238 		.ep = {
2239 			.name		= "ep13in-iso",
2240 			.ops		= &pxa25x_ep_ops,
2241 			.maxpacket	= ISO_FIFO_SIZE,
2242 			.caps		= USB_EP_CAPS(USB_EP_CAPS_TYPE_ISO,
2243 						USB_EP_CAPS_DIR_IN),
2244 		},
2245 		.dev		= &memory,
2246 		.fifo_size	= ISO_FIFO_SIZE,
2247 		.bEndpointAddress = USB_DIR_IN | 13,
2248 		.bmAttributes	= USB_ENDPOINT_XFER_ISOC,
2249 		.regoff_udccs	= UDCCS13,
2250 		.regoff_uddr	= UDDR13,
2251 	},
2252 	.ep[14] = {
2253 		.ep = {
2254 			.name		= "ep14out-iso",
2255 			.ops		= &pxa25x_ep_ops,
2256 			.maxpacket	= ISO_FIFO_SIZE,
2257 			.caps		= USB_EP_CAPS(USB_EP_CAPS_TYPE_ISO,
2258 						USB_EP_CAPS_DIR_OUT),
2259 		},
2260 		.dev		= &memory,
2261 		.fifo_size	= ISO_FIFO_SIZE,
2262 		.bEndpointAddress = 14,
2263 		.bmAttributes	= USB_ENDPOINT_XFER_ISOC,
2264 		.regoff_udccs	= UDCCS14,
2265 		.regoff_ubcr	= UBCR14,
2266 		.regoff_uddr	= UDDR14,
2267 	},
2268 	.ep[15] = {
2269 		.ep = {
2270 			.name		= "ep15in-int",
2271 			.ops		= &pxa25x_ep_ops,
2272 			.maxpacket	= INT_FIFO_SIZE,
2273 			.caps		= USB_EP_CAPS(0, 0),
2274 		},
2275 		.dev		= &memory,
2276 		.fifo_size	= INT_FIFO_SIZE,
2277 		.bEndpointAddress = USB_DIR_IN | 15,
2278 		.bmAttributes	= USB_ENDPOINT_XFER_INT,
2279 		.regoff_udccs	= UDCCS15,
2280 		.regoff_uddr	= UDDR15,
2281 	},
2282 #endif /* !CONFIG_USB_PXA25X_SMALL */
2283 };
2284 
2285 #define CP15R0_VENDOR_MASK	0xffffe000
2286 
2287 #if	defined(CONFIG_ARCH_PXA)
2288 #define CP15R0_XSCALE_VALUE	0x69052000	/* intel/arm/xscale */
2289 
2290 #elif	defined(CONFIG_ARCH_IXP4XX)
2291 #define CP15R0_XSCALE_VALUE	0x69054000	/* intel/arm/ixp4xx */
2292 
2293 #endif
2294 
2295 #define CP15R0_PROD_MASK	0x000003f0
2296 #define PXA25x			0x00000100	/* and PXA26x */
2297 #define PXA210			0x00000120
2298 
2299 #define CP15R0_REV_MASK		0x0000000f
2300 
2301 #define CP15R0_PRODREV_MASK	(CP15R0_PROD_MASK | CP15R0_REV_MASK)
2302 
2303 #define PXA255_A0		0x00000106	/* or PXA260_B1 */
2304 #define PXA250_C0		0x00000105	/* or PXA26x_B0 */
2305 #define PXA250_B2		0x00000104
2306 #define PXA250_B1		0x00000103	/* or PXA260_A0 */
2307 #define PXA250_B0		0x00000102
2308 #define PXA250_A1		0x00000101
2309 #define PXA250_A0		0x00000100
2310 
2311 #define PXA210_C0		0x00000125
2312 #define PXA210_B2		0x00000124
2313 #define PXA210_B1		0x00000123
2314 #define PXA210_B0		0x00000122
2315 #define IXP425_A0		0x000001c1
2316 #define IXP425_B0		0x000001f1
2317 #define IXP465_AD		0x00000200
2318 
2319 /*
2320  *	probe - binds to the platform device
2321  */
2322 static int pxa25x_udc_probe(struct platform_device *pdev)
2323 {
2324 	struct pxa25x_udc *dev = &memory;
2325 	int retval, irq;
2326 	u32 chiprev;
2327 
2328 	pr_info("%s: version %s\n", driver_name, DRIVER_VERSION);
2329 
2330 	/* insist on Intel/ARM/XScale */
2331 	asm("mrc p15, 0, %0, c0, c0" : "=r" (chiprev));
2332 	if ((chiprev & CP15R0_VENDOR_MASK) != CP15R0_XSCALE_VALUE) {
2333 		pr_err("%s: not XScale!\n", driver_name);
2334 		return -ENODEV;
2335 	}
2336 
2337 	/* trigger chiprev-specific logic */
2338 	switch (chiprev & CP15R0_PRODREV_MASK) {
2339 #if	defined(CONFIG_ARCH_PXA)
2340 	case PXA255_A0:
2341 		dev->has_cfr = 1;
2342 		break;
2343 	case PXA250_A0:
2344 	case PXA250_A1:
2345 		/* A0/A1 "not released"; ep 13, 15 unusable */
2346 		fallthrough;
2347 	case PXA250_B2: case PXA210_B2:
2348 	case PXA250_B1: case PXA210_B1:
2349 	case PXA250_B0: case PXA210_B0:
2350 		/* OUT-DMA is broken ... */
2351 		fallthrough;
2352 	case PXA250_C0: case PXA210_C0:
2353 		break;
2354 #elif	defined(CONFIG_ARCH_IXP4XX)
2355 	case IXP425_A0:
2356 	case IXP425_B0:
2357 	case IXP465_AD:
2358 		dev->has_cfr = 1;
2359 		break;
2360 #endif
2361 	default:
2362 		pr_err("%s: unrecognized processor: %08x\n",
2363 			driver_name, chiprev);
2364 		/* iop3xx, ixp4xx, ... */
2365 		return -ENODEV;
2366 	}
2367 
2368 	irq = platform_get_irq(pdev, 0);
2369 	if (irq < 0)
2370 		return irq;
2371 
2372 	dev->regs = devm_platform_ioremap_resource(pdev, 0);
2373 	if (IS_ERR(dev->regs))
2374 		return PTR_ERR(dev->regs);
2375 
2376 	dev->clk = devm_clk_get(&pdev->dev, NULL);
2377 	if (IS_ERR(dev->clk))
2378 		return PTR_ERR(dev->clk);
2379 
2380 	pr_debug("%s: IRQ %d%s%s\n", driver_name, irq,
2381 		dev->has_cfr ? "" : " (!cfr)",
2382 		SIZE_STR "(pio)"
2383 		);
2384 
2385 	/* other non-static parts of init */
2386 	dev->dev = &pdev->dev;
2387 	dev->mach = dev_get_platdata(&pdev->dev);
2388 
2389 	dev->transceiver = devm_usb_get_phy(&pdev->dev, USB_PHY_TYPE_USB2);
2390 
2391 	if (gpio_is_valid(dev->mach->gpio_pullup)) {
2392 		retval = devm_gpio_request(&pdev->dev, dev->mach->gpio_pullup,
2393 					   "pca25x_udc GPIO PULLUP");
2394 		if (retval) {
2395 			dev_dbg(&pdev->dev,
2396 				"can't get pullup gpio %d, err: %d\n",
2397 				dev->mach->gpio_pullup, retval);
2398 			goto err;
2399 		}
2400 		gpio_direction_output(dev->mach->gpio_pullup, 0);
2401 	}
2402 
2403 	timer_setup(&dev->timer, udc_watchdog, 0);
2404 
2405 	the_controller = dev;
2406 	platform_set_drvdata(pdev, dev);
2407 
2408 	udc_disable(dev);
2409 	udc_reinit(dev);
2410 
2411 	dev->vbus = 0;
2412 
2413 	/* irq setup after old hardware state is cleaned up */
2414 	retval = devm_request_irq(&pdev->dev, irq, pxa25x_udc_irq, 0,
2415 				  driver_name, dev);
2416 	if (retval != 0) {
2417 		pr_err("%s: can't get irq %d, err %d\n",
2418 			driver_name, irq, retval);
2419 		goto err;
2420 	}
2421 	dev->got_irq = 1;
2422 
2423 #ifdef CONFIG_ARCH_LUBBOCK
2424 	if (machine_is_lubbock()) {
2425 		retval = devm_request_irq(&pdev->dev, LUBBOCK_USB_DISC_IRQ,
2426 					  lubbock_vbus_irq, 0, driver_name,
2427 					  dev);
2428 		if (retval != 0) {
2429 			pr_err("%s: can't get irq %i, err %d\n",
2430 				driver_name, LUBBOCK_USB_DISC_IRQ, retval);
2431 			goto err;
2432 		}
2433 		retval = devm_request_irq(&pdev->dev, LUBBOCK_USB_IRQ,
2434 					  lubbock_vbus_irq, 0, driver_name,
2435 					  dev);
2436 		if (retval != 0) {
2437 			pr_err("%s: can't get irq %i, err %d\n",
2438 				driver_name, LUBBOCK_USB_IRQ, retval);
2439 			goto err;
2440 		}
2441 	} else
2442 #endif
2443 	create_debug_files(dev);
2444 
2445 	retval = usb_add_gadget_udc(&pdev->dev, &dev->gadget);
2446 	if (!retval)
2447 		return retval;
2448 
2449 	remove_debug_files(dev);
2450  err:
2451 	if (!IS_ERR_OR_NULL(dev->transceiver))
2452 		dev->transceiver = NULL;
2453 	return retval;
2454 }
2455 
2456 static void pxa25x_udc_shutdown(struct platform_device *_dev)
2457 {
2458 	pullup_off();
2459 }
2460 
2461 static int pxa25x_udc_remove(struct platform_device *pdev)
2462 {
2463 	struct pxa25x_udc *dev = platform_get_drvdata(pdev);
2464 
2465 	if (dev->driver)
2466 		return -EBUSY;
2467 
2468 	usb_del_gadget_udc(&dev->gadget);
2469 	dev->pullup = 0;
2470 	pullup(dev);
2471 
2472 	remove_debug_files(dev);
2473 
2474 	if (!IS_ERR_OR_NULL(dev->transceiver))
2475 		dev->transceiver = NULL;
2476 
2477 	the_controller = NULL;
2478 	return 0;
2479 }
2480 
2481 /*-------------------------------------------------------------------------*/
2482 
2483 #ifdef	CONFIG_PM
2484 
2485 /* USB suspend (controlled by the host) and system suspend (controlled
2486  * by the PXA) don't necessarily work well together.  If USB is active,
2487  * the 48 MHz clock is required; so the system can't enter 33 MHz idle
2488  * mode, or any deeper PM saving state.
2489  *
2490  * For now, we punt and forcibly disconnect from the USB host when PXA
2491  * enters any suspend state.  While we're disconnected, we always disable
2492  * the 48MHz USB clock ... allowing PXA sleep and/or 33 MHz idle states.
2493  * Boards without software pullup control shouldn't use those states.
2494  * VBUS IRQs should probably be ignored so that the PXA device just acts
2495  * "dead" to USB hosts until system resume.
2496  */
2497 static int pxa25x_udc_suspend(struct platform_device *dev, pm_message_t state)
2498 {
2499 	struct pxa25x_udc	*udc = platform_get_drvdata(dev);
2500 	unsigned long flags;
2501 
2502 	if (!gpio_is_valid(udc->mach->gpio_pullup) && !udc->mach->udc_command)
2503 		WARNING("USB host won't detect disconnect!\n");
2504 	udc->suspended = 1;
2505 
2506 	local_irq_save(flags);
2507 	pullup(udc);
2508 	local_irq_restore(flags);
2509 
2510 	return 0;
2511 }
2512 
2513 static int pxa25x_udc_resume(struct platform_device *dev)
2514 {
2515 	struct pxa25x_udc	*udc = platform_get_drvdata(dev);
2516 	unsigned long flags;
2517 
2518 	udc->suspended = 0;
2519 	local_irq_save(flags);
2520 	pullup(udc);
2521 	local_irq_restore(flags);
2522 
2523 	return 0;
2524 }
2525 
2526 #else
2527 #define	pxa25x_udc_suspend	NULL
2528 #define	pxa25x_udc_resume	NULL
2529 #endif
2530 
2531 /*-------------------------------------------------------------------------*/
2532 
2533 static struct platform_driver udc_driver = {
2534 	.shutdown	= pxa25x_udc_shutdown,
2535 	.probe		= pxa25x_udc_probe,
2536 	.remove		= pxa25x_udc_remove,
2537 	.suspend	= pxa25x_udc_suspend,
2538 	.resume		= pxa25x_udc_resume,
2539 	.driver		= {
2540 		.name	= "pxa25x-udc",
2541 	},
2542 };
2543 
2544 module_platform_driver(udc_driver);
2545 
2546 MODULE_DESCRIPTION(DRIVER_DESC);
2547 MODULE_AUTHOR("Frank Becker, Robert Schwebel, David Brownell");
2548 MODULE_LICENSE("GPL");
2549 MODULE_ALIAS("platform:pxa25x-udc");
2550