190fccb52SAndrzej Pietrasiewicz /* 290fccb52SAndrzej Pietrasiewicz * M66592 UDC (USB gadget) 390fccb52SAndrzej Pietrasiewicz * 490fccb52SAndrzej Pietrasiewicz * Copyright (C) 2006-2007 Renesas Solutions Corp. 590fccb52SAndrzej Pietrasiewicz * 690fccb52SAndrzej Pietrasiewicz * Author : Yoshihiro Shimoda <yoshihiro.shimoda.uh@renesas.com> 790fccb52SAndrzej Pietrasiewicz * 890fccb52SAndrzej Pietrasiewicz * This program is free software; you can redistribute it and/or modify 990fccb52SAndrzej Pietrasiewicz * it under the terms of the GNU General Public License as published by 1090fccb52SAndrzej Pietrasiewicz * the Free Software Foundation; version 2 of the License. 1190fccb52SAndrzej Pietrasiewicz */ 1290fccb52SAndrzej Pietrasiewicz 1390fccb52SAndrzej Pietrasiewicz #ifndef __M66592_UDC_H__ 1490fccb52SAndrzej Pietrasiewicz #define __M66592_UDC_H__ 1590fccb52SAndrzej Pietrasiewicz 1690fccb52SAndrzej Pietrasiewicz #include <linux/clk.h> 1790fccb52SAndrzej Pietrasiewicz #include <linux/usb/m66592.h> 1890fccb52SAndrzej Pietrasiewicz 1990fccb52SAndrzej Pietrasiewicz #define M66592_SYSCFG 0x00 2090fccb52SAndrzej Pietrasiewicz #define M66592_XTAL 0xC000 /* b15-14: Crystal selection */ 2190fccb52SAndrzej Pietrasiewicz #define M66592_XTAL48 0x8000 /* 48MHz */ 2290fccb52SAndrzej Pietrasiewicz #define M66592_XTAL24 0x4000 /* 24MHz */ 2390fccb52SAndrzej Pietrasiewicz #define M66592_XTAL12 0x0000 /* 12MHz */ 2490fccb52SAndrzej Pietrasiewicz #define M66592_XCKE 0x2000 /* b13: External clock enable */ 2590fccb52SAndrzej Pietrasiewicz #define M66592_RCKE 0x1000 /* b12: Register clock enable */ 2690fccb52SAndrzej Pietrasiewicz #define M66592_PLLC 0x0800 /* b11: PLL control */ 2790fccb52SAndrzej Pietrasiewicz #define M66592_SCKE 0x0400 /* b10: USB clock enable */ 2890fccb52SAndrzej Pietrasiewicz #define M66592_ATCKM 0x0100 /* b8: Automatic clock supply */ 2990fccb52SAndrzej Pietrasiewicz #define M66592_HSE 0x0080 /* b7: Hi-speed enable */ 3090fccb52SAndrzej Pietrasiewicz #define M66592_DCFM 0x0040 /* b6: Controller function select */ 3190fccb52SAndrzej Pietrasiewicz #define M66592_DMRPD 0x0020 /* b5: D- pull down control */ 3290fccb52SAndrzej Pietrasiewicz #define M66592_DPRPU 0x0010 /* b4: D+ pull up control */ 3390fccb52SAndrzej Pietrasiewicz #define M66592_FSRPC 0x0004 /* b2: Full-speed receiver enable */ 3490fccb52SAndrzej Pietrasiewicz #define M66592_PCUT 0x0002 /* b1: Low power sleep enable */ 3590fccb52SAndrzej Pietrasiewicz #define M66592_USBE 0x0001 /* b0: USB module operation enable */ 3690fccb52SAndrzej Pietrasiewicz 3790fccb52SAndrzej Pietrasiewicz #define M66592_SYSSTS 0x02 3890fccb52SAndrzej Pietrasiewicz #define M66592_LNST 0x0003 /* b1-0: D+, D- line status */ 3990fccb52SAndrzej Pietrasiewicz #define M66592_SE1 0x0003 /* SE1 */ 4090fccb52SAndrzej Pietrasiewicz #define M66592_KSTS 0x0002 /* K State */ 4190fccb52SAndrzej Pietrasiewicz #define M66592_JSTS 0x0001 /* J State */ 4290fccb52SAndrzej Pietrasiewicz #define M66592_SE0 0x0000 /* SE0 */ 4390fccb52SAndrzej Pietrasiewicz 4490fccb52SAndrzej Pietrasiewicz #define M66592_DVSTCTR 0x04 4590fccb52SAndrzej Pietrasiewicz #define M66592_WKUP 0x0100 /* b8: Remote wakeup */ 4690fccb52SAndrzej Pietrasiewicz #define M66592_RWUPE 0x0080 /* b7: Remote wakeup sense */ 4790fccb52SAndrzej Pietrasiewicz #define M66592_USBRST 0x0040 /* b6: USB reset enable */ 4890fccb52SAndrzej Pietrasiewicz #define M66592_RESUME 0x0020 /* b5: Resume enable */ 4990fccb52SAndrzej Pietrasiewicz #define M66592_UACT 0x0010 /* b4: USB bus enable */ 5090fccb52SAndrzej Pietrasiewicz #define M66592_RHST 0x0003 /* b1-0: Reset handshake status */ 5190fccb52SAndrzej Pietrasiewicz #define M66592_HSMODE 0x0003 /* Hi-Speed mode */ 5290fccb52SAndrzej Pietrasiewicz #define M66592_FSMODE 0x0002 /* Full-Speed mode */ 5390fccb52SAndrzej Pietrasiewicz #define M66592_HSPROC 0x0001 /* HS handshake is processing */ 5490fccb52SAndrzej Pietrasiewicz 5590fccb52SAndrzej Pietrasiewicz #define M66592_TESTMODE 0x06 5690fccb52SAndrzej Pietrasiewicz #define M66592_UTST 0x000F /* b4-0: Test select */ 5790fccb52SAndrzej Pietrasiewicz #define M66592_H_TST_PACKET 0x000C /* HOST TEST Packet */ 5890fccb52SAndrzej Pietrasiewicz #define M66592_H_TST_SE0_NAK 0x000B /* HOST TEST SE0 NAK */ 5990fccb52SAndrzej Pietrasiewicz #define M66592_H_TST_K 0x000A /* HOST TEST K */ 6090fccb52SAndrzej Pietrasiewicz #define M66592_H_TST_J 0x0009 /* HOST TEST J */ 6190fccb52SAndrzej Pietrasiewicz #define M66592_H_TST_NORMAL 0x0000 /* HOST Normal Mode */ 6290fccb52SAndrzej Pietrasiewicz #define M66592_P_TST_PACKET 0x0004 /* PERI TEST Packet */ 6390fccb52SAndrzej Pietrasiewicz #define M66592_P_TST_SE0_NAK 0x0003 /* PERI TEST SE0 NAK */ 6490fccb52SAndrzej Pietrasiewicz #define M66592_P_TST_K 0x0002 /* PERI TEST K */ 6590fccb52SAndrzej Pietrasiewicz #define M66592_P_TST_J 0x0001 /* PERI TEST J */ 6690fccb52SAndrzej Pietrasiewicz #define M66592_P_TST_NORMAL 0x0000 /* PERI Normal Mode */ 6790fccb52SAndrzej Pietrasiewicz 6890fccb52SAndrzej Pietrasiewicz /* built-in registers */ 6990fccb52SAndrzej Pietrasiewicz #define M66592_CFBCFG 0x0A 7090fccb52SAndrzej Pietrasiewicz #define M66592_D0FBCFG 0x0C 7190fccb52SAndrzej Pietrasiewicz #define M66592_LITTLE 0x0100 /* b8: Little endian mode */ 7290fccb52SAndrzej Pietrasiewicz /* external chip case */ 7390fccb52SAndrzej Pietrasiewicz #define M66592_PINCFG 0x0A 7490fccb52SAndrzej Pietrasiewicz #define M66592_LDRV 0x8000 /* b15: Drive Current Adjust */ 7590fccb52SAndrzej Pietrasiewicz #define M66592_BIGEND 0x0100 /* b8: Big endian mode */ 7690fccb52SAndrzej Pietrasiewicz 7790fccb52SAndrzej Pietrasiewicz #define M66592_DMA0CFG 0x0C 7890fccb52SAndrzej Pietrasiewicz #define M66592_DMA1CFG 0x0E 7990fccb52SAndrzej Pietrasiewicz #define M66592_DREQA 0x4000 /* b14: Dreq active select */ 8090fccb52SAndrzej Pietrasiewicz #define M66592_BURST 0x2000 /* b13: Burst mode */ 8190fccb52SAndrzej Pietrasiewicz #define M66592_DACKA 0x0400 /* b10: Dack active select */ 8290fccb52SAndrzej Pietrasiewicz #define M66592_DFORM 0x0380 /* b9-7: DMA mode select */ 8390fccb52SAndrzej Pietrasiewicz #define M66592_CPU_ADR_RD_WR 0x0000 /* Address + RD/WR mode (CPU bus) */ 8490fccb52SAndrzej Pietrasiewicz #define M66592_CPU_DACK_RD_WR 0x0100 /* DACK + RD/WR mode (CPU bus) */ 8590fccb52SAndrzej Pietrasiewicz #define M66592_CPU_DACK_ONLY 0x0180 /* DACK only mode (CPU bus) */ 8690fccb52SAndrzej Pietrasiewicz #define M66592_SPLIT_DACK_ONLY 0x0200 /* DACK only mode (SPLIT bus) */ 8790fccb52SAndrzej Pietrasiewicz #define M66592_SPLIT_DACK_DSTB 0x0300 /* DACK + DSTB0 mode (SPLIT bus) */ 8890fccb52SAndrzej Pietrasiewicz #define M66592_DENDA 0x0040 /* b6: Dend active select */ 8990fccb52SAndrzej Pietrasiewicz #define M66592_PKTM 0x0020 /* b5: Packet mode */ 9090fccb52SAndrzej Pietrasiewicz #define M66592_DENDE 0x0010 /* b4: Dend enable */ 9190fccb52SAndrzej Pietrasiewicz #define M66592_OBUS 0x0004 /* b2: OUTbus mode */ 9290fccb52SAndrzej Pietrasiewicz 9390fccb52SAndrzej Pietrasiewicz /* common case */ 9490fccb52SAndrzej Pietrasiewicz #define M66592_CFIFO 0x10 9590fccb52SAndrzej Pietrasiewicz #define M66592_D0FIFO 0x14 9690fccb52SAndrzej Pietrasiewicz #define M66592_D1FIFO 0x18 9790fccb52SAndrzej Pietrasiewicz 9890fccb52SAndrzej Pietrasiewicz #define M66592_CFIFOSEL 0x1E 9990fccb52SAndrzej Pietrasiewicz #define M66592_D0FIFOSEL 0x24 10090fccb52SAndrzej Pietrasiewicz #define M66592_D1FIFOSEL 0x2A 10190fccb52SAndrzej Pietrasiewicz #define M66592_RCNT 0x8000 /* b15: Read count mode */ 10290fccb52SAndrzej Pietrasiewicz #define M66592_REW 0x4000 /* b14: Buffer rewind */ 10390fccb52SAndrzej Pietrasiewicz #define M66592_DCLRM 0x2000 /* b13: DMA buffer clear mode */ 10490fccb52SAndrzej Pietrasiewicz #define M66592_DREQE 0x1000 /* b12: DREQ output enable */ 10590fccb52SAndrzej Pietrasiewicz #define M66592_MBW_8 0x0000 /* 8bit */ 10690fccb52SAndrzej Pietrasiewicz #define M66592_MBW_16 0x0400 /* 16bit */ 10790fccb52SAndrzej Pietrasiewicz #define M66592_MBW_32 0x0800 /* 32bit */ 10890fccb52SAndrzej Pietrasiewicz #define M66592_TRENB 0x0200 /* b9: Transaction counter enable */ 10990fccb52SAndrzej Pietrasiewicz #define M66592_TRCLR 0x0100 /* b8: Transaction counter clear */ 11090fccb52SAndrzej Pietrasiewicz #define M66592_DEZPM 0x0080 /* b7: Zero-length packet mode */ 11190fccb52SAndrzej Pietrasiewicz #define M66592_ISEL 0x0020 /* b5: DCP FIFO port direction select */ 11290fccb52SAndrzej Pietrasiewicz #define M66592_CURPIPE 0x0007 /* b2-0: PIPE select */ 11390fccb52SAndrzej Pietrasiewicz 11490fccb52SAndrzej Pietrasiewicz #define M66592_CFIFOCTR 0x20 11590fccb52SAndrzej Pietrasiewicz #define M66592_D0FIFOCTR 0x26 11690fccb52SAndrzej Pietrasiewicz #define M66592_D1FIFOCTR 0x2c 11790fccb52SAndrzej Pietrasiewicz #define M66592_BVAL 0x8000 /* b15: Buffer valid flag */ 11890fccb52SAndrzej Pietrasiewicz #define M66592_BCLR 0x4000 /* b14: Buffer clear */ 11990fccb52SAndrzej Pietrasiewicz #define M66592_FRDY 0x2000 /* b13: FIFO ready */ 12090fccb52SAndrzej Pietrasiewicz #define M66592_DTLN 0x0FFF /* b11-0: FIFO received data length */ 12190fccb52SAndrzej Pietrasiewicz 12290fccb52SAndrzej Pietrasiewicz #define M66592_CFIFOSIE 0x22 12390fccb52SAndrzej Pietrasiewicz #define M66592_TGL 0x8000 /* b15: Buffer toggle */ 12490fccb52SAndrzej Pietrasiewicz #define M66592_SCLR 0x4000 /* b14: Buffer clear */ 12590fccb52SAndrzej Pietrasiewicz #define M66592_SBUSY 0x2000 /* b13: SIE_FIFO busy */ 12690fccb52SAndrzej Pietrasiewicz 12790fccb52SAndrzej Pietrasiewicz #define M66592_D0FIFOTRN 0x28 12890fccb52SAndrzej Pietrasiewicz #define M66592_D1FIFOTRN 0x2E 12990fccb52SAndrzej Pietrasiewicz #define M66592_TRNCNT 0xFFFF /* b15-0: Transaction counter */ 13090fccb52SAndrzej Pietrasiewicz 13190fccb52SAndrzej Pietrasiewicz #define M66592_INTENB0 0x30 13290fccb52SAndrzej Pietrasiewicz #define M66592_VBSE 0x8000 /* b15: VBUS interrupt */ 13390fccb52SAndrzej Pietrasiewicz #define M66592_RSME 0x4000 /* b14: Resume interrupt */ 13490fccb52SAndrzej Pietrasiewicz #define M66592_SOFE 0x2000 /* b13: Frame update interrupt */ 13590fccb52SAndrzej Pietrasiewicz #define M66592_DVSE 0x1000 /* b12: Device state transition interrupt */ 13690fccb52SAndrzej Pietrasiewicz #define M66592_CTRE 0x0800 /* b11: Control transfer stage transition irq */ 13790fccb52SAndrzej Pietrasiewicz #define M66592_BEMPE 0x0400 /* b10: Buffer empty interrupt */ 13890fccb52SAndrzej Pietrasiewicz #define M66592_NRDYE 0x0200 /* b9: Buffer not ready interrupt */ 13990fccb52SAndrzej Pietrasiewicz #define M66592_BRDYE 0x0100 /* b8: Buffer ready interrupt */ 14090fccb52SAndrzej Pietrasiewicz #define M66592_URST 0x0080 /* b7: USB reset detected interrupt */ 14190fccb52SAndrzej Pietrasiewicz #define M66592_SADR 0x0040 /* b6: Set address executed interrupt */ 14290fccb52SAndrzej Pietrasiewicz #define M66592_SCFG 0x0020 /* b5: Set configuration executed interrupt */ 14390fccb52SAndrzej Pietrasiewicz #define M66592_SUSP 0x0010 /* b4: Suspend detected interrupt */ 14490fccb52SAndrzej Pietrasiewicz #define M66592_WDST 0x0008 /* b3: Control write data stage completed irq */ 14590fccb52SAndrzej Pietrasiewicz #define M66592_RDST 0x0004 /* b2: Control read data stage completed irq */ 14690fccb52SAndrzej Pietrasiewicz #define M66592_CMPL 0x0002 /* b1: Control transfer complete interrupt */ 14790fccb52SAndrzej Pietrasiewicz #define M66592_SERR 0x0001 /* b0: Sequence error interrupt */ 14890fccb52SAndrzej Pietrasiewicz 14990fccb52SAndrzej Pietrasiewicz #define M66592_INTENB1 0x32 15090fccb52SAndrzej Pietrasiewicz #define M66592_BCHGE 0x4000 /* b14: USB us chenge interrupt */ 15190fccb52SAndrzej Pietrasiewicz #define M66592_DTCHE 0x1000 /* b12: Detach sense interrupt */ 15290fccb52SAndrzej Pietrasiewicz #define M66592_SIGNE 0x0020 /* b5: SETUP IGNORE interrupt */ 15390fccb52SAndrzej Pietrasiewicz #define M66592_SACKE 0x0010 /* b4: SETUP ACK interrupt */ 15490fccb52SAndrzej Pietrasiewicz #define M66592_BRDYM 0x0004 /* b2: BRDY clear timing */ 15590fccb52SAndrzej Pietrasiewicz #define M66592_INTL 0x0002 /* b1: Interrupt sense select */ 15690fccb52SAndrzej Pietrasiewicz #define M66592_PCSE 0x0001 /* b0: PCUT enable by CS assert */ 15790fccb52SAndrzej Pietrasiewicz 15890fccb52SAndrzej Pietrasiewicz #define M66592_BRDYENB 0x36 15990fccb52SAndrzej Pietrasiewicz #define M66592_BRDYSTS 0x46 16090fccb52SAndrzej Pietrasiewicz #define M66592_BRDY7 0x0080 /* b7: PIPE7 */ 16190fccb52SAndrzej Pietrasiewicz #define M66592_BRDY6 0x0040 /* b6: PIPE6 */ 16290fccb52SAndrzej Pietrasiewicz #define M66592_BRDY5 0x0020 /* b5: PIPE5 */ 16390fccb52SAndrzej Pietrasiewicz #define M66592_BRDY4 0x0010 /* b4: PIPE4 */ 16490fccb52SAndrzej Pietrasiewicz #define M66592_BRDY3 0x0008 /* b3: PIPE3 */ 16590fccb52SAndrzej Pietrasiewicz #define M66592_BRDY2 0x0004 /* b2: PIPE2 */ 16690fccb52SAndrzej Pietrasiewicz #define M66592_BRDY1 0x0002 /* b1: PIPE1 */ 16790fccb52SAndrzej Pietrasiewicz #define M66592_BRDY0 0x0001 /* b1: PIPE0 */ 16890fccb52SAndrzej Pietrasiewicz 16990fccb52SAndrzej Pietrasiewicz #define M66592_NRDYENB 0x38 17090fccb52SAndrzej Pietrasiewicz #define M66592_NRDYSTS 0x48 17190fccb52SAndrzej Pietrasiewicz #define M66592_NRDY7 0x0080 /* b7: PIPE7 */ 17290fccb52SAndrzej Pietrasiewicz #define M66592_NRDY6 0x0040 /* b6: PIPE6 */ 17390fccb52SAndrzej Pietrasiewicz #define M66592_NRDY5 0x0020 /* b5: PIPE5 */ 17490fccb52SAndrzej Pietrasiewicz #define M66592_NRDY4 0x0010 /* b4: PIPE4 */ 17590fccb52SAndrzej Pietrasiewicz #define M66592_NRDY3 0x0008 /* b3: PIPE3 */ 17690fccb52SAndrzej Pietrasiewicz #define M66592_NRDY2 0x0004 /* b2: PIPE2 */ 17790fccb52SAndrzej Pietrasiewicz #define M66592_NRDY1 0x0002 /* b1: PIPE1 */ 17890fccb52SAndrzej Pietrasiewicz #define M66592_NRDY0 0x0001 /* b1: PIPE0 */ 17990fccb52SAndrzej Pietrasiewicz 18090fccb52SAndrzej Pietrasiewicz #define M66592_BEMPENB 0x3A 18190fccb52SAndrzej Pietrasiewicz #define M66592_BEMPSTS 0x4A 18290fccb52SAndrzej Pietrasiewicz #define M66592_BEMP7 0x0080 /* b7: PIPE7 */ 18390fccb52SAndrzej Pietrasiewicz #define M66592_BEMP6 0x0040 /* b6: PIPE6 */ 18490fccb52SAndrzej Pietrasiewicz #define M66592_BEMP5 0x0020 /* b5: PIPE5 */ 18590fccb52SAndrzej Pietrasiewicz #define M66592_BEMP4 0x0010 /* b4: PIPE4 */ 18690fccb52SAndrzej Pietrasiewicz #define M66592_BEMP3 0x0008 /* b3: PIPE3 */ 18790fccb52SAndrzej Pietrasiewicz #define M66592_BEMP2 0x0004 /* b2: PIPE2 */ 18890fccb52SAndrzej Pietrasiewicz #define M66592_BEMP1 0x0002 /* b1: PIPE1 */ 18990fccb52SAndrzej Pietrasiewicz #define M66592_BEMP0 0x0001 /* b0: PIPE0 */ 19090fccb52SAndrzej Pietrasiewicz 19190fccb52SAndrzej Pietrasiewicz #define M66592_SOFCFG 0x3C 19290fccb52SAndrzej Pietrasiewicz #define M66592_SOFM 0x000C /* b3-2: SOF palse mode */ 19390fccb52SAndrzej Pietrasiewicz #define M66592_SOF_125US 0x0008 /* SOF OUT 125us uFrame Signal */ 19490fccb52SAndrzej Pietrasiewicz #define M66592_SOF_1MS 0x0004 /* SOF OUT 1ms Frame Signal */ 19590fccb52SAndrzej Pietrasiewicz #define M66592_SOF_DISABLE 0x0000 /* SOF OUT Disable */ 19690fccb52SAndrzej Pietrasiewicz 19790fccb52SAndrzej Pietrasiewicz #define M66592_INTSTS0 0x40 19890fccb52SAndrzej Pietrasiewicz #define M66592_VBINT 0x8000 /* b15: VBUS interrupt */ 19990fccb52SAndrzej Pietrasiewicz #define M66592_RESM 0x4000 /* b14: Resume interrupt */ 20090fccb52SAndrzej Pietrasiewicz #define M66592_SOFR 0x2000 /* b13: SOF frame update interrupt */ 20190fccb52SAndrzej Pietrasiewicz #define M66592_DVST 0x1000 /* b12: Device state transition */ 20290fccb52SAndrzej Pietrasiewicz #define M66592_CTRT 0x0800 /* b11: Control stage transition */ 20390fccb52SAndrzej Pietrasiewicz #define M66592_BEMP 0x0400 /* b10: Buffer empty interrupt */ 20490fccb52SAndrzej Pietrasiewicz #define M66592_NRDY 0x0200 /* b9: Buffer not ready interrupt */ 20590fccb52SAndrzej Pietrasiewicz #define M66592_BRDY 0x0100 /* b8: Buffer ready interrupt */ 20690fccb52SAndrzej Pietrasiewicz #define M66592_VBSTS 0x0080 /* b7: VBUS input port */ 20790fccb52SAndrzej Pietrasiewicz #define M66592_DVSQ 0x0070 /* b6-4: Device state */ 20890fccb52SAndrzej Pietrasiewicz #define M66592_DS_SPD_CNFG 0x0070 /* Suspend Configured */ 20990fccb52SAndrzej Pietrasiewicz #define M66592_DS_SPD_ADDR 0x0060 /* Suspend Address */ 21090fccb52SAndrzej Pietrasiewicz #define M66592_DS_SPD_DFLT 0x0050 /* Suspend Default */ 21190fccb52SAndrzej Pietrasiewicz #define M66592_DS_SPD_POWR 0x0040 /* Suspend Powered */ 21290fccb52SAndrzej Pietrasiewicz #define M66592_DS_SUSP 0x0040 /* Suspend */ 21390fccb52SAndrzej Pietrasiewicz #define M66592_DS_CNFG 0x0030 /* Configured */ 21490fccb52SAndrzej Pietrasiewicz #define M66592_DS_ADDS 0x0020 /* Address */ 21590fccb52SAndrzej Pietrasiewicz #define M66592_DS_DFLT 0x0010 /* Default */ 21690fccb52SAndrzej Pietrasiewicz #define M66592_DS_POWR 0x0000 /* Powered */ 21790fccb52SAndrzej Pietrasiewicz #define M66592_DVSQS 0x0030 /* b5-4: Device state */ 21890fccb52SAndrzej Pietrasiewicz #define M66592_VALID 0x0008 /* b3: Setup packet detected flag */ 21990fccb52SAndrzej Pietrasiewicz #define M66592_CTSQ 0x0007 /* b2-0: Control transfer stage */ 22090fccb52SAndrzej Pietrasiewicz #define M66592_CS_SQER 0x0006 /* Sequence error */ 22190fccb52SAndrzej Pietrasiewicz #define M66592_CS_WRND 0x0005 /* Control write nodata status */ 22290fccb52SAndrzej Pietrasiewicz #define M66592_CS_WRSS 0x0004 /* Control write status stage */ 22390fccb52SAndrzej Pietrasiewicz #define M66592_CS_WRDS 0x0003 /* Control write data stage */ 22490fccb52SAndrzej Pietrasiewicz #define M66592_CS_RDSS 0x0002 /* Control read status stage */ 22590fccb52SAndrzej Pietrasiewicz #define M66592_CS_RDDS 0x0001 /* Control read data stage */ 22690fccb52SAndrzej Pietrasiewicz #define M66592_CS_IDST 0x0000 /* Idle or setup stage */ 22790fccb52SAndrzej Pietrasiewicz 22890fccb52SAndrzej Pietrasiewicz #define M66592_INTSTS1 0x42 22990fccb52SAndrzej Pietrasiewicz #define M66592_BCHG 0x4000 /* b14: USB bus chenge interrupt */ 23090fccb52SAndrzej Pietrasiewicz #define M66592_DTCH 0x1000 /* b12: Detach sense interrupt */ 23190fccb52SAndrzej Pietrasiewicz #define M66592_SIGN 0x0020 /* b5: SETUP IGNORE interrupt */ 23290fccb52SAndrzej Pietrasiewicz #define M66592_SACK 0x0010 /* b4: SETUP ACK interrupt */ 23390fccb52SAndrzej Pietrasiewicz 23490fccb52SAndrzej Pietrasiewicz #define M66592_FRMNUM 0x4C 23590fccb52SAndrzej Pietrasiewicz #define M66592_OVRN 0x8000 /* b15: Overrun error */ 23690fccb52SAndrzej Pietrasiewicz #define M66592_CRCE 0x4000 /* b14: Received data error */ 23790fccb52SAndrzej Pietrasiewicz #define M66592_SOFRM 0x0800 /* b11: SOF output mode */ 23890fccb52SAndrzej Pietrasiewicz #define M66592_FRNM 0x07FF /* b10-0: Frame number */ 23990fccb52SAndrzej Pietrasiewicz 24090fccb52SAndrzej Pietrasiewicz #define M66592_UFRMNUM 0x4E 24190fccb52SAndrzej Pietrasiewicz #define M66592_UFRNM 0x0007 /* b2-0: Micro frame number */ 24290fccb52SAndrzej Pietrasiewicz 24390fccb52SAndrzej Pietrasiewicz #define M66592_RECOVER 0x50 24490fccb52SAndrzej Pietrasiewicz #define M66592_STSRECOV 0x0700 /* Status recovery */ 24590fccb52SAndrzej Pietrasiewicz #define M66592_STSR_HI 0x0400 /* FULL(0) or HI(1) Speed */ 24690fccb52SAndrzej Pietrasiewicz #define M66592_STSR_DEFAULT 0x0100 /* Default state */ 24790fccb52SAndrzej Pietrasiewicz #define M66592_STSR_ADDRESS 0x0200 /* Address state */ 24890fccb52SAndrzej Pietrasiewicz #define M66592_STSR_CONFIG 0x0300 /* Configured state */ 24990fccb52SAndrzej Pietrasiewicz #define M66592_USBADDR 0x007F /* b6-0: USB address */ 25090fccb52SAndrzej Pietrasiewicz 25190fccb52SAndrzej Pietrasiewicz #define M66592_USBREQ 0x54 25290fccb52SAndrzej Pietrasiewicz #define M66592_bRequest 0xFF00 /* b15-8: bRequest */ 25390fccb52SAndrzej Pietrasiewicz #define M66592_GET_STATUS 0x0000 25490fccb52SAndrzej Pietrasiewicz #define M66592_CLEAR_FEATURE 0x0100 25590fccb52SAndrzej Pietrasiewicz #define M66592_ReqRESERVED 0x0200 25690fccb52SAndrzej Pietrasiewicz #define M66592_SET_FEATURE 0x0300 25790fccb52SAndrzej Pietrasiewicz #define M66592_ReqRESERVED1 0x0400 25890fccb52SAndrzej Pietrasiewicz #define M66592_SET_ADDRESS 0x0500 25990fccb52SAndrzej Pietrasiewicz #define M66592_GET_DESCRIPTOR 0x0600 26090fccb52SAndrzej Pietrasiewicz #define M66592_SET_DESCRIPTOR 0x0700 26190fccb52SAndrzej Pietrasiewicz #define M66592_GET_CONFIGURATION 0x0800 26290fccb52SAndrzej Pietrasiewicz #define M66592_SET_CONFIGURATION 0x0900 26390fccb52SAndrzej Pietrasiewicz #define M66592_GET_INTERFACE 0x0A00 26490fccb52SAndrzej Pietrasiewicz #define M66592_SET_INTERFACE 0x0B00 26590fccb52SAndrzej Pietrasiewicz #define M66592_SYNCH_FRAME 0x0C00 26690fccb52SAndrzej Pietrasiewicz #define M66592_bmRequestType 0x00FF /* b7-0: bmRequestType */ 26790fccb52SAndrzej Pietrasiewicz #define M66592_bmRequestTypeDir 0x0080 /* b7 : Data direction */ 26890fccb52SAndrzej Pietrasiewicz #define M66592_HOST_TO_DEVICE 0x0000 26990fccb52SAndrzej Pietrasiewicz #define M66592_DEVICE_TO_HOST 0x0080 27090fccb52SAndrzej Pietrasiewicz #define M66592_bmRequestTypeType 0x0060 /* b6-5: Type */ 27190fccb52SAndrzej Pietrasiewicz #define M66592_STANDARD 0x0000 27290fccb52SAndrzej Pietrasiewicz #define M66592_CLASS 0x0020 27390fccb52SAndrzej Pietrasiewicz #define M66592_VENDOR 0x0040 27490fccb52SAndrzej Pietrasiewicz #define M66592_bmRequestTypeRecip 0x001F /* b4-0: Recipient */ 27590fccb52SAndrzej Pietrasiewicz #define M66592_DEVICE 0x0000 27690fccb52SAndrzej Pietrasiewicz #define M66592_INTERFACE 0x0001 27790fccb52SAndrzej Pietrasiewicz #define M66592_ENDPOINT 0x0002 27890fccb52SAndrzej Pietrasiewicz 27990fccb52SAndrzej Pietrasiewicz #define M66592_USBVAL 0x56 28090fccb52SAndrzej Pietrasiewicz #define M66592_wValue 0xFFFF /* b15-0: wValue */ 28190fccb52SAndrzej Pietrasiewicz /* Standard Feature Selector */ 28290fccb52SAndrzej Pietrasiewicz #define M66592_ENDPOINT_HALT 0x0000 28390fccb52SAndrzej Pietrasiewicz #define M66592_DEVICE_REMOTE_WAKEUP 0x0001 28490fccb52SAndrzej Pietrasiewicz #define M66592_TEST_MODE 0x0002 28590fccb52SAndrzej Pietrasiewicz /* Descriptor Types */ 28690fccb52SAndrzej Pietrasiewicz #define M66592_DT_TYPE 0xFF00 28790fccb52SAndrzej Pietrasiewicz #define M66592_GET_DT_TYPE(v) (((v) & DT_TYPE) >> 8) 28890fccb52SAndrzej Pietrasiewicz #define M66592_DT_DEVICE 0x01 28990fccb52SAndrzej Pietrasiewicz #define M66592_DT_CONFIGURATION 0x02 29090fccb52SAndrzej Pietrasiewicz #define M66592_DT_STRING 0x03 29190fccb52SAndrzej Pietrasiewicz #define M66592_DT_INTERFACE 0x04 29290fccb52SAndrzej Pietrasiewicz #define M66592_DT_ENDPOINT 0x05 29390fccb52SAndrzej Pietrasiewicz #define M66592_DT_DEVICE_QUALIFIER 0x06 29490fccb52SAndrzej Pietrasiewicz #define M66592_DT_OTHER_SPEED_CONFIGURATION 0x07 29590fccb52SAndrzej Pietrasiewicz #define M66592_DT_INTERFACE_POWER 0x08 29690fccb52SAndrzej Pietrasiewicz #define M66592_DT_INDEX 0x00FF 29790fccb52SAndrzej Pietrasiewicz #define M66592_CONF_NUM 0x00FF 29890fccb52SAndrzej Pietrasiewicz #define M66592_ALT_SET 0x00FF 29990fccb52SAndrzej Pietrasiewicz 30090fccb52SAndrzej Pietrasiewicz #define M66592_USBINDEX 0x58 30190fccb52SAndrzej Pietrasiewicz #define M66592_wIndex 0xFFFF /* b15-0: wIndex */ 30290fccb52SAndrzej Pietrasiewicz #define M66592_TEST_SELECT 0xFF00 /* b15-b8: Test Mode */ 30390fccb52SAndrzej Pietrasiewicz #define M66592_TEST_J 0x0100 /* Test_J */ 30490fccb52SAndrzej Pietrasiewicz #define M66592_TEST_K 0x0200 /* Test_K */ 30590fccb52SAndrzej Pietrasiewicz #define M66592_TEST_SE0_NAK 0x0300 /* Test_SE0_NAK */ 30690fccb52SAndrzej Pietrasiewicz #define M66592_TEST_PACKET 0x0400 /* Test_Packet */ 30790fccb52SAndrzej Pietrasiewicz #define M66592_TEST_FORCE_ENABLE 0x0500 /* Test_Force_Enable */ 30890fccb52SAndrzej Pietrasiewicz #define M66592_TEST_STSelectors 0x0600 /* Standard test selectors */ 30990fccb52SAndrzej Pietrasiewicz #define M66592_TEST_Reserved 0x4000 /* Reserved */ 31090fccb52SAndrzej Pietrasiewicz #define M66592_TEST_VSTModes 0xC000 /* Vendor-specific tests */ 31190fccb52SAndrzej Pietrasiewicz #define M66592_EP_DIR 0x0080 /* b7: Endpoint Direction */ 31290fccb52SAndrzej Pietrasiewicz #define M66592_EP_DIR_IN 0x0080 31390fccb52SAndrzej Pietrasiewicz #define M66592_EP_DIR_OUT 0x0000 31490fccb52SAndrzej Pietrasiewicz 31590fccb52SAndrzej Pietrasiewicz #define M66592_USBLENG 0x5A 31690fccb52SAndrzej Pietrasiewicz #define M66592_wLength 0xFFFF /* b15-0: wLength */ 31790fccb52SAndrzej Pietrasiewicz 31890fccb52SAndrzej Pietrasiewicz #define M66592_DCPCFG 0x5C 31990fccb52SAndrzej Pietrasiewicz #define M66592_CNTMD 0x0100 /* b8: Continuous transfer mode */ 32090fccb52SAndrzej Pietrasiewicz #define M66592_DIR 0x0010 /* b4: Control transfer DIR select */ 32190fccb52SAndrzej Pietrasiewicz 32290fccb52SAndrzej Pietrasiewicz #define M66592_DCPMAXP 0x5E 32390fccb52SAndrzej Pietrasiewicz #define M66592_DEVSEL 0xC000 /* b15-14: Device address select */ 32490fccb52SAndrzej Pietrasiewicz #define M66592_DEVICE_0 0x0000 /* Device address 0 */ 32590fccb52SAndrzej Pietrasiewicz #define M66592_DEVICE_1 0x4000 /* Device address 1 */ 32690fccb52SAndrzej Pietrasiewicz #define M66592_DEVICE_2 0x8000 /* Device address 2 */ 32790fccb52SAndrzej Pietrasiewicz #define M66592_DEVICE_3 0xC000 /* Device address 3 */ 32890fccb52SAndrzej Pietrasiewicz #define M66592_MAXP 0x007F /* b6-0: Maxpacket size of ep0 */ 32990fccb52SAndrzej Pietrasiewicz 33090fccb52SAndrzej Pietrasiewicz #define M66592_DCPCTR 0x60 33190fccb52SAndrzej Pietrasiewicz #define M66592_BSTS 0x8000 /* b15: Buffer status */ 33290fccb52SAndrzej Pietrasiewicz #define M66592_SUREQ 0x4000 /* b14: Send USB request */ 33390fccb52SAndrzej Pietrasiewicz #define M66592_SQCLR 0x0100 /* b8: Sequence toggle bit clear */ 33490fccb52SAndrzej Pietrasiewicz #define M66592_SQSET 0x0080 /* b7: Sequence toggle bit set */ 33590fccb52SAndrzej Pietrasiewicz #define M66592_SQMON 0x0040 /* b6: Sequence toggle bit monitor */ 33690fccb52SAndrzej Pietrasiewicz #define M66592_CCPL 0x0004 /* b2: control transfer complete */ 33790fccb52SAndrzej Pietrasiewicz #define M66592_PID 0x0003 /* b1-0: Response PID */ 33890fccb52SAndrzej Pietrasiewicz #define M66592_PID_STALL 0x0002 /* STALL */ 33990fccb52SAndrzej Pietrasiewicz #define M66592_PID_BUF 0x0001 /* BUF */ 34090fccb52SAndrzej Pietrasiewicz #define M66592_PID_NAK 0x0000 /* NAK */ 34190fccb52SAndrzej Pietrasiewicz 34290fccb52SAndrzej Pietrasiewicz #define M66592_PIPESEL 0x64 34390fccb52SAndrzej Pietrasiewicz #define M66592_PIPENM 0x0007 /* b2-0: Pipe select */ 34490fccb52SAndrzej Pietrasiewicz #define M66592_PIPE0 0x0000 /* PIPE 0 */ 34590fccb52SAndrzej Pietrasiewicz #define M66592_PIPE1 0x0001 /* PIPE 1 */ 34690fccb52SAndrzej Pietrasiewicz #define M66592_PIPE2 0x0002 /* PIPE 2 */ 34790fccb52SAndrzej Pietrasiewicz #define M66592_PIPE3 0x0003 /* PIPE 3 */ 34890fccb52SAndrzej Pietrasiewicz #define M66592_PIPE4 0x0004 /* PIPE 4 */ 34990fccb52SAndrzej Pietrasiewicz #define M66592_PIPE5 0x0005 /* PIPE 5 */ 35090fccb52SAndrzej Pietrasiewicz #define M66592_PIPE6 0x0006 /* PIPE 6 */ 35190fccb52SAndrzej Pietrasiewicz #define M66592_PIPE7 0x0007 /* PIPE 7 */ 35290fccb52SAndrzej Pietrasiewicz 35390fccb52SAndrzej Pietrasiewicz #define M66592_PIPECFG 0x66 35490fccb52SAndrzej Pietrasiewicz #define M66592_TYP 0xC000 /* b15-14: Transfer type */ 35590fccb52SAndrzej Pietrasiewicz #define M66592_ISO 0xC000 /* Isochronous */ 35690fccb52SAndrzej Pietrasiewicz #define M66592_INT 0x8000 /* Interrupt */ 35790fccb52SAndrzej Pietrasiewicz #define M66592_BULK 0x4000 /* Bulk */ 35890fccb52SAndrzej Pietrasiewicz #define M66592_BFRE 0x0400 /* b10: Buffer ready interrupt mode */ 35990fccb52SAndrzej Pietrasiewicz #define M66592_DBLB 0x0200 /* b9: Double buffer mode select */ 36090fccb52SAndrzej Pietrasiewicz #define M66592_CNTMD 0x0100 /* b8: Continuous transfer mode */ 36190fccb52SAndrzej Pietrasiewicz #define M66592_SHTNAK 0x0080 /* b7: Transfer end NAK */ 36290fccb52SAndrzej Pietrasiewicz #define M66592_DIR 0x0010 /* b4: Transfer direction select */ 36390fccb52SAndrzej Pietrasiewicz #define M66592_DIR_H_OUT 0x0010 /* HOST OUT */ 36490fccb52SAndrzej Pietrasiewicz #define M66592_DIR_P_IN 0x0010 /* PERI IN */ 36590fccb52SAndrzej Pietrasiewicz #define M66592_DIR_H_IN 0x0000 /* HOST IN */ 36690fccb52SAndrzej Pietrasiewicz #define M66592_DIR_P_OUT 0x0000 /* PERI OUT */ 36790fccb52SAndrzej Pietrasiewicz #define M66592_EPNUM 0x000F /* b3-0: Eendpoint number select */ 36890fccb52SAndrzej Pietrasiewicz #define M66592_EP1 0x0001 36990fccb52SAndrzej Pietrasiewicz #define M66592_EP2 0x0002 37090fccb52SAndrzej Pietrasiewicz #define M66592_EP3 0x0003 37190fccb52SAndrzej Pietrasiewicz #define M66592_EP4 0x0004 37290fccb52SAndrzej Pietrasiewicz #define M66592_EP5 0x0005 37390fccb52SAndrzej Pietrasiewicz #define M66592_EP6 0x0006 37490fccb52SAndrzej Pietrasiewicz #define M66592_EP7 0x0007 37590fccb52SAndrzej Pietrasiewicz #define M66592_EP8 0x0008 37690fccb52SAndrzej Pietrasiewicz #define M66592_EP9 0x0009 37790fccb52SAndrzej Pietrasiewicz #define M66592_EP10 0x000A 37890fccb52SAndrzej Pietrasiewicz #define M66592_EP11 0x000B 37990fccb52SAndrzej Pietrasiewicz #define M66592_EP12 0x000C 38090fccb52SAndrzej Pietrasiewicz #define M66592_EP13 0x000D 38190fccb52SAndrzej Pietrasiewicz #define M66592_EP14 0x000E 38290fccb52SAndrzej Pietrasiewicz #define M66592_EP15 0x000F 38390fccb52SAndrzej Pietrasiewicz 38490fccb52SAndrzej Pietrasiewicz #define M66592_PIPEBUF 0x68 38590fccb52SAndrzej Pietrasiewicz #define M66592_BUFSIZE 0x7C00 /* b14-10: Pipe buffer size */ 38690fccb52SAndrzej Pietrasiewicz #define M66592_BUF_SIZE(x) ((((x) / 64) - 1) << 10) 38790fccb52SAndrzej Pietrasiewicz #define M66592_BUFNMB 0x00FF /* b7-0: Pipe buffer number */ 38890fccb52SAndrzej Pietrasiewicz 38990fccb52SAndrzej Pietrasiewicz #define M66592_PIPEMAXP 0x6A 39090fccb52SAndrzej Pietrasiewicz #define M66592_MXPS 0x07FF /* b10-0: Maxpacket size */ 39190fccb52SAndrzej Pietrasiewicz 39290fccb52SAndrzej Pietrasiewicz #define M66592_PIPEPERI 0x6C 39390fccb52SAndrzej Pietrasiewicz #define M66592_IFIS 0x1000 /* b12: ISO in-buffer flush mode */ 39490fccb52SAndrzej Pietrasiewicz #define M66592_IITV 0x0007 /* b2-0: ISO interval */ 39590fccb52SAndrzej Pietrasiewicz 39690fccb52SAndrzej Pietrasiewicz #define M66592_PIPE1CTR 0x70 39790fccb52SAndrzej Pietrasiewicz #define M66592_PIPE2CTR 0x72 39890fccb52SAndrzej Pietrasiewicz #define M66592_PIPE3CTR 0x74 39990fccb52SAndrzej Pietrasiewicz #define M66592_PIPE4CTR 0x76 40090fccb52SAndrzej Pietrasiewicz #define M66592_PIPE5CTR 0x78 40190fccb52SAndrzej Pietrasiewicz #define M66592_PIPE6CTR 0x7A 40290fccb52SAndrzej Pietrasiewicz #define M66592_PIPE7CTR 0x7C 40390fccb52SAndrzej Pietrasiewicz #define M66592_BSTS 0x8000 /* b15: Buffer status */ 40490fccb52SAndrzej Pietrasiewicz #define M66592_INBUFM 0x4000 /* b14: IN buffer monitor (PIPE 1-5) */ 40590fccb52SAndrzej Pietrasiewicz #define M66592_ACLRM 0x0200 /* b9: Out buffer auto clear mode */ 40690fccb52SAndrzej Pietrasiewicz #define M66592_SQCLR 0x0100 /* b8: Sequence toggle bit clear */ 40790fccb52SAndrzej Pietrasiewicz #define M66592_SQSET 0x0080 /* b7: Sequence toggle bit set */ 40890fccb52SAndrzej Pietrasiewicz #define M66592_SQMON 0x0040 /* b6: Sequence toggle bit monitor */ 40990fccb52SAndrzej Pietrasiewicz #define M66592_PID 0x0003 /* b1-0: Response PID */ 41090fccb52SAndrzej Pietrasiewicz 41190fccb52SAndrzej Pietrasiewicz #define M66592_INVALID_REG 0x7E 41290fccb52SAndrzej Pietrasiewicz 41390fccb52SAndrzej Pietrasiewicz 41490fccb52SAndrzej Pietrasiewicz #define get_pipectr_addr(pipenum) (M66592_PIPE1CTR + (pipenum - 1) * 2) 41590fccb52SAndrzej Pietrasiewicz 41690fccb52SAndrzej Pietrasiewicz #define M66592_MAX_SAMPLING 10 41790fccb52SAndrzej Pietrasiewicz 41890fccb52SAndrzej Pietrasiewicz #define M66592_MAX_NUM_PIPE 8 41990fccb52SAndrzej Pietrasiewicz #define M66592_MAX_NUM_BULK 3 42090fccb52SAndrzej Pietrasiewicz #define M66592_MAX_NUM_ISOC 2 42190fccb52SAndrzej Pietrasiewicz #define M66592_MAX_NUM_INT 2 42290fccb52SAndrzej Pietrasiewicz 42390fccb52SAndrzej Pietrasiewicz #define M66592_BASE_PIPENUM_BULK 3 42490fccb52SAndrzej Pietrasiewicz #define M66592_BASE_PIPENUM_ISOC 1 42590fccb52SAndrzej Pietrasiewicz #define M66592_BASE_PIPENUM_INT 6 42690fccb52SAndrzej Pietrasiewicz 42790fccb52SAndrzej Pietrasiewicz #define M66592_BASE_BUFNUM 6 42890fccb52SAndrzej Pietrasiewicz #define M66592_MAX_BUFNUM 0x4F 42990fccb52SAndrzej Pietrasiewicz 43090fccb52SAndrzej Pietrasiewicz struct m66592_pipe_info { 43190fccb52SAndrzej Pietrasiewicz u16 pipe; 43290fccb52SAndrzej Pietrasiewicz u16 epnum; 43390fccb52SAndrzej Pietrasiewicz u16 maxpacket; 43490fccb52SAndrzej Pietrasiewicz u16 type; 43590fccb52SAndrzej Pietrasiewicz u16 interval; 43690fccb52SAndrzej Pietrasiewicz u16 dir_in; 43790fccb52SAndrzej Pietrasiewicz }; 43890fccb52SAndrzej Pietrasiewicz 43990fccb52SAndrzej Pietrasiewicz struct m66592_request { 44090fccb52SAndrzej Pietrasiewicz struct usb_request req; 44190fccb52SAndrzej Pietrasiewicz struct list_head queue; 44290fccb52SAndrzej Pietrasiewicz }; 44390fccb52SAndrzej Pietrasiewicz 44490fccb52SAndrzej Pietrasiewicz struct m66592_ep { 44590fccb52SAndrzej Pietrasiewicz struct usb_ep ep; 44690fccb52SAndrzej Pietrasiewicz struct m66592 *m66592; 44790fccb52SAndrzej Pietrasiewicz 44890fccb52SAndrzej Pietrasiewicz struct list_head queue; 44990fccb52SAndrzej Pietrasiewicz unsigned busy:1; 45090fccb52SAndrzej Pietrasiewicz unsigned internal_ccpl:1; /* use only control */ 45190fccb52SAndrzej Pietrasiewicz 45290fccb52SAndrzej Pietrasiewicz /* this member can able to after m66592_enable */ 45390fccb52SAndrzej Pietrasiewicz unsigned use_dma:1; 45490fccb52SAndrzej Pietrasiewicz u16 pipenum; 45590fccb52SAndrzej Pietrasiewicz u16 type; 45690fccb52SAndrzej Pietrasiewicz 45790fccb52SAndrzej Pietrasiewicz /* register address */ 45890fccb52SAndrzej Pietrasiewicz unsigned long fifoaddr; 45990fccb52SAndrzej Pietrasiewicz unsigned long fifosel; 46090fccb52SAndrzej Pietrasiewicz unsigned long fifoctr; 46190fccb52SAndrzej Pietrasiewicz unsigned long fifotrn; 46290fccb52SAndrzej Pietrasiewicz unsigned long pipectr; 46390fccb52SAndrzej Pietrasiewicz }; 46490fccb52SAndrzej Pietrasiewicz 46590fccb52SAndrzej Pietrasiewicz struct m66592 { 46690fccb52SAndrzej Pietrasiewicz spinlock_t lock; 46790fccb52SAndrzej Pietrasiewicz void __iomem *reg; 46890fccb52SAndrzej Pietrasiewicz struct clk *clk; 46990fccb52SAndrzej Pietrasiewicz struct m66592_platdata *pdata; 47090fccb52SAndrzej Pietrasiewicz unsigned long irq_trigger; 47190fccb52SAndrzej Pietrasiewicz 47290fccb52SAndrzej Pietrasiewicz struct usb_gadget gadget; 47390fccb52SAndrzej Pietrasiewicz struct usb_gadget_driver *driver; 47490fccb52SAndrzej Pietrasiewicz 47590fccb52SAndrzej Pietrasiewicz struct m66592_ep ep[M66592_MAX_NUM_PIPE]; 47690fccb52SAndrzej Pietrasiewicz struct m66592_ep *pipenum2ep[M66592_MAX_NUM_PIPE]; 47790fccb52SAndrzej Pietrasiewicz struct m66592_ep *epaddr2ep[16]; 47890fccb52SAndrzej Pietrasiewicz 47990fccb52SAndrzej Pietrasiewicz struct usb_request *ep0_req; /* for internal request */ 48090fccb52SAndrzej Pietrasiewicz __le16 ep0_data; /* for internal request */ 48190fccb52SAndrzej Pietrasiewicz u16 old_vbus; 48290fccb52SAndrzej Pietrasiewicz 48390fccb52SAndrzej Pietrasiewicz struct timer_list timer; 48490fccb52SAndrzej Pietrasiewicz 48590fccb52SAndrzej Pietrasiewicz int scount; 48690fccb52SAndrzej Pietrasiewicz 48790fccb52SAndrzej Pietrasiewicz int old_dvsq; 48890fccb52SAndrzej Pietrasiewicz 48990fccb52SAndrzej Pietrasiewicz /* pipe config */ 49090fccb52SAndrzej Pietrasiewicz int bulk; 49190fccb52SAndrzej Pietrasiewicz int interrupt; 49290fccb52SAndrzej Pietrasiewicz int isochronous; 49390fccb52SAndrzej Pietrasiewicz int num_dma; 49490fccb52SAndrzej Pietrasiewicz }; 49590fccb52SAndrzej Pietrasiewicz #define to_m66592(g) (container_of((g), struct m66592, gadget)) 49690fccb52SAndrzej Pietrasiewicz 49790fccb52SAndrzej Pietrasiewicz #define gadget_to_m66592(_gadget) container_of(_gadget, struct m66592, gadget) 49890fccb52SAndrzej Pietrasiewicz #define m66592_to_gadget(m66592) (&m66592->gadget) 49990fccb52SAndrzej Pietrasiewicz 50090fccb52SAndrzej Pietrasiewicz #define is_bulk_pipe(pipenum) \ 50190fccb52SAndrzej Pietrasiewicz ((pipenum >= M66592_BASE_PIPENUM_BULK) && \ 50290fccb52SAndrzej Pietrasiewicz (pipenum < (M66592_BASE_PIPENUM_BULK + M66592_MAX_NUM_BULK))) 50390fccb52SAndrzej Pietrasiewicz #define is_interrupt_pipe(pipenum) \ 50490fccb52SAndrzej Pietrasiewicz ((pipenum >= M66592_BASE_PIPENUM_INT) && \ 50590fccb52SAndrzej Pietrasiewicz (pipenum < (M66592_BASE_PIPENUM_INT + M66592_MAX_NUM_INT))) 50690fccb52SAndrzej Pietrasiewicz #define is_isoc_pipe(pipenum) \ 50790fccb52SAndrzej Pietrasiewicz ((pipenum >= M66592_BASE_PIPENUM_ISOC) && \ 50890fccb52SAndrzej Pietrasiewicz (pipenum < (M66592_BASE_PIPENUM_ISOC + M66592_MAX_NUM_ISOC))) 50990fccb52SAndrzej Pietrasiewicz 51090fccb52SAndrzej Pietrasiewicz #define enable_irq_ready(m66592, pipenum) \ 51190fccb52SAndrzej Pietrasiewicz enable_pipe_irq(m66592, pipenum, M66592_BRDYENB) 51290fccb52SAndrzej Pietrasiewicz #define disable_irq_ready(m66592, pipenum) \ 51390fccb52SAndrzej Pietrasiewicz disable_pipe_irq(m66592, pipenum, M66592_BRDYENB) 51490fccb52SAndrzej Pietrasiewicz #define enable_irq_empty(m66592, pipenum) \ 51590fccb52SAndrzej Pietrasiewicz enable_pipe_irq(m66592, pipenum, M66592_BEMPENB) 51690fccb52SAndrzej Pietrasiewicz #define disable_irq_empty(m66592, pipenum) \ 51790fccb52SAndrzej Pietrasiewicz disable_pipe_irq(m66592, pipenum, M66592_BEMPENB) 51890fccb52SAndrzej Pietrasiewicz #define enable_irq_nrdy(m66592, pipenum) \ 51990fccb52SAndrzej Pietrasiewicz enable_pipe_irq(m66592, pipenum, M66592_NRDYENB) 52090fccb52SAndrzej Pietrasiewicz #define disable_irq_nrdy(m66592, pipenum) \ 52190fccb52SAndrzej Pietrasiewicz disable_pipe_irq(m66592, pipenum, M66592_NRDYENB) 52290fccb52SAndrzej Pietrasiewicz 52390fccb52SAndrzej Pietrasiewicz /*-------------------------------------------------------------------------*/ 52490fccb52SAndrzej Pietrasiewicz static inline u16 m66592_read(struct m66592 *m66592, unsigned long offset) 52590fccb52SAndrzej Pietrasiewicz { 52690fccb52SAndrzej Pietrasiewicz return ioread16(m66592->reg + offset); 52790fccb52SAndrzej Pietrasiewicz } 52890fccb52SAndrzej Pietrasiewicz 52990fccb52SAndrzej Pietrasiewicz static inline void m66592_read_fifo(struct m66592 *m66592, 53090fccb52SAndrzej Pietrasiewicz unsigned long offset, 53190fccb52SAndrzej Pietrasiewicz void *buf, unsigned long len) 53290fccb52SAndrzej Pietrasiewicz { 53390fccb52SAndrzej Pietrasiewicz void __iomem *fifoaddr = m66592->reg + offset; 53490fccb52SAndrzej Pietrasiewicz 53590fccb52SAndrzej Pietrasiewicz if (m66592->pdata->on_chip) { 53690fccb52SAndrzej Pietrasiewicz len = (len + 3) / 4; 53790fccb52SAndrzej Pietrasiewicz ioread32_rep(fifoaddr, buf, len); 53890fccb52SAndrzej Pietrasiewicz } else { 53990fccb52SAndrzej Pietrasiewicz len = (len + 1) / 2; 54090fccb52SAndrzej Pietrasiewicz ioread16_rep(fifoaddr, buf, len); 54190fccb52SAndrzej Pietrasiewicz } 54290fccb52SAndrzej Pietrasiewicz } 54390fccb52SAndrzej Pietrasiewicz 54490fccb52SAndrzej Pietrasiewicz static inline void m66592_write(struct m66592 *m66592, u16 val, 54590fccb52SAndrzej Pietrasiewicz unsigned long offset) 54690fccb52SAndrzej Pietrasiewicz { 54790fccb52SAndrzej Pietrasiewicz iowrite16(val, m66592->reg + offset); 54890fccb52SAndrzej Pietrasiewicz } 54990fccb52SAndrzej Pietrasiewicz 55090fccb52SAndrzej Pietrasiewicz static inline void m66592_mdfy(struct m66592 *m66592, u16 val, u16 pat, 55190fccb52SAndrzej Pietrasiewicz unsigned long offset) 55290fccb52SAndrzej Pietrasiewicz { 55390fccb52SAndrzej Pietrasiewicz u16 tmp; 55490fccb52SAndrzej Pietrasiewicz tmp = m66592_read(m66592, offset); 55590fccb52SAndrzej Pietrasiewicz tmp = tmp & (~pat); 55690fccb52SAndrzej Pietrasiewicz tmp = tmp | val; 55790fccb52SAndrzej Pietrasiewicz m66592_write(m66592, tmp, offset); 55890fccb52SAndrzej Pietrasiewicz } 55990fccb52SAndrzej Pietrasiewicz 56090fccb52SAndrzej Pietrasiewicz #define m66592_bclr(m66592, val, offset) \ 56190fccb52SAndrzej Pietrasiewicz m66592_mdfy(m66592, 0, val, offset) 56290fccb52SAndrzej Pietrasiewicz #define m66592_bset(m66592, val, offset) \ 56390fccb52SAndrzej Pietrasiewicz m66592_mdfy(m66592, val, 0, offset) 56490fccb52SAndrzej Pietrasiewicz 56590fccb52SAndrzej Pietrasiewicz static inline void m66592_write_fifo(struct m66592 *m66592, 56690fccb52SAndrzej Pietrasiewicz struct m66592_ep *ep, 56790fccb52SAndrzej Pietrasiewicz void *buf, unsigned long len) 56890fccb52SAndrzej Pietrasiewicz { 56990fccb52SAndrzej Pietrasiewicz void __iomem *fifoaddr = m66592->reg + ep->fifoaddr; 57090fccb52SAndrzej Pietrasiewicz 57190fccb52SAndrzej Pietrasiewicz if (m66592->pdata->on_chip) { 57290fccb52SAndrzej Pietrasiewicz unsigned long count; 57390fccb52SAndrzej Pietrasiewicz unsigned char *pb; 57490fccb52SAndrzej Pietrasiewicz int i; 57590fccb52SAndrzej Pietrasiewicz 57690fccb52SAndrzej Pietrasiewicz count = len / 4; 57790fccb52SAndrzej Pietrasiewicz iowrite32_rep(fifoaddr, buf, count); 57890fccb52SAndrzej Pietrasiewicz 57990fccb52SAndrzej Pietrasiewicz if (len & 0x00000003) { 58090fccb52SAndrzej Pietrasiewicz pb = buf + count * 4; 58190fccb52SAndrzej Pietrasiewicz for (i = 0; i < (len & 0x00000003); i++) { 58290fccb52SAndrzej Pietrasiewicz if (m66592_read(m66592, M66592_CFBCFG)) /* le */ 58390fccb52SAndrzej Pietrasiewicz iowrite8(pb[i], fifoaddr + (3 - i)); 58490fccb52SAndrzej Pietrasiewicz else 58590fccb52SAndrzej Pietrasiewicz iowrite8(pb[i], fifoaddr + i); 58690fccb52SAndrzej Pietrasiewicz } 58790fccb52SAndrzej Pietrasiewicz } 58890fccb52SAndrzej Pietrasiewicz } else { 58990fccb52SAndrzej Pietrasiewicz unsigned long odd = len & 0x0001; 59090fccb52SAndrzej Pietrasiewicz 59190fccb52SAndrzej Pietrasiewicz len = len / 2; 59290fccb52SAndrzej Pietrasiewicz iowrite16_rep(fifoaddr, buf, len); 59390fccb52SAndrzej Pietrasiewicz if (odd) { 59490fccb52SAndrzej Pietrasiewicz unsigned char *p = buf + len*2; 59590fccb52SAndrzej Pietrasiewicz if (m66592->pdata->wr0_shorted_to_wr1) 59690fccb52SAndrzej Pietrasiewicz m66592_bclr(m66592, M66592_MBW_16, ep->fifosel); 59790fccb52SAndrzej Pietrasiewicz iowrite8(*p, fifoaddr); 59890fccb52SAndrzej Pietrasiewicz if (m66592->pdata->wr0_shorted_to_wr1) 59990fccb52SAndrzej Pietrasiewicz m66592_bset(m66592, M66592_MBW_16, ep->fifosel); 60090fccb52SAndrzej Pietrasiewicz } 60190fccb52SAndrzej Pietrasiewicz } 60290fccb52SAndrzej Pietrasiewicz } 60390fccb52SAndrzej Pietrasiewicz 60490fccb52SAndrzej Pietrasiewicz #endif /* ifndef __M66592_UDC_H__ */ 60590fccb52SAndrzej Pietrasiewicz 60690fccb52SAndrzej Pietrasiewicz 607