1 /*
2  * M66592 UDC (USB gadget)
3  *
4  * Copyright (C) 2006-2007 Renesas Solutions Corp.
5  *
6  * Author : Yoshihiro Shimoda <yoshihiro.shimoda.uh@renesas.com>
7  *
8  * This program is free software; you can redistribute it and/or modify
9  * it under the terms of the GNU General Public License as published by
10  * the Free Software Foundation; version 2 of the License.
11  */
12 
13 #include <linux/module.h>
14 #include <linux/interrupt.h>
15 #include <linux/delay.h>
16 #include <linux/io.h>
17 #include <linux/platform_device.h>
18 #include <linux/slab.h>
19 #include <linux/err.h>
20 #include <linux/usb/ch9.h>
21 #include <linux/usb/gadget.h>
22 
23 #include "m66592-udc.h"
24 
25 MODULE_DESCRIPTION("M66592 USB gadget driver");
26 MODULE_LICENSE("GPL");
27 MODULE_AUTHOR("Yoshihiro Shimoda");
28 MODULE_ALIAS("platform:m66592_udc");
29 
30 #define DRIVER_VERSION	"21 July 2009"
31 
32 static const char udc_name[] = "m66592_udc";
33 static const char *m66592_ep_name[] = {
34 	"ep0", "ep1", "ep2", "ep3", "ep4", "ep5", "ep6", "ep7"
35 };
36 
37 static void disable_controller(struct m66592 *m66592);
38 static void irq_ep0_write(struct m66592_ep *ep, struct m66592_request *req);
39 static void irq_packet_write(struct m66592_ep *ep, struct m66592_request *req);
40 static int m66592_queue(struct usb_ep *_ep, struct usb_request *_req,
41 			gfp_t gfp_flags);
42 
43 static void transfer_complete(struct m66592_ep *ep,
44 		struct m66592_request *req, int status);
45 
46 /*-------------------------------------------------------------------------*/
47 static inline u16 get_usb_speed(struct m66592 *m66592)
48 {
49 	return (m66592_read(m66592, M66592_DVSTCTR) & M66592_RHST);
50 }
51 
52 static void enable_pipe_irq(struct m66592 *m66592, u16 pipenum,
53 		unsigned long reg)
54 {
55 	u16 tmp;
56 
57 	tmp = m66592_read(m66592, M66592_INTENB0);
58 	m66592_bclr(m66592, M66592_BEMPE | M66592_NRDYE | M66592_BRDYE,
59 			M66592_INTENB0);
60 	m66592_bset(m66592, (1 << pipenum), reg);
61 	m66592_write(m66592, tmp, M66592_INTENB0);
62 }
63 
64 static void disable_pipe_irq(struct m66592 *m66592, u16 pipenum,
65 		unsigned long reg)
66 {
67 	u16 tmp;
68 
69 	tmp = m66592_read(m66592, M66592_INTENB0);
70 	m66592_bclr(m66592, M66592_BEMPE | M66592_NRDYE | M66592_BRDYE,
71 			M66592_INTENB0);
72 	m66592_bclr(m66592, (1 << pipenum), reg);
73 	m66592_write(m66592, tmp, M66592_INTENB0);
74 }
75 
76 static void m66592_usb_connect(struct m66592 *m66592)
77 {
78 	m66592_bset(m66592, M66592_CTRE, M66592_INTENB0);
79 	m66592_bset(m66592, M66592_WDST | M66592_RDST | M66592_CMPL,
80 			M66592_INTENB0);
81 	m66592_bset(m66592, M66592_BEMPE | M66592_BRDYE, M66592_INTENB0);
82 
83 	m66592_bset(m66592, M66592_DPRPU, M66592_SYSCFG);
84 }
85 
86 static void m66592_usb_disconnect(struct m66592 *m66592)
87 __releases(m66592->lock)
88 __acquires(m66592->lock)
89 {
90 	m66592_bclr(m66592, M66592_CTRE, M66592_INTENB0);
91 	m66592_bclr(m66592, M66592_WDST | M66592_RDST | M66592_CMPL,
92 			M66592_INTENB0);
93 	m66592_bclr(m66592, M66592_BEMPE | M66592_BRDYE, M66592_INTENB0);
94 	m66592_bclr(m66592, M66592_DPRPU, M66592_SYSCFG);
95 
96 	m66592->gadget.speed = USB_SPEED_UNKNOWN;
97 	spin_unlock(&m66592->lock);
98 	m66592->driver->disconnect(&m66592->gadget);
99 	spin_lock(&m66592->lock);
100 
101 	disable_controller(m66592);
102 	INIT_LIST_HEAD(&m66592->ep[0].queue);
103 }
104 
105 static inline u16 control_reg_get_pid(struct m66592 *m66592, u16 pipenum)
106 {
107 	u16 pid = 0;
108 	unsigned long offset;
109 
110 	if (pipenum == 0)
111 		pid = m66592_read(m66592, M66592_DCPCTR) & M66592_PID;
112 	else if (pipenum < M66592_MAX_NUM_PIPE) {
113 		offset = get_pipectr_addr(pipenum);
114 		pid = m66592_read(m66592, offset) & M66592_PID;
115 	} else
116 		pr_err("unexpect pipe num (%d)\n", pipenum);
117 
118 	return pid;
119 }
120 
121 static inline void control_reg_set_pid(struct m66592 *m66592, u16 pipenum,
122 		u16 pid)
123 {
124 	unsigned long offset;
125 
126 	if (pipenum == 0)
127 		m66592_mdfy(m66592, pid, M66592_PID, M66592_DCPCTR);
128 	else if (pipenum < M66592_MAX_NUM_PIPE) {
129 		offset = get_pipectr_addr(pipenum);
130 		m66592_mdfy(m66592, pid, M66592_PID, offset);
131 	} else
132 		pr_err("unexpect pipe num (%d)\n", pipenum);
133 }
134 
135 static inline void pipe_start(struct m66592 *m66592, u16 pipenum)
136 {
137 	control_reg_set_pid(m66592, pipenum, M66592_PID_BUF);
138 }
139 
140 static inline void pipe_stop(struct m66592 *m66592, u16 pipenum)
141 {
142 	control_reg_set_pid(m66592, pipenum, M66592_PID_NAK);
143 }
144 
145 static inline void pipe_stall(struct m66592 *m66592, u16 pipenum)
146 {
147 	control_reg_set_pid(m66592, pipenum, M66592_PID_STALL);
148 }
149 
150 static inline u16 control_reg_get(struct m66592 *m66592, u16 pipenum)
151 {
152 	u16 ret = 0;
153 	unsigned long offset;
154 
155 	if (pipenum == 0)
156 		ret = m66592_read(m66592, M66592_DCPCTR);
157 	else if (pipenum < M66592_MAX_NUM_PIPE) {
158 		offset = get_pipectr_addr(pipenum);
159 		ret = m66592_read(m66592, offset);
160 	} else
161 		pr_err("unexpect pipe num (%d)\n", pipenum);
162 
163 	return ret;
164 }
165 
166 static inline void control_reg_sqclr(struct m66592 *m66592, u16 pipenum)
167 {
168 	unsigned long offset;
169 
170 	pipe_stop(m66592, pipenum);
171 
172 	if (pipenum == 0)
173 		m66592_bset(m66592, M66592_SQCLR, M66592_DCPCTR);
174 	else if (pipenum < M66592_MAX_NUM_PIPE) {
175 		offset = get_pipectr_addr(pipenum);
176 		m66592_bset(m66592, M66592_SQCLR, offset);
177 	} else
178 		pr_err("unexpect pipe num(%d)\n", pipenum);
179 }
180 
181 static inline int get_buffer_size(struct m66592 *m66592, u16 pipenum)
182 {
183 	u16 tmp;
184 	int size;
185 
186 	if (pipenum == 0) {
187 		tmp = m66592_read(m66592, M66592_DCPCFG);
188 		if ((tmp & M66592_CNTMD) != 0)
189 			size = 256;
190 		else {
191 			tmp = m66592_read(m66592, M66592_DCPMAXP);
192 			size = tmp & M66592_MAXP;
193 		}
194 	} else {
195 		m66592_write(m66592, pipenum, M66592_PIPESEL);
196 		tmp = m66592_read(m66592, M66592_PIPECFG);
197 		if ((tmp & M66592_CNTMD) != 0) {
198 			tmp = m66592_read(m66592, M66592_PIPEBUF);
199 			size = ((tmp >> 10) + 1) * 64;
200 		} else {
201 			tmp = m66592_read(m66592, M66592_PIPEMAXP);
202 			size = tmp & M66592_MXPS;
203 		}
204 	}
205 
206 	return size;
207 }
208 
209 static inline void pipe_change(struct m66592 *m66592, u16 pipenum)
210 {
211 	struct m66592_ep *ep = m66592->pipenum2ep[pipenum];
212 	unsigned short mbw;
213 
214 	if (ep->use_dma)
215 		return;
216 
217 	m66592_mdfy(m66592, pipenum, M66592_CURPIPE, ep->fifosel);
218 
219 	ndelay(450);
220 
221 	if (m66592->pdata->on_chip)
222 		mbw = M66592_MBW_32;
223 	else
224 		mbw = M66592_MBW_16;
225 
226 	m66592_bset(m66592, mbw, ep->fifosel);
227 }
228 
229 static int pipe_buffer_setting(struct m66592 *m66592,
230 		struct m66592_pipe_info *info)
231 {
232 	u16 bufnum = 0, buf_bsize = 0;
233 	u16 pipecfg = 0;
234 
235 	if (info->pipe == 0)
236 		return -EINVAL;
237 
238 	m66592_write(m66592, info->pipe, M66592_PIPESEL);
239 
240 	if (info->dir_in)
241 		pipecfg |= M66592_DIR;
242 	pipecfg |= info->type;
243 	pipecfg |= info->epnum;
244 	switch (info->type) {
245 	case M66592_INT:
246 		bufnum = 4 + (info->pipe - M66592_BASE_PIPENUM_INT);
247 		buf_bsize = 0;
248 		break;
249 	case M66592_BULK:
250 		/* isochronous pipes may be used as bulk pipes */
251 		if (info->pipe >= M66592_BASE_PIPENUM_BULK)
252 			bufnum = info->pipe - M66592_BASE_PIPENUM_BULK;
253 		else
254 			bufnum = info->pipe - M66592_BASE_PIPENUM_ISOC;
255 
256 		bufnum = M66592_BASE_BUFNUM + (bufnum * 16);
257 		buf_bsize = 7;
258 		pipecfg |= M66592_DBLB;
259 		if (!info->dir_in)
260 			pipecfg |= M66592_SHTNAK;
261 		break;
262 	case M66592_ISO:
263 		bufnum = M66592_BASE_BUFNUM +
264 			 (info->pipe - M66592_BASE_PIPENUM_ISOC) * 16;
265 		buf_bsize = 7;
266 		break;
267 	}
268 
269 	if (buf_bsize && ((bufnum + 16) >= M66592_MAX_BUFNUM)) {
270 		pr_err("m66592 pipe memory is insufficient\n");
271 		return -ENOMEM;
272 	}
273 
274 	m66592_write(m66592, pipecfg, M66592_PIPECFG);
275 	m66592_write(m66592, (buf_bsize << 10) | (bufnum), M66592_PIPEBUF);
276 	m66592_write(m66592, info->maxpacket, M66592_PIPEMAXP);
277 	if (info->interval)
278 		info->interval--;
279 	m66592_write(m66592, info->interval, M66592_PIPEPERI);
280 
281 	return 0;
282 }
283 
284 static void pipe_buffer_release(struct m66592 *m66592,
285 				struct m66592_pipe_info *info)
286 {
287 	if (info->pipe == 0)
288 		return;
289 
290 	if (is_bulk_pipe(info->pipe)) {
291 		m66592->bulk--;
292 	} else if (is_interrupt_pipe(info->pipe))
293 		m66592->interrupt--;
294 	else if (is_isoc_pipe(info->pipe)) {
295 		m66592->isochronous--;
296 		if (info->type == M66592_BULK)
297 			m66592->bulk--;
298 	} else
299 		pr_err("ep_release: unexpect pipenum (%d)\n",
300 				info->pipe);
301 }
302 
303 static void pipe_initialize(struct m66592_ep *ep)
304 {
305 	struct m66592 *m66592 = ep->m66592;
306 	unsigned short mbw;
307 
308 	m66592_mdfy(m66592, 0, M66592_CURPIPE, ep->fifosel);
309 
310 	m66592_write(m66592, M66592_ACLRM, ep->pipectr);
311 	m66592_write(m66592, 0, ep->pipectr);
312 	m66592_write(m66592, M66592_SQCLR, ep->pipectr);
313 	if (ep->use_dma) {
314 		m66592_mdfy(m66592, ep->pipenum, M66592_CURPIPE, ep->fifosel);
315 
316 		ndelay(450);
317 
318 		if (m66592->pdata->on_chip)
319 			mbw = M66592_MBW_32;
320 		else
321 			mbw = M66592_MBW_16;
322 
323 		m66592_bset(m66592, mbw, ep->fifosel);
324 	}
325 }
326 
327 static void m66592_ep_setting(struct m66592 *m66592, struct m66592_ep *ep,
328 		const struct usb_endpoint_descriptor *desc,
329 		u16 pipenum, int dma)
330 {
331 	if ((pipenum != 0) && dma) {
332 		if (m66592->num_dma == 0) {
333 			m66592->num_dma++;
334 			ep->use_dma = 1;
335 			ep->fifoaddr = M66592_D0FIFO;
336 			ep->fifosel = M66592_D0FIFOSEL;
337 			ep->fifoctr = M66592_D0FIFOCTR;
338 			ep->fifotrn = M66592_D0FIFOTRN;
339 		} else if (!m66592->pdata->on_chip && m66592->num_dma == 1) {
340 			m66592->num_dma++;
341 			ep->use_dma = 1;
342 			ep->fifoaddr = M66592_D1FIFO;
343 			ep->fifosel = M66592_D1FIFOSEL;
344 			ep->fifoctr = M66592_D1FIFOCTR;
345 			ep->fifotrn = M66592_D1FIFOTRN;
346 		} else {
347 			ep->use_dma = 0;
348 			ep->fifoaddr = M66592_CFIFO;
349 			ep->fifosel = M66592_CFIFOSEL;
350 			ep->fifoctr = M66592_CFIFOCTR;
351 			ep->fifotrn = 0;
352 		}
353 	} else {
354 		ep->use_dma = 0;
355 		ep->fifoaddr = M66592_CFIFO;
356 		ep->fifosel = M66592_CFIFOSEL;
357 		ep->fifoctr = M66592_CFIFOCTR;
358 		ep->fifotrn = 0;
359 	}
360 
361 	ep->pipectr = get_pipectr_addr(pipenum);
362 	ep->pipenum = pipenum;
363 	ep->ep.maxpacket = usb_endpoint_maxp(desc);
364 	m66592->pipenum2ep[pipenum] = ep;
365 	m66592->epaddr2ep[desc->bEndpointAddress&USB_ENDPOINT_NUMBER_MASK] = ep;
366 	INIT_LIST_HEAD(&ep->queue);
367 }
368 
369 static void m66592_ep_release(struct m66592_ep *ep)
370 {
371 	struct m66592 *m66592 = ep->m66592;
372 	u16 pipenum = ep->pipenum;
373 
374 	if (pipenum == 0)
375 		return;
376 
377 	if (ep->use_dma)
378 		m66592->num_dma--;
379 	ep->pipenum = 0;
380 	ep->busy = 0;
381 	ep->use_dma = 0;
382 }
383 
384 static int alloc_pipe_config(struct m66592_ep *ep,
385 		const struct usb_endpoint_descriptor *desc)
386 {
387 	struct m66592 *m66592 = ep->m66592;
388 	struct m66592_pipe_info info;
389 	int dma = 0;
390 	int *counter;
391 	int ret;
392 
393 	ep->ep.desc = desc;
394 
395 	BUG_ON(ep->pipenum);
396 
397 	switch (desc->bmAttributes & USB_ENDPOINT_XFERTYPE_MASK) {
398 	case USB_ENDPOINT_XFER_BULK:
399 		if (m66592->bulk >= M66592_MAX_NUM_BULK) {
400 			if (m66592->isochronous >= M66592_MAX_NUM_ISOC) {
401 				pr_err("bulk pipe is insufficient\n");
402 				return -ENODEV;
403 			} else {
404 				info.pipe = M66592_BASE_PIPENUM_ISOC
405 						+ m66592->isochronous;
406 				counter = &m66592->isochronous;
407 			}
408 		} else {
409 			info.pipe = M66592_BASE_PIPENUM_BULK + m66592->bulk;
410 			counter = &m66592->bulk;
411 		}
412 		info.type = M66592_BULK;
413 		dma = 1;
414 		break;
415 	case USB_ENDPOINT_XFER_INT:
416 		if (m66592->interrupt >= M66592_MAX_NUM_INT) {
417 			pr_err("interrupt pipe is insufficient\n");
418 			return -ENODEV;
419 		}
420 		info.pipe = M66592_BASE_PIPENUM_INT + m66592->interrupt;
421 		info.type = M66592_INT;
422 		counter = &m66592->interrupt;
423 		break;
424 	case USB_ENDPOINT_XFER_ISOC:
425 		if (m66592->isochronous >= M66592_MAX_NUM_ISOC) {
426 			pr_err("isochronous pipe is insufficient\n");
427 			return -ENODEV;
428 		}
429 		info.pipe = M66592_BASE_PIPENUM_ISOC + m66592->isochronous;
430 		info.type = M66592_ISO;
431 		counter = &m66592->isochronous;
432 		break;
433 	default:
434 		pr_err("unexpect xfer type\n");
435 		return -EINVAL;
436 	}
437 	ep->type = info.type;
438 
439 	info.epnum = desc->bEndpointAddress & USB_ENDPOINT_NUMBER_MASK;
440 	info.maxpacket = usb_endpoint_maxp(desc);
441 	info.interval = desc->bInterval;
442 	if (desc->bEndpointAddress & USB_ENDPOINT_DIR_MASK)
443 		info.dir_in = 1;
444 	else
445 		info.dir_in = 0;
446 
447 	ret = pipe_buffer_setting(m66592, &info);
448 	if (ret < 0) {
449 		pr_err("pipe_buffer_setting fail\n");
450 		return ret;
451 	}
452 
453 	(*counter)++;
454 	if ((counter == &m66592->isochronous) && info.type == M66592_BULK)
455 		m66592->bulk++;
456 
457 	m66592_ep_setting(m66592, ep, desc, info.pipe, dma);
458 	pipe_initialize(ep);
459 
460 	return 0;
461 }
462 
463 static int free_pipe_config(struct m66592_ep *ep)
464 {
465 	struct m66592 *m66592 = ep->m66592;
466 	struct m66592_pipe_info info;
467 
468 	info.pipe = ep->pipenum;
469 	info.type = ep->type;
470 	pipe_buffer_release(m66592, &info);
471 	m66592_ep_release(ep);
472 
473 	return 0;
474 }
475 
476 /*-------------------------------------------------------------------------*/
477 static void pipe_irq_enable(struct m66592 *m66592, u16 pipenum)
478 {
479 	enable_irq_ready(m66592, pipenum);
480 	enable_irq_nrdy(m66592, pipenum);
481 }
482 
483 static void pipe_irq_disable(struct m66592 *m66592, u16 pipenum)
484 {
485 	disable_irq_ready(m66592, pipenum);
486 	disable_irq_nrdy(m66592, pipenum);
487 }
488 
489 /* if complete is true, gadget driver complete function is not call */
490 static void control_end(struct m66592 *m66592, unsigned ccpl)
491 {
492 	m66592->ep[0].internal_ccpl = ccpl;
493 	pipe_start(m66592, 0);
494 	m66592_bset(m66592, M66592_CCPL, M66592_DCPCTR);
495 }
496 
497 static void start_ep0_write(struct m66592_ep *ep, struct m66592_request *req)
498 {
499 	struct m66592 *m66592 = ep->m66592;
500 
501 	pipe_change(m66592, ep->pipenum);
502 	m66592_mdfy(m66592, M66592_ISEL | M66592_PIPE0,
503 			(M66592_ISEL | M66592_CURPIPE),
504 			M66592_CFIFOSEL);
505 	m66592_write(m66592, M66592_BCLR, ep->fifoctr);
506 	if (req->req.length == 0) {
507 		m66592_bset(m66592, M66592_BVAL, ep->fifoctr);
508 		pipe_start(m66592, 0);
509 		transfer_complete(ep, req, 0);
510 	} else {
511 		m66592_write(m66592, ~M66592_BEMP0, M66592_BEMPSTS);
512 		irq_ep0_write(ep, req);
513 	}
514 }
515 
516 static void start_packet_write(struct m66592_ep *ep, struct m66592_request *req)
517 {
518 	struct m66592 *m66592 = ep->m66592;
519 	u16 tmp;
520 
521 	pipe_change(m66592, ep->pipenum);
522 	disable_irq_empty(m66592, ep->pipenum);
523 	pipe_start(m66592, ep->pipenum);
524 
525 	tmp = m66592_read(m66592, ep->fifoctr);
526 	if (unlikely((tmp & M66592_FRDY) == 0))
527 		pipe_irq_enable(m66592, ep->pipenum);
528 	else
529 		irq_packet_write(ep, req);
530 }
531 
532 static void start_packet_read(struct m66592_ep *ep, struct m66592_request *req)
533 {
534 	struct m66592 *m66592 = ep->m66592;
535 	u16 pipenum = ep->pipenum;
536 
537 	if (ep->pipenum == 0) {
538 		m66592_mdfy(m66592, M66592_PIPE0,
539 				(M66592_ISEL | M66592_CURPIPE),
540 				M66592_CFIFOSEL);
541 		m66592_write(m66592, M66592_BCLR, ep->fifoctr);
542 		pipe_start(m66592, pipenum);
543 		pipe_irq_enable(m66592, pipenum);
544 	} else {
545 		if (ep->use_dma) {
546 			m66592_bset(m66592, M66592_TRCLR, ep->fifosel);
547 			pipe_change(m66592, pipenum);
548 			m66592_bset(m66592, M66592_TRENB, ep->fifosel);
549 			m66592_write(m66592,
550 				(req->req.length + ep->ep.maxpacket - 1)
551 					/ ep->ep.maxpacket,
552 				ep->fifotrn);
553 		}
554 		pipe_start(m66592, pipenum);	/* trigger once */
555 		pipe_irq_enable(m66592, pipenum);
556 	}
557 }
558 
559 static void start_packet(struct m66592_ep *ep, struct m66592_request *req)
560 {
561 	if (ep->ep.desc->bEndpointAddress & USB_DIR_IN)
562 		start_packet_write(ep, req);
563 	else
564 		start_packet_read(ep, req);
565 }
566 
567 static void start_ep0(struct m66592_ep *ep, struct m66592_request *req)
568 {
569 	u16 ctsq;
570 
571 	ctsq = m66592_read(ep->m66592, M66592_INTSTS0) & M66592_CTSQ;
572 
573 	switch (ctsq) {
574 	case M66592_CS_RDDS:
575 		start_ep0_write(ep, req);
576 		break;
577 	case M66592_CS_WRDS:
578 		start_packet_read(ep, req);
579 		break;
580 
581 	case M66592_CS_WRND:
582 		control_end(ep->m66592, 0);
583 		break;
584 	default:
585 		pr_err("start_ep0: unexpect ctsq(%x)\n", ctsq);
586 		break;
587 	}
588 }
589 
590 static void init_controller(struct m66592 *m66592)
591 {
592 	unsigned int endian;
593 
594 	if (m66592->pdata->on_chip) {
595 		if (m66592->pdata->endian)
596 			endian = 0; /* big endian */
597 		else
598 			endian = M66592_LITTLE; /* little endian */
599 
600 		m66592_bset(m66592, M66592_HSE, M66592_SYSCFG);	/* High spd */
601 		m66592_bclr(m66592, M66592_USBE, M66592_SYSCFG);
602 		m66592_bclr(m66592, M66592_DPRPU, M66592_SYSCFG);
603 		m66592_bset(m66592, M66592_USBE, M66592_SYSCFG);
604 
605 		/* This is a workaound for SH7722 2nd cut */
606 		m66592_bset(m66592, 0x8000, M66592_DVSTCTR);
607 		m66592_bset(m66592, 0x1000, M66592_TESTMODE);
608 		m66592_bclr(m66592, 0x8000, M66592_DVSTCTR);
609 
610 		m66592_bset(m66592, M66592_INTL, M66592_INTENB1);
611 
612 		m66592_write(m66592, 0, M66592_CFBCFG);
613 		m66592_write(m66592, 0, M66592_D0FBCFG);
614 		m66592_bset(m66592, endian, M66592_CFBCFG);
615 		m66592_bset(m66592, endian, M66592_D0FBCFG);
616 	} else {
617 		unsigned int clock, vif, irq_sense;
618 
619 		if (m66592->pdata->endian)
620 			endian = M66592_BIGEND; /* big endian */
621 		else
622 			endian = 0; /* little endian */
623 
624 		if (m66592->pdata->vif)
625 			vif = M66592_LDRV; /* 3.3v */
626 		else
627 			vif = 0; /* 1.5v */
628 
629 		switch (m66592->pdata->xtal) {
630 		case M66592_PLATDATA_XTAL_12MHZ:
631 			clock = M66592_XTAL12;
632 			break;
633 		case M66592_PLATDATA_XTAL_24MHZ:
634 			clock = M66592_XTAL24;
635 			break;
636 		case M66592_PLATDATA_XTAL_48MHZ:
637 			clock = M66592_XTAL48;
638 			break;
639 		default:
640 			pr_warning("m66592-udc: xtal configuration error\n");
641 			clock = 0;
642 		}
643 
644 		switch (m66592->irq_trigger) {
645 		case IRQF_TRIGGER_LOW:
646 			irq_sense = M66592_INTL;
647 			break;
648 		case IRQF_TRIGGER_FALLING:
649 			irq_sense = 0;
650 			break;
651 		default:
652 			pr_warning("m66592-udc: irq trigger config error\n");
653 			irq_sense = 0;
654 		}
655 
656 		m66592_bset(m66592,
657 			    (vif & M66592_LDRV) | (endian & M66592_BIGEND),
658 			    M66592_PINCFG);
659 		m66592_bset(m66592, M66592_HSE, M66592_SYSCFG);	/* High spd */
660 		m66592_mdfy(m66592, clock & M66592_XTAL, M66592_XTAL,
661 			    M66592_SYSCFG);
662 		m66592_bclr(m66592, M66592_USBE, M66592_SYSCFG);
663 		m66592_bclr(m66592, M66592_DPRPU, M66592_SYSCFG);
664 		m66592_bset(m66592, M66592_USBE, M66592_SYSCFG);
665 
666 		m66592_bset(m66592, M66592_XCKE, M66592_SYSCFG);
667 
668 		msleep(3);
669 
670 		m66592_bset(m66592, M66592_RCKE | M66592_PLLC, M66592_SYSCFG);
671 
672 		msleep(1);
673 
674 		m66592_bset(m66592, M66592_SCKE, M66592_SYSCFG);
675 
676 		m66592_bset(m66592, irq_sense & M66592_INTL, M66592_INTENB1);
677 		m66592_write(m66592, M66592_BURST | M66592_CPU_ADR_RD_WR,
678 			     M66592_DMA0CFG);
679 	}
680 }
681 
682 static void disable_controller(struct m66592 *m66592)
683 {
684 	m66592_bclr(m66592, M66592_UTST, M66592_TESTMODE);
685 	if (!m66592->pdata->on_chip) {
686 		m66592_bclr(m66592, M66592_SCKE, M66592_SYSCFG);
687 		udelay(1);
688 		m66592_bclr(m66592, M66592_PLLC, M66592_SYSCFG);
689 		udelay(1);
690 		m66592_bclr(m66592, M66592_RCKE, M66592_SYSCFG);
691 		udelay(1);
692 		m66592_bclr(m66592, M66592_XCKE, M66592_SYSCFG);
693 	}
694 }
695 
696 static void m66592_start_xclock(struct m66592 *m66592)
697 {
698 	u16 tmp;
699 
700 	if (!m66592->pdata->on_chip) {
701 		tmp = m66592_read(m66592, M66592_SYSCFG);
702 		if (!(tmp & M66592_XCKE))
703 			m66592_bset(m66592, M66592_XCKE, M66592_SYSCFG);
704 	}
705 }
706 
707 /*-------------------------------------------------------------------------*/
708 static void transfer_complete(struct m66592_ep *ep,
709 		struct m66592_request *req, int status)
710 __releases(m66592->lock)
711 __acquires(m66592->lock)
712 {
713 	int restart = 0;
714 
715 	if (unlikely(ep->pipenum == 0)) {
716 		if (ep->internal_ccpl) {
717 			ep->internal_ccpl = 0;
718 			return;
719 		}
720 	}
721 
722 	list_del_init(&req->queue);
723 	if (ep->m66592->gadget.speed == USB_SPEED_UNKNOWN)
724 		req->req.status = -ESHUTDOWN;
725 	else
726 		req->req.status = status;
727 
728 	if (!list_empty(&ep->queue))
729 		restart = 1;
730 
731 	spin_unlock(&ep->m66592->lock);
732 	usb_gadget_giveback_request(&ep->ep, &req->req);
733 	spin_lock(&ep->m66592->lock);
734 
735 	if (restart) {
736 		req = list_entry(ep->queue.next, struct m66592_request, queue);
737 		if (ep->ep.desc)
738 			start_packet(ep, req);
739 	}
740 }
741 
742 static void irq_ep0_write(struct m66592_ep *ep, struct m66592_request *req)
743 {
744 	int i;
745 	u16 tmp;
746 	unsigned bufsize;
747 	size_t size;
748 	void *buf;
749 	u16 pipenum = ep->pipenum;
750 	struct m66592 *m66592 = ep->m66592;
751 
752 	pipe_change(m66592, pipenum);
753 	m66592_bset(m66592, M66592_ISEL, ep->fifosel);
754 
755 	i = 0;
756 	do {
757 		tmp = m66592_read(m66592, ep->fifoctr);
758 		if (i++ > 100000) {
759 			pr_err("pipe0 is busy. maybe cpu i/o bus "
760 				"conflict. please power off this controller.");
761 			return;
762 		}
763 		ndelay(1);
764 	} while ((tmp & M66592_FRDY) == 0);
765 
766 	/* prepare parameters */
767 	bufsize = get_buffer_size(m66592, pipenum);
768 	buf = req->req.buf + req->req.actual;
769 	size = min(bufsize, req->req.length - req->req.actual);
770 
771 	/* write fifo */
772 	if (req->req.buf) {
773 		if (size > 0)
774 			m66592_write_fifo(m66592, ep, buf, size);
775 		if ((size == 0) || ((size % ep->ep.maxpacket) != 0))
776 			m66592_bset(m66592, M66592_BVAL, ep->fifoctr);
777 	}
778 
779 	/* update parameters */
780 	req->req.actual += size;
781 
782 	/* check transfer finish */
783 	if ((!req->req.zero && (req->req.actual == req->req.length))
784 			|| (size % ep->ep.maxpacket)
785 			|| (size == 0)) {
786 		disable_irq_ready(m66592, pipenum);
787 		disable_irq_empty(m66592, pipenum);
788 	} else {
789 		disable_irq_ready(m66592, pipenum);
790 		enable_irq_empty(m66592, pipenum);
791 	}
792 	pipe_start(m66592, pipenum);
793 }
794 
795 static void irq_packet_write(struct m66592_ep *ep, struct m66592_request *req)
796 {
797 	u16 tmp;
798 	unsigned bufsize;
799 	size_t size;
800 	void *buf;
801 	u16 pipenum = ep->pipenum;
802 	struct m66592 *m66592 = ep->m66592;
803 
804 	pipe_change(m66592, pipenum);
805 	tmp = m66592_read(m66592, ep->fifoctr);
806 	if (unlikely((tmp & M66592_FRDY) == 0)) {
807 		pipe_stop(m66592, pipenum);
808 		pipe_irq_disable(m66592, pipenum);
809 		pr_err("write fifo not ready. pipnum=%d\n", pipenum);
810 		return;
811 	}
812 
813 	/* prepare parameters */
814 	bufsize = get_buffer_size(m66592, pipenum);
815 	buf = req->req.buf + req->req.actual;
816 	size = min(bufsize, req->req.length - req->req.actual);
817 
818 	/* write fifo */
819 	if (req->req.buf) {
820 		m66592_write_fifo(m66592, ep, buf, size);
821 		if ((size == 0)
822 				|| ((size % ep->ep.maxpacket) != 0)
823 				|| ((bufsize != ep->ep.maxpacket)
824 					&& (bufsize > size)))
825 			m66592_bset(m66592, M66592_BVAL, ep->fifoctr);
826 	}
827 
828 	/* update parameters */
829 	req->req.actual += size;
830 	/* check transfer finish */
831 	if ((!req->req.zero && (req->req.actual == req->req.length))
832 			|| (size % ep->ep.maxpacket)
833 			|| (size == 0)) {
834 		disable_irq_ready(m66592, pipenum);
835 		enable_irq_empty(m66592, pipenum);
836 	} else {
837 		disable_irq_empty(m66592, pipenum);
838 		pipe_irq_enable(m66592, pipenum);
839 	}
840 }
841 
842 static void irq_packet_read(struct m66592_ep *ep, struct m66592_request *req)
843 {
844 	u16 tmp;
845 	int rcv_len, bufsize, req_len;
846 	int size;
847 	void *buf;
848 	u16 pipenum = ep->pipenum;
849 	struct m66592 *m66592 = ep->m66592;
850 	int finish = 0;
851 
852 	pipe_change(m66592, pipenum);
853 	tmp = m66592_read(m66592, ep->fifoctr);
854 	if (unlikely((tmp & M66592_FRDY) == 0)) {
855 		req->req.status = -EPIPE;
856 		pipe_stop(m66592, pipenum);
857 		pipe_irq_disable(m66592, pipenum);
858 		pr_err("read fifo not ready");
859 		return;
860 	}
861 
862 	/* prepare parameters */
863 	rcv_len = tmp & M66592_DTLN;
864 	bufsize = get_buffer_size(m66592, pipenum);
865 
866 	buf = req->req.buf + req->req.actual;
867 	req_len = req->req.length - req->req.actual;
868 	if (rcv_len < bufsize)
869 		size = min(rcv_len, req_len);
870 	else
871 		size = min(bufsize, req_len);
872 
873 	/* update parameters */
874 	req->req.actual += size;
875 
876 	/* check transfer finish */
877 	if ((!req->req.zero && (req->req.actual == req->req.length))
878 			|| (size % ep->ep.maxpacket)
879 			|| (size == 0)) {
880 		pipe_stop(m66592, pipenum);
881 		pipe_irq_disable(m66592, pipenum);
882 		finish = 1;
883 	}
884 
885 	/* read fifo */
886 	if (req->req.buf) {
887 		if (size == 0)
888 			m66592_write(m66592, M66592_BCLR, ep->fifoctr);
889 		else
890 			m66592_read_fifo(m66592, ep->fifoaddr, buf, size);
891 	}
892 
893 	if ((ep->pipenum != 0) && finish)
894 		transfer_complete(ep, req, 0);
895 }
896 
897 static void irq_pipe_ready(struct m66592 *m66592, u16 status, u16 enb)
898 {
899 	u16 check;
900 	u16 pipenum;
901 	struct m66592_ep *ep;
902 	struct m66592_request *req;
903 
904 	if ((status & M66592_BRDY0) && (enb & M66592_BRDY0)) {
905 		m66592_write(m66592, ~M66592_BRDY0, M66592_BRDYSTS);
906 		m66592_mdfy(m66592, M66592_PIPE0, M66592_CURPIPE,
907 				M66592_CFIFOSEL);
908 
909 		ep = &m66592->ep[0];
910 		req = list_entry(ep->queue.next, struct m66592_request, queue);
911 		irq_packet_read(ep, req);
912 	} else {
913 		for (pipenum = 1; pipenum < M66592_MAX_NUM_PIPE; pipenum++) {
914 			check = 1 << pipenum;
915 			if ((status & check) && (enb & check)) {
916 				m66592_write(m66592, ~check, M66592_BRDYSTS);
917 				ep = m66592->pipenum2ep[pipenum];
918 				req = list_entry(ep->queue.next,
919 						 struct m66592_request, queue);
920 				if (ep->ep.desc->bEndpointAddress & USB_DIR_IN)
921 					irq_packet_write(ep, req);
922 				else
923 					irq_packet_read(ep, req);
924 			}
925 		}
926 	}
927 }
928 
929 static void irq_pipe_empty(struct m66592 *m66592, u16 status, u16 enb)
930 {
931 	u16 tmp;
932 	u16 check;
933 	u16 pipenum;
934 	struct m66592_ep *ep;
935 	struct m66592_request *req;
936 
937 	if ((status & M66592_BEMP0) && (enb & M66592_BEMP0)) {
938 		m66592_write(m66592, ~M66592_BEMP0, M66592_BEMPSTS);
939 
940 		ep = &m66592->ep[0];
941 		req = list_entry(ep->queue.next, struct m66592_request, queue);
942 		irq_ep0_write(ep, req);
943 	} else {
944 		for (pipenum = 1; pipenum < M66592_MAX_NUM_PIPE; pipenum++) {
945 			check = 1 << pipenum;
946 			if ((status & check) && (enb & check)) {
947 				m66592_write(m66592, ~check, M66592_BEMPSTS);
948 				tmp = control_reg_get(m66592, pipenum);
949 				if ((tmp & M66592_INBUFM) == 0) {
950 					disable_irq_empty(m66592, pipenum);
951 					pipe_irq_disable(m66592, pipenum);
952 					pipe_stop(m66592, pipenum);
953 					ep = m66592->pipenum2ep[pipenum];
954 					req = list_entry(ep->queue.next,
955 							 struct m66592_request,
956 							 queue);
957 					if (!list_empty(&ep->queue))
958 						transfer_complete(ep, req, 0);
959 				}
960 			}
961 		}
962 	}
963 }
964 
965 static void get_status(struct m66592 *m66592, struct usb_ctrlrequest *ctrl)
966 __releases(m66592->lock)
967 __acquires(m66592->lock)
968 {
969 	struct m66592_ep *ep;
970 	u16 pid;
971 	u16 status = 0;
972 	u16 w_index = le16_to_cpu(ctrl->wIndex);
973 
974 	switch (ctrl->bRequestType & USB_RECIP_MASK) {
975 	case USB_RECIP_DEVICE:
976 		status = 1 << USB_DEVICE_SELF_POWERED;
977 		break;
978 	case USB_RECIP_INTERFACE:
979 		status = 0;
980 		break;
981 	case USB_RECIP_ENDPOINT:
982 		ep = m66592->epaddr2ep[w_index & USB_ENDPOINT_NUMBER_MASK];
983 		pid = control_reg_get_pid(m66592, ep->pipenum);
984 		if (pid == M66592_PID_STALL)
985 			status = 1 << USB_ENDPOINT_HALT;
986 		else
987 			status = 0;
988 		break;
989 	default:
990 		pipe_stall(m66592, 0);
991 		return;		/* exit */
992 	}
993 
994 	m66592->ep0_data = cpu_to_le16(status);
995 	m66592->ep0_req->buf = &m66592->ep0_data;
996 	m66592->ep0_req->length = 2;
997 	/* AV: what happens if we get called again before that gets through? */
998 	spin_unlock(&m66592->lock);
999 	m66592_queue(m66592->gadget.ep0, m66592->ep0_req, GFP_KERNEL);
1000 	spin_lock(&m66592->lock);
1001 }
1002 
1003 static void clear_feature(struct m66592 *m66592, struct usb_ctrlrequest *ctrl)
1004 {
1005 	switch (ctrl->bRequestType & USB_RECIP_MASK) {
1006 	case USB_RECIP_DEVICE:
1007 		control_end(m66592, 1);
1008 		break;
1009 	case USB_RECIP_INTERFACE:
1010 		control_end(m66592, 1);
1011 		break;
1012 	case USB_RECIP_ENDPOINT: {
1013 		struct m66592_ep *ep;
1014 		struct m66592_request *req;
1015 		u16 w_index = le16_to_cpu(ctrl->wIndex);
1016 
1017 		ep = m66592->epaddr2ep[w_index & USB_ENDPOINT_NUMBER_MASK];
1018 		pipe_stop(m66592, ep->pipenum);
1019 		control_reg_sqclr(m66592, ep->pipenum);
1020 
1021 		control_end(m66592, 1);
1022 
1023 		req = list_entry(ep->queue.next,
1024 		struct m66592_request, queue);
1025 		if (ep->busy) {
1026 			ep->busy = 0;
1027 			if (list_empty(&ep->queue))
1028 				break;
1029 			start_packet(ep, req);
1030 		} else if (!list_empty(&ep->queue))
1031 			pipe_start(m66592, ep->pipenum);
1032 		}
1033 		break;
1034 	default:
1035 		pipe_stall(m66592, 0);
1036 		break;
1037 	}
1038 }
1039 
1040 static void set_feature(struct m66592 *m66592, struct usb_ctrlrequest *ctrl)
1041 {
1042 	u16 tmp;
1043 	int timeout = 3000;
1044 
1045 	switch (ctrl->bRequestType & USB_RECIP_MASK) {
1046 	case USB_RECIP_DEVICE:
1047 		switch (le16_to_cpu(ctrl->wValue)) {
1048 		case USB_DEVICE_TEST_MODE:
1049 			control_end(m66592, 1);
1050 			/* Wait for the completion of status stage */
1051 			do {
1052 				tmp = m66592_read(m66592, M66592_INTSTS0) &
1053 								M66592_CTSQ;
1054 				udelay(1);
1055 			} while (tmp != M66592_CS_IDST || timeout-- > 0);
1056 
1057 			if (tmp == M66592_CS_IDST)
1058 				m66592_bset(m66592,
1059 					    le16_to_cpu(ctrl->wIndex >> 8),
1060 					    M66592_TESTMODE);
1061 			break;
1062 		default:
1063 			pipe_stall(m66592, 0);
1064 			break;
1065 		}
1066 		break;
1067 	case USB_RECIP_INTERFACE:
1068 		control_end(m66592, 1);
1069 		break;
1070 	case USB_RECIP_ENDPOINT: {
1071 		struct m66592_ep *ep;
1072 		u16 w_index = le16_to_cpu(ctrl->wIndex);
1073 
1074 		ep = m66592->epaddr2ep[w_index & USB_ENDPOINT_NUMBER_MASK];
1075 		pipe_stall(m66592, ep->pipenum);
1076 
1077 		control_end(m66592, 1);
1078 		}
1079 		break;
1080 	default:
1081 		pipe_stall(m66592, 0);
1082 		break;
1083 	}
1084 }
1085 
1086 /* if return value is true, call class driver's setup() */
1087 static int setup_packet(struct m66592 *m66592, struct usb_ctrlrequest *ctrl)
1088 {
1089 	u16 *p = (u16 *)ctrl;
1090 	unsigned long offset = M66592_USBREQ;
1091 	int i, ret = 0;
1092 
1093 	/* read fifo */
1094 	m66592_write(m66592, ~M66592_VALID, M66592_INTSTS0);
1095 
1096 	for (i = 0; i < 4; i++)
1097 		p[i] = m66592_read(m66592, offset + i*2);
1098 
1099 	/* check request */
1100 	if ((ctrl->bRequestType & USB_TYPE_MASK) == USB_TYPE_STANDARD) {
1101 		switch (ctrl->bRequest) {
1102 		case USB_REQ_GET_STATUS:
1103 			get_status(m66592, ctrl);
1104 			break;
1105 		case USB_REQ_CLEAR_FEATURE:
1106 			clear_feature(m66592, ctrl);
1107 			break;
1108 		case USB_REQ_SET_FEATURE:
1109 			set_feature(m66592, ctrl);
1110 			break;
1111 		default:
1112 			ret = 1;
1113 			break;
1114 		}
1115 	} else
1116 		ret = 1;
1117 	return ret;
1118 }
1119 
1120 static void m66592_update_usb_speed(struct m66592 *m66592)
1121 {
1122 	u16 speed = get_usb_speed(m66592);
1123 
1124 	switch (speed) {
1125 	case M66592_HSMODE:
1126 		m66592->gadget.speed = USB_SPEED_HIGH;
1127 		break;
1128 	case M66592_FSMODE:
1129 		m66592->gadget.speed = USB_SPEED_FULL;
1130 		break;
1131 	default:
1132 		m66592->gadget.speed = USB_SPEED_UNKNOWN;
1133 		pr_err("USB speed unknown\n");
1134 	}
1135 }
1136 
1137 static void irq_device_state(struct m66592 *m66592)
1138 {
1139 	u16 dvsq;
1140 
1141 	dvsq = m66592_read(m66592, M66592_INTSTS0) & M66592_DVSQ;
1142 	m66592_write(m66592, ~M66592_DVST, M66592_INTSTS0);
1143 
1144 	if (dvsq == M66592_DS_DFLT) {	/* bus reset */
1145 		m66592->driver->disconnect(&m66592->gadget);
1146 		m66592_update_usb_speed(m66592);
1147 	}
1148 	if (m66592->old_dvsq == M66592_DS_CNFG && dvsq != M66592_DS_CNFG)
1149 		m66592_update_usb_speed(m66592);
1150 	if ((dvsq == M66592_DS_CNFG || dvsq == M66592_DS_ADDS)
1151 			&& m66592->gadget.speed == USB_SPEED_UNKNOWN)
1152 		m66592_update_usb_speed(m66592);
1153 
1154 	m66592->old_dvsq = dvsq;
1155 }
1156 
1157 static void irq_control_stage(struct m66592 *m66592)
1158 __releases(m66592->lock)
1159 __acquires(m66592->lock)
1160 {
1161 	struct usb_ctrlrequest ctrl;
1162 	u16 ctsq;
1163 
1164 	ctsq = m66592_read(m66592, M66592_INTSTS0) & M66592_CTSQ;
1165 	m66592_write(m66592, ~M66592_CTRT, M66592_INTSTS0);
1166 
1167 	switch (ctsq) {
1168 	case M66592_CS_IDST: {
1169 		struct m66592_ep *ep;
1170 		struct m66592_request *req;
1171 		ep = &m66592->ep[0];
1172 		req = list_entry(ep->queue.next, struct m66592_request, queue);
1173 		transfer_complete(ep, req, 0);
1174 		}
1175 		break;
1176 
1177 	case M66592_CS_RDDS:
1178 	case M66592_CS_WRDS:
1179 	case M66592_CS_WRND:
1180 		if (setup_packet(m66592, &ctrl)) {
1181 			spin_unlock(&m66592->lock);
1182 			if (m66592->driver->setup(&m66592->gadget, &ctrl) < 0)
1183 				pipe_stall(m66592, 0);
1184 			spin_lock(&m66592->lock);
1185 		}
1186 		break;
1187 	case M66592_CS_RDSS:
1188 	case M66592_CS_WRSS:
1189 		control_end(m66592, 0);
1190 		break;
1191 	default:
1192 		pr_err("ctrl_stage: unexpect ctsq(%x)\n", ctsq);
1193 		break;
1194 	}
1195 }
1196 
1197 static irqreturn_t m66592_irq(int irq, void *_m66592)
1198 {
1199 	struct m66592 *m66592 = _m66592;
1200 	u16 intsts0;
1201 	u16 intenb0;
1202 	u16 brdysts, nrdysts, bempsts;
1203 	u16 brdyenb, nrdyenb, bempenb;
1204 	u16 savepipe;
1205 	u16 mask0;
1206 
1207 	spin_lock(&m66592->lock);
1208 
1209 	intsts0 = m66592_read(m66592, M66592_INTSTS0);
1210 	intenb0 = m66592_read(m66592, M66592_INTENB0);
1211 
1212 	if (m66592->pdata->on_chip && !intsts0 && !intenb0) {
1213 		/*
1214 		 * When USB clock stops, it cannot read register. Even if a
1215 		 * clock stops, the interrupt occurs. So this driver turn on
1216 		 * a clock by this timing and do re-reading of register.
1217 		 */
1218 		m66592_start_xclock(m66592);
1219 		intsts0 = m66592_read(m66592, M66592_INTSTS0);
1220 		intenb0 = m66592_read(m66592, M66592_INTENB0);
1221 	}
1222 
1223 	savepipe = m66592_read(m66592, M66592_CFIFOSEL);
1224 
1225 	mask0 = intsts0 & intenb0;
1226 	if (mask0) {
1227 		brdysts = m66592_read(m66592, M66592_BRDYSTS);
1228 		nrdysts = m66592_read(m66592, M66592_NRDYSTS);
1229 		bempsts = m66592_read(m66592, M66592_BEMPSTS);
1230 		brdyenb = m66592_read(m66592, M66592_BRDYENB);
1231 		nrdyenb = m66592_read(m66592, M66592_NRDYENB);
1232 		bempenb = m66592_read(m66592, M66592_BEMPENB);
1233 
1234 		if (mask0 & M66592_VBINT) {
1235 			m66592_write(m66592,  0xffff & ~M66592_VBINT,
1236 					M66592_INTSTS0);
1237 			m66592_start_xclock(m66592);
1238 
1239 			/* start vbus sampling */
1240 			m66592->old_vbus = m66592_read(m66592, M66592_INTSTS0)
1241 					& M66592_VBSTS;
1242 			m66592->scount = M66592_MAX_SAMPLING;
1243 
1244 			mod_timer(&m66592->timer,
1245 					jiffies + msecs_to_jiffies(50));
1246 		}
1247 		if (intsts0 & M66592_DVSQ)
1248 			irq_device_state(m66592);
1249 
1250 		if ((intsts0 & M66592_BRDY) && (intenb0 & M66592_BRDYE)
1251 				&& (brdysts & brdyenb)) {
1252 			irq_pipe_ready(m66592, brdysts, brdyenb);
1253 		}
1254 		if ((intsts0 & M66592_BEMP) && (intenb0 & M66592_BEMPE)
1255 				&& (bempsts & bempenb)) {
1256 			irq_pipe_empty(m66592, bempsts, bempenb);
1257 		}
1258 
1259 		if (intsts0 & M66592_CTRT)
1260 			irq_control_stage(m66592);
1261 	}
1262 
1263 	m66592_write(m66592, savepipe, M66592_CFIFOSEL);
1264 
1265 	spin_unlock(&m66592->lock);
1266 	return IRQ_HANDLED;
1267 }
1268 
1269 static void m66592_timer(unsigned long _m66592)
1270 {
1271 	struct m66592 *m66592 = (struct m66592 *)_m66592;
1272 	unsigned long flags;
1273 	u16 tmp;
1274 
1275 	spin_lock_irqsave(&m66592->lock, flags);
1276 	tmp = m66592_read(m66592, M66592_SYSCFG);
1277 	if (!(tmp & M66592_RCKE)) {
1278 		m66592_bset(m66592, M66592_RCKE | M66592_PLLC, M66592_SYSCFG);
1279 		udelay(10);
1280 		m66592_bset(m66592, M66592_SCKE, M66592_SYSCFG);
1281 	}
1282 	if (m66592->scount > 0) {
1283 		tmp = m66592_read(m66592, M66592_INTSTS0) & M66592_VBSTS;
1284 		if (tmp == m66592->old_vbus) {
1285 			m66592->scount--;
1286 			if (m66592->scount == 0) {
1287 				if (tmp == M66592_VBSTS)
1288 					m66592_usb_connect(m66592);
1289 				else
1290 					m66592_usb_disconnect(m66592);
1291 			} else {
1292 				mod_timer(&m66592->timer,
1293 					jiffies + msecs_to_jiffies(50));
1294 			}
1295 		} else {
1296 			m66592->scount = M66592_MAX_SAMPLING;
1297 			m66592->old_vbus = tmp;
1298 			mod_timer(&m66592->timer,
1299 					jiffies + msecs_to_jiffies(50));
1300 		}
1301 	}
1302 	spin_unlock_irqrestore(&m66592->lock, flags);
1303 }
1304 
1305 /*-------------------------------------------------------------------------*/
1306 static int m66592_enable(struct usb_ep *_ep,
1307 			 const struct usb_endpoint_descriptor *desc)
1308 {
1309 	struct m66592_ep *ep;
1310 
1311 	ep = container_of(_ep, struct m66592_ep, ep);
1312 	return alloc_pipe_config(ep, desc);
1313 }
1314 
1315 static int m66592_disable(struct usb_ep *_ep)
1316 {
1317 	struct m66592_ep *ep;
1318 	struct m66592_request *req;
1319 	unsigned long flags;
1320 
1321 	ep = container_of(_ep, struct m66592_ep, ep);
1322 	BUG_ON(!ep);
1323 
1324 	while (!list_empty(&ep->queue)) {
1325 		req = list_entry(ep->queue.next, struct m66592_request, queue);
1326 		spin_lock_irqsave(&ep->m66592->lock, flags);
1327 		transfer_complete(ep, req, -ECONNRESET);
1328 		spin_unlock_irqrestore(&ep->m66592->lock, flags);
1329 	}
1330 
1331 	pipe_irq_disable(ep->m66592, ep->pipenum);
1332 	return free_pipe_config(ep);
1333 }
1334 
1335 static struct usb_request *m66592_alloc_request(struct usb_ep *_ep,
1336 						gfp_t gfp_flags)
1337 {
1338 	struct m66592_request *req;
1339 
1340 	req = kzalloc(sizeof(struct m66592_request), gfp_flags);
1341 	if (!req)
1342 		return NULL;
1343 
1344 	INIT_LIST_HEAD(&req->queue);
1345 
1346 	return &req->req;
1347 }
1348 
1349 static void m66592_free_request(struct usb_ep *_ep, struct usb_request *_req)
1350 {
1351 	struct m66592_request *req;
1352 
1353 	req = container_of(_req, struct m66592_request, req);
1354 	kfree(req);
1355 }
1356 
1357 static int m66592_queue(struct usb_ep *_ep, struct usb_request *_req,
1358 			gfp_t gfp_flags)
1359 {
1360 	struct m66592_ep *ep;
1361 	struct m66592_request *req;
1362 	unsigned long flags;
1363 	int request = 0;
1364 
1365 	ep = container_of(_ep, struct m66592_ep, ep);
1366 	req = container_of(_req, struct m66592_request, req);
1367 
1368 	if (ep->m66592->gadget.speed == USB_SPEED_UNKNOWN)
1369 		return -ESHUTDOWN;
1370 
1371 	spin_lock_irqsave(&ep->m66592->lock, flags);
1372 
1373 	if (list_empty(&ep->queue))
1374 		request = 1;
1375 
1376 	list_add_tail(&req->queue, &ep->queue);
1377 	req->req.actual = 0;
1378 	req->req.status = -EINPROGRESS;
1379 
1380 	if (ep->ep.desc == NULL)	/* control */
1381 		start_ep0(ep, req);
1382 	else {
1383 		if (request && !ep->busy)
1384 			start_packet(ep, req);
1385 	}
1386 
1387 	spin_unlock_irqrestore(&ep->m66592->lock, flags);
1388 
1389 	return 0;
1390 }
1391 
1392 static int m66592_dequeue(struct usb_ep *_ep, struct usb_request *_req)
1393 {
1394 	struct m66592_ep *ep;
1395 	struct m66592_request *req;
1396 	unsigned long flags;
1397 
1398 	ep = container_of(_ep, struct m66592_ep, ep);
1399 	req = container_of(_req, struct m66592_request, req);
1400 
1401 	spin_lock_irqsave(&ep->m66592->lock, flags);
1402 	if (!list_empty(&ep->queue))
1403 		transfer_complete(ep, req, -ECONNRESET);
1404 	spin_unlock_irqrestore(&ep->m66592->lock, flags);
1405 
1406 	return 0;
1407 }
1408 
1409 static int m66592_set_halt(struct usb_ep *_ep, int value)
1410 {
1411 	struct m66592_ep *ep;
1412 	struct m66592_request *req;
1413 	unsigned long flags;
1414 	int ret = 0;
1415 
1416 	ep = container_of(_ep, struct m66592_ep, ep);
1417 	req = list_entry(ep->queue.next, struct m66592_request, queue);
1418 
1419 	spin_lock_irqsave(&ep->m66592->lock, flags);
1420 	if (!list_empty(&ep->queue)) {
1421 		ret = -EAGAIN;
1422 		goto out;
1423 	}
1424 	if (value) {
1425 		ep->busy = 1;
1426 		pipe_stall(ep->m66592, ep->pipenum);
1427 	} else {
1428 		ep->busy = 0;
1429 		pipe_stop(ep->m66592, ep->pipenum);
1430 	}
1431 
1432 out:
1433 	spin_unlock_irqrestore(&ep->m66592->lock, flags);
1434 	return ret;
1435 }
1436 
1437 static void m66592_fifo_flush(struct usb_ep *_ep)
1438 {
1439 	struct m66592_ep *ep;
1440 	unsigned long flags;
1441 
1442 	ep = container_of(_ep, struct m66592_ep, ep);
1443 	spin_lock_irqsave(&ep->m66592->lock, flags);
1444 	if (list_empty(&ep->queue) && !ep->busy) {
1445 		pipe_stop(ep->m66592, ep->pipenum);
1446 		m66592_bclr(ep->m66592, M66592_BCLR, ep->fifoctr);
1447 	}
1448 	spin_unlock_irqrestore(&ep->m66592->lock, flags);
1449 }
1450 
1451 static struct usb_ep_ops m66592_ep_ops = {
1452 	.enable		= m66592_enable,
1453 	.disable	= m66592_disable,
1454 
1455 	.alloc_request	= m66592_alloc_request,
1456 	.free_request	= m66592_free_request,
1457 
1458 	.queue		= m66592_queue,
1459 	.dequeue	= m66592_dequeue,
1460 
1461 	.set_halt	= m66592_set_halt,
1462 	.fifo_flush	= m66592_fifo_flush,
1463 };
1464 
1465 /*-------------------------------------------------------------------------*/
1466 static int m66592_udc_start(struct usb_gadget *g,
1467 		struct usb_gadget_driver *driver)
1468 {
1469 	struct m66592 *m66592 = to_m66592(g);
1470 
1471 	/* hook up the driver */
1472 	driver->driver.bus = NULL;
1473 	m66592->driver = driver;
1474 
1475 	m66592_bset(m66592, M66592_VBSE | M66592_URST, M66592_INTENB0);
1476 	if (m66592_read(m66592, M66592_INTSTS0) & M66592_VBSTS) {
1477 		m66592_start_xclock(m66592);
1478 		/* start vbus sampling */
1479 		m66592->old_vbus = m66592_read(m66592,
1480 					 M66592_INTSTS0) & M66592_VBSTS;
1481 		m66592->scount = M66592_MAX_SAMPLING;
1482 		mod_timer(&m66592->timer, jiffies + msecs_to_jiffies(50));
1483 	}
1484 
1485 	return 0;
1486 }
1487 
1488 static int m66592_udc_stop(struct usb_gadget *g,
1489 		struct usb_gadget_driver *driver)
1490 {
1491 	struct m66592 *m66592 = to_m66592(g);
1492 
1493 	m66592_bclr(m66592, M66592_VBSE | M66592_URST, M66592_INTENB0);
1494 
1495 	init_controller(m66592);
1496 	disable_controller(m66592);
1497 
1498 	m66592->driver = NULL;
1499 
1500 	return 0;
1501 }
1502 
1503 /*-------------------------------------------------------------------------*/
1504 static int m66592_get_frame(struct usb_gadget *_gadget)
1505 {
1506 	struct m66592 *m66592 = gadget_to_m66592(_gadget);
1507 	return m66592_read(m66592, M66592_FRMNUM) & 0x03FF;
1508 }
1509 
1510 static int m66592_pullup(struct usb_gadget *gadget, int is_on)
1511 {
1512 	struct m66592 *m66592 = gadget_to_m66592(gadget);
1513 	unsigned long flags;
1514 
1515 	spin_lock_irqsave(&m66592->lock, flags);
1516 	if (is_on)
1517 		m66592_bset(m66592, M66592_DPRPU, M66592_SYSCFG);
1518 	else
1519 		m66592_bclr(m66592, M66592_DPRPU, M66592_SYSCFG);
1520 	spin_unlock_irqrestore(&m66592->lock, flags);
1521 
1522 	return 0;
1523 }
1524 
1525 static const struct usb_gadget_ops m66592_gadget_ops = {
1526 	.get_frame		= m66592_get_frame,
1527 	.udc_start		= m66592_udc_start,
1528 	.udc_stop		= m66592_udc_stop,
1529 	.pullup			= m66592_pullup,
1530 };
1531 
1532 static int __exit m66592_remove(struct platform_device *pdev)
1533 {
1534 	struct m66592		*m66592 = platform_get_drvdata(pdev);
1535 
1536 	usb_del_gadget_udc(&m66592->gadget);
1537 
1538 	del_timer_sync(&m66592->timer);
1539 	iounmap(m66592->reg);
1540 	free_irq(platform_get_irq(pdev, 0), m66592);
1541 	m66592_free_request(&m66592->ep[0].ep, m66592->ep0_req);
1542 	if (m66592->pdata->on_chip) {
1543 		clk_disable(m66592->clk);
1544 		clk_put(m66592->clk);
1545 	}
1546 	kfree(m66592);
1547 	return 0;
1548 }
1549 
1550 static void nop_completion(struct usb_ep *ep, struct usb_request *r)
1551 {
1552 }
1553 
1554 static int m66592_probe(struct platform_device *pdev)
1555 {
1556 	struct resource *res, *ires;
1557 	void __iomem *reg = NULL;
1558 	struct m66592 *m66592 = NULL;
1559 	char clk_name[8];
1560 	int ret = 0;
1561 	int i;
1562 
1563 	res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
1564 	if (!res) {
1565 		ret = -ENODEV;
1566 		pr_err("platform_get_resource error.\n");
1567 		goto clean_up;
1568 	}
1569 
1570 	ires = platform_get_resource(pdev, IORESOURCE_IRQ, 0);
1571 	if (!ires) {
1572 		ret = -ENODEV;
1573 		dev_err(&pdev->dev,
1574 			"platform_get_resource IORESOURCE_IRQ error.\n");
1575 		goto clean_up;
1576 	}
1577 
1578 	reg = ioremap(res->start, resource_size(res));
1579 	if (reg == NULL) {
1580 		ret = -ENOMEM;
1581 		pr_err("ioremap error.\n");
1582 		goto clean_up;
1583 	}
1584 
1585 	if (dev_get_platdata(&pdev->dev) == NULL) {
1586 		dev_err(&pdev->dev, "no platform data\n");
1587 		ret = -ENODEV;
1588 		goto clean_up;
1589 	}
1590 
1591 	/* initialize ucd */
1592 	m66592 = kzalloc(sizeof(struct m66592), GFP_KERNEL);
1593 	if (m66592 == NULL) {
1594 		ret = -ENOMEM;
1595 		goto clean_up;
1596 	}
1597 
1598 	m66592->pdata = dev_get_platdata(&pdev->dev);
1599 	m66592->irq_trigger = ires->flags & IRQF_TRIGGER_MASK;
1600 
1601 	spin_lock_init(&m66592->lock);
1602 	platform_set_drvdata(pdev, m66592);
1603 
1604 	m66592->gadget.ops = &m66592_gadget_ops;
1605 	m66592->gadget.max_speed = USB_SPEED_HIGH;
1606 	m66592->gadget.name = udc_name;
1607 
1608 	init_timer(&m66592->timer);
1609 	m66592->timer.function = m66592_timer;
1610 	m66592->timer.data = (unsigned long)m66592;
1611 	m66592->reg = reg;
1612 
1613 	ret = request_irq(ires->start, m66592_irq, IRQF_SHARED,
1614 			udc_name, m66592);
1615 	if (ret < 0) {
1616 		pr_err("request_irq error (%d)\n", ret);
1617 		goto clean_up;
1618 	}
1619 
1620 	if (m66592->pdata->on_chip) {
1621 		snprintf(clk_name, sizeof(clk_name), "usbf%d", pdev->id);
1622 		m66592->clk = clk_get(&pdev->dev, clk_name);
1623 		if (IS_ERR(m66592->clk)) {
1624 			dev_err(&pdev->dev, "cannot get clock \"%s\"\n",
1625 				clk_name);
1626 			ret = PTR_ERR(m66592->clk);
1627 			goto clean_up2;
1628 		}
1629 		clk_enable(m66592->clk);
1630 	}
1631 
1632 	INIT_LIST_HEAD(&m66592->gadget.ep_list);
1633 	m66592->gadget.ep0 = &m66592->ep[0].ep;
1634 	INIT_LIST_HEAD(&m66592->gadget.ep0->ep_list);
1635 	for (i = 0; i < M66592_MAX_NUM_PIPE; i++) {
1636 		struct m66592_ep *ep = &m66592->ep[i];
1637 
1638 		if (i != 0) {
1639 			INIT_LIST_HEAD(&m66592->ep[i].ep.ep_list);
1640 			list_add_tail(&m66592->ep[i].ep.ep_list,
1641 					&m66592->gadget.ep_list);
1642 		}
1643 		ep->m66592 = m66592;
1644 		INIT_LIST_HEAD(&ep->queue);
1645 		ep->ep.name = m66592_ep_name[i];
1646 		ep->ep.ops = &m66592_ep_ops;
1647 		usb_ep_set_maxpacket_limit(&ep->ep, 512);
1648 	}
1649 	usb_ep_set_maxpacket_limit(&m66592->ep[0].ep, 64);
1650 	m66592->ep[0].pipenum = 0;
1651 	m66592->ep[0].fifoaddr = M66592_CFIFO;
1652 	m66592->ep[0].fifosel = M66592_CFIFOSEL;
1653 	m66592->ep[0].fifoctr = M66592_CFIFOCTR;
1654 	m66592->ep[0].fifotrn = 0;
1655 	m66592->ep[0].pipectr = get_pipectr_addr(0);
1656 	m66592->pipenum2ep[0] = &m66592->ep[0];
1657 	m66592->epaddr2ep[0] = &m66592->ep[0];
1658 
1659 	m66592->ep0_req = m66592_alloc_request(&m66592->ep[0].ep, GFP_KERNEL);
1660 	if (m66592->ep0_req == NULL) {
1661 		ret = -ENOMEM;
1662 		goto clean_up3;
1663 	}
1664 	m66592->ep0_req->complete = nop_completion;
1665 
1666 	init_controller(m66592);
1667 
1668 	ret = usb_add_gadget_udc(&pdev->dev, &m66592->gadget);
1669 	if (ret)
1670 		goto err_add_udc;
1671 
1672 	dev_info(&pdev->dev, "version %s\n", DRIVER_VERSION);
1673 	return 0;
1674 
1675 err_add_udc:
1676 	m66592_free_request(&m66592->ep[0].ep, m66592->ep0_req);
1677 
1678 clean_up3:
1679 	if (m66592->pdata->on_chip) {
1680 		clk_disable(m66592->clk);
1681 		clk_put(m66592->clk);
1682 	}
1683 clean_up2:
1684 	free_irq(ires->start, m66592);
1685 clean_up:
1686 	if (m66592) {
1687 		if (m66592->ep0_req)
1688 			m66592_free_request(&m66592->ep[0].ep, m66592->ep0_req);
1689 		kfree(m66592);
1690 	}
1691 	if (reg)
1692 		iounmap(reg);
1693 
1694 	return ret;
1695 }
1696 
1697 /*-------------------------------------------------------------------------*/
1698 static struct platform_driver m66592_driver = {
1699 	.remove =	__exit_p(m66592_remove),
1700 	.driver		= {
1701 		.name =	(char *) udc_name,
1702 		.owner	= THIS_MODULE,
1703 	},
1704 };
1705 
1706 module_platform_driver_probe(m66592_driver, m66592_probe);
1707