1 // SPDX-License-Identifier: GPL-2.0+ 2 /* 3 * USB Gadget driver for LPC32xx 4 * 5 * Authors: 6 * Kevin Wells <kevin.wells@nxp.com> 7 * Mike James 8 * Roland Stigge <stigge@antcom.de> 9 * 10 * Copyright (C) 2006 Philips Semiconductors 11 * Copyright (C) 2009 NXP Semiconductors 12 * Copyright (C) 2012 Roland Stigge 13 * 14 * Note: This driver is based on original work done by Mike James for 15 * the LPC3180. 16 */ 17 18 #include <linux/clk.h> 19 #include <linux/delay.h> 20 #include <linux/dma-mapping.h> 21 #include <linux/dmapool.h> 22 #include <linux/i2c.h> 23 #include <linux/interrupt.h> 24 #include <linux/module.h> 25 #include <linux/of.h> 26 #include <linux/platform_device.h> 27 #include <linux/proc_fs.h> 28 #include <linux/slab.h> 29 #include <linux/usb/ch9.h> 30 #include <linux/usb/gadget.h> 31 #include <linux/usb/isp1301.h> 32 33 #ifdef CONFIG_USB_GADGET_DEBUG_FILES 34 #include <linux/debugfs.h> 35 #include <linux/seq_file.h> 36 #endif 37 38 #include <mach/hardware.h> 39 40 /* 41 * USB device configuration structure 42 */ 43 typedef void (*usc_chg_event)(int); 44 struct lpc32xx_usbd_cfg { 45 int vbus_drv_pol; /* 0=active low drive for VBUS via ISP1301 */ 46 usc_chg_event conn_chgb; /* Connection change event (optional) */ 47 usc_chg_event susp_chgb; /* Suspend/resume event (optional) */ 48 usc_chg_event rmwk_chgb; /* Enable/disable remote wakeup */ 49 }; 50 51 /* 52 * controller driver data structures 53 */ 54 55 /* 16 endpoints (not to be confused with 32 hardware endpoints) */ 56 #define NUM_ENDPOINTS 16 57 58 /* 59 * IRQ indices make reading the code a little easier 60 */ 61 #define IRQ_USB_LP 0 62 #define IRQ_USB_HP 1 63 #define IRQ_USB_DEVDMA 2 64 #define IRQ_USB_ATX 3 65 66 #define EP_OUT 0 /* RX (from host) */ 67 #define EP_IN 1 /* TX (to host) */ 68 69 /* Returns the interrupt mask for the selected hardware endpoint */ 70 #define EP_MASK_SEL(ep, dir) (1 << (((ep) * 2) + dir)) 71 72 #define EP_INT_TYPE 0 73 #define EP_ISO_TYPE 1 74 #define EP_BLK_TYPE 2 75 #define EP_CTL_TYPE 3 76 77 /* EP0 states */ 78 #define WAIT_FOR_SETUP 0 /* Wait for setup packet */ 79 #define DATA_IN 1 /* Expect dev->host transfer */ 80 #define DATA_OUT 2 /* Expect host->dev transfer */ 81 82 /* DD (DMA Descriptor) structure, requires word alignment, this is already 83 * defined in the LPC32XX USB device header file, but this version is slightly 84 * modified to tag some work data with each DMA descriptor. */ 85 struct lpc32xx_usbd_dd_gad { 86 u32 dd_next_phy; 87 u32 dd_setup; 88 u32 dd_buffer_addr; 89 u32 dd_status; 90 u32 dd_iso_ps_mem_addr; 91 u32 this_dma; 92 u32 iso_status[6]; /* 5 spare */ 93 u32 dd_next_v; 94 }; 95 96 /* 97 * Logical endpoint structure 98 */ 99 struct lpc32xx_ep { 100 struct usb_ep ep; 101 struct list_head queue; 102 struct lpc32xx_udc *udc; 103 104 u32 hwep_num_base; /* Physical hardware EP */ 105 u32 hwep_num; /* Maps to hardware endpoint */ 106 u32 maxpacket; 107 u32 lep; 108 109 bool is_in; 110 bool req_pending; 111 u32 eptype; 112 113 u32 totalints; 114 115 bool wedge; 116 }; 117 118 /* 119 * Common UDC structure 120 */ 121 struct lpc32xx_udc { 122 struct usb_gadget gadget; 123 struct usb_gadget_driver *driver; 124 struct platform_device *pdev; 125 struct device *dev; 126 struct dentry *pde; 127 spinlock_t lock; 128 struct i2c_client *isp1301_i2c_client; 129 130 /* Board and device specific */ 131 struct lpc32xx_usbd_cfg *board; 132 u32 io_p_start; 133 u32 io_p_size; 134 void __iomem *udp_baseaddr; 135 int udp_irq[4]; 136 struct clk *usb_slv_clk; 137 138 /* DMA support */ 139 u32 *udca_v_base; 140 u32 udca_p_base; 141 struct dma_pool *dd_cache; 142 143 /* Common EP and control data */ 144 u32 enabled_devints; 145 u32 enabled_hwepints; 146 u32 dev_status; 147 u32 realized_eps; 148 149 /* VBUS detection, pullup, and power flags */ 150 u8 vbus; 151 u8 last_vbus; 152 int pullup; 153 int poweron; 154 155 /* Work queues related to I2C support */ 156 struct work_struct pullup_job; 157 struct work_struct vbus_job; 158 struct work_struct power_job; 159 160 /* USB device peripheral - various */ 161 struct lpc32xx_ep ep[NUM_ENDPOINTS]; 162 bool enabled; 163 bool clocked; 164 bool suspended; 165 int ep0state; 166 atomic_t enabled_ep_cnt; 167 wait_queue_head_t ep_disable_wait_queue; 168 }; 169 170 /* 171 * Endpoint request 172 */ 173 struct lpc32xx_request { 174 struct usb_request req; 175 struct list_head queue; 176 struct lpc32xx_usbd_dd_gad *dd_desc_ptr; 177 bool mapped; 178 bool send_zlp; 179 }; 180 181 static inline struct lpc32xx_udc *to_udc(struct usb_gadget *g) 182 { 183 return container_of(g, struct lpc32xx_udc, gadget); 184 } 185 186 #define ep_dbg(epp, fmt, arg...) \ 187 dev_dbg(epp->udc->dev, "%s: " fmt, __func__, ## arg) 188 #define ep_err(epp, fmt, arg...) \ 189 dev_err(epp->udc->dev, "%s: " fmt, __func__, ## arg) 190 #define ep_info(epp, fmt, arg...) \ 191 dev_info(epp->udc->dev, "%s: " fmt, __func__, ## arg) 192 #define ep_warn(epp, fmt, arg...) \ 193 dev_warn(epp->udc->dev, "%s:" fmt, __func__, ## arg) 194 195 #define UDCA_BUFF_SIZE (128) 196 197 /********************************************************************** 198 * USB device controller register offsets 199 **********************************************************************/ 200 201 #define USBD_DEVINTST(x) ((x) + 0x200) 202 #define USBD_DEVINTEN(x) ((x) + 0x204) 203 #define USBD_DEVINTCLR(x) ((x) + 0x208) 204 #define USBD_DEVINTSET(x) ((x) + 0x20C) 205 #define USBD_CMDCODE(x) ((x) + 0x210) 206 #define USBD_CMDDATA(x) ((x) + 0x214) 207 #define USBD_RXDATA(x) ((x) + 0x218) 208 #define USBD_TXDATA(x) ((x) + 0x21C) 209 #define USBD_RXPLEN(x) ((x) + 0x220) 210 #define USBD_TXPLEN(x) ((x) + 0x224) 211 #define USBD_CTRL(x) ((x) + 0x228) 212 #define USBD_DEVINTPRI(x) ((x) + 0x22C) 213 #define USBD_EPINTST(x) ((x) + 0x230) 214 #define USBD_EPINTEN(x) ((x) + 0x234) 215 #define USBD_EPINTCLR(x) ((x) + 0x238) 216 #define USBD_EPINTSET(x) ((x) + 0x23C) 217 #define USBD_EPINTPRI(x) ((x) + 0x240) 218 #define USBD_REEP(x) ((x) + 0x244) 219 #define USBD_EPIND(x) ((x) + 0x248) 220 #define USBD_EPMAXPSIZE(x) ((x) + 0x24C) 221 /* DMA support registers only below */ 222 /* Set, clear, or get enabled state of the DMA request status. If 223 * enabled, an IN or OUT token will start a DMA transfer for the EP */ 224 #define USBD_DMARST(x) ((x) + 0x250) 225 #define USBD_DMARCLR(x) ((x) + 0x254) 226 #define USBD_DMARSET(x) ((x) + 0x258) 227 /* DMA UDCA head pointer */ 228 #define USBD_UDCAH(x) ((x) + 0x280) 229 /* EP DMA status, enable, and disable. This is used to specifically 230 * enabled or disable DMA for a specific EP */ 231 #define USBD_EPDMAST(x) ((x) + 0x284) 232 #define USBD_EPDMAEN(x) ((x) + 0x288) 233 #define USBD_EPDMADIS(x) ((x) + 0x28C) 234 /* DMA master interrupts enable and pending interrupts */ 235 #define USBD_DMAINTST(x) ((x) + 0x290) 236 #define USBD_DMAINTEN(x) ((x) + 0x294) 237 /* DMA end of transfer interrupt enable, disable, status */ 238 #define USBD_EOTINTST(x) ((x) + 0x2A0) 239 #define USBD_EOTINTCLR(x) ((x) + 0x2A4) 240 #define USBD_EOTINTSET(x) ((x) + 0x2A8) 241 /* New DD request interrupt enable, disable, status */ 242 #define USBD_NDDRTINTST(x) ((x) + 0x2AC) 243 #define USBD_NDDRTINTCLR(x) ((x) + 0x2B0) 244 #define USBD_NDDRTINTSET(x) ((x) + 0x2B4) 245 /* DMA error interrupt enable, disable, status */ 246 #define USBD_SYSERRTINTST(x) ((x) + 0x2B8) 247 #define USBD_SYSERRTINTCLR(x) ((x) + 0x2BC) 248 #define USBD_SYSERRTINTSET(x) ((x) + 0x2C0) 249 250 /********************************************************************** 251 * USBD_DEVINTST/USBD_DEVINTEN/USBD_DEVINTCLR/USBD_DEVINTSET/ 252 * USBD_DEVINTPRI register definitions 253 **********************************************************************/ 254 #define USBD_ERR_INT (1 << 9) 255 #define USBD_EP_RLZED (1 << 8) 256 #define USBD_TXENDPKT (1 << 7) 257 #define USBD_RXENDPKT (1 << 6) 258 #define USBD_CDFULL (1 << 5) 259 #define USBD_CCEMPTY (1 << 4) 260 #define USBD_DEV_STAT (1 << 3) 261 #define USBD_EP_SLOW (1 << 2) 262 #define USBD_EP_FAST (1 << 1) 263 #define USBD_FRAME (1 << 0) 264 265 /********************************************************************** 266 * USBD_EPINTST/USBD_EPINTEN/USBD_EPINTCLR/USBD_EPINTSET/ 267 * USBD_EPINTPRI register definitions 268 **********************************************************************/ 269 /* End point selection macro (RX) */ 270 #define USBD_RX_EP_SEL(e) (1 << ((e) << 1)) 271 272 /* End point selection macro (TX) */ 273 #define USBD_TX_EP_SEL(e) (1 << (((e) << 1) + 1)) 274 275 /********************************************************************** 276 * USBD_REEP/USBD_DMARST/USBD_DMARCLR/USBD_DMARSET/USBD_EPDMAST/ 277 * USBD_EPDMAEN/USBD_EPDMADIS/ 278 * USBD_NDDRTINTST/USBD_NDDRTINTCLR/USBD_NDDRTINTSET/ 279 * USBD_EOTINTST/USBD_EOTINTCLR/USBD_EOTINTSET/ 280 * USBD_SYSERRTINTST/USBD_SYSERRTINTCLR/USBD_SYSERRTINTSET 281 * register definitions 282 **********************************************************************/ 283 /* Endpoint selection macro */ 284 #define USBD_EP_SEL(e) (1 << (e)) 285 286 /********************************************************************** 287 * SBD_DMAINTST/USBD_DMAINTEN 288 **********************************************************************/ 289 #define USBD_SYS_ERR_INT (1 << 2) 290 #define USBD_NEW_DD_INT (1 << 1) 291 #define USBD_EOT_INT (1 << 0) 292 293 /********************************************************************** 294 * USBD_RXPLEN register definitions 295 **********************************************************************/ 296 #define USBD_PKT_RDY (1 << 11) 297 #define USBD_DV (1 << 10) 298 #define USBD_PK_LEN_MASK 0x3FF 299 300 /********************************************************************** 301 * USBD_CTRL register definitions 302 **********************************************************************/ 303 #define USBD_LOG_ENDPOINT(e) ((e) << 2) 304 #define USBD_WR_EN (1 << 1) 305 #define USBD_RD_EN (1 << 0) 306 307 /********************************************************************** 308 * USBD_CMDCODE register definitions 309 **********************************************************************/ 310 #define USBD_CMD_CODE(c) ((c) << 16) 311 #define USBD_CMD_PHASE(p) ((p) << 8) 312 313 /********************************************************************** 314 * USBD_DMARST/USBD_DMARCLR/USBD_DMARSET register definitions 315 **********************************************************************/ 316 #define USBD_DMAEP(e) (1 << (e)) 317 318 /* DD (DMA Descriptor) structure, requires word alignment */ 319 struct lpc32xx_usbd_dd { 320 u32 *dd_next; 321 u32 dd_setup; 322 u32 dd_buffer_addr; 323 u32 dd_status; 324 u32 dd_iso_ps_mem_addr; 325 }; 326 327 /* dd_setup bit defines */ 328 #define DD_SETUP_ATLE_DMA_MODE 0x01 329 #define DD_SETUP_NEXT_DD_VALID 0x04 330 #define DD_SETUP_ISO_EP 0x10 331 #define DD_SETUP_PACKETLEN(n) (((n) & 0x7FF) << 5) 332 #define DD_SETUP_DMALENBYTES(n) (((n) & 0xFFFF) << 16) 333 334 /* dd_status bit defines */ 335 #define DD_STATUS_DD_RETIRED 0x01 336 #define DD_STATUS_STS_MASK 0x1E 337 #define DD_STATUS_STS_NS 0x00 /* Not serviced */ 338 #define DD_STATUS_STS_BS 0x02 /* Being serviced */ 339 #define DD_STATUS_STS_NC 0x04 /* Normal completion */ 340 #define DD_STATUS_STS_DUR 0x06 /* Data underrun (short packet) */ 341 #define DD_STATUS_STS_DOR 0x08 /* Data overrun */ 342 #define DD_STATUS_STS_SE 0x12 /* System error */ 343 #define DD_STATUS_PKT_VAL 0x20 /* Packet valid */ 344 #define DD_STATUS_LSB_EX 0x40 /* LS byte extracted (ATLE) */ 345 #define DD_STATUS_MSB_EX 0x80 /* MS byte extracted (ATLE) */ 346 #define DD_STATUS_MLEN(n) (((n) >> 8) & 0x3F) 347 #define DD_STATUS_CURDMACNT(n) (((n) >> 16) & 0xFFFF) 348 349 /* 350 * 351 * Protocol engine bits below 352 * 353 */ 354 /* Device Interrupt Bit Definitions */ 355 #define FRAME_INT 0x00000001 356 #define EP_FAST_INT 0x00000002 357 #define EP_SLOW_INT 0x00000004 358 #define DEV_STAT_INT 0x00000008 359 #define CCEMTY_INT 0x00000010 360 #define CDFULL_INT 0x00000020 361 #define RxENDPKT_INT 0x00000040 362 #define TxENDPKT_INT 0x00000080 363 #define EP_RLZED_INT 0x00000100 364 #define ERR_INT 0x00000200 365 366 /* Rx & Tx Packet Length Definitions */ 367 #define PKT_LNGTH_MASK 0x000003FF 368 #define PKT_DV 0x00000400 369 #define PKT_RDY 0x00000800 370 371 /* USB Control Definitions */ 372 #define CTRL_RD_EN 0x00000001 373 #define CTRL_WR_EN 0x00000002 374 375 /* Command Codes */ 376 #define CMD_SET_ADDR 0x00D00500 377 #define CMD_CFG_DEV 0x00D80500 378 #define CMD_SET_MODE 0x00F30500 379 #define CMD_RD_FRAME 0x00F50500 380 #define DAT_RD_FRAME 0x00F50200 381 #define CMD_RD_TEST 0x00FD0500 382 #define DAT_RD_TEST 0x00FD0200 383 #define CMD_SET_DEV_STAT 0x00FE0500 384 #define CMD_GET_DEV_STAT 0x00FE0500 385 #define DAT_GET_DEV_STAT 0x00FE0200 386 #define CMD_GET_ERR_CODE 0x00FF0500 387 #define DAT_GET_ERR_CODE 0x00FF0200 388 #define CMD_RD_ERR_STAT 0x00FB0500 389 #define DAT_RD_ERR_STAT 0x00FB0200 390 #define DAT_WR_BYTE(x) (0x00000100 | ((x) << 16)) 391 #define CMD_SEL_EP(x) (0x00000500 | ((x) << 16)) 392 #define DAT_SEL_EP(x) (0x00000200 | ((x) << 16)) 393 #define CMD_SEL_EP_CLRI(x) (0x00400500 | ((x) << 16)) 394 #define DAT_SEL_EP_CLRI(x) (0x00400200 | ((x) << 16)) 395 #define CMD_SET_EP_STAT(x) (0x00400500 | ((x) << 16)) 396 #define CMD_CLR_BUF 0x00F20500 397 #define DAT_CLR_BUF 0x00F20200 398 #define CMD_VALID_BUF 0x00FA0500 399 400 /* Device Address Register Definitions */ 401 #define DEV_ADDR_MASK 0x7F 402 #define DEV_EN 0x80 403 404 /* Device Configure Register Definitions */ 405 #define CONF_DVICE 0x01 406 407 /* Device Mode Register Definitions */ 408 #define AP_CLK 0x01 409 #define INAK_CI 0x02 410 #define INAK_CO 0x04 411 #define INAK_II 0x08 412 #define INAK_IO 0x10 413 #define INAK_BI 0x20 414 #define INAK_BO 0x40 415 416 /* Device Status Register Definitions */ 417 #define DEV_CON 0x01 418 #define DEV_CON_CH 0x02 419 #define DEV_SUS 0x04 420 #define DEV_SUS_CH 0x08 421 #define DEV_RST 0x10 422 423 /* Error Code Register Definitions */ 424 #define ERR_EC_MASK 0x0F 425 #define ERR_EA 0x10 426 427 /* Error Status Register Definitions */ 428 #define ERR_PID 0x01 429 #define ERR_UEPKT 0x02 430 #define ERR_DCRC 0x04 431 #define ERR_TIMOUT 0x08 432 #define ERR_EOP 0x10 433 #define ERR_B_OVRN 0x20 434 #define ERR_BTSTF 0x40 435 #define ERR_TGL 0x80 436 437 /* Endpoint Select Register Definitions */ 438 #define EP_SEL_F 0x01 439 #define EP_SEL_ST 0x02 440 #define EP_SEL_STP 0x04 441 #define EP_SEL_PO 0x08 442 #define EP_SEL_EPN 0x10 443 #define EP_SEL_B_1_FULL 0x20 444 #define EP_SEL_B_2_FULL 0x40 445 446 /* Endpoint Status Register Definitions */ 447 #define EP_STAT_ST 0x01 448 #define EP_STAT_DA 0x20 449 #define EP_STAT_RF_MO 0x40 450 #define EP_STAT_CND_ST 0x80 451 452 /* Clear Buffer Register Definitions */ 453 #define CLR_BUF_PO 0x01 454 455 /* DMA Interrupt Bit Definitions */ 456 #define EOT_INT 0x01 457 #define NDD_REQ_INT 0x02 458 #define SYS_ERR_INT 0x04 459 460 #define DRIVER_VERSION "1.03" 461 static const char driver_name[] = "lpc32xx_udc"; 462 463 /* 464 * 465 * proc interface support 466 * 467 */ 468 #ifdef CONFIG_USB_GADGET_DEBUG_FILES 469 static char *epnames[] = {"INT", "ISO", "BULK", "CTRL"}; 470 static const char debug_filename[] = "driver/udc"; 471 472 static void proc_ep_show(struct seq_file *s, struct lpc32xx_ep *ep) 473 { 474 struct lpc32xx_request *req; 475 476 seq_printf(s, "\n"); 477 seq_printf(s, "%12s, maxpacket %4d %3s", 478 ep->ep.name, ep->ep.maxpacket, 479 ep->is_in ? "in" : "out"); 480 seq_printf(s, " type %4s", epnames[ep->eptype]); 481 seq_printf(s, " ints: %12d", ep->totalints); 482 483 if (list_empty(&ep->queue)) 484 seq_printf(s, "\t(queue empty)\n"); 485 else { 486 list_for_each_entry(req, &ep->queue, queue) { 487 u32 length = req->req.actual; 488 489 seq_printf(s, "\treq %p len %d/%d buf %p\n", 490 &req->req, length, 491 req->req.length, req->req.buf); 492 } 493 } 494 } 495 496 static int proc_udc_show(struct seq_file *s, void *unused) 497 { 498 struct lpc32xx_udc *udc = s->private; 499 struct lpc32xx_ep *ep; 500 unsigned long flags; 501 502 seq_printf(s, "%s: version %s\n", driver_name, DRIVER_VERSION); 503 504 spin_lock_irqsave(&udc->lock, flags); 505 506 seq_printf(s, "vbus %s, pullup %s, %s powered%s, gadget %s\n\n", 507 udc->vbus ? "present" : "off", 508 udc->enabled ? (udc->vbus ? "active" : "enabled") : 509 "disabled", 510 udc->gadget.is_selfpowered ? "self" : "VBUS", 511 udc->suspended ? ", suspended" : "", 512 udc->driver ? udc->driver->driver.name : "(none)"); 513 514 if (udc->enabled && udc->vbus) { 515 proc_ep_show(s, &udc->ep[0]); 516 list_for_each_entry(ep, &udc->gadget.ep_list, ep.ep_list) 517 proc_ep_show(s, ep); 518 } 519 520 spin_unlock_irqrestore(&udc->lock, flags); 521 522 return 0; 523 } 524 525 static int proc_udc_open(struct inode *inode, struct file *file) 526 { 527 return single_open(file, proc_udc_show, PDE_DATA(inode)); 528 } 529 530 static const struct file_operations proc_ops = { 531 .owner = THIS_MODULE, 532 .open = proc_udc_open, 533 .read = seq_read, 534 .llseek = seq_lseek, 535 .release = single_release, 536 }; 537 538 static void create_debug_file(struct lpc32xx_udc *udc) 539 { 540 udc->pde = debugfs_create_file(debug_filename, 0, NULL, udc, &proc_ops); 541 } 542 543 static void remove_debug_file(struct lpc32xx_udc *udc) 544 { 545 debugfs_remove(udc->pde); 546 } 547 548 #else 549 static inline void create_debug_file(struct lpc32xx_udc *udc) {} 550 static inline void remove_debug_file(struct lpc32xx_udc *udc) {} 551 #endif 552 553 /* Primary initialization sequence for the ISP1301 transceiver */ 554 static void isp1301_udc_configure(struct lpc32xx_udc *udc) 555 { 556 /* LPC32XX only supports DAT_SE0 USB mode */ 557 /* This sequence is important */ 558 559 /* Disable transparent UART mode first */ 560 i2c_smbus_write_byte_data(udc->isp1301_i2c_client, 561 (ISP1301_I2C_MODE_CONTROL_1 | ISP1301_I2C_REG_CLEAR_ADDR), 562 MC1_UART_EN); 563 564 /* Set full speed and SE0 mode */ 565 i2c_smbus_write_byte_data(udc->isp1301_i2c_client, 566 (ISP1301_I2C_MODE_CONTROL_1 | ISP1301_I2C_REG_CLEAR_ADDR), ~0); 567 i2c_smbus_write_byte_data(udc->isp1301_i2c_client, 568 ISP1301_I2C_MODE_CONTROL_1, (MC1_SPEED_REG | MC1_DAT_SE0)); 569 570 /* 571 * The PSW_OE enable bit state is reversed in the ISP1301 User's Guide 572 */ 573 i2c_smbus_write_byte_data(udc->isp1301_i2c_client, 574 (ISP1301_I2C_MODE_CONTROL_2 | ISP1301_I2C_REG_CLEAR_ADDR), ~0); 575 i2c_smbus_write_byte_data(udc->isp1301_i2c_client, 576 ISP1301_I2C_MODE_CONTROL_2, (MC2_BI_DI | MC2_SPD_SUSP_CTRL)); 577 578 /* Driver VBUS_DRV high or low depending on board setup */ 579 if (udc->board->vbus_drv_pol != 0) 580 i2c_smbus_write_byte_data(udc->isp1301_i2c_client, 581 ISP1301_I2C_OTG_CONTROL_1, OTG1_VBUS_DRV); 582 else 583 i2c_smbus_write_byte_data(udc->isp1301_i2c_client, 584 ISP1301_I2C_OTG_CONTROL_1 | ISP1301_I2C_REG_CLEAR_ADDR, 585 OTG1_VBUS_DRV); 586 587 /* Bi-directional mode with suspend control 588 * Enable both pulldowns for now - the pullup will be enable when VBUS 589 * is detected */ 590 i2c_smbus_write_byte_data(udc->isp1301_i2c_client, 591 (ISP1301_I2C_OTG_CONTROL_1 | ISP1301_I2C_REG_CLEAR_ADDR), ~0); 592 i2c_smbus_write_byte_data(udc->isp1301_i2c_client, 593 ISP1301_I2C_OTG_CONTROL_1, 594 (0 | OTG1_DM_PULLDOWN | OTG1_DP_PULLDOWN)); 595 596 /* Discharge VBUS (just in case) */ 597 i2c_smbus_write_byte_data(udc->isp1301_i2c_client, 598 ISP1301_I2C_OTG_CONTROL_1, OTG1_VBUS_DISCHRG); 599 msleep(1); 600 i2c_smbus_write_byte_data(udc->isp1301_i2c_client, 601 (ISP1301_I2C_OTG_CONTROL_1 | ISP1301_I2C_REG_CLEAR_ADDR), 602 OTG1_VBUS_DISCHRG); 603 604 /* Clear and enable VBUS high edge interrupt */ 605 i2c_smbus_write_byte_data(udc->isp1301_i2c_client, 606 ISP1301_I2C_INTERRUPT_LATCH | ISP1301_I2C_REG_CLEAR_ADDR, ~0); 607 i2c_smbus_write_byte_data(udc->isp1301_i2c_client, 608 ISP1301_I2C_INTERRUPT_FALLING | ISP1301_I2C_REG_CLEAR_ADDR, ~0); 609 i2c_smbus_write_byte_data(udc->isp1301_i2c_client, 610 ISP1301_I2C_INTERRUPT_FALLING, INT_VBUS_VLD); 611 i2c_smbus_write_byte_data(udc->isp1301_i2c_client, 612 ISP1301_I2C_INTERRUPT_RISING | ISP1301_I2C_REG_CLEAR_ADDR, ~0); 613 i2c_smbus_write_byte_data(udc->isp1301_i2c_client, 614 ISP1301_I2C_INTERRUPT_RISING, INT_VBUS_VLD); 615 616 dev_info(udc->dev, "ISP1301 Vendor ID : 0x%04x\n", 617 i2c_smbus_read_word_data(udc->isp1301_i2c_client, 0x00)); 618 dev_info(udc->dev, "ISP1301 Product ID : 0x%04x\n", 619 i2c_smbus_read_word_data(udc->isp1301_i2c_client, 0x02)); 620 dev_info(udc->dev, "ISP1301 Version ID : 0x%04x\n", 621 i2c_smbus_read_word_data(udc->isp1301_i2c_client, 0x14)); 622 } 623 624 /* Enables or disables the USB device pullup via the ISP1301 transceiver */ 625 static void isp1301_pullup_set(struct lpc32xx_udc *udc) 626 { 627 if (udc->pullup) 628 /* Enable pullup for bus signalling */ 629 i2c_smbus_write_byte_data(udc->isp1301_i2c_client, 630 ISP1301_I2C_OTG_CONTROL_1, OTG1_DP_PULLUP); 631 else 632 /* Enable pullup for bus signalling */ 633 i2c_smbus_write_byte_data(udc->isp1301_i2c_client, 634 ISP1301_I2C_OTG_CONTROL_1 | ISP1301_I2C_REG_CLEAR_ADDR, 635 OTG1_DP_PULLUP); 636 } 637 638 static void pullup_work(struct work_struct *work) 639 { 640 struct lpc32xx_udc *udc = 641 container_of(work, struct lpc32xx_udc, pullup_job); 642 643 isp1301_pullup_set(udc); 644 } 645 646 static void isp1301_pullup_enable(struct lpc32xx_udc *udc, int en_pullup, 647 int block) 648 { 649 if (en_pullup == udc->pullup) 650 return; 651 652 udc->pullup = en_pullup; 653 if (block) 654 isp1301_pullup_set(udc); 655 else 656 /* defer slow i2c pull up setting */ 657 schedule_work(&udc->pullup_job); 658 } 659 660 #ifdef CONFIG_PM 661 /* Powers up or down the ISP1301 transceiver */ 662 static void isp1301_set_powerstate(struct lpc32xx_udc *udc, int enable) 663 { 664 if (enable != 0) 665 /* Power up ISP1301 - this ISP1301 will automatically wakeup 666 when VBUS is detected */ 667 i2c_smbus_write_byte_data(udc->isp1301_i2c_client, 668 ISP1301_I2C_MODE_CONTROL_2 | ISP1301_I2C_REG_CLEAR_ADDR, 669 MC2_GLOBAL_PWR_DN); 670 else 671 /* Power down ISP1301 */ 672 i2c_smbus_write_byte_data(udc->isp1301_i2c_client, 673 ISP1301_I2C_MODE_CONTROL_2, MC2_GLOBAL_PWR_DN); 674 } 675 676 static void power_work(struct work_struct *work) 677 { 678 struct lpc32xx_udc *udc = 679 container_of(work, struct lpc32xx_udc, power_job); 680 681 isp1301_set_powerstate(udc, udc->poweron); 682 } 683 #endif 684 685 /* 686 * 687 * USB protocol engine command/data read/write helper functions 688 * 689 */ 690 /* Issues a single command to the USB device state machine */ 691 static void udc_protocol_cmd_w(struct lpc32xx_udc *udc, u32 cmd) 692 { 693 u32 pass = 0; 694 int to; 695 696 /* EP may lock on CLRI if this read isn't done */ 697 u32 tmp = readl(USBD_DEVINTST(udc->udp_baseaddr)); 698 (void) tmp; 699 700 while (pass == 0) { 701 writel(USBD_CCEMPTY, USBD_DEVINTCLR(udc->udp_baseaddr)); 702 703 /* Write command code */ 704 writel(cmd, USBD_CMDCODE(udc->udp_baseaddr)); 705 to = 10000; 706 while (((readl(USBD_DEVINTST(udc->udp_baseaddr)) & 707 USBD_CCEMPTY) == 0) && (to > 0)) { 708 to--; 709 } 710 711 if (to > 0) 712 pass = 1; 713 714 cpu_relax(); 715 } 716 } 717 718 /* Issues 2 commands (or command and data) to the USB device state machine */ 719 static inline void udc_protocol_cmd_data_w(struct lpc32xx_udc *udc, u32 cmd, 720 u32 data) 721 { 722 udc_protocol_cmd_w(udc, cmd); 723 udc_protocol_cmd_w(udc, data); 724 } 725 726 /* Issues a single command to the USB device state machine and reads 727 * response data */ 728 static u32 udc_protocol_cmd_r(struct lpc32xx_udc *udc, u32 cmd) 729 { 730 u32 tmp; 731 int to = 1000; 732 733 /* Write a command and read data from the protocol engine */ 734 writel((USBD_CDFULL | USBD_CCEMPTY), 735 USBD_DEVINTCLR(udc->udp_baseaddr)); 736 737 /* Write command code */ 738 udc_protocol_cmd_w(udc, cmd); 739 740 tmp = readl(USBD_DEVINTST(udc->udp_baseaddr)); 741 while ((!(readl(USBD_DEVINTST(udc->udp_baseaddr)) & USBD_CDFULL)) 742 && (to > 0)) 743 to--; 744 if (!to) 745 dev_dbg(udc->dev, 746 "Protocol engine didn't receive response (CDFULL)\n"); 747 748 return readl(USBD_CMDDATA(udc->udp_baseaddr)); 749 } 750 751 /* 752 * 753 * USB device interrupt mask support functions 754 * 755 */ 756 /* Enable one or more USB device interrupts */ 757 static inline void uda_enable_devint(struct lpc32xx_udc *udc, u32 devmask) 758 { 759 udc->enabled_devints |= devmask; 760 writel(udc->enabled_devints, USBD_DEVINTEN(udc->udp_baseaddr)); 761 } 762 763 /* Disable one or more USB device interrupts */ 764 static inline void uda_disable_devint(struct lpc32xx_udc *udc, u32 mask) 765 { 766 udc->enabled_devints &= ~mask; 767 writel(udc->enabled_devints, USBD_DEVINTEN(udc->udp_baseaddr)); 768 } 769 770 /* Clear one or more USB device interrupts */ 771 static inline void uda_clear_devint(struct lpc32xx_udc *udc, u32 mask) 772 { 773 writel(mask, USBD_DEVINTCLR(udc->udp_baseaddr)); 774 } 775 776 /* 777 * 778 * Endpoint interrupt disable/enable functions 779 * 780 */ 781 /* Enable one or more USB endpoint interrupts */ 782 static void uda_enable_hwepint(struct lpc32xx_udc *udc, u32 hwep) 783 { 784 udc->enabled_hwepints |= (1 << hwep); 785 writel(udc->enabled_hwepints, USBD_EPINTEN(udc->udp_baseaddr)); 786 } 787 788 /* Disable one or more USB endpoint interrupts */ 789 static void uda_disable_hwepint(struct lpc32xx_udc *udc, u32 hwep) 790 { 791 udc->enabled_hwepints &= ~(1 << hwep); 792 writel(udc->enabled_hwepints, USBD_EPINTEN(udc->udp_baseaddr)); 793 } 794 795 /* Clear one or more USB endpoint interrupts */ 796 static inline void uda_clear_hwepint(struct lpc32xx_udc *udc, u32 hwep) 797 { 798 writel((1 << hwep), USBD_EPINTCLR(udc->udp_baseaddr)); 799 } 800 801 /* Enable DMA for the HW channel */ 802 static inline void udc_ep_dma_enable(struct lpc32xx_udc *udc, u32 hwep) 803 { 804 writel((1 << hwep), USBD_EPDMAEN(udc->udp_baseaddr)); 805 } 806 807 /* Disable DMA for the HW channel */ 808 static inline void udc_ep_dma_disable(struct lpc32xx_udc *udc, u32 hwep) 809 { 810 writel((1 << hwep), USBD_EPDMADIS(udc->udp_baseaddr)); 811 } 812 813 /* 814 * 815 * Endpoint realize/unrealize functions 816 * 817 */ 818 /* Before an endpoint can be used, it needs to be realized 819 * in the USB protocol engine - this realizes the endpoint. 820 * The interrupt (FIFO or DMA) is not enabled with this function */ 821 static void udc_realize_hwep(struct lpc32xx_udc *udc, u32 hwep, 822 u32 maxpacket) 823 { 824 int to = 1000; 825 826 writel(USBD_EP_RLZED, USBD_DEVINTCLR(udc->udp_baseaddr)); 827 writel(hwep, USBD_EPIND(udc->udp_baseaddr)); 828 udc->realized_eps |= (1 << hwep); 829 writel(udc->realized_eps, USBD_REEP(udc->udp_baseaddr)); 830 writel(maxpacket, USBD_EPMAXPSIZE(udc->udp_baseaddr)); 831 832 /* Wait until endpoint is realized in hardware */ 833 while ((!(readl(USBD_DEVINTST(udc->udp_baseaddr)) & 834 USBD_EP_RLZED)) && (to > 0)) 835 to--; 836 if (!to) 837 dev_dbg(udc->dev, "EP not correctly realized in hardware\n"); 838 839 writel(USBD_EP_RLZED, USBD_DEVINTCLR(udc->udp_baseaddr)); 840 } 841 842 /* Unrealize an EP */ 843 static void udc_unrealize_hwep(struct lpc32xx_udc *udc, u32 hwep) 844 { 845 udc->realized_eps &= ~(1 << hwep); 846 writel(udc->realized_eps, USBD_REEP(udc->udp_baseaddr)); 847 } 848 849 /* 850 * 851 * Endpoint support functions 852 * 853 */ 854 /* Select and clear endpoint interrupt */ 855 static u32 udc_selep_clrint(struct lpc32xx_udc *udc, u32 hwep) 856 { 857 udc_protocol_cmd_w(udc, CMD_SEL_EP_CLRI(hwep)); 858 return udc_protocol_cmd_r(udc, DAT_SEL_EP_CLRI(hwep)); 859 } 860 861 /* Disables the endpoint in the USB protocol engine */ 862 static void udc_disable_hwep(struct lpc32xx_udc *udc, u32 hwep) 863 { 864 udc_protocol_cmd_data_w(udc, CMD_SET_EP_STAT(hwep), 865 DAT_WR_BYTE(EP_STAT_DA)); 866 } 867 868 /* Stalls the endpoint - endpoint will return STALL */ 869 static void udc_stall_hwep(struct lpc32xx_udc *udc, u32 hwep) 870 { 871 udc_protocol_cmd_data_w(udc, CMD_SET_EP_STAT(hwep), 872 DAT_WR_BYTE(EP_STAT_ST)); 873 } 874 875 /* Clear stall or reset endpoint */ 876 static void udc_clrstall_hwep(struct lpc32xx_udc *udc, u32 hwep) 877 { 878 udc_protocol_cmd_data_w(udc, CMD_SET_EP_STAT(hwep), 879 DAT_WR_BYTE(0)); 880 } 881 882 /* Select an endpoint for endpoint status, clear, validate */ 883 static void udc_select_hwep(struct lpc32xx_udc *udc, u32 hwep) 884 { 885 udc_protocol_cmd_w(udc, CMD_SEL_EP(hwep)); 886 } 887 888 /* 889 * 890 * Endpoint buffer management functions 891 * 892 */ 893 /* Clear the current endpoint's buffer */ 894 static void udc_clr_buffer_hwep(struct lpc32xx_udc *udc, u32 hwep) 895 { 896 udc_select_hwep(udc, hwep); 897 udc_protocol_cmd_w(udc, CMD_CLR_BUF); 898 } 899 900 /* Validate the current endpoint's buffer */ 901 static void udc_val_buffer_hwep(struct lpc32xx_udc *udc, u32 hwep) 902 { 903 udc_select_hwep(udc, hwep); 904 udc_protocol_cmd_w(udc, CMD_VALID_BUF); 905 } 906 907 static inline u32 udc_clearep_getsts(struct lpc32xx_udc *udc, u32 hwep) 908 { 909 /* Clear EP interrupt */ 910 uda_clear_hwepint(udc, hwep); 911 return udc_selep_clrint(udc, hwep); 912 } 913 914 /* 915 * 916 * USB EP DMA support 917 * 918 */ 919 /* Allocate a DMA Descriptor */ 920 static struct lpc32xx_usbd_dd_gad *udc_dd_alloc(struct lpc32xx_udc *udc) 921 { 922 dma_addr_t dma; 923 struct lpc32xx_usbd_dd_gad *dd; 924 925 dd = (struct lpc32xx_usbd_dd_gad *) dma_pool_alloc( 926 udc->dd_cache, (GFP_KERNEL | GFP_DMA), &dma); 927 if (dd) 928 dd->this_dma = dma; 929 930 return dd; 931 } 932 933 /* Free a DMA Descriptor */ 934 static void udc_dd_free(struct lpc32xx_udc *udc, struct lpc32xx_usbd_dd_gad *dd) 935 { 936 dma_pool_free(udc->dd_cache, dd, dd->this_dma); 937 } 938 939 /* 940 * 941 * USB setup and shutdown functions 942 * 943 */ 944 /* Enables or disables most of the USB system clocks when low power mode is 945 * needed. Clocks are typically started on a connection event, and disabled 946 * when a cable is disconnected */ 947 static void udc_clk_set(struct lpc32xx_udc *udc, int enable) 948 { 949 if (enable != 0) { 950 if (udc->clocked) 951 return; 952 953 udc->clocked = 1; 954 clk_prepare_enable(udc->usb_slv_clk); 955 } else { 956 if (!udc->clocked) 957 return; 958 959 udc->clocked = 0; 960 clk_disable_unprepare(udc->usb_slv_clk); 961 } 962 } 963 964 /* Set/reset USB device address */ 965 static void udc_set_address(struct lpc32xx_udc *udc, u32 addr) 966 { 967 /* Address will be latched at the end of the status phase, or 968 latched immediately if function is called twice */ 969 udc_protocol_cmd_data_w(udc, CMD_SET_ADDR, 970 DAT_WR_BYTE(DEV_EN | addr)); 971 } 972 973 /* Setup up a IN request for DMA transfer - this consists of determining the 974 * list of DMA addresses for the transfer, allocating DMA Descriptors, 975 * installing the DD into the UDCA, and then enabling the DMA for that EP */ 976 static int udc_ep_in_req_dma(struct lpc32xx_udc *udc, struct lpc32xx_ep *ep) 977 { 978 struct lpc32xx_request *req; 979 u32 hwep = ep->hwep_num; 980 981 ep->req_pending = 1; 982 983 /* There will always be a request waiting here */ 984 req = list_entry(ep->queue.next, struct lpc32xx_request, queue); 985 986 /* Place the DD Descriptor into the UDCA */ 987 udc->udca_v_base[hwep] = req->dd_desc_ptr->this_dma; 988 989 /* Enable DMA and interrupt for the HW EP */ 990 udc_ep_dma_enable(udc, hwep); 991 992 /* Clear ZLP if last packet is not of MAXP size */ 993 if (req->req.length % ep->ep.maxpacket) 994 req->send_zlp = 0; 995 996 return 0; 997 } 998 999 /* Setup up a OUT request for DMA transfer - this consists of determining the 1000 * list of DMA addresses for the transfer, allocating DMA Descriptors, 1001 * installing the DD into the UDCA, and then enabling the DMA for that EP */ 1002 static int udc_ep_out_req_dma(struct lpc32xx_udc *udc, struct lpc32xx_ep *ep) 1003 { 1004 struct lpc32xx_request *req; 1005 u32 hwep = ep->hwep_num; 1006 1007 ep->req_pending = 1; 1008 1009 /* There will always be a request waiting here */ 1010 req = list_entry(ep->queue.next, struct lpc32xx_request, queue); 1011 1012 /* Place the DD Descriptor into the UDCA */ 1013 udc->udca_v_base[hwep] = req->dd_desc_ptr->this_dma; 1014 1015 /* Enable DMA and interrupt for the HW EP */ 1016 udc_ep_dma_enable(udc, hwep); 1017 return 0; 1018 } 1019 1020 static void udc_disable(struct lpc32xx_udc *udc) 1021 { 1022 u32 i; 1023 1024 /* Disable device */ 1025 udc_protocol_cmd_data_w(udc, CMD_CFG_DEV, DAT_WR_BYTE(0)); 1026 udc_protocol_cmd_data_w(udc, CMD_SET_DEV_STAT, DAT_WR_BYTE(0)); 1027 1028 /* Disable all device interrupts (including EP0) */ 1029 uda_disable_devint(udc, 0x3FF); 1030 1031 /* Disable and reset all endpoint interrupts */ 1032 for (i = 0; i < 32; i++) { 1033 uda_disable_hwepint(udc, i); 1034 uda_clear_hwepint(udc, i); 1035 udc_disable_hwep(udc, i); 1036 udc_unrealize_hwep(udc, i); 1037 udc->udca_v_base[i] = 0; 1038 1039 /* Disable and clear all interrupts and DMA */ 1040 udc_ep_dma_disable(udc, i); 1041 writel((1 << i), USBD_EOTINTCLR(udc->udp_baseaddr)); 1042 writel((1 << i), USBD_NDDRTINTCLR(udc->udp_baseaddr)); 1043 writel((1 << i), USBD_SYSERRTINTCLR(udc->udp_baseaddr)); 1044 writel((1 << i), USBD_DMARCLR(udc->udp_baseaddr)); 1045 } 1046 1047 /* Disable DMA interrupts */ 1048 writel(0, USBD_DMAINTEN(udc->udp_baseaddr)); 1049 1050 writel(0, USBD_UDCAH(udc->udp_baseaddr)); 1051 } 1052 1053 static void udc_enable(struct lpc32xx_udc *udc) 1054 { 1055 u32 i; 1056 struct lpc32xx_ep *ep = &udc->ep[0]; 1057 1058 /* Start with known state */ 1059 udc_disable(udc); 1060 1061 /* Enable device */ 1062 udc_protocol_cmd_data_w(udc, CMD_SET_DEV_STAT, DAT_WR_BYTE(DEV_CON)); 1063 1064 /* EP interrupts on high priority, FRAME interrupt on low priority */ 1065 writel(USBD_EP_FAST, USBD_DEVINTPRI(udc->udp_baseaddr)); 1066 writel(0xFFFF, USBD_EPINTPRI(udc->udp_baseaddr)); 1067 1068 /* Clear any pending device interrupts */ 1069 writel(0x3FF, USBD_DEVINTCLR(udc->udp_baseaddr)); 1070 1071 /* Setup UDCA - not yet used (DMA) */ 1072 writel(udc->udca_p_base, USBD_UDCAH(udc->udp_baseaddr)); 1073 1074 /* Only enable EP0 in and out for now, EP0 only works in FIFO mode */ 1075 for (i = 0; i <= 1; i++) { 1076 udc_realize_hwep(udc, i, ep->ep.maxpacket); 1077 uda_enable_hwepint(udc, i); 1078 udc_select_hwep(udc, i); 1079 udc_clrstall_hwep(udc, i); 1080 udc_clr_buffer_hwep(udc, i); 1081 } 1082 1083 /* Device interrupt setup */ 1084 uda_clear_devint(udc, (USBD_ERR_INT | USBD_DEV_STAT | USBD_EP_SLOW | 1085 USBD_EP_FAST)); 1086 uda_enable_devint(udc, (USBD_ERR_INT | USBD_DEV_STAT | USBD_EP_SLOW | 1087 USBD_EP_FAST)); 1088 1089 /* Set device address to 0 - called twice to force a latch in the USB 1090 engine without the need of a setup packet status closure */ 1091 udc_set_address(udc, 0); 1092 udc_set_address(udc, 0); 1093 1094 /* Enable master DMA interrupts */ 1095 writel((USBD_SYS_ERR_INT | USBD_EOT_INT), 1096 USBD_DMAINTEN(udc->udp_baseaddr)); 1097 1098 udc->dev_status = 0; 1099 } 1100 1101 /* 1102 * 1103 * USB device board specific events handled via callbacks 1104 * 1105 */ 1106 /* Connection change event - notify board function of change */ 1107 static void uda_power_event(struct lpc32xx_udc *udc, u32 conn) 1108 { 1109 /* Just notify of a connection change event (optional) */ 1110 if (udc->board->conn_chgb != NULL) 1111 udc->board->conn_chgb(conn); 1112 } 1113 1114 /* Suspend/resume event - notify board function of change */ 1115 static void uda_resm_susp_event(struct lpc32xx_udc *udc, u32 conn) 1116 { 1117 /* Just notify of a Suspend/resume change event (optional) */ 1118 if (udc->board->susp_chgb != NULL) 1119 udc->board->susp_chgb(conn); 1120 1121 if (conn) 1122 udc->suspended = 0; 1123 else 1124 udc->suspended = 1; 1125 } 1126 1127 /* Remote wakeup enable/disable - notify board function of change */ 1128 static void uda_remwkp_cgh(struct lpc32xx_udc *udc) 1129 { 1130 if (udc->board->rmwk_chgb != NULL) 1131 udc->board->rmwk_chgb(udc->dev_status & 1132 (1 << USB_DEVICE_REMOTE_WAKEUP)); 1133 } 1134 1135 /* Reads data from FIFO, adjusts for alignment and data size */ 1136 static void udc_pop_fifo(struct lpc32xx_udc *udc, u8 *data, u32 bytes) 1137 { 1138 int n, i, bl; 1139 u16 *p16; 1140 u32 *p32, tmp, cbytes; 1141 1142 /* Use optimal data transfer method based on source address and size */ 1143 switch (((u32) data) & 0x3) { 1144 case 0: /* 32-bit aligned */ 1145 p32 = (u32 *) data; 1146 cbytes = (bytes & ~0x3); 1147 1148 /* Copy 32-bit aligned data first */ 1149 for (n = 0; n < cbytes; n += 4) 1150 *p32++ = readl(USBD_RXDATA(udc->udp_baseaddr)); 1151 1152 /* Handle any remaining bytes */ 1153 bl = bytes - cbytes; 1154 if (bl) { 1155 tmp = readl(USBD_RXDATA(udc->udp_baseaddr)); 1156 for (n = 0; n < bl; n++) 1157 data[cbytes + n] = ((tmp >> (n * 8)) & 0xFF); 1158 1159 } 1160 break; 1161 1162 case 1: /* 8-bit aligned */ 1163 case 3: 1164 /* Each byte has to be handled independently */ 1165 for (n = 0; n < bytes; n += 4) { 1166 tmp = readl(USBD_RXDATA(udc->udp_baseaddr)); 1167 1168 bl = bytes - n; 1169 if (bl > 3) 1170 bl = 3; 1171 1172 for (i = 0; i < bl; i++) 1173 data[n + i] = (u8) ((tmp >> (n * 8)) & 0xFF); 1174 } 1175 break; 1176 1177 case 2: /* 16-bit aligned */ 1178 p16 = (u16 *) data; 1179 cbytes = (bytes & ~0x3); 1180 1181 /* Copy 32-bit sized objects first with 16-bit alignment */ 1182 for (n = 0; n < cbytes; n += 4) { 1183 tmp = readl(USBD_RXDATA(udc->udp_baseaddr)); 1184 *p16++ = (u16)(tmp & 0xFFFF); 1185 *p16++ = (u16)((tmp >> 16) & 0xFFFF); 1186 } 1187 1188 /* Handle any remaining bytes */ 1189 bl = bytes - cbytes; 1190 if (bl) { 1191 tmp = readl(USBD_RXDATA(udc->udp_baseaddr)); 1192 for (n = 0; n < bl; n++) 1193 data[cbytes + n] = ((tmp >> (n * 8)) & 0xFF); 1194 } 1195 break; 1196 } 1197 } 1198 1199 /* Read data from the FIFO for an endpoint. This function is for endpoints (such 1200 * as EP0) that don't use DMA. This function should only be called if a packet 1201 * is known to be ready to read for the endpoint. Note that the endpoint must 1202 * be selected in the protocol engine prior to this call. */ 1203 static u32 udc_read_hwep(struct lpc32xx_udc *udc, u32 hwep, u32 *data, 1204 u32 bytes) 1205 { 1206 u32 tmpv; 1207 int to = 1000; 1208 u32 tmp, hwrep = ((hwep & 0x1E) << 1) | CTRL_RD_EN; 1209 1210 /* Setup read of endpoint */ 1211 writel(hwrep, USBD_CTRL(udc->udp_baseaddr)); 1212 1213 /* Wait until packet is ready */ 1214 while ((((tmpv = readl(USBD_RXPLEN(udc->udp_baseaddr))) & 1215 PKT_RDY) == 0) && (to > 0)) 1216 to--; 1217 if (!to) 1218 dev_dbg(udc->dev, "No packet ready on FIFO EP read\n"); 1219 1220 /* Mask out count */ 1221 tmp = tmpv & PKT_LNGTH_MASK; 1222 if (bytes < tmp) 1223 tmp = bytes; 1224 1225 if ((tmp > 0) && (data != NULL)) 1226 udc_pop_fifo(udc, (u8 *) data, tmp); 1227 1228 writel(((hwep & 0x1E) << 1), USBD_CTRL(udc->udp_baseaddr)); 1229 1230 /* Clear the buffer */ 1231 udc_clr_buffer_hwep(udc, hwep); 1232 1233 return tmp; 1234 } 1235 1236 /* Stuffs data into the FIFO, adjusts for alignment and data size */ 1237 static void udc_stuff_fifo(struct lpc32xx_udc *udc, u8 *data, u32 bytes) 1238 { 1239 int n, i, bl; 1240 u16 *p16; 1241 u32 *p32, tmp, cbytes; 1242 1243 /* Use optimal data transfer method based on source address and size */ 1244 switch (((u32) data) & 0x3) { 1245 case 0: /* 32-bit aligned */ 1246 p32 = (u32 *) data; 1247 cbytes = (bytes & ~0x3); 1248 1249 /* Copy 32-bit aligned data first */ 1250 for (n = 0; n < cbytes; n += 4) 1251 writel(*p32++, USBD_TXDATA(udc->udp_baseaddr)); 1252 1253 /* Handle any remaining bytes */ 1254 bl = bytes - cbytes; 1255 if (bl) { 1256 tmp = 0; 1257 for (n = 0; n < bl; n++) 1258 tmp |= data[cbytes + n] << (n * 8); 1259 1260 writel(tmp, USBD_TXDATA(udc->udp_baseaddr)); 1261 } 1262 break; 1263 1264 case 1: /* 8-bit aligned */ 1265 case 3: 1266 /* Each byte has to be handled independently */ 1267 for (n = 0; n < bytes; n += 4) { 1268 bl = bytes - n; 1269 if (bl > 4) 1270 bl = 4; 1271 1272 tmp = 0; 1273 for (i = 0; i < bl; i++) 1274 tmp |= data[n + i] << (i * 8); 1275 1276 writel(tmp, USBD_TXDATA(udc->udp_baseaddr)); 1277 } 1278 break; 1279 1280 case 2: /* 16-bit aligned */ 1281 p16 = (u16 *) data; 1282 cbytes = (bytes & ~0x3); 1283 1284 /* Copy 32-bit aligned data first */ 1285 for (n = 0; n < cbytes; n += 4) { 1286 tmp = *p16++ & 0xFFFF; 1287 tmp |= (*p16++ & 0xFFFF) << 16; 1288 writel(tmp, USBD_TXDATA(udc->udp_baseaddr)); 1289 } 1290 1291 /* Handle any remaining bytes */ 1292 bl = bytes - cbytes; 1293 if (bl) { 1294 tmp = 0; 1295 for (n = 0; n < bl; n++) 1296 tmp |= data[cbytes + n] << (n * 8); 1297 1298 writel(tmp, USBD_TXDATA(udc->udp_baseaddr)); 1299 } 1300 break; 1301 } 1302 } 1303 1304 /* Write data to the FIFO for an endpoint. This function is for endpoints (such 1305 * as EP0) that don't use DMA. Note that the endpoint must be selected in the 1306 * protocol engine prior to this call. */ 1307 static void udc_write_hwep(struct lpc32xx_udc *udc, u32 hwep, u32 *data, 1308 u32 bytes) 1309 { 1310 u32 hwwep = ((hwep & 0x1E) << 1) | CTRL_WR_EN; 1311 1312 if ((bytes > 0) && (data == NULL)) 1313 return; 1314 1315 /* Setup write of endpoint */ 1316 writel(hwwep, USBD_CTRL(udc->udp_baseaddr)); 1317 1318 writel(bytes, USBD_TXPLEN(udc->udp_baseaddr)); 1319 1320 /* Need at least 1 byte to trigger TX */ 1321 if (bytes == 0) 1322 writel(0, USBD_TXDATA(udc->udp_baseaddr)); 1323 else 1324 udc_stuff_fifo(udc, (u8 *) data, bytes); 1325 1326 writel(((hwep & 0x1E) << 1), USBD_CTRL(udc->udp_baseaddr)); 1327 1328 udc_val_buffer_hwep(udc, hwep); 1329 } 1330 1331 /* USB device reset - resets USB to a default state with just EP0 1332 enabled */ 1333 static void uda_usb_reset(struct lpc32xx_udc *udc) 1334 { 1335 u32 i = 0; 1336 /* Re-init device controller and EP0 */ 1337 udc_enable(udc); 1338 udc->gadget.speed = USB_SPEED_FULL; 1339 1340 for (i = 1; i < NUM_ENDPOINTS; i++) { 1341 struct lpc32xx_ep *ep = &udc->ep[i]; 1342 ep->req_pending = 0; 1343 } 1344 } 1345 1346 /* Send a ZLP on EP0 */ 1347 static void udc_ep0_send_zlp(struct lpc32xx_udc *udc) 1348 { 1349 udc_write_hwep(udc, EP_IN, NULL, 0); 1350 } 1351 1352 /* Get current frame number */ 1353 static u16 udc_get_current_frame(struct lpc32xx_udc *udc) 1354 { 1355 u16 flo, fhi; 1356 1357 udc_protocol_cmd_w(udc, CMD_RD_FRAME); 1358 flo = (u16) udc_protocol_cmd_r(udc, DAT_RD_FRAME); 1359 fhi = (u16) udc_protocol_cmd_r(udc, DAT_RD_FRAME); 1360 1361 return (fhi << 8) | flo; 1362 } 1363 1364 /* Set the device as configured - enables all endpoints */ 1365 static inline void udc_set_device_configured(struct lpc32xx_udc *udc) 1366 { 1367 udc_protocol_cmd_data_w(udc, CMD_CFG_DEV, DAT_WR_BYTE(CONF_DVICE)); 1368 } 1369 1370 /* Set the device as unconfigured - disables all endpoints */ 1371 static inline void udc_set_device_unconfigured(struct lpc32xx_udc *udc) 1372 { 1373 udc_protocol_cmd_data_w(udc, CMD_CFG_DEV, DAT_WR_BYTE(0)); 1374 } 1375 1376 /* reinit == restore initial software state */ 1377 static void udc_reinit(struct lpc32xx_udc *udc) 1378 { 1379 u32 i; 1380 1381 INIT_LIST_HEAD(&udc->gadget.ep_list); 1382 INIT_LIST_HEAD(&udc->gadget.ep0->ep_list); 1383 1384 for (i = 0; i < NUM_ENDPOINTS; i++) { 1385 struct lpc32xx_ep *ep = &udc->ep[i]; 1386 1387 if (i != 0) 1388 list_add_tail(&ep->ep.ep_list, &udc->gadget.ep_list); 1389 usb_ep_set_maxpacket_limit(&ep->ep, ep->maxpacket); 1390 INIT_LIST_HEAD(&ep->queue); 1391 ep->req_pending = 0; 1392 } 1393 1394 udc->ep0state = WAIT_FOR_SETUP; 1395 } 1396 1397 /* Must be called with lock */ 1398 static void done(struct lpc32xx_ep *ep, struct lpc32xx_request *req, int status) 1399 { 1400 struct lpc32xx_udc *udc = ep->udc; 1401 1402 list_del_init(&req->queue); 1403 if (req->req.status == -EINPROGRESS) 1404 req->req.status = status; 1405 else 1406 status = req->req.status; 1407 1408 if (ep->lep) { 1409 usb_gadget_unmap_request(&udc->gadget, &req->req, ep->is_in); 1410 1411 /* Free DDs */ 1412 udc_dd_free(udc, req->dd_desc_ptr); 1413 } 1414 1415 if (status && status != -ESHUTDOWN) 1416 ep_dbg(ep, "%s done %p, status %d\n", ep->ep.name, req, status); 1417 1418 ep->req_pending = 0; 1419 spin_unlock(&udc->lock); 1420 usb_gadget_giveback_request(&ep->ep, &req->req); 1421 spin_lock(&udc->lock); 1422 } 1423 1424 /* Must be called with lock */ 1425 static void nuke(struct lpc32xx_ep *ep, int status) 1426 { 1427 struct lpc32xx_request *req; 1428 1429 while (!list_empty(&ep->queue)) { 1430 req = list_entry(ep->queue.next, struct lpc32xx_request, queue); 1431 done(ep, req, status); 1432 } 1433 1434 if (status == -ESHUTDOWN) { 1435 uda_disable_hwepint(ep->udc, ep->hwep_num); 1436 udc_disable_hwep(ep->udc, ep->hwep_num); 1437 } 1438 } 1439 1440 /* IN endpoint 0 transfer */ 1441 static int udc_ep0_in_req(struct lpc32xx_udc *udc) 1442 { 1443 struct lpc32xx_request *req; 1444 struct lpc32xx_ep *ep0 = &udc->ep[0]; 1445 u32 tsend, ts = 0; 1446 1447 if (list_empty(&ep0->queue)) 1448 /* Nothing to send */ 1449 return 0; 1450 else 1451 req = list_entry(ep0->queue.next, struct lpc32xx_request, 1452 queue); 1453 1454 tsend = ts = req->req.length - req->req.actual; 1455 if (ts == 0) { 1456 /* Send a ZLP */ 1457 udc_ep0_send_zlp(udc); 1458 done(ep0, req, 0); 1459 return 1; 1460 } else if (ts > ep0->ep.maxpacket) 1461 ts = ep0->ep.maxpacket; /* Just send what we can */ 1462 1463 /* Write data to the EP0 FIFO and start transfer */ 1464 udc_write_hwep(udc, EP_IN, (req->req.buf + req->req.actual), ts); 1465 1466 /* Increment data pointer */ 1467 req->req.actual += ts; 1468 1469 if (tsend >= ep0->ep.maxpacket) 1470 return 0; /* Stay in data transfer state */ 1471 1472 /* Transfer request is complete */ 1473 udc->ep0state = WAIT_FOR_SETUP; 1474 done(ep0, req, 0); 1475 return 1; 1476 } 1477 1478 /* OUT endpoint 0 transfer */ 1479 static int udc_ep0_out_req(struct lpc32xx_udc *udc) 1480 { 1481 struct lpc32xx_request *req; 1482 struct lpc32xx_ep *ep0 = &udc->ep[0]; 1483 u32 tr, bufferspace; 1484 1485 if (list_empty(&ep0->queue)) 1486 return 0; 1487 else 1488 req = list_entry(ep0->queue.next, struct lpc32xx_request, 1489 queue); 1490 1491 if (req) { 1492 if (req->req.length == 0) { 1493 /* Just dequeue request */ 1494 done(ep0, req, 0); 1495 udc->ep0state = WAIT_FOR_SETUP; 1496 return 1; 1497 } 1498 1499 /* Get data from FIFO */ 1500 bufferspace = req->req.length - req->req.actual; 1501 if (bufferspace > ep0->ep.maxpacket) 1502 bufferspace = ep0->ep.maxpacket; 1503 1504 /* Copy data to buffer */ 1505 prefetchw(req->req.buf + req->req.actual); 1506 tr = udc_read_hwep(udc, EP_OUT, req->req.buf + req->req.actual, 1507 bufferspace); 1508 req->req.actual += bufferspace; 1509 1510 if (tr < ep0->ep.maxpacket) { 1511 /* This is the last packet */ 1512 done(ep0, req, 0); 1513 udc->ep0state = WAIT_FOR_SETUP; 1514 return 1; 1515 } 1516 } 1517 1518 return 0; 1519 } 1520 1521 /* Must be called with lock */ 1522 static void stop_activity(struct lpc32xx_udc *udc) 1523 { 1524 struct usb_gadget_driver *driver = udc->driver; 1525 int i; 1526 1527 if (udc->gadget.speed == USB_SPEED_UNKNOWN) 1528 driver = NULL; 1529 1530 udc->gadget.speed = USB_SPEED_UNKNOWN; 1531 udc->suspended = 0; 1532 1533 for (i = 0; i < NUM_ENDPOINTS; i++) { 1534 struct lpc32xx_ep *ep = &udc->ep[i]; 1535 nuke(ep, -ESHUTDOWN); 1536 } 1537 if (driver) { 1538 spin_unlock(&udc->lock); 1539 driver->disconnect(&udc->gadget); 1540 spin_lock(&udc->lock); 1541 } 1542 1543 isp1301_pullup_enable(udc, 0, 0); 1544 udc_disable(udc); 1545 udc_reinit(udc); 1546 } 1547 1548 /* 1549 * Activate or kill host pullup 1550 * Can be called with or without lock 1551 */ 1552 static void pullup(struct lpc32xx_udc *udc, int is_on) 1553 { 1554 if (!udc->clocked) 1555 return; 1556 1557 if (!udc->enabled || !udc->vbus) 1558 is_on = 0; 1559 1560 if (is_on != udc->pullup) 1561 isp1301_pullup_enable(udc, is_on, 0); 1562 } 1563 1564 /* Must be called without lock */ 1565 static int lpc32xx_ep_disable(struct usb_ep *_ep) 1566 { 1567 struct lpc32xx_ep *ep = container_of(_ep, struct lpc32xx_ep, ep); 1568 struct lpc32xx_udc *udc = ep->udc; 1569 unsigned long flags; 1570 1571 if ((ep->hwep_num_base == 0) || (ep->hwep_num == 0)) 1572 return -EINVAL; 1573 spin_lock_irqsave(&udc->lock, flags); 1574 1575 nuke(ep, -ESHUTDOWN); 1576 1577 /* Clear all DMA statuses for this EP */ 1578 udc_ep_dma_disable(udc, ep->hwep_num); 1579 writel(1 << ep->hwep_num, USBD_EOTINTCLR(udc->udp_baseaddr)); 1580 writel(1 << ep->hwep_num, USBD_NDDRTINTCLR(udc->udp_baseaddr)); 1581 writel(1 << ep->hwep_num, USBD_SYSERRTINTCLR(udc->udp_baseaddr)); 1582 writel(1 << ep->hwep_num, USBD_DMARCLR(udc->udp_baseaddr)); 1583 1584 /* Remove the DD pointer in the UDCA */ 1585 udc->udca_v_base[ep->hwep_num] = 0; 1586 1587 /* Disable and reset endpoint and interrupt */ 1588 uda_clear_hwepint(udc, ep->hwep_num); 1589 udc_unrealize_hwep(udc, ep->hwep_num); 1590 1591 ep->hwep_num = 0; 1592 1593 spin_unlock_irqrestore(&udc->lock, flags); 1594 1595 atomic_dec(&udc->enabled_ep_cnt); 1596 wake_up(&udc->ep_disable_wait_queue); 1597 1598 return 0; 1599 } 1600 1601 /* Must be called without lock */ 1602 static int lpc32xx_ep_enable(struct usb_ep *_ep, 1603 const struct usb_endpoint_descriptor *desc) 1604 { 1605 struct lpc32xx_ep *ep = container_of(_ep, struct lpc32xx_ep, ep); 1606 struct lpc32xx_udc *udc = ep->udc; 1607 u16 maxpacket; 1608 u32 tmp; 1609 unsigned long flags; 1610 1611 /* Verify EP data */ 1612 if ((!_ep) || (!ep) || (!desc) || 1613 (desc->bDescriptorType != USB_DT_ENDPOINT)) { 1614 dev_dbg(udc->dev, "bad ep or descriptor\n"); 1615 return -EINVAL; 1616 } 1617 maxpacket = usb_endpoint_maxp(desc); 1618 if ((maxpacket == 0) || (maxpacket > ep->maxpacket)) { 1619 dev_dbg(udc->dev, "bad ep descriptor's packet size\n"); 1620 return -EINVAL; 1621 } 1622 1623 /* Don't touch EP0 */ 1624 if (ep->hwep_num_base == 0) { 1625 dev_dbg(udc->dev, "Can't re-enable EP0!!!\n"); 1626 return -EINVAL; 1627 } 1628 1629 /* Is driver ready? */ 1630 if ((!udc->driver) || (udc->gadget.speed == USB_SPEED_UNKNOWN)) { 1631 dev_dbg(udc->dev, "bogus device state\n"); 1632 return -ESHUTDOWN; 1633 } 1634 1635 tmp = desc->bmAttributes & USB_ENDPOINT_XFERTYPE_MASK; 1636 switch (tmp) { 1637 case USB_ENDPOINT_XFER_CONTROL: 1638 return -EINVAL; 1639 1640 case USB_ENDPOINT_XFER_INT: 1641 if (maxpacket > ep->maxpacket) { 1642 dev_dbg(udc->dev, 1643 "Bad INT endpoint maxpacket %d\n", maxpacket); 1644 return -EINVAL; 1645 } 1646 break; 1647 1648 case USB_ENDPOINT_XFER_BULK: 1649 switch (maxpacket) { 1650 case 8: 1651 case 16: 1652 case 32: 1653 case 64: 1654 break; 1655 1656 default: 1657 dev_dbg(udc->dev, 1658 "Bad BULK endpoint maxpacket %d\n", maxpacket); 1659 return -EINVAL; 1660 } 1661 break; 1662 1663 case USB_ENDPOINT_XFER_ISOC: 1664 break; 1665 } 1666 spin_lock_irqsave(&udc->lock, flags); 1667 1668 /* Initialize endpoint to match the selected descriptor */ 1669 ep->is_in = (desc->bEndpointAddress & USB_DIR_IN) != 0; 1670 ep->ep.maxpacket = maxpacket; 1671 1672 /* Map hardware endpoint from base and direction */ 1673 if (ep->is_in) 1674 /* IN endpoints are offset 1 from the OUT endpoint */ 1675 ep->hwep_num = ep->hwep_num_base + EP_IN; 1676 else 1677 ep->hwep_num = ep->hwep_num_base; 1678 1679 ep_dbg(ep, "EP enabled: %s, HW:%d, MP:%d IN:%d\n", ep->ep.name, 1680 ep->hwep_num, maxpacket, (ep->is_in == 1)); 1681 1682 /* Realize the endpoint, interrupt is enabled later when 1683 * buffers are queued, IN EPs will NAK until buffers are ready */ 1684 udc_realize_hwep(udc, ep->hwep_num, ep->ep.maxpacket); 1685 udc_clr_buffer_hwep(udc, ep->hwep_num); 1686 uda_disable_hwepint(udc, ep->hwep_num); 1687 udc_clrstall_hwep(udc, ep->hwep_num); 1688 1689 /* Clear all DMA statuses for this EP */ 1690 udc_ep_dma_disable(udc, ep->hwep_num); 1691 writel(1 << ep->hwep_num, USBD_EOTINTCLR(udc->udp_baseaddr)); 1692 writel(1 << ep->hwep_num, USBD_NDDRTINTCLR(udc->udp_baseaddr)); 1693 writel(1 << ep->hwep_num, USBD_SYSERRTINTCLR(udc->udp_baseaddr)); 1694 writel(1 << ep->hwep_num, USBD_DMARCLR(udc->udp_baseaddr)); 1695 1696 spin_unlock_irqrestore(&udc->lock, flags); 1697 1698 atomic_inc(&udc->enabled_ep_cnt); 1699 return 0; 1700 } 1701 1702 /* 1703 * Allocate a USB request list 1704 * Can be called with or without lock 1705 */ 1706 static struct usb_request *lpc32xx_ep_alloc_request(struct usb_ep *_ep, 1707 gfp_t gfp_flags) 1708 { 1709 struct lpc32xx_request *req; 1710 1711 req = kzalloc(sizeof(struct lpc32xx_request), gfp_flags); 1712 if (!req) 1713 return NULL; 1714 1715 INIT_LIST_HEAD(&req->queue); 1716 return &req->req; 1717 } 1718 1719 /* 1720 * De-allocate a USB request list 1721 * Can be called with or without lock 1722 */ 1723 static void lpc32xx_ep_free_request(struct usb_ep *_ep, 1724 struct usb_request *_req) 1725 { 1726 struct lpc32xx_request *req; 1727 1728 req = container_of(_req, struct lpc32xx_request, req); 1729 BUG_ON(!list_empty(&req->queue)); 1730 kfree(req); 1731 } 1732 1733 /* Must be called without lock */ 1734 static int lpc32xx_ep_queue(struct usb_ep *_ep, 1735 struct usb_request *_req, gfp_t gfp_flags) 1736 { 1737 struct lpc32xx_request *req; 1738 struct lpc32xx_ep *ep; 1739 struct lpc32xx_udc *udc; 1740 unsigned long flags; 1741 int status = 0; 1742 1743 req = container_of(_req, struct lpc32xx_request, req); 1744 ep = container_of(_ep, struct lpc32xx_ep, ep); 1745 1746 if (!_ep || !_req || !_req->complete || !_req->buf || 1747 !list_empty(&req->queue)) 1748 return -EINVAL; 1749 1750 udc = ep->udc; 1751 1752 if (udc->gadget.speed == USB_SPEED_UNKNOWN) 1753 return -EPIPE; 1754 1755 if (ep->lep) { 1756 struct lpc32xx_usbd_dd_gad *dd; 1757 1758 status = usb_gadget_map_request(&udc->gadget, _req, ep->is_in); 1759 if (status) 1760 return status; 1761 1762 /* For the request, build a list of DDs */ 1763 dd = udc_dd_alloc(udc); 1764 if (!dd) { 1765 /* Error allocating DD */ 1766 return -ENOMEM; 1767 } 1768 req->dd_desc_ptr = dd; 1769 1770 /* Setup the DMA descriptor */ 1771 dd->dd_next_phy = dd->dd_next_v = 0; 1772 dd->dd_buffer_addr = req->req.dma; 1773 dd->dd_status = 0; 1774 1775 /* Special handling for ISO EPs */ 1776 if (ep->eptype == EP_ISO_TYPE) { 1777 dd->dd_setup = DD_SETUP_ISO_EP | 1778 DD_SETUP_PACKETLEN(0) | 1779 DD_SETUP_DMALENBYTES(1); 1780 dd->dd_iso_ps_mem_addr = dd->this_dma + 24; 1781 if (ep->is_in) 1782 dd->iso_status[0] = req->req.length; 1783 else 1784 dd->iso_status[0] = 0; 1785 } else 1786 dd->dd_setup = DD_SETUP_PACKETLEN(ep->ep.maxpacket) | 1787 DD_SETUP_DMALENBYTES(req->req.length); 1788 } 1789 1790 ep_dbg(ep, "%s queue req %p len %d buf %p (in=%d) z=%d\n", _ep->name, 1791 _req, _req->length, _req->buf, ep->is_in, _req->zero); 1792 1793 spin_lock_irqsave(&udc->lock, flags); 1794 1795 _req->status = -EINPROGRESS; 1796 _req->actual = 0; 1797 req->send_zlp = _req->zero; 1798 1799 /* Kickstart empty queues */ 1800 if (list_empty(&ep->queue)) { 1801 list_add_tail(&req->queue, &ep->queue); 1802 1803 if (ep->hwep_num_base == 0) { 1804 /* Handle expected data direction */ 1805 if (ep->is_in) { 1806 /* IN packet to host */ 1807 udc->ep0state = DATA_IN; 1808 status = udc_ep0_in_req(udc); 1809 } else { 1810 /* OUT packet from host */ 1811 udc->ep0state = DATA_OUT; 1812 status = udc_ep0_out_req(udc); 1813 } 1814 } else if (ep->is_in) { 1815 /* IN packet to host and kick off transfer */ 1816 if (!ep->req_pending) 1817 udc_ep_in_req_dma(udc, ep); 1818 } else 1819 /* OUT packet from host and kick off list */ 1820 if (!ep->req_pending) 1821 udc_ep_out_req_dma(udc, ep); 1822 } else 1823 list_add_tail(&req->queue, &ep->queue); 1824 1825 spin_unlock_irqrestore(&udc->lock, flags); 1826 1827 return (status < 0) ? status : 0; 1828 } 1829 1830 /* Must be called without lock */ 1831 static int lpc32xx_ep_dequeue(struct usb_ep *_ep, struct usb_request *_req) 1832 { 1833 struct lpc32xx_ep *ep; 1834 struct lpc32xx_request *req; 1835 unsigned long flags; 1836 1837 ep = container_of(_ep, struct lpc32xx_ep, ep); 1838 if (!_ep || ep->hwep_num_base == 0) 1839 return -EINVAL; 1840 1841 spin_lock_irqsave(&ep->udc->lock, flags); 1842 1843 /* make sure it's actually queued on this endpoint */ 1844 list_for_each_entry(req, &ep->queue, queue) { 1845 if (&req->req == _req) 1846 break; 1847 } 1848 if (&req->req != _req) { 1849 spin_unlock_irqrestore(&ep->udc->lock, flags); 1850 return -EINVAL; 1851 } 1852 1853 done(ep, req, -ECONNRESET); 1854 1855 spin_unlock_irqrestore(&ep->udc->lock, flags); 1856 1857 return 0; 1858 } 1859 1860 /* Must be called without lock */ 1861 static int lpc32xx_ep_set_halt(struct usb_ep *_ep, int value) 1862 { 1863 struct lpc32xx_ep *ep = container_of(_ep, struct lpc32xx_ep, ep); 1864 struct lpc32xx_udc *udc = ep->udc; 1865 unsigned long flags; 1866 1867 if ((!ep) || (ep->hwep_num <= 1)) 1868 return -EINVAL; 1869 1870 /* Don't halt an IN EP */ 1871 if (ep->is_in) 1872 return -EAGAIN; 1873 1874 spin_lock_irqsave(&udc->lock, flags); 1875 1876 if (value == 1) { 1877 /* stall */ 1878 udc_protocol_cmd_data_w(udc, CMD_SET_EP_STAT(ep->hwep_num), 1879 DAT_WR_BYTE(EP_STAT_ST)); 1880 } else { 1881 /* End stall */ 1882 ep->wedge = 0; 1883 udc_protocol_cmd_data_w(udc, CMD_SET_EP_STAT(ep->hwep_num), 1884 DAT_WR_BYTE(0)); 1885 } 1886 1887 spin_unlock_irqrestore(&udc->lock, flags); 1888 1889 return 0; 1890 } 1891 1892 /* set the halt feature and ignores clear requests */ 1893 static int lpc32xx_ep_set_wedge(struct usb_ep *_ep) 1894 { 1895 struct lpc32xx_ep *ep = container_of(_ep, struct lpc32xx_ep, ep); 1896 1897 if (!_ep || !ep->udc) 1898 return -EINVAL; 1899 1900 ep->wedge = 1; 1901 1902 return usb_ep_set_halt(_ep); 1903 } 1904 1905 static const struct usb_ep_ops lpc32xx_ep_ops = { 1906 .enable = lpc32xx_ep_enable, 1907 .disable = lpc32xx_ep_disable, 1908 .alloc_request = lpc32xx_ep_alloc_request, 1909 .free_request = lpc32xx_ep_free_request, 1910 .queue = lpc32xx_ep_queue, 1911 .dequeue = lpc32xx_ep_dequeue, 1912 .set_halt = lpc32xx_ep_set_halt, 1913 .set_wedge = lpc32xx_ep_set_wedge, 1914 }; 1915 1916 /* Send a ZLP on a non-0 IN EP */ 1917 void udc_send_in_zlp(struct lpc32xx_udc *udc, struct lpc32xx_ep *ep) 1918 { 1919 /* Clear EP status */ 1920 udc_clearep_getsts(udc, ep->hwep_num); 1921 1922 /* Send ZLP via FIFO mechanism */ 1923 udc_write_hwep(udc, ep->hwep_num, NULL, 0); 1924 } 1925 1926 /* 1927 * Handle EP completion for ZLP 1928 * This function will only be called when a delayed ZLP needs to be sent out 1929 * after a DMA transfer has filled both buffers. 1930 */ 1931 void udc_handle_eps(struct lpc32xx_udc *udc, struct lpc32xx_ep *ep) 1932 { 1933 u32 epstatus; 1934 struct lpc32xx_request *req; 1935 1936 if (ep->hwep_num <= 0) 1937 return; 1938 1939 uda_clear_hwepint(udc, ep->hwep_num); 1940 1941 /* If this interrupt isn't enabled, return now */ 1942 if (!(udc->enabled_hwepints & (1 << ep->hwep_num))) 1943 return; 1944 1945 /* Get endpoint status */ 1946 epstatus = udc_clearep_getsts(udc, ep->hwep_num); 1947 1948 /* 1949 * This should never happen, but protect against writing to the 1950 * buffer when full. 1951 */ 1952 if (epstatus & EP_SEL_F) 1953 return; 1954 1955 if (ep->is_in) { 1956 udc_send_in_zlp(udc, ep); 1957 uda_disable_hwepint(udc, ep->hwep_num); 1958 } else 1959 return; 1960 1961 /* If there isn't a request waiting, something went wrong */ 1962 req = list_entry(ep->queue.next, struct lpc32xx_request, queue); 1963 if (req) { 1964 done(ep, req, 0); 1965 1966 /* Start another request if ready */ 1967 if (!list_empty(&ep->queue)) { 1968 if (ep->is_in) 1969 udc_ep_in_req_dma(udc, ep); 1970 else 1971 udc_ep_out_req_dma(udc, ep); 1972 } else 1973 ep->req_pending = 0; 1974 } 1975 } 1976 1977 1978 /* DMA end of transfer completion */ 1979 static void udc_handle_dma_ep(struct lpc32xx_udc *udc, struct lpc32xx_ep *ep) 1980 { 1981 u32 status, epstatus; 1982 struct lpc32xx_request *req; 1983 struct lpc32xx_usbd_dd_gad *dd; 1984 1985 #ifdef CONFIG_USB_GADGET_DEBUG_FILES 1986 ep->totalints++; 1987 #endif 1988 1989 req = list_entry(ep->queue.next, struct lpc32xx_request, queue); 1990 if (!req) { 1991 ep_err(ep, "DMA interrupt on no req!\n"); 1992 return; 1993 } 1994 dd = req->dd_desc_ptr; 1995 1996 /* DMA descriptor should always be retired for this call */ 1997 if (!(dd->dd_status & DD_STATUS_DD_RETIRED)) 1998 ep_warn(ep, "DMA descriptor did not retire\n"); 1999 2000 /* Disable DMA */ 2001 udc_ep_dma_disable(udc, ep->hwep_num); 2002 writel((1 << ep->hwep_num), USBD_EOTINTCLR(udc->udp_baseaddr)); 2003 writel((1 << ep->hwep_num), USBD_NDDRTINTCLR(udc->udp_baseaddr)); 2004 2005 /* System error? */ 2006 if (readl(USBD_SYSERRTINTST(udc->udp_baseaddr)) & 2007 (1 << ep->hwep_num)) { 2008 writel((1 << ep->hwep_num), 2009 USBD_SYSERRTINTCLR(udc->udp_baseaddr)); 2010 ep_err(ep, "AHB critical error!\n"); 2011 ep->req_pending = 0; 2012 2013 /* The error could have occurred on a packet of a multipacket 2014 * transfer, so recovering the transfer is not possible. Close 2015 * the request with an error */ 2016 done(ep, req, -ECONNABORTED); 2017 return; 2018 } 2019 2020 /* Handle the current DD's status */ 2021 status = dd->dd_status; 2022 switch (status & DD_STATUS_STS_MASK) { 2023 case DD_STATUS_STS_NS: 2024 /* DD not serviced? This shouldn't happen! */ 2025 ep->req_pending = 0; 2026 ep_err(ep, "DMA critical EP error: DD not serviced (0x%x)!\n", 2027 status); 2028 2029 done(ep, req, -ECONNABORTED); 2030 return; 2031 2032 case DD_STATUS_STS_BS: 2033 /* Interrupt only fires on EOT - This shouldn't happen! */ 2034 ep->req_pending = 0; 2035 ep_err(ep, "DMA critical EP error: EOT prior to service completion (0x%x)!\n", 2036 status); 2037 done(ep, req, -ECONNABORTED); 2038 return; 2039 2040 case DD_STATUS_STS_NC: 2041 case DD_STATUS_STS_DUR: 2042 /* Really just a short packet, not an underrun */ 2043 /* This is a good status and what we expect */ 2044 break; 2045 2046 default: 2047 /* Data overrun, system error, or unknown */ 2048 ep->req_pending = 0; 2049 ep_err(ep, "DMA critical EP error: System error (0x%x)!\n", 2050 status); 2051 done(ep, req, -ECONNABORTED); 2052 return; 2053 } 2054 2055 /* ISO endpoints are handled differently */ 2056 if (ep->eptype == EP_ISO_TYPE) { 2057 if (ep->is_in) 2058 req->req.actual = req->req.length; 2059 else 2060 req->req.actual = dd->iso_status[0] & 0xFFFF; 2061 } else 2062 req->req.actual += DD_STATUS_CURDMACNT(status); 2063 2064 /* Send a ZLP if necessary. This will be done for non-int 2065 * packets which have a size that is a divisor of MAXP */ 2066 if (req->send_zlp) { 2067 /* 2068 * If at least 1 buffer is available, send the ZLP now. 2069 * Otherwise, the ZLP send needs to be deferred until a 2070 * buffer is available. 2071 */ 2072 if (udc_clearep_getsts(udc, ep->hwep_num) & EP_SEL_F) { 2073 udc_clearep_getsts(udc, ep->hwep_num); 2074 uda_enable_hwepint(udc, ep->hwep_num); 2075 epstatus = udc_clearep_getsts(udc, ep->hwep_num); 2076 2077 /* Let the EP interrupt handle the ZLP */ 2078 return; 2079 } else 2080 udc_send_in_zlp(udc, ep); 2081 } 2082 2083 /* Transfer request is complete */ 2084 done(ep, req, 0); 2085 2086 /* Start another request if ready */ 2087 udc_clearep_getsts(udc, ep->hwep_num); 2088 if (!list_empty((&ep->queue))) { 2089 if (ep->is_in) 2090 udc_ep_in_req_dma(udc, ep); 2091 else 2092 udc_ep_out_req_dma(udc, ep); 2093 } else 2094 ep->req_pending = 0; 2095 2096 } 2097 2098 /* 2099 * 2100 * Endpoint 0 functions 2101 * 2102 */ 2103 static void udc_handle_dev(struct lpc32xx_udc *udc) 2104 { 2105 u32 tmp; 2106 2107 udc_protocol_cmd_w(udc, CMD_GET_DEV_STAT); 2108 tmp = udc_protocol_cmd_r(udc, DAT_GET_DEV_STAT); 2109 2110 if (tmp & DEV_RST) 2111 uda_usb_reset(udc); 2112 else if (tmp & DEV_CON_CH) 2113 uda_power_event(udc, (tmp & DEV_CON)); 2114 else if (tmp & DEV_SUS_CH) { 2115 if (tmp & DEV_SUS) { 2116 if (udc->vbus == 0) 2117 stop_activity(udc); 2118 else if ((udc->gadget.speed != USB_SPEED_UNKNOWN) && 2119 udc->driver) { 2120 /* Power down transceiver */ 2121 udc->poweron = 0; 2122 schedule_work(&udc->pullup_job); 2123 uda_resm_susp_event(udc, 1); 2124 } 2125 } else if ((udc->gadget.speed != USB_SPEED_UNKNOWN) && 2126 udc->driver && udc->vbus) { 2127 uda_resm_susp_event(udc, 0); 2128 /* Power up transceiver */ 2129 udc->poweron = 1; 2130 schedule_work(&udc->pullup_job); 2131 } 2132 } 2133 } 2134 2135 static int udc_get_status(struct lpc32xx_udc *udc, u16 reqtype, u16 wIndex) 2136 { 2137 struct lpc32xx_ep *ep; 2138 u32 ep0buff = 0, tmp; 2139 2140 switch (reqtype & USB_RECIP_MASK) { 2141 case USB_RECIP_INTERFACE: 2142 break; /* Not supported */ 2143 2144 case USB_RECIP_DEVICE: 2145 ep0buff = udc->gadget.is_selfpowered; 2146 if (udc->dev_status & (1 << USB_DEVICE_REMOTE_WAKEUP)) 2147 ep0buff |= (1 << USB_DEVICE_REMOTE_WAKEUP); 2148 break; 2149 2150 case USB_RECIP_ENDPOINT: 2151 tmp = wIndex & USB_ENDPOINT_NUMBER_MASK; 2152 ep = &udc->ep[tmp]; 2153 if ((tmp == 0) || (tmp >= NUM_ENDPOINTS)) 2154 return -EOPNOTSUPP; 2155 2156 if (wIndex & USB_DIR_IN) { 2157 if (!ep->is_in) 2158 return -EOPNOTSUPP; /* Something's wrong */ 2159 } else if (ep->is_in) 2160 return -EOPNOTSUPP; /* Not an IN endpoint */ 2161 2162 /* Get status of the endpoint */ 2163 udc_protocol_cmd_w(udc, CMD_SEL_EP(ep->hwep_num)); 2164 tmp = udc_protocol_cmd_r(udc, DAT_SEL_EP(ep->hwep_num)); 2165 2166 if (tmp & EP_SEL_ST) 2167 ep0buff = (1 << USB_ENDPOINT_HALT); 2168 else 2169 ep0buff = 0; 2170 break; 2171 2172 default: 2173 break; 2174 } 2175 2176 /* Return data */ 2177 udc_write_hwep(udc, EP_IN, &ep0buff, 2); 2178 2179 return 0; 2180 } 2181 2182 static void udc_handle_ep0_setup(struct lpc32xx_udc *udc) 2183 { 2184 struct lpc32xx_ep *ep, *ep0 = &udc->ep[0]; 2185 struct usb_ctrlrequest ctrlpkt; 2186 int i, bytes; 2187 u16 wIndex, wValue, wLength, reqtype, req, tmp; 2188 2189 /* Nuke previous transfers */ 2190 nuke(ep0, -EPROTO); 2191 2192 /* Get setup packet */ 2193 bytes = udc_read_hwep(udc, EP_OUT, (u32 *) &ctrlpkt, 8); 2194 if (bytes != 8) { 2195 ep_warn(ep0, "Incorrectly sized setup packet (s/b 8, is %d)!\n", 2196 bytes); 2197 return; 2198 } 2199 2200 /* Native endianness */ 2201 wIndex = le16_to_cpu(ctrlpkt.wIndex); 2202 wValue = le16_to_cpu(ctrlpkt.wValue); 2203 wLength = le16_to_cpu(ctrlpkt.wLength); 2204 reqtype = le16_to_cpu(ctrlpkt.bRequestType); 2205 2206 /* Set direction of EP0 */ 2207 if (likely(reqtype & USB_DIR_IN)) 2208 ep0->is_in = 1; 2209 else 2210 ep0->is_in = 0; 2211 2212 /* Handle SETUP packet */ 2213 req = le16_to_cpu(ctrlpkt.bRequest); 2214 switch (req) { 2215 case USB_REQ_CLEAR_FEATURE: 2216 case USB_REQ_SET_FEATURE: 2217 switch (reqtype) { 2218 case (USB_TYPE_STANDARD | USB_RECIP_DEVICE): 2219 if (wValue != USB_DEVICE_REMOTE_WAKEUP) 2220 goto stall; /* Nothing else handled */ 2221 2222 /* Tell board about event */ 2223 if (req == USB_REQ_CLEAR_FEATURE) 2224 udc->dev_status &= 2225 ~(1 << USB_DEVICE_REMOTE_WAKEUP); 2226 else 2227 udc->dev_status |= 2228 (1 << USB_DEVICE_REMOTE_WAKEUP); 2229 uda_remwkp_cgh(udc); 2230 goto zlp_send; 2231 2232 case (USB_TYPE_STANDARD | USB_RECIP_ENDPOINT): 2233 tmp = wIndex & USB_ENDPOINT_NUMBER_MASK; 2234 if ((wValue != USB_ENDPOINT_HALT) || 2235 (tmp >= NUM_ENDPOINTS)) 2236 break; 2237 2238 /* Find hardware endpoint from logical endpoint */ 2239 ep = &udc->ep[tmp]; 2240 tmp = ep->hwep_num; 2241 if (tmp == 0) 2242 break; 2243 2244 if (req == USB_REQ_SET_FEATURE) 2245 udc_stall_hwep(udc, tmp); 2246 else if (!ep->wedge) 2247 udc_clrstall_hwep(udc, tmp); 2248 2249 goto zlp_send; 2250 2251 default: 2252 break; 2253 } 2254 2255 2256 case USB_REQ_SET_ADDRESS: 2257 if (reqtype == (USB_TYPE_STANDARD | USB_RECIP_DEVICE)) { 2258 udc_set_address(udc, wValue); 2259 goto zlp_send; 2260 } 2261 break; 2262 2263 case USB_REQ_GET_STATUS: 2264 udc_get_status(udc, reqtype, wIndex); 2265 return; 2266 2267 default: 2268 break; /* Let GadgetFS handle the descriptor instead */ 2269 } 2270 2271 if (likely(udc->driver)) { 2272 /* device-2-host (IN) or no data setup command, process 2273 * immediately */ 2274 spin_unlock(&udc->lock); 2275 i = udc->driver->setup(&udc->gadget, &ctrlpkt); 2276 2277 spin_lock(&udc->lock); 2278 if (req == USB_REQ_SET_CONFIGURATION) { 2279 /* Configuration is set after endpoints are realized */ 2280 if (wValue) { 2281 /* Set configuration */ 2282 udc_set_device_configured(udc); 2283 2284 udc_protocol_cmd_data_w(udc, CMD_SET_MODE, 2285 DAT_WR_BYTE(AP_CLK | 2286 INAK_BI | INAK_II)); 2287 } else { 2288 /* Clear configuration */ 2289 udc_set_device_unconfigured(udc); 2290 2291 /* Disable NAK interrupts */ 2292 udc_protocol_cmd_data_w(udc, CMD_SET_MODE, 2293 DAT_WR_BYTE(AP_CLK)); 2294 } 2295 } 2296 2297 if (i < 0) { 2298 /* setup processing failed, force stall */ 2299 dev_dbg(udc->dev, 2300 "req %02x.%02x protocol STALL; stat %d\n", 2301 reqtype, req, i); 2302 udc->ep0state = WAIT_FOR_SETUP; 2303 goto stall; 2304 } 2305 } 2306 2307 if (!ep0->is_in) 2308 udc_ep0_send_zlp(udc); /* ZLP IN packet on data phase */ 2309 2310 return; 2311 2312 stall: 2313 udc_stall_hwep(udc, EP_IN); 2314 return; 2315 2316 zlp_send: 2317 udc_ep0_send_zlp(udc); 2318 return; 2319 } 2320 2321 /* IN endpoint 0 transfer */ 2322 static void udc_handle_ep0_in(struct lpc32xx_udc *udc) 2323 { 2324 struct lpc32xx_ep *ep0 = &udc->ep[0]; 2325 u32 epstatus; 2326 2327 /* Clear EP interrupt */ 2328 epstatus = udc_clearep_getsts(udc, EP_IN); 2329 2330 #ifdef CONFIG_USB_GADGET_DEBUG_FILES 2331 ep0->totalints++; 2332 #endif 2333 2334 /* Stalled? Clear stall and reset buffers */ 2335 if (epstatus & EP_SEL_ST) { 2336 udc_clrstall_hwep(udc, EP_IN); 2337 nuke(ep0, -ECONNABORTED); 2338 udc->ep0state = WAIT_FOR_SETUP; 2339 return; 2340 } 2341 2342 /* Is a buffer available? */ 2343 if (!(epstatus & EP_SEL_F)) { 2344 /* Handle based on current state */ 2345 if (udc->ep0state == DATA_IN) 2346 udc_ep0_in_req(udc); 2347 else { 2348 /* Unknown state for EP0 oe end of DATA IN phase */ 2349 nuke(ep0, -ECONNABORTED); 2350 udc->ep0state = WAIT_FOR_SETUP; 2351 } 2352 } 2353 } 2354 2355 /* OUT endpoint 0 transfer */ 2356 static void udc_handle_ep0_out(struct lpc32xx_udc *udc) 2357 { 2358 struct lpc32xx_ep *ep0 = &udc->ep[0]; 2359 u32 epstatus; 2360 2361 /* Clear EP interrupt */ 2362 epstatus = udc_clearep_getsts(udc, EP_OUT); 2363 2364 2365 #ifdef CONFIG_USB_GADGET_DEBUG_FILES 2366 ep0->totalints++; 2367 #endif 2368 2369 /* Stalled? */ 2370 if (epstatus & EP_SEL_ST) { 2371 udc_clrstall_hwep(udc, EP_OUT); 2372 nuke(ep0, -ECONNABORTED); 2373 udc->ep0state = WAIT_FOR_SETUP; 2374 return; 2375 } 2376 2377 /* A NAK may occur if a packet couldn't be received yet */ 2378 if (epstatus & EP_SEL_EPN) 2379 return; 2380 /* Setup packet incoming? */ 2381 if (epstatus & EP_SEL_STP) { 2382 nuke(ep0, 0); 2383 udc->ep0state = WAIT_FOR_SETUP; 2384 } 2385 2386 /* Data available? */ 2387 if (epstatus & EP_SEL_F) 2388 /* Handle based on current state */ 2389 switch (udc->ep0state) { 2390 case WAIT_FOR_SETUP: 2391 udc_handle_ep0_setup(udc); 2392 break; 2393 2394 case DATA_OUT: 2395 udc_ep0_out_req(udc); 2396 break; 2397 2398 default: 2399 /* Unknown state for EP0 */ 2400 nuke(ep0, -ECONNABORTED); 2401 udc->ep0state = WAIT_FOR_SETUP; 2402 } 2403 } 2404 2405 /* Must be called without lock */ 2406 static int lpc32xx_get_frame(struct usb_gadget *gadget) 2407 { 2408 int frame; 2409 unsigned long flags; 2410 struct lpc32xx_udc *udc = to_udc(gadget); 2411 2412 if (!udc->clocked) 2413 return -EINVAL; 2414 2415 spin_lock_irqsave(&udc->lock, flags); 2416 2417 frame = (int) udc_get_current_frame(udc); 2418 2419 spin_unlock_irqrestore(&udc->lock, flags); 2420 2421 return frame; 2422 } 2423 2424 static int lpc32xx_wakeup(struct usb_gadget *gadget) 2425 { 2426 return -ENOTSUPP; 2427 } 2428 2429 static int lpc32xx_set_selfpowered(struct usb_gadget *gadget, int is_on) 2430 { 2431 gadget->is_selfpowered = (is_on != 0); 2432 2433 return 0; 2434 } 2435 2436 /* 2437 * vbus is here! turn everything on that's ready 2438 * Must be called without lock 2439 */ 2440 static int lpc32xx_vbus_session(struct usb_gadget *gadget, int is_active) 2441 { 2442 unsigned long flags; 2443 struct lpc32xx_udc *udc = to_udc(gadget); 2444 2445 spin_lock_irqsave(&udc->lock, flags); 2446 2447 /* Doesn't need lock */ 2448 if (udc->driver) { 2449 udc_clk_set(udc, 1); 2450 udc_enable(udc); 2451 pullup(udc, is_active); 2452 } else { 2453 stop_activity(udc); 2454 pullup(udc, 0); 2455 2456 spin_unlock_irqrestore(&udc->lock, flags); 2457 /* 2458 * Wait for all the endpoints to disable, 2459 * before disabling clocks. Don't wait if 2460 * endpoints are not enabled. 2461 */ 2462 if (atomic_read(&udc->enabled_ep_cnt)) 2463 wait_event_interruptible(udc->ep_disable_wait_queue, 2464 (atomic_read(&udc->enabled_ep_cnt) == 0)); 2465 2466 spin_lock_irqsave(&udc->lock, flags); 2467 2468 udc_clk_set(udc, 0); 2469 } 2470 2471 spin_unlock_irqrestore(&udc->lock, flags); 2472 2473 return 0; 2474 } 2475 2476 /* Can be called with or without lock */ 2477 static int lpc32xx_pullup(struct usb_gadget *gadget, int is_on) 2478 { 2479 struct lpc32xx_udc *udc = to_udc(gadget); 2480 2481 /* Doesn't need lock */ 2482 pullup(udc, is_on); 2483 2484 return 0; 2485 } 2486 2487 static int lpc32xx_start(struct usb_gadget *, struct usb_gadget_driver *); 2488 static int lpc32xx_stop(struct usb_gadget *); 2489 2490 static const struct usb_gadget_ops lpc32xx_udc_ops = { 2491 .get_frame = lpc32xx_get_frame, 2492 .wakeup = lpc32xx_wakeup, 2493 .set_selfpowered = lpc32xx_set_selfpowered, 2494 .vbus_session = lpc32xx_vbus_session, 2495 .pullup = lpc32xx_pullup, 2496 .udc_start = lpc32xx_start, 2497 .udc_stop = lpc32xx_stop, 2498 }; 2499 2500 static void nop_release(struct device *dev) 2501 { 2502 /* nothing to free */ 2503 } 2504 2505 static const struct lpc32xx_udc controller_template = { 2506 .gadget = { 2507 .ops = &lpc32xx_udc_ops, 2508 .name = driver_name, 2509 .dev = { 2510 .init_name = "gadget", 2511 .release = nop_release, 2512 } 2513 }, 2514 .ep[0] = { 2515 .ep = { 2516 .name = "ep0", 2517 .ops = &lpc32xx_ep_ops, 2518 .caps = USB_EP_CAPS(USB_EP_CAPS_TYPE_CONTROL, 2519 USB_EP_CAPS_DIR_ALL), 2520 }, 2521 .maxpacket = 64, 2522 .hwep_num_base = 0, 2523 .hwep_num = 0, /* Can be 0 or 1, has special handling */ 2524 .lep = 0, 2525 .eptype = EP_CTL_TYPE, 2526 }, 2527 .ep[1] = { 2528 .ep = { 2529 .name = "ep1-int", 2530 .ops = &lpc32xx_ep_ops, 2531 .caps = USB_EP_CAPS(USB_EP_CAPS_TYPE_INT, 2532 USB_EP_CAPS_DIR_ALL), 2533 }, 2534 .maxpacket = 64, 2535 .hwep_num_base = 2, 2536 .hwep_num = 0, /* 2 or 3, will be set later */ 2537 .lep = 1, 2538 .eptype = EP_INT_TYPE, 2539 }, 2540 .ep[2] = { 2541 .ep = { 2542 .name = "ep2-bulk", 2543 .ops = &lpc32xx_ep_ops, 2544 .caps = USB_EP_CAPS(USB_EP_CAPS_TYPE_BULK, 2545 USB_EP_CAPS_DIR_ALL), 2546 }, 2547 .maxpacket = 64, 2548 .hwep_num_base = 4, 2549 .hwep_num = 0, /* 4 or 5, will be set later */ 2550 .lep = 2, 2551 .eptype = EP_BLK_TYPE, 2552 }, 2553 .ep[3] = { 2554 .ep = { 2555 .name = "ep3-iso", 2556 .ops = &lpc32xx_ep_ops, 2557 .caps = USB_EP_CAPS(USB_EP_CAPS_TYPE_ISO, 2558 USB_EP_CAPS_DIR_ALL), 2559 }, 2560 .maxpacket = 1023, 2561 .hwep_num_base = 6, 2562 .hwep_num = 0, /* 6 or 7, will be set later */ 2563 .lep = 3, 2564 .eptype = EP_ISO_TYPE, 2565 }, 2566 .ep[4] = { 2567 .ep = { 2568 .name = "ep4-int", 2569 .ops = &lpc32xx_ep_ops, 2570 .caps = USB_EP_CAPS(USB_EP_CAPS_TYPE_INT, 2571 USB_EP_CAPS_DIR_ALL), 2572 }, 2573 .maxpacket = 64, 2574 .hwep_num_base = 8, 2575 .hwep_num = 0, /* 8 or 9, will be set later */ 2576 .lep = 4, 2577 .eptype = EP_INT_TYPE, 2578 }, 2579 .ep[5] = { 2580 .ep = { 2581 .name = "ep5-bulk", 2582 .ops = &lpc32xx_ep_ops, 2583 .caps = USB_EP_CAPS(USB_EP_CAPS_TYPE_BULK, 2584 USB_EP_CAPS_DIR_ALL), 2585 }, 2586 .maxpacket = 64, 2587 .hwep_num_base = 10, 2588 .hwep_num = 0, /* 10 or 11, will be set later */ 2589 .lep = 5, 2590 .eptype = EP_BLK_TYPE, 2591 }, 2592 .ep[6] = { 2593 .ep = { 2594 .name = "ep6-iso", 2595 .ops = &lpc32xx_ep_ops, 2596 .caps = USB_EP_CAPS(USB_EP_CAPS_TYPE_ISO, 2597 USB_EP_CAPS_DIR_ALL), 2598 }, 2599 .maxpacket = 1023, 2600 .hwep_num_base = 12, 2601 .hwep_num = 0, /* 12 or 13, will be set later */ 2602 .lep = 6, 2603 .eptype = EP_ISO_TYPE, 2604 }, 2605 .ep[7] = { 2606 .ep = { 2607 .name = "ep7-int", 2608 .ops = &lpc32xx_ep_ops, 2609 .caps = USB_EP_CAPS(USB_EP_CAPS_TYPE_INT, 2610 USB_EP_CAPS_DIR_ALL), 2611 }, 2612 .maxpacket = 64, 2613 .hwep_num_base = 14, 2614 .hwep_num = 0, 2615 .lep = 7, 2616 .eptype = EP_INT_TYPE, 2617 }, 2618 .ep[8] = { 2619 .ep = { 2620 .name = "ep8-bulk", 2621 .ops = &lpc32xx_ep_ops, 2622 .caps = USB_EP_CAPS(USB_EP_CAPS_TYPE_BULK, 2623 USB_EP_CAPS_DIR_ALL), 2624 }, 2625 .maxpacket = 64, 2626 .hwep_num_base = 16, 2627 .hwep_num = 0, 2628 .lep = 8, 2629 .eptype = EP_BLK_TYPE, 2630 }, 2631 .ep[9] = { 2632 .ep = { 2633 .name = "ep9-iso", 2634 .ops = &lpc32xx_ep_ops, 2635 .caps = USB_EP_CAPS(USB_EP_CAPS_TYPE_ISO, 2636 USB_EP_CAPS_DIR_ALL), 2637 }, 2638 .maxpacket = 1023, 2639 .hwep_num_base = 18, 2640 .hwep_num = 0, 2641 .lep = 9, 2642 .eptype = EP_ISO_TYPE, 2643 }, 2644 .ep[10] = { 2645 .ep = { 2646 .name = "ep10-int", 2647 .ops = &lpc32xx_ep_ops, 2648 .caps = USB_EP_CAPS(USB_EP_CAPS_TYPE_INT, 2649 USB_EP_CAPS_DIR_ALL), 2650 }, 2651 .maxpacket = 64, 2652 .hwep_num_base = 20, 2653 .hwep_num = 0, 2654 .lep = 10, 2655 .eptype = EP_INT_TYPE, 2656 }, 2657 .ep[11] = { 2658 .ep = { 2659 .name = "ep11-bulk", 2660 .ops = &lpc32xx_ep_ops, 2661 .caps = USB_EP_CAPS(USB_EP_CAPS_TYPE_BULK, 2662 USB_EP_CAPS_DIR_ALL), 2663 }, 2664 .maxpacket = 64, 2665 .hwep_num_base = 22, 2666 .hwep_num = 0, 2667 .lep = 11, 2668 .eptype = EP_BLK_TYPE, 2669 }, 2670 .ep[12] = { 2671 .ep = { 2672 .name = "ep12-iso", 2673 .ops = &lpc32xx_ep_ops, 2674 .caps = USB_EP_CAPS(USB_EP_CAPS_TYPE_ISO, 2675 USB_EP_CAPS_DIR_ALL), 2676 }, 2677 .maxpacket = 1023, 2678 .hwep_num_base = 24, 2679 .hwep_num = 0, 2680 .lep = 12, 2681 .eptype = EP_ISO_TYPE, 2682 }, 2683 .ep[13] = { 2684 .ep = { 2685 .name = "ep13-int", 2686 .ops = &lpc32xx_ep_ops, 2687 .caps = USB_EP_CAPS(USB_EP_CAPS_TYPE_INT, 2688 USB_EP_CAPS_DIR_ALL), 2689 }, 2690 .maxpacket = 64, 2691 .hwep_num_base = 26, 2692 .hwep_num = 0, 2693 .lep = 13, 2694 .eptype = EP_INT_TYPE, 2695 }, 2696 .ep[14] = { 2697 .ep = { 2698 .name = "ep14-bulk", 2699 .ops = &lpc32xx_ep_ops, 2700 .caps = USB_EP_CAPS(USB_EP_CAPS_TYPE_BULK, 2701 USB_EP_CAPS_DIR_ALL), 2702 }, 2703 .maxpacket = 64, 2704 .hwep_num_base = 28, 2705 .hwep_num = 0, 2706 .lep = 14, 2707 .eptype = EP_BLK_TYPE, 2708 }, 2709 .ep[15] = { 2710 .ep = { 2711 .name = "ep15-bulk", 2712 .ops = &lpc32xx_ep_ops, 2713 .caps = USB_EP_CAPS(USB_EP_CAPS_TYPE_BULK, 2714 USB_EP_CAPS_DIR_ALL), 2715 }, 2716 .maxpacket = 1023, 2717 .hwep_num_base = 30, 2718 .hwep_num = 0, 2719 .lep = 15, 2720 .eptype = EP_BLK_TYPE, 2721 }, 2722 }; 2723 2724 /* ISO and status interrupts */ 2725 static irqreturn_t lpc32xx_usb_lp_irq(int irq, void *_udc) 2726 { 2727 u32 tmp, devstat; 2728 struct lpc32xx_udc *udc = _udc; 2729 2730 spin_lock(&udc->lock); 2731 2732 /* Read the device status register */ 2733 devstat = readl(USBD_DEVINTST(udc->udp_baseaddr)); 2734 2735 devstat &= ~USBD_EP_FAST; 2736 writel(devstat, USBD_DEVINTCLR(udc->udp_baseaddr)); 2737 devstat = devstat & udc->enabled_devints; 2738 2739 /* Device specific handling needed? */ 2740 if (devstat & USBD_DEV_STAT) 2741 udc_handle_dev(udc); 2742 2743 /* Start of frame? (devstat & FRAME_INT): 2744 * The frame interrupt isn't really needed for ISO support, 2745 * as the driver will queue the necessary packets */ 2746 2747 /* Error? */ 2748 if (devstat & ERR_INT) { 2749 /* All types of errors, from cable removal during transfer to 2750 * misc protocol and bit errors. These are mostly for just info, 2751 * as the USB hardware will work around these. If these errors 2752 * happen alot, something is wrong. */ 2753 udc_protocol_cmd_w(udc, CMD_RD_ERR_STAT); 2754 tmp = udc_protocol_cmd_r(udc, DAT_RD_ERR_STAT); 2755 dev_dbg(udc->dev, "Device error (0x%x)!\n", tmp); 2756 } 2757 2758 spin_unlock(&udc->lock); 2759 2760 return IRQ_HANDLED; 2761 } 2762 2763 /* EP interrupts */ 2764 static irqreturn_t lpc32xx_usb_hp_irq(int irq, void *_udc) 2765 { 2766 u32 tmp; 2767 struct lpc32xx_udc *udc = _udc; 2768 2769 spin_lock(&udc->lock); 2770 2771 /* Read the device status register */ 2772 writel(USBD_EP_FAST, USBD_DEVINTCLR(udc->udp_baseaddr)); 2773 2774 /* Endpoints */ 2775 tmp = readl(USBD_EPINTST(udc->udp_baseaddr)); 2776 2777 /* Special handling for EP0 */ 2778 if (tmp & (EP_MASK_SEL(0, EP_OUT) | EP_MASK_SEL(0, EP_IN))) { 2779 /* Handle EP0 IN */ 2780 if (tmp & (EP_MASK_SEL(0, EP_IN))) 2781 udc_handle_ep0_in(udc); 2782 2783 /* Handle EP0 OUT */ 2784 if (tmp & (EP_MASK_SEL(0, EP_OUT))) 2785 udc_handle_ep0_out(udc); 2786 } 2787 2788 /* All other EPs */ 2789 if (tmp & ~(EP_MASK_SEL(0, EP_OUT) | EP_MASK_SEL(0, EP_IN))) { 2790 int i; 2791 2792 /* Handle other EP interrupts */ 2793 for (i = 1; i < NUM_ENDPOINTS; i++) { 2794 if (tmp & (1 << udc->ep[i].hwep_num)) 2795 udc_handle_eps(udc, &udc->ep[i]); 2796 } 2797 } 2798 2799 spin_unlock(&udc->lock); 2800 2801 return IRQ_HANDLED; 2802 } 2803 2804 static irqreturn_t lpc32xx_usb_devdma_irq(int irq, void *_udc) 2805 { 2806 struct lpc32xx_udc *udc = _udc; 2807 2808 int i; 2809 u32 tmp; 2810 2811 spin_lock(&udc->lock); 2812 2813 /* Handle EP DMA EOT interrupts */ 2814 tmp = readl(USBD_EOTINTST(udc->udp_baseaddr)) | 2815 (readl(USBD_EPDMAST(udc->udp_baseaddr)) & 2816 readl(USBD_NDDRTINTST(udc->udp_baseaddr))) | 2817 readl(USBD_SYSERRTINTST(udc->udp_baseaddr)); 2818 for (i = 1; i < NUM_ENDPOINTS; i++) { 2819 if (tmp & (1 << udc->ep[i].hwep_num)) 2820 udc_handle_dma_ep(udc, &udc->ep[i]); 2821 } 2822 2823 spin_unlock(&udc->lock); 2824 2825 return IRQ_HANDLED; 2826 } 2827 2828 /* 2829 * 2830 * VBUS detection, pullup handler, and Gadget cable state notification 2831 * 2832 */ 2833 static void vbus_work(struct work_struct *work) 2834 { 2835 u8 value; 2836 struct lpc32xx_udc *udc = container_of(work, struct lpc32xx_udc, 2837 vbus_job); 2838 2839 if (udc->enabled != 0) { 2840 /* Discharge VBUS real quick */ 2841 i2c_smbus_write_byte_data(udc->isp1301_i2c_client, 2842 ISP1301_I2C_OTG_CONTROL_1, OTG1_VBUS_DISCHRG); 2843 2844 /* Give VBUS some time (100mS) to discharge */ 2845 msleep(100); 2846 2847 /* Disable VBUS discharge resistor */ 2848 i2c_smbus_write_byte_data(udc->isp1301_i2c_client, 2849 ISP1301_I2C_OTG_CONTROL_1 | ISP1301_I2C_REG_CLEAR_ADDR, 2850 OTG1_VBUS_DISCHRG); 2851 2852 /* Clear interrupt */ 2853 i2c_smbus_write_byte_data(udc->isp1301_i2c_client, 2854 ISP1301_I2C_INTERRUPT_LATCH | 2855 ISP1301_I2C_REG_CLEAR_ADDR, ~0); 2856 2857 /* Get the VBUS status from the transceiver */ 2858 value = i2c_smbus_read_byte_data(udc->isp1301_i2c_client, 2859 ISP1301_I2C_INTERRUPT_SOURCE); 2860 2861 /* VBUS on or off? */ 2862 if (value & INT_SESS_VLD) 2863 udc->vbus = 1; 2864 else 2865 udc->vbus = 0; 2866 2867 /* VBUS changed? */ 2868 if (udc->last_vbus != udc->vbus) { 2869 udc->last_vbus = udc->vbus; 2870 lpc32xx_vbus_session(&udc->gadget, udc->vbus); 2871 } 2872 } 2873 2874 /* Re-enable after completion */ 2875 enable_irq(udc->udp_irq[IRQ_USB_ATX]); 2876 } 2877 2878 static irqreturn_t lpc32xx_usb_vbus_irq(int irq, void *_udc) 2879 { 2880 struct lpc32xx_udc *udc = _udc; 2881 2882 /* Defer handling of VBUS IRQ to work queue */ 2883 disable_irq_nosync(udc->udp_irq[IRQ_USB_ATX]); 2884 schedule_work(&udc->vbus_job); 2885 2886 return IRQ_HANDLED; 2887 } 2888 2889 static int lpc32xx_start(struct usb_gadget *gadget, 2890 struct usb_gadget_driver *driver) 2891 { 2892 struct lpc32xx_udc *udc = to_udc(gadget); 2893 int i; 2894 2895 if (!driver || driver->max_speed < USB_SPEED_FULL || !driver->setup) { 2896 dev_err(udc->dev, "bad parameter.\n"); 2897 return -EINVAL; 2898 } 2899 2900 if (udc->driver) { 2901 dev_err(udc->dev, "UDC already has a gadget driver\n"); 2902 return -EBUSY; 2903 } 2904 2905 udc->driver = driver; 2906 udc->gadget.dev.of_node = udc->dev->of_node; 2907 udc->enabled = 1; 2908 udc->gadget.is_selfpowered = 1; 2909 udc->vbus = 0; 2910 2911 /* Force VBUS process once to check for cable insertion */ 2912 udc->last_vbus = udc->vbus = 0; 2913 schedule_work(&udc->vbus_job); 2914 2915 /* Do not re-enable ATX IRQ (3) */ 2916 for (i = IRQ_USB_LP; i < IRQ_USB_ATX; i++) 2917 enable_irq(udc->udp_irq[i]); 2918 2919 return 0; 2920 } 2921 2922 static int lpc32xx_stop(struct usb_gadget *gadget) 2923 { 2924 int i; 2925 struct lpc32xx_udc *udc = to_udc(gadget); 2926 2927 for (i = IRQ_USB_LP; i <= IRQ_USB_ATX; i++) 2928 disable_irq(udc->udp_irq[i]); 2929 2930 if (udc->clocked) { 2931 spin_lock(&udc->lock); 2932 stop_activity(udc); 2933 spin_unlock(&udc->lock); 2934 2935 /* 2936 * Wait for all the endpoints to disable, 2937 * before disabling clocks. Don't wait if 2938 * endpoints are not enabled. 2939 */ 2940 if (atomic_read(&udc->enabled_ep_cnt)) 2941 wait_event_interruptible(udc->ep_disable_wait_queue, 2942 (atomic_read(&udc->enabled_ep_cnt) == 0)); 2943 2944 spin_lock(&udc->lock); 2945 udc_clk_set(udc, 0); 2946 spin_unlock(&udc->lock); 2947 } 2948 2949 udc->enabled = 0; 2950 udc->driver = NULL; 2951 2952 return 0; 2953 } 2954 2955 static void lpc32xx_udc_shutdown(struct platform_device *dev) 2956 { 2957 /* Force disconnect on reboot */ 2958 struct lpc32xx_udc *udc = platform_get_drvdata(dev); 2959 2960 pullup(udc, 0); 2961 } 2962 2963 /* 2964 * Callbacks to be overridden by options passed via OF (TODO) 2965 */ 2966 2967 static void lpc32xx_usbd_conn_chg(int conn) 2968 { 2969 /* Do nothing, it might be nice to enable an LED 2970 * based on conn state being !0 */ 2971 } 2972 2973 static void lpc32xx_usbd_susp_chg(int susp) 2974 { 2975 /* Device suspend if susp != 0 */ 2976 } 2977 2978 static void lpc32xx_rmwkup_chg(int remote_wakup_enable) 2979 { 2980 /* Enable or disable USB remote wakeup */ 2981 } 2982 2983 struct lpc32xx_usbd_cfg lpc32xx_usbddata = { 2984 .vbus_drv_pol = 0, 2985 .conn_chgb = &lpc32xx_usbd_conn_chg, 2986 .susp_chgb = &lpc32xx_usbd_susp_chg, 2987 .rmwk_chgb = &lpc32xx_rmwkup_chg, 2988 }; 2989 2990 2991 static u64 lpc32xx_usbd_dmamask = ~(u32) 0x7F; 2992 2993 static int lpc32xx_udc_probe(struct platform_device *pdev) 2994 { 2995 struct device *dev = &pdev->dev; 2996 struct lpc32xx_udc *udc; 2997 int retval, i; 2998 struct resource *res; 2999 dma_addr_t dma_handle; 3000 struct device_node *isp1301_node; 3001 3002 udc = kmemdup(&controller_template, sizeof(*udc), GFP_KERNEL); 3003 if (!udc) 3004 return -ENOMEM; 3005 3006 for (i = 0; i <= 15; i++) 3007 udc->ep[i].udc = udc; 3008 udc->gadget.ep0 = &udc->ep[0].ep; 3009 3010 /* init software state */ 3011 udc->gadget.dev.parent = dev; 3012 udc->pdev = pdev; 3013 udc->dev = &pdev->dev; 3014 udc->enabled = 0; 3015 3016 if (pdev->dev.of_node) { 3017 isp1301_node = of_parse_phandle(pdev->dev.of_node, 3018 "transceiver", 0); 3019 } else { 3020 isp1301_node = NULL; 3021 } 3022 3023 udc->isp1301_i2c_client = isp1301_get_client(isp1301_node); 3024 if (!udc->isp1301_i2c_client) { 3025 retval = -EPROBE_DEFER; 3026 goto phy_fail; 3027 } 3028 3029 dev_info(udc->dev, "ISP1301 I2C device at address 0x%x\n", 3030 udc->isp1301_i2c_client->addr); 3031 3032 pdev->dev.dma_mask = &lpc32xx_usbd_dmamask; 3033 retval = dma_set_coherent_mask(&pdev->dev, DMA_BIT_MASK(32)); 3034 if (retval) 3035 goto resource_fail; 3036 3037 udc->board = &lpc32xx_usbddata; 3038 3039 /* 3040 * Resources are mapped as follows: 3041 * IORESOURCE_MEM, base address and size of USB space 3042 * IORESOURCE_IRQ, USB device low priority interrupt number 3043 * IORESOURCE_IRQ, USB device high priority interrupt number 3044 * IORESOURCE_IRQ, USB device interrupt number 3045 * IORESOURCE_IRQ, USB transceiver interrupt number 3046 */ 3047 res = platform_get_resource(pdev, IORESOURCE_MEM, 0); 3048 if (!res) { 3049 retval = -ENXIO; 3050 goto resource_fail; 3051 } 3052 3053 spin_lock_init(&udc->lock); 3054 3055 /* Get IRQs */ 3056 for (i = 0; i < 4; i++) { 3057 udc->udp_irq[i] = platform_get_irq(pdev, i); 3058 if (udc->udp_irq[i] < 0) { 3059 dev_err(udc->dev, 3060 "irq resource %d not available!\n", i); 3061 retval = udc->udp_irq[i]; 3062 goto irq_fail; 3063 } 3064 } 3065 3066 udc->io_p_start = res->start; 3067 udc->io_p_size = resource_size(res); 3068 if (!request_mem_region(udc->io_p_start, udc->io_p_size, driver_name)) { 3069 dev_err(udc->dev, "someone's using UDC memory\n"); 3070 retval = -EBUSY; 3071 goto request_mem_region_fail; 3072 } 3073 3074 udc->udp_baseaddr = ioremap(udc->io_p_start, udc->io_p_size); 3075 if (!udc->udp_baseaddr) { 3076 retval = -ENOMEM; 3077 dev_err(udc->dev, "IO map failure\n"); 3078 goto io_map_fail; 3079 } 3080 3081 /* Get USB device clock */ 3082 udc->usb_slv_clk = clk_get(&pdev->dev, NULL); 3083 if (IS_ERR(udc->usb_slv_clk)) { 3084 dev_err(udc->dev, "failed to acquire USB device clock\n"); 3085 retval = PTR_ERR(udc->usb_slv_clk); 3086 goto usb_clk_get_fail; 3087 } 3088 3089 /* Enable USB device clock */ 3090 retval = clk_prepare_enable(udc->usb_slv_clk); 3091 if (retval < 0) { 3092 dev_err(udc->dev, "failed to start USB device clock\n"); 3093 goto usb_clk_enable_fail; 3094 } 3095 3096 /* Setup deferred workqueue data */ 3097 udc->poweron = udc->pullup = 0; 3098 INIT_WORK(&udc->pullup_job, pullup_work); 3099 INIT_WORK(&udc->vbus_job, vbus_work); 3100 #ifdef CONFIG_PM 3101 INIT_WORK(&udc->power_job, power_work); 3102 #endif 3103 3104 /* All clocks are now on */ 3105 udc->clocked = 1; 3106 3107 isp1301_udc_configure(udc); 3108 /* Allocate memory for the UDCA */ 3109 udc->udca_v_base = dma_alloc_coherent(&pdev->dev, UDCA_BUFF_SIZE, 3110 &dma_handle, 3111 (GFP_KERNEL | GFP_DMA)); 3112 if (!udc->udca_v_base) { 3113 dev_err(udc->dev, "error getting UDCA region\n"); 3114 retval = -ENOMEM; 3115 goto i2c_fail; 3116 } 3117 udc->udca_p_base = dma_handle; 3118 dev_dbg(udc->dev, "DMA buffer(0x%x bytes), P:0x%08x, V:0x%p\n", 3119 UDCA_BUFF_SIZE, udc->udca_p_base, udc->udca_v_base); 3120 3121 /* Setup the DD DMA memory pool */ 3122 udc->dd_cache = dma_pool_create("udc_dd", udc->dev, 3123 sizeof(struct lpc32xx_usbd_dd_gad), 3124 sizeof(u32), 0); 3125 if (!udc->dd_cache) { 3126 dev_err(udc->dev, "error getting DD DMA region\n"); 3127 retval = -ENOMEM; 3128 goto dma_alloc_fail; 3129 } 3130 3131 /* Clear USB peripheral and initialize gadget endpoints */ 3132 udc_disable(udc); 3133 udc_reinit(udc); 3134 3135 /* Request IRQs - low and high priority USB device IRQs are routed to 3136 * the same handler, while the DMA interrupt is routed elsewhere */ 3137 retval = request_irq(udc->udp_irq[IRQ_USB_LP], lpc32xx_usb_lp_irq, 3138 0, "udc_lp", udc); 3139 if (retval < 0) { 3140 dev_err(udc->dev, "LP request irq %d failed\n", 3141 udc->udp_irq[IRQ_USB_LP]); 3142 goto irq_lp_fail; 3143 } 3144 retval = request_irq(udc->udp_irq[IRQ_USB_HP], lpc32xx_usb_hp_irq, 3145 0, "udc_hp", udc); 3146 if (retval < 0) { 3147 dev_err(udc->dev, "HP request irq %d failed\n", 3148 udc->udp_irq[IRQ_USB_HP]); 3149 goto irq_hp_fail; 3150 } 3151 3152 retval = request_irq(udc->udp_irq[IRQ_USB_DEVDMA], 3153 lpc32xx_usb_devdma_irq, 0, "udc_dma", udc); 3154 if (retval < 0) { 3155 dev_err(udc->dev, "DEV request irq %d failed\n", 3156 udc->udp_irq[IRQ_USB_DEVDMA]); 3157 goto irq_dev_fail; 3158 } 3159 3160 /* The transceiver interrupt is used for VBUS detection and will 3161 kick off the VBUS handler function */ 3162 retval = request_irq(udc->udp_irq[IRQ_USB_ATX], lpc32xx_usb_vbus_irq, 3163 0, "udc_otg", udc); 3164 if (retval < 0) { 3165 dev_err(udc->dev, "VBUS request irq %d failed\n", 3166 udc->udp_irq[IRQ_USB_ATX]); 3167 goto irq_xcvr_fail; 3168 } 3169 3170 /* Initialize wait queue */ 3171 init_waitqueue_head(&udc->ep_disable_wait_queue); 3172 atomic_set(&udc->enabled_ep_cnt, 0); 3173 3174 /* Keep all IRQs disabled until GadgetFS starts up */ 3175 for (i = IRQ_USB_LP; i <= IRQ_USB_ATX; i++) 3176 disable_irq(udc->udp_irq[i]); 3177 3178 retval = usb_add_gadget_udc(dev, &udc->gadget); 3179 if (retval < 0) 3180 goto add_gadget_fail; 3181 3182 dev_set_drvdata(dev, udc); 3183 device_init_wakeup(dev, 1); 3184 create_debug_file(udc); 3185 3186 /* Disable clocks for now */ 3187 udc_clk_set(udc, 0); 3188 3189 dev_info(udc->dev, "%s version %s\n", driver_name, DRIVER_VERSION); 3190 return 0; 3191 3192 add_gadget_fail: 3193 free_irq(udc->udp_irq[IRQ_USB_ATX], udc); 3194 irq_xcvr_fail: 3195 free_irq(udc->udp_irq[IRQ_USB_DEVDMA], udc); 3196 irq_dev_fail: 3197 free_irq(udc->udp_irq[IRQ_USB_HP], udc); 3198 irq_hp_fail: 3199 free_irq(udc->udp_irq[IRQ_USB_LP], udc); 3200 irq_lp_fail: 3201 dma_pool_destroy(udc->dd_cache); 3202 dma_alloc_fail: 3203 dma_free_coherent(&pdev->dev, UDCA_BUFF_SIZE, 3204 udc->udca_v_base, udc->udca_p_base); 3205 i2c_fail: 3206 clk_disable_unprepare(udc->usb_slv_clk); 3207 usb_clk_enable_fail: 3208 clk_put(udc->usb_slv_clk); 3209 usb_clk_get_fail: 3210 iounmap(udc->udp_baseaddr); 3211 io_map_fail: 3212 release_mem_region(udc->io_p_start, udc->io_p_size); 3213 dev_err(udc->dev, "%s probe failed, %d\n", driver_name, retval); 3214 request_mem_region_fail: 3215 irq_fail: 3216 resource_fail: 3217 phy_fail: 3218 kfree(udc); 3219 return retval; 3220 } 3221 3222 static int lpc32xx_udc_remove(struct platform_device *pdev) 3223 { 3224 struct lpc32xx_udc *udc = platform_get_drvdata(pdev); 3225 3226 usb_del_gadget_udc(&udc->gadget); 3227 if (udc->driver) 3228 return -EBUSY; 3229 3230 udc_clk_set(udc, 1); 3231 udc_disable(udc); 3232 pullup(udc, 0); 3233 3234 free_irq(udc->udp_irq[IRQ_USB_ATX], udc); 3235 3236 device_init_wakeup(&pdev->dev, 0); 3237 remove_debug_file(udc); 3238 3239 dma_pool_destroy(udc->dd_cache); 3240 dma_free_coherent(&pdev->dev, UDCA_BUFF_SIZE, 3241 udc->udca_v_base, udc->udca_p_base); 3242 free_irq(udc->udp_irq[IRQ_USB_DEVDMA], udc); 3243 free_irq(udc->udp_irq[IRQ_USB_HP], udc); 3244 free_irq(udc->udp_irq[IRQ_USB_LP], udc); 3245 3246 clk_disable_unprepare(udc->usb_slv_clk); 3247 clk_put(udc->usb_slv_clk); 3248 3249 iounmap(udc->udp_baseaddr); 3250 release_mem_region(udc->io_p_start, udc->io_p_size); 3251 kfree(udc); 3252 3253 return 0; 3254 } 3255 3256 #ifdef CONFIG_PM 3257 static int lpc32xx_udc_suspend(struct platform_device *pdev, pm_message_t mesg) 3258 { 3259 struct lpc32xx_udc *udc = platform_get_drvdata(pdev); 3260 3261 if (udc->clocked) { 3262 /* Power down ISP */ 3263 udc->poweron = 0; 3264 isp1301_set_powerstate(udc, 0); 3265 3266 /* Disable clocking */ 3267 udc_clk_set(udc, 0); 3268 3269 /* Keep clock flag on, so we know to re-enable clocks 3270 on resume */ 3271 udc->clocked = 1; 3272 3273 /* Kill global USB clock */ 3274 clk_disable_unprepare(udc->usb_slv_clk); 3275 } 3276 3277 return 0; 3278 } 3279 3280 static int lpc32xx_udc_resume(struct platform_device *pdev) 3281 { 3282 struct lpc32xx_udc *udc = platform_get_drvdata(pdev); 3283 3284 if (udc->clocked) { 3285 /* Enable global USB clock */ 3286 clk_prepare_enable(udc->usb_slv_clk); 3287 3288 /* Enable clocking */ 3289 udc_clk_set(udc, 1); 3290 3291 /* ISP back to normal power mode */ 3292 udc->poweron = 1; 3293 isp1301_set_powerstate(udc, 1); 3294 } 3295 3296 return 0; 3297 } 3298 #else 3299 #define lpc32xx_udc_suspend NULL 3300 #define lpc32xx_udc_resume NULL 3301 #endif 3302 3303 #ifdef CONFIG_OF 3304 static const struct of_device_id lpc32xx_udc_of_match[] = { 3305 { .compatible = "nxp,lpc3220-udc", }, 3306 { }, 3307 }; 3308 MODULE_DEVICE_TABLE(of, lpc32xx_udc_of_match); 3309 #endif 3310 3311 static struct platform_driver lpc32xx_udc_driver = { 3312 .remove = lpc32xx_udc_remove, 3313 .shutdown = lpc32xx_udc_shutdown, 3314 .suspend = lpc32xx_udc_suspend, 3315 .resume = lpc32xx_udc_resume, 3316 .driver = { 3317 .name = (char *) driver_name, 3318 .of_match_table = of_match_ptr(lpc32xx_udc_of_match), 3319 }, 3320 }; 3321 3322 module_platform_driver_probe(lpc32xx_udc_driver, lpc32xx_udc_probe); 3323 3324 MODULE_DESCRIPTION("LPC32XX udc driver"); 3325 MODULE_AUTHOR("Kevin Wells <kevin.wells@nxp.com>"); 3326 MODULE_AUTHOR("Roland Stigge <stigge@antcom.de>"); 3327 MODULE_LICENSE("GPL"); 3328 MODULE_ALIAS("platform:lpc32xx_udc"); 3329