1 /*
2  * USB Gadget driver for LPC32xx
3  *
4  * Authors:
5  *    Kevin Wells <kevin.wells@nxp.com>
6  *    Mike James
7  *    Roland Stigge <stigge@antcom.de>
8  *
9  * Copyright (C) 2006 Philips Semiconductors
10  * Copyright (C) 2009 NXP Semiconductors
11  * Copyright (C) 2012 Roland Stigge
12  *
13  * Note: This driver is based on original work done by Mike James for
14  *       the LPC3180.
15  *
16  * This program is free software; you can redistribute it and/or modify
17  * it under the terms of the GNU General Public License as published by
18  * the Free Software Foundation; either version 2 of the License, or
19  * (at your option) any later version.
20  *
21  * This program is distributed in the hope that it will be useful,
22  * but WITHOUT ANY WARRANTY; without even the implied warranty of
23  * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
24  * GNU General Public License for more details.
25  *
26  * You should have received a copy of the GNU General Public License
27  * along with this program; if not, write to the Free Software
28  * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307  USA
29  */
30 
31 #include <linux/kernel.h>
32 #include <linux/module.h>
33 #include <linux/platform_device.h>
34 #include <linux/delay.h>
35 #include <linux/ioport.h>
36 #include <linux/slab.h>
37 #include <linux/errno.h>
38 #include <linux/init.h>
39 #include <linux/list.h>
40 #include <linux/interrupt.h>
41 #include <linux/proc_fs.h>
42 #include <linux/clk.h>
43 #include <linux/usb/ch9.h>
44 #include <linux/usb/gadget.h>
45 #include <linux/i2c.h>
46 #include <linux/kthread.h>
47 #include <linux/freezer.h>
48 #include <linux/dma-mapping.h>
49 #include <linux/dmapool.h>
50 #include <linux/workqueue.h>
51 #include <linux/of.h>
52 #include <linux/usb/isp1301.h>
53 
54 #include <asm/byteorder.h>
55 #include <mach/hardware.h>
56 #include <linux/io.h>
57 #include <asm/irq.h>
58 
59 #include <mach/platform.h>
60 #include <mach/irqs.h>
61 #include <mach/board.h>
62 #ifdef CONFIG_USB_GADGET_DEBUG_FILES
63 #include <linux/debugfs.h>
64 #include <linux/seq_file.h>
65 #endif
66 
67 /*
68  * USB device configuration structure
69  */
70 typedef void (*usc_chg_event)(int);
71 struct lpc32xx_usbd_cfg {
72 	int vbus_drv_pol;   /* 0=active low drive for VBUS via ISP1301 */
73 	usc_chg_event conn_chgb; /* Connection change event (optional) */
74 	usc_chg_event susp_chgb; /* Suspend/resume event (optional) */
75 	usc_chg_event rmwk_chgb; /* Enable/disable remote wakeup */
76 };
77 
78 /*
79  * controller driver data structures
80  */
81 
82 /* 16 endpoints (not to be confused with 32 hardware endpoints) */
83 #define	NUM_ENDPOINTS	16
84 
85 /*
86  * IRQ indices make reading the code a little easier
87  */
88 #define IRQ_USB_LP	0
89 #define IRQ_USB_HP	1
90 #define IRQ_USB_DEVDMA	2
91 #define IRQ_USB_ATX	3
92 
93 #define EP_OUT 0 /* RX (from host) */
94 #define EP_IN 1 /* TX (to host) */
95 
96 /* Returns the interrupt mask for the selected hardware endpoint */
97 #define EP_MASK_SEL(ep, dir) (1 << (((ep) * 2) + dir))
98 
99 #define EP_INT_TYPE 0
100 #define EP_ISO_TYPE 1
101 #define EP_BLK_TYPE 2
102 #define EP_CTL_TYPE 3
103 
104 /* EP0 states */
105 #define WAIT_FOR_SETUP 0 /* Wait for setup packet */
106 #define DATA_IN        1 /* Expect dev->host transfer */
107 #define DATA_OUT       2 /* Expect host->dev transfer */
108 
109 /* DD (DMA Descriptor) structure, requires word alignment, this is already
110  * defined in the LPC32XX USB device header file, but this version is slightly
111  * modified to tag some work data with each DMA descriptor. */
112 struct lpc32xx_usbd_dd_gad {
113 	u32 dd_next_phy;
114 	u32 dd_setup;
115 	u32 dd_buffer_addr;
116 	u32 dd_status;
117 	u32 dd_iso_ps_mem_addr;
118 	u32 this_dma;
119 	u32 iso_status[6]; /* 5 spare */
120 	u32 dd_next_v;
121 };
122 
123 /*
124  * Logical endpoint structure
125  */
126 struct lpc32xx_ep {
127 	struct usb_ep		ep;
128 	struct list_head	queue;
129 	struct lpc32xx_udc	*udc;
130 
131 	u32			hwep_num_base; /* Physical hardware EP */
132 	u32			hwep_num; /* Maps to hardware endpoint */
133 	u32			maxpacket;
134 	u32			lep;
135 
136 	bool			is_in;
137 	bool			req_pending;
138 	u32			eptype;
139 
140 	u32                     totalints;
141 
142 	bool			wedge;
143 };
144 
145 /*
146  * Common UDC structure
147  */
148 struct lpc32xx_udc {
149 	struct usb_gadget	gadget;
150 	struct usb_gadget_driver *driver;
151 	struct platform_device	*pdev;
152 	struct device		*dev;
153 	struct dentry		*pde;
154 	spinlock_t		lock;
155 	struct i2c_client	*isp1301_i2c_client;
156 
157 	/* Board and device specific */
158 	struct lpc32xx_usbd_cfg	*board;
159 	u32			io_p_start;
160 	u32			io_p_size;
161 	void __iomem		*udp_baseaddr;
162 	int			udp_irq[4];
163 	struct clk		*usb_pll_clk;
164 	struct clk		*usb_slv_clk;
165 	struct clk		*usb_otg_clk;
166 
167 	/* DMA support */
168 	u32			*udca_v_base;
169 	u32			udca_p_base;
170 	struct dma_pool		*dd_cache;
171 
172 	/* Common EP and control data */
173 	u32			enabled_devints;
174 	u32			enabled_hwepints;
175 	u32			dev_status;
176 	u32			realized_eps;
177 
178 	/* VBUS detection, pullup, and power flags */
179 	u8			vbus;
180 	u8			last_vbus;
181 	int			pullup;
182 	int			poweron;
183 
184 	/* Work queues related to I2C support */
185 	struct work_struct	pullup_job;
186 	struct work_struct	vbus_job;
187 	struct work_struct	power_job;
188 
189 	/* USB device peripheral - various */
190 	struct lpc32xx_ep	ep[NUM_ENDPOINTS];
191 	bool			enabled;
192 	bool			clocked;
193 	bool			suspended;
194 	bool			selfpowered;
195 	int                     ep0state;
196 	atomic_t                enabled_ep_cnt;
197 	wait_queue_head_t       ep_disable_wait_queue;
198 };
199 
200 /*
201  * Endpoint request
202  */
203 struct lpc32xx_request {
204 	struct usb_request	req;
205 	struct list_head	queue;
206 	struct lpc32xx_usbd_dd_gad *dd_desc_ptr;
207 	bool			mapped;
208 	bool			send_zlp;
209 };
210 
211 static inline struct lpc32xx_udc *to_udc(struct usb_gadget *g)
212 {
213 	return container_of(g, struct lpc32xx_udc, gadget);
214 }
215 
216 #define ep_dbg(epp, fmt, arg...) \
217 	dev_dbg(epp->udc->dev, "%s: " fmt, __func__, ## arg)
218 #define ep_err(epp, fmt, arg...) \
219 	dev_err(epp->udc->dev, "%s: " fmt, __func__, ## arg)
220 #define ep_info(epp, fmt, arg...) \
221 	dev_info(epp->udc->dev, "%s: " fmt, __func__, ## arg)
222 #define ep_warn(epp, fmt, arg...) \
223 	dev_warn(epp->udc->dev, "%s:" fmt, __func__, ## arg)
224 
225 #define UDCA_BUFF_SIZE (128)
226 
227 /* TODO: When the clock framework is introduced in LPC32xx, IO_ADDRESS will
228  * be replaced with an inremap()ed pointer
229  * */
230 #define USB_CTRL		IO_ADDRESS(LPC32XX_CLK_PM_BASE + 0x64)
231 
232 /* USB_CTRL bit defines */
233 #define USB_SLAVE_HCLK_EN	(1 << 24)
234 #define USB_HOST_NEED_CLK_EN	(1 << 21)
235 #define USB_DEV_NEED_CLK_EN	(1 << 22)
236 
237 /**********************************************************************
238  * USB device controller register offsets
239  **********************************************************************/
240 
241 #define USBD_DEVINTST(x)	((x) + 0x200)
242 #define USBD_DEVINTEN(x)	((x) + 0x204)
243 #define USBD_DEVINTCLR(x)	((x) + 0x208)
244 #define USBD_DEVINTSET(x)	((x) + 0x20C)
245 #define USBD_CMDCODE(x)		((x) + 0x210)
246 #define USBD_CMDDATA(x)		((x) + 0x214)
247 #define USBD_RXDATA(x)		((x) + 0x218)
248 #define USBD_TXDATA(x)		((x) + 0x21C)
249 #define USBD_RXPLEN(x)		((x) + 0x220)
250 #define USBD_TXPLEN(x)		((x) + 0x224)
251 #define USBD_CTRL(x)		((x) + 0x228)
252 #define USBD_DEVINTPRI(x)	((x) + 0x22C)
253 #define USBD_EPINTST(x)		((x) + 0x230)
254 #define USBD_EPINTEN(x)		((x) + 0x234)
255 #define USBD_EPINTCLR(x)	((x) + 0x238)
256 #define USBD_EPINTSET(x)	((x) + 0x23C)
257 #define USBD_EPINTPRI(x)	((x) + 0x240)
258 #define USBD_REEP(x)		((x) + 0x244)
259 #define USBD_EPIND(x)		((x) + 0x248)
260 #define USBD_EPMAXPSIZE(x)	((x) + 0x24C)
261 /* DMA support registers only below */
262 /* Set, clear, or get enabled state of the DMA request status. If
263  * enabled, an IN or OUT token will start a DMA transfer for the EP */
264 #define USBD_DMARST(x)		((x) + 0x250)
265 #define USBD_DMARCLR(x)		((x) + 0x254)
266 #define USBD_DMARSET(x)		((x) + 0x258)
267 /* DMA UDCA head pointer */
268 #define USBD_UDCAH(x)		((x) + 0x280)
269 /* EP DMA status, enable, and disable. This is used to specifically
270  * enabled or disable DMA for a specific EP */
271 #define USBD_EPDMAST(x)		((x) + 0x284)
272 #define USBD_EPDMAEN(x)		((x) + 0x288)
273 #define USBD_EPDMADIS(x)	((x) + 0x28C)
274 /* DMA master interrupts enable and pending interrupts */
275 #define USBD_DMAINTST(x)	((x) + 0x290)
276 #define USBD_DMAINTEN(x)	((x) + 0x294)
277 /* DMA end of transfer interrupt enable, disable, status */
278 #define USBD_EOTINTST(x)	((x) + 0x2A0)
279 #define USBD_EOTINTCLR(x)	((x) + 0x2A4)
280 #define USBD_EOTINTSET(x)	((x) + 0x2A8)
281 /* New DD request interrupt enable, disable, status */
282 #define USBD_NDDRTINTST(x)	((x) + 0x2AC)
283 #define USBD_NDDRTINTCLR(x)	((x) + 0x2B0)
284 #define USBD_NDDRTINTSET(x)	((x) + 0x2B4)
285 /* DMA error interrupt enable, disable, status */
286 #define USBD_SYSERRTINTST(x)	((x) + 0x2B8)
287 #define USBD_SYSERRTINTCLR(x)	((x) + 0x2BC)
288 #define USBD_SYSERRTINTSET(x)	((x) + 0x2C0)
289 
290 /**********************************************************************
291  * USBD_DEVINTST/USBD_DEVINTEN/USBD_DEVINTCLR/USBD_DEVINTSET/
292  * USBD_DEVINTPRI register definitions
293  **********************************************************************/
294 #define USBD_ERR_INT		(1 << 9)
295 #define USBD_EP_RLZED		(1 << 8)
296 #define USBD_TXENDPKT		(1 << 7)
297 #define USBD_RXENDPKT		(1 << 6)
298 #define USBD_CDFULL		(1 << 5)
299 #define USBD_CCEMPTY		(1 << 4)
300 #define USBD_DEV_STAT		(1 << 3)
301 #define USBD_EP_SLOW		(1 << 2)
302 #define USBD_EP_FAST		(1 << 1)
303 #define USBD_FRAME		(1 << 0)
304 
305 /**********************************************************************
306  * USBD_EPINTST/USBD_EPINTEN/USBD_EPINTCLR/USBD_EPINTSET/
307  * USBD_EPINTPRI register definitions
308  **********************************************************************/
309 /* End point selection macro (RX) */
310 #define USBD_RX_EP_SEL(e)	(1 << ((e) << 1))
311 
312 /* End point selection macro (TX) */
313 #define USBD_TX_EP_SEL(e)	(1 << (((e) << 1) + 1))
314 
315 /**********************************************************************
316  * USBD_REEP/USBD_DMARST/USBD_DMARCLR/USBD_DMARSET/USBD_EPDMAST/
317  * USBD_EPDMAEN/USBD_EPDMADIS/
318  * USBD_NDDRTINTST/USBD_NDDRTINTCLR/USBD_NDDRTINTSET/
319  * USBD_EOTINTST/USBD_EOTINTCLR/USBD_EOTINTSET/
320  * USBD_SYSERRTINTST/USBD_SYSERRTINTCLR/USBD_SYSERRTINTSET
321  * register definitions
322  **********************************************************************/
323 /* Endpoint selection macro */
324 #define USBD_EP_SEL(e)		(1 << (e))
325 
326 /**********************************************************************
327  * SBD_DMAINTST/USBD_DMAINTEN
328  **********************************************************************/
329 #define USBD_SYS_ERR_INT	(1 << 2)
330 #define USBD_NEW_DD_INT		(1 << 1)
331 #define USBD_EOT_INT		(1 << 0)
332 
333 /**********************************************************************
334  * USBD_RXPLEN register definitions
335  **********************************************************************/
336 #define USBD_PKT_RDY		(1 << 11)
337 #define USBD_DV			(1 << 10)
338 #define USBD_PK_LEN_MASK	0x3FF
339 
340 /**********************************************************************
341  * USBD_CTRL register definitions
342  **********************************************************************/
343 #define USBD_LOG_ENDPOINT(e)	((e) << 2)
344 #define USBD_WR_EN		(1 << 1)
345 #define USBD_RD_EN		(1 << 0)
346 
347 /**********************************************************************
348  * USBD_CMDCODE register definitions
349  **********************************************************************/
350 #define USBD_CMD_CODE(c)	((c) << 16)
351 #define USBD_CMD_PHASE(p)	((p) << 8)
352 
353 /**********************************************************************
354  * USBD_DMARST/USBD_DMARCLR/USBD_DMARSET register definitions
355  **********************************************************************/
356 #define USBD_DMAEP(e)		(1 << (e))
357 
358 /* DD (DMA Descriptor) structure, requires word alignment */
359 struct lpc32xx_usbd_dd {
360 	u32 *dd_next;
361 	u32 dd_setup;
362 	u32 dd_buffer_addr;
363 	u32 dd_status;
364 	u32 dd_iso_ps_mem_addr;
365 };
366 
367 /* dd_setup bit defines */
368 #define DD_SETUP_ATLE_DMA_MODE	0x01
369 #define DD_SETUP_NEXT_DD_VALID	0x04
370 #define DD_SETUP_ISO_EP		0x10
371 #define DD_SETUP_PACKETLEN(n)	(((n) & 0x7FF) << 5)
372 #define DD_SETUP_DMALENBYTES(n)	(((n) & 0xFFFF) << 16)
373 
374 /* dd_status bit defines */
375 #define DD_STATUS_DD_RETIRED	0x01
376 #define DD_STATUS_STS_MASK	0x1E
377 #define DD_STATUS_STS_NS	0x00 /* Not serviced */
378 #define DD_STATUS_STS_BS	0x02 /* Being serviced */
379 #define DD_STATUS_STS_NC	0x04 /* Normal completion */
380 #define DD_STATUS_STS_DUR	0x06 /* Data underrun (short packet) */
381 #define DD_STATUS_STS_DOR	0x08 /* Data overrun */
382 #define DD_STATUS_STS_SE	0x12 /* System error */
383 #define DD_STATUS_PKT_VAL	0x20 /* Packet valid */
384 #define DD_STATUS_LSB_EX	0x40 /* LS byte extracted (ATLE) */
385 #define DD_STATUS_MSB_EX	0x80 /* MS byte extracted (ATLE) */
386 #define DD_STATUS_MLEN(n)	(((n) >> 8) & 0x3F)
387 #define DD_STATUS_CURDMACNT(n)	(((n) >> 16) & 0xFFFF)
388 
389 /*
390  *
391  * Protocol engine bits below
392  *
393  */
394 /* Device Interrupt Bit Definitions */
395 #define FRAME_INT		0x00000001
396 #define EP_FAST_INT		0x00000002
397 #define EP_SLOW_INT		0x00000004
398 #define DEV_STAT_INT		0x00000008
399 #define CCEMTY_INT		0x00000010
400 #define CDFULL_INT		0x00000020
401 #define RxENDPKT_INT		0x00000040
402 #define TxENDPKT_INT		0x00000080
403 #define EP_RLZED_INT		0x00000100
404 #define ERR_INT			0x00000200
405 
406 /* Rx & Tx Packet Length Definitions */
407 #define PKT_LNGTH_MASK		0x000003FF
408 #define PKT_DV			0x00000400
409 #define PKT_RDY			0x00000800
410 
411 /* USB Control Definitions */
412 #define CTRL_RD_EN		0x00000001
413 #define CTRL_WR_EN		0x00000002
414 
415 /* Command Codes */
416 #define CMD_SET_ADDR		0x00D00500
417 #define CMD_CFG_DEV		0x00D80500
418 #define CMD_SET_MODE		0x00F30500
419 #define CMD_RD_FRAME		0x00F50500
420 #define DAT_RD_FRAME		0x00F50200
421 #define CMD_RD_TEST		0x00FD0500
422 #define DAT_RD_TEST		0x00FD0200
423 #define CMD_SET_DEV_STAT	0x00FE0500
424 #define CMD_GET_DEV_STAT	0x00FE0500
425 #define DAT_GET_DEV_STAT	0x00FE0200
426 #define CMD_GET_ERR_CODE	0x00FF0500
427 #define DAT_GET_ERR_CODE	0x00FF0200
428 #define CMD_RD_ERR_STAT		0x00FB0500
429 #define DAT_RD_ERR_STAT		0x00FB0200
430 #define DAT_WR_BYTE(x)		(0x00000100 | ((x) << 16))
431 #define CMD_SEL_EP(x)		(0x00000500 | ((x) << 16))
432 #define DAT_SEL_EP(x)		(0x00000200 | ((x) << 16))
433 #define CMD_SEL_EP_CLRI(x)	(0x00400500 | ((x) << 16))
434 #define DAT_SEL_EP_CLRI(x)	(0x00400200 | ((x) << 16))
435 #define CMD_SET_EP_STAT(x)	(0x00400500 | ((x) << 16))
436 #define CMD_CLR_BUF		0x00F20500
437 #define DAT_CLR_BUF		0x00F20200
438 #define CMD_VALID_BUF		0x00FA0500
439 
440 /* Device Address Register Definitions */
441 #define DEV_ADDR_MASK		0x7F
442 #define DEV_EN			0x80
443 
444 /* Device Configure Register Definitions */
445 #define CONF_DVICE		0x01
446 
447 /* Device Mode Register Definitions */
448 #define AP_CLK			0x01
449 #define INAK_CI			0x02
450 #define INAK_CO			0x04
451 #define INAK_II			0x08
452 #define INAK_IO			0x10
453 #define INAK_BI			0x20
454 #define INAK_BO			0x40
455 
456 /* Device Status Register Definitions */
457 #define DEV_CON			0x01
458 #define DEV_CON_CH		0x02
459 #define DEV_SUS			0x04
460 #define DEV_SUS_CH		0x08
461 #define DEV_RST			0x10
462 
463 /* Error Code Register Definitions */
464 #define ERR_EC_MASK		0x0F
465 #define ERR_EA			0x10
466 
467 /* Error Status Register Definitions */
468 #define ERR_PID			0x01
469 #define ERR_UEPKT		0x02
470 #define ERR_DCRC		0x04
471 #define ERR_TIMOUT		0x08
472 #define ERR_EOP			0x10
473 #define ERR_B_OVRN		0x20
474 #define ERR_BTSTF		0x40
475 #define ERR_TGL			0x80
476 
477 /* Endpoint Select Register Definitions */
478 #define EP_SEL_F		0x01
479 #define EP_SEL_ST		0x02
480 #define EP_SEL_STP		0x04
481 #define EP_SEL_PO		0x08
482 #define EP_SEL_EPN		0x10
483 #define EP_SEL_B_1_FULL		0x20
484 #define EP_SEL_B_2_FULL		0x40
485 
486 /* Endpoint Status Register Definitions */
487 #define EP_STAT_ST		0x01
488 #define EP_STAT_DA		0x20
489 #define EP_STAT_RF_MO		0x40
490 #define EP_STAT_CND_ST		0x80
491 
492 /* Clear Buffer Register Definitions */
493 #define CLR_BUF_PO		0x01
494 
495 /* DMA Interrupt Bit Definitions */
496 #define EOT_INT			0x01
497 #define NDD_REQ_INT		0x02
498 #define SYS_ERR_INT		0x04
499 
500 #define	DRIVER_VERSION	"1.03"
501 static const char driver_name[] = "lpc32xx_udc";
502 
503 /*
504  *
505  * proc interface support
506  *
507  */
508 #ifdef CONFIG_USB_GADGET_DEBUG_FILES
509 static char *epnames[] = {"INT", "ISO", "BULK", "CTRL"};
510 static const char debug_filename[] = "driver/udc";
511 
512 static void proc_ep_show(struct seq_file *s, struct lpc32xx_ep *ep)
513 {
514 	struct lpc32xx_request *req;
515 
516 	seq_printf(s, "\n");
517 	seq_printf(s, "%12s, maxpacket %4d %3s",
518 			ep->ep.name, ep->ep.maxpacket,
519 			ep->is_in ? "in" : "out");
520 	seq_printf(s, " type %4s", epnames[ep->eptype]);
521 	seq_printf(s, " ints: %12d", ep->totalints);
522 
523 	if (list_empty(&ep->queue))
524 		seq_printf(s, "\t(queue empty)\n");
525 	else {
526 		list_for_each_entry(req, &ep->queue, queue) {
527 			u32 length = req->req.actual;
528 
529 			seq_printf(s, "\treq %p len %d/%d buf %p\n",
530 				   &req->req, length,
531 				   req->req.length, req->req.buf);
532 		}
533 	}
534 }
535 
536 static int proc_udc_show(struct seq_file *s, void *unused)
537 {
538 	struct lpc32xx_udc *udc = s->private;
539 	struct lpc32xx_ep *ep;
540 	unsigned long flags;
541 
542 	seq_printf(s, "%s: version %s\n", driver_name, DRIVER_VERSION);
543 
544 	spin_lock_irqsave(&udc->lock, flags);
545 
546 	seq_printf(s, "vbus %s, pullup %s, %s powered%s, gadget %s\n\n",
547 		   udc->vbus ? "present" : "off",
548 		   udc->enabled ? (udc->vbus ? "active" : "enabled") :
549 		   "disabled",
550 		   udc->selfpowered ? "self" : "VBUS",
551 		   udc->suspended ? ", suspended" : "",
552 		   udc->driver ? udc->driver->driver.name : "(none)");
553 
554 	if (udc->enabled && udc->vbus) {
555 		proc_ep_show(s, &udc->ep[0]);
556 		list_for_each_entry(ep, &udc->gadget.ep_list, ep.ep_list)
557 			proc_ep_show(s, ep);
558 	}
559 
560 	spin_unlock_irqrestore(&udc->lock, flags);
561 
562 	return 0;
563 }
564 
565 static int proc_udc_open(struct inode *inode, struct file *file)
566 {
567 	return single_open(file, proc_udc_show, PDE_DATA(inode));
568 }
569 
570 static const struct file_operations proc_ops = {
571 	.owner		= THIS_MODULE,
572 	.open		= proc_udc_open,
573 	.read		= seq_read,
574 	.llseek		= seq_lseek,
575 	.release	= single_release,
576 };
577 
578 static void create_debug_file(struct lpc32xx_udc *udc)
579 {
580 	udc->pde = debugfs_create_file(debug_filename, 0, NULL, udc, &proc_ops);
581 }
582 
583 static void remove_debug_file(struct lpc32xx_udc *udc)
584 {
585 	debugfs_remove(udc->pde);
586 }
587 
588 #else
589 static inline void create_debug_file(struct lpc32xx_udc *udc) {}
590 static inline void remove_debug_file(struct lpc32xx_udc *udc) {}
591 #endif
592 
593 /* Primary initialization sequence for the ISP1301 transceiver */
594 static void isp1301_udc_configure(struct lpc32xx_udc *udc)
595 {
596 	/* LPC32XX only supports DAT_SE0 USB mode */
597 	/* This sequence is important */
598 
599 	/* Disable transparent UART mode first */
600 	i2c_smbus_write_byte_data(udc->isp1301_i2c_client,
601 		(ISP1301_I2C_MODE_CONTROL_1 | ISP1301_I2C_REG_CLEAR_ADDR),
602 		MC1_UART_EN);
603 
604 	/* Set full speed and SE0 mode */
605 	i2c_smbus_write_byte_data(udc->isp1301_i2c_client,
606 		(ISP1301_I2C_MODE_CONTROL_1 | ISP1301_I2C_REG_CLEAR_ADDR), ~0);
607 	i2c_smbus_write_byte_data(udc->isp1301_i2c_client,
608 		ISP1301_I2C_MODE_CONTROL_1, (MC1_SPEED_REG | MC1_DAT_SE0));
609 
610 	/*
611 	 * The PSW_OE enable bit state is reversed in the ISP1301 User's Guide
612 	 */
613 	i2c_smbus_write_byte_data(udc->isp1301_i2c_client,
614 		(ISP1301_I2C_MODE_CONTROL_2 | ISP1301_I2C_REG_CLEAR_ADDR), ~0);
615 	i2c_smbus_write_byte_data(udc->isp1301_i2c_client,
616 		ISP1301_I2C_MODE_CONTROL_2, (MC2_BI_DI | MC2_SPD_SUSP_CTRL));
617 
618 	/* Driver VBUS_DRV high or low depending on board setup */
619 	if (udc->board->vbus_drv_pol != 0)
620 		i2c_smbus_write_byte_data(udc->isp1301_i2c_client,
621 			ISP1301_I2C_OTG_CONTROL_1, OTG1_VBUS_DRV);
622 	else
623 		i2c_smbus_write_byte_data(udc->isp1301_i2c_client,
624 			ISP1301_I2C_OTG_CONTROL_1 | ISP1301_I2C_REG_CLEAR_ADDR,
625 			OTG1_VBUS_DRV);
626 
627 	/* Bi-directional mode with suspend control
628 	 * Enable both pulldowns for now - the pullup will be enable when VBUS
629 	 * is detected */
630 	i2c_smbus_write_byte_data(udc->isp1301_i2c_client,
631 		(ISP1301_I2C_OTG_CONTROL_1 | ISP1301_I2C_REG_CLEAR_ADDR), ~0);
632 	i2c_smbus_write_byte_data(udc->isp1301_i2c_client,
633 		ISP1301_I2C_OTG_CONTROL_1,
634 		(0 | OTG1_DM_PULLDOWN | OTG1_DP_PULLDOWN));
635 
636 	/* Discharge VBUS (just in case) */
637 	i2c_smbus_write_byte_data(udc->isp1301_i2c_client,
638 		ISP1301_I2C_OTG_CONTROL_1, OTG1_VBUS_DISCHRG);
639 	msleep(1);
640 	i2c_smbus_write_byte_data(udc->isp1301_i2c_client,
641 		(ISP1301_I2C_OTG_CONTROL_1 | ISP1301_I2C_REG_CLEAR_ADDR),
642 		OTG1_VBUS_DISCHRG);
643 
644 	/* Clear and enable VBUS high edge interrupt */
645 	i2c_smbus_write_byte_data(udc->isp1301_i2c_client,
646 		ISP1301_I2C_INTERRUPT_LATCH | ISP1301_I2C_REG_CLEAR_ADDR, ~0);
647 	i2c_smbus_write_byte_data(udc->isp1301_i2c_client,
648 		ISP1301_I2C_INTERRUPT_FALLING | ISP1301_I2C_REG_CLEAR_ADDR, ~0);
649 	i2c_smbus_write_byte_data(udc->isp1301_i2c_client,
650 		ISP1301_I2C_INTERRUPT_FALLING, INT_VBUS_VLD);
651 	i2c_smbus_write_byte_data(udc->isp1301_i2c_client,
652 		ISP1301_I2C_INTERRUPT_RISING | ISP1301_I2C_REG_CLEAR_ADDR, ~0);
653 	i2c_smbus_write_byte_data(udc->isp1301_i2c_client,
654 		ISP1301_I2C_INTERRUPT_RISING, INT_VBUS_VLD);
655 
656 	/* Enable usb_need_clk clock after transceiver is initialized */
657 	writel((readl(USB_CTRL) | USB_DEV_NEED_CLK_EN), USB_CTRL);
658 
659 	dev_info(udc->dev, "ISP1301 Vendor ID  : 0x%04x\n",
660 		 i2c_smbus_read_word_data(udc->isp1301_i2c_client, 0x00));
661 	dev_info(udc->dev, "ISP1301 Product ID : 0x%04x\n",
662 		 i2c_smbus_read_word_data(udc->isp1301_i2c_client, 0x02));
663 	dev_info(udc->dev, "ISP1301 Version ID : 0x%04x\n",
664 		 i2c_smbus_read_word_data(udc->isp1301_i2c_client, 0x14));
665 }
666 
667 /* Enables or disables the USB device pullup via the ISP1301 transceiver */
668 static void isp1301_pullup_set(struct lpc32xx_udc *udc)
669 {
670 	if (udc->pullup)
671 		/* Enable pullup for bus signalling */
672 		i2c_smbus_write_byte_data(udc->isp1301_i2c_client,
673 			ISP1301_I2C_OTG_CONTROL_1, OTG1_DP_PULLUP);
674 	else
675 		/* Enable pullup for bus signalling */
676 		i2c_smbus_write_byte_data(udc->isp1301_i2c_client,
677 			ISP1301_I2C_OTG_CONTROL_1 | ISP1301_I2C_REG_CLEAR_ADDR,
678 			OTG1_DP_PULLUP);
679 }
680 
681 static void pullup_work(struct work_struct *work)
682 {
683 	struct lpc32xx_udc *udc =
684 		container_of(work, struct lpc32xx_udc, pullup_job);
685 
686 	isp1301_pullup_set(udc);
687 }
688 
689 static void isp1301_pullup_enable(struct lpc32xx_udc *udc, int en_pullup,
690 				  int block)
691 {
692 	if (en_pullup == udc->pullup)
693 		return;
694 
695 	udc->pullup = en_pullup;
696 	if (block)
697 		isp1301_pullup_set(udc);
698 	else
699 		/* defer slow i2c pull up setting */
700 		schedule_work(&udc->pullup_job);
701 }
702 
703 #ifdef CONFIG_PM
704 /* Powers up or down the ISP1301 transceiver */
705 static void isp1301_set_powerstate(struct lpc32xx_udc *udc, int enable)
706 {
707 	if (enable != 0)
708 		/* Power up ISP1301 - this ISP1301 will automatically wakeup
709 		   when VBUS is detected */
710 		i2c_smbus_write_byte_data(udc->isp1301_i2c_client,
711 			ISP1301_I2C_MODE_CONTROL_2 | ISP1301_I2C_REG_CLEAR_ADDR,
712 			MC2_GLOBAL_PWR_DN);
713 	else
714 		/* Power down ISP1301 */
715 		i2c_smbus_write_byte_data(udc->isp1301_i2c_client,
716 			ISP1301_I2C_MODE_CONTROL_2, MC2_GLOBAL_PWR_DN);
717 }
718 
719 static void power_work(struct work_struct *work)
720 {
721 	struct lpc32xx_udc *udc =
722 		container_of(work, struct lpc32xx_udc, power_job);
723 
724 	isp1301_set_powerstate(udc, udc->poweron);
725 }
726 #endif
727 
728 /*
729  *
730  * USB protocol engine command/data read/write helper functions
731  *
732  */
733 /* Issues a single command to the USB device state machine */
734 static void udc_protocol_cmd_w(struct lpc32xx_udc *udc, u32 cmd)
735 {
736 	u32 pass = 0;
737 	int to;
738 
739 	/* EP may lock on CLRI if this read isn't done */
740 	u32 tmp = readl(USBD_DEVINTST(udc->udp_baseaddr));
741 	(void) tmp;
742 
743 	while (pass == 0) {
744 		writel(USBD_CCEMPTY, USBD_DEVINTCLR(udc->udp_baseaddr));
745 
746 		/* Write command code */
747 		writel(cmd, USBD_CMDCODE(udc->udp_baseaddr));
748 		to = 10000;
749 		while (((readl(USBD_DEVINTST(udc->udp_baseaddr)) &
750 			 USBD_CCEMPTY) == 0) && (to > 0)) {
751 			to--;
752 		}
753 
754 		if (to > 0)
755 			pass = 1;
756 
757 		cpu_relax();
758 	}
759 }
760 
761 /* Issues 2 commands (or command and data) to the USB device state machine */
762 static inline void udc_protocol_cmd_data_w(struct lpc32xx_udc *udc, u32 cmd,
763 					   u32 data)
764 {
765 	udc_protocol_cmd_w(udc, cmd);
766 	udc_protocol_cmd_w(udc, data);
767 }
768 
769 /* Issues a single command to the USB device state machine and reads
770  * response data */
771 static u32 udc_protocol_cmd_r(struct lpc32xx_udc *udc, u32 cmd)
772 {
773 	u32 tmp;
774 	int to = 1000;
775 
776 	/* Write a command and read data from the protocol engine */
777 	writel((USBD_CDFULL | USBD_CCEMPTY),
778 		     USBD_DEVINTCLR(udc->udp_baseaddr));
779 
780 	/* Write command code */
781 	udc_protocol_cmd_w(udc, cmd);
782 
783 	tmp = readl(USBD_DEVINTST(udc->udp_baseaddr));
784 	while ((!(readl(USBD_DEVINTST(udc->udp_baseaddr)) & USBD_CDFULL))
785 	       && (to > 0))
786 		to--;
787 	if (!to)
788 		dev_dbg(udc->dev,
789 			"Protocol engine didn't receive response (CDFULL)\n");
790 
791 	return readl(USBD_CMDDATA(udc->udp_baseaddr));
792 }
793 
794 /*
795  *
796  * USB device interrupt mask support functions
797  *
798  */
799 /* Enable one or more USB device interrupts */
800 static inline void uda_enable_devint(struct lpc32xx_udc *udc, u32 devmask)
801 {
802 	udc->enabled_devints |= devmask;
803 	writel(udc->enabled_devints, USBD_DEVINTEN(udc->udp_baseaddr));
804 }
805 
806 /* Disable one or more USB device interrupts */
807 static inline void uda_disable_devint(struct lpc32xx_udc *udc, u32 mask)
808 {
809 	udc->enabled_devints &= ~mask;
810 	writel(udc->enabled_devints, USBD_DEVINTEN(udc->udp_baseaddr));
811 }
812 
813 /* Clear one or more USB device interrupts */
814 static inline void uda_clear_devint(struct lpc32xx_udc *udc, u32 mask)
815 {
816 	writel(mask, USBD_DEVINTCLR(udc->udp_baseaddr));
817 }
818 
819 /*
820  *
821  * Endpoint interrupt disable/enable functions
822  *
823  */
824 /* Enable one or more USB endpoint interrupts */
825 static void uda_enable_hwepint(struct lpc32xx_udc *udc, u32 hwep)
826 {
827 	udc->enabled_hwepints |= (1 << hwep);
828 	writel(udc->enabled_hwepints, USBD_EPINTEN(udc->udp_baseaddr));
829 }
830 
831 /* Disable one or more USB endpoint interrupts */
832 static void uda_disable_hwepint(struct lpc32xx_udc *udc, u32 hwep)
833 {
834 	udc->enabled_hwepints &= ~(1 << hwep);
835 	writel(udc->enabled_hwepints, USBD_EPINTEN(udc->udp_baseaddr));
836 }
837 
838 /* Clear one or more USB endpoint interrupts */
839 static inline void uda_clear_hwepint(struct lpc32xx_udc *udc, u32 hwep)
840 {
841 	writel((1 << hwep), USBD_EPINTCLR(udc->udp_baseaddr));
842 }
843 
844 /* Enable DMA for the HW channel */
845 static inline void udc_ep_dma_enable(struct lpc32xx_udc *udc, u32 hwep)
846 {
847 	writel((1 << hwep), USBD_EPDMAEN(udc->udp_baseaddr));
848 }
849 
850 /* Disable DMA for the HW channel */
851 static inline void udc_ep_dma_disable(struct lpc32xx_udc *udc, u32 hwep)
852 {
853 	writel((1 << hwep), USBD_EPDMADIS(udc->udp_baseaddr));
854 }
855 
856 /*
857  *
858  * Endpoint realize/unrealize functions
859  *
860  */
861 /* Before an endpoint can be used, it needs to be realized
862  * in the USB protocol engine - this realizes the endpoint.
863  * The interrupt (FIFO or DMA) is not enabled with this function */
864 static void udc_realize_hwep(struct lpc32xx_udc *udc, u32 hwep,
865 			     u32 maxpacket)
866 {
867 	int to = 1000;
868 
869 	writel(USBD_EP_RLZED, USBD_DEVINTCLR(udc->udp_baseaddr));
870 	writel(hwep, USBD_EPIND(udc->udp_baseaddr));
871 	udc->realized_eps |= (1 << hwep);
872 	writel(udc->realized_eps, USBD_REEP(udc->udp_baseaddr));
873 	writel(maxpacket, USBD_EPMAXPSIZE(udc->udp_baseaddr));
874 
875 	/* Wait until endpoint is realized in hardware */
876 	while ((!(readl(USBD_DEVINTST(udc->udp_baseaddr)) &
877 		  USBD_EP_RLZED)) && (to > 0))
878 		to--;
879 	if (!to)
880 		dev_dbg(udc->dev, "EP not correctly realized in hardware\n");
881 
882 	writel(USBD_EP_RLZED, USBD_DEVINTCLR(udc->udp_baseaddr));
883 }
884 
885 /* Unrealize an EP */
886 static void udc_unrealize_hwep(struct lpc32xx_udc *udc, u32 hwep)
887 {
888 	udc->realized_eps &= ~(1 << hwep);
889 	writel(udc->realized_eps, USBD_REEP(udc->udp_baseaddr));
890 }
891 
892 /*
893  *
894  * Endpoint support functions
895  *
896  */
897 /* Select and clear endpoint interrupt */
898 static u32 udc_selep_clrint(struct lpc32xx_udc *udc, u32 hwep)
899 {
900 	udc_protocol_cmd_w(udc, CMD_SEL_EP_CLRI(hwep));
901 	return udc_protocol_cmd_r(udc, DAT_SEL_EP_CLRI(hwep));
902 }
903 
904 /* Disables the endpoint in the USB protocol engine */
905 static void udc_disable_hwep(struct lpc32xx_udc *udc, u32 hwep)
906 {
907 	udc_protocol_cmd_data_w(udc, CMD_SET_EP_STAT(hwep),
908 				DAT_WR_BYTE(EP_STAT_DA));
909 }
910 
911 /* Stalls the endpoint - endpoint will return STALL */
912 static void udc_stall_hwep(struct lpc32xx_udc *udc, u32 hwep)
913 {
914 	udc_protocol_cmd_data_w(udc, CMD_SET_EP_STAT(hwep),
915 				DAT_WR_BYTE(EP_STAT_ST));
916 }
917 
918 /* Clear stall or reset endpoint */
919 static void udc_clrstall_hwep(struct lpc32xx_udc *udc, u32 hwep)
920 {
921 	udc_protocol_cmd_data_w(udc, CMD_SET_EP_STAT(hwep),
922 				DAT_WR_BYTE(0));
923 }
924 
925 /* Select an endpoint for endpoint status, clear, validate */
926 static void udc_select_hwep(struct lpc32xx_udc *udc, u32 hwep)
927 {
928 	udc_protocol_cmd_w(udc, CMD_SEL_EP(hwep));
929 }
930 
931 /*
932  *
933  * Endpoint buffer management functions
934  *
935  */
936 /* Clear the current endpoint's buffer */
937 static void udc_clr_buffer_hwep(struct lpc32xx_udc *udc, u32 hwep)
938 {
939 	udc_select_hwep(udc, hwep);
940 	udc_protocol_cmd_w(udc, CMD_CLR_BUF);
941 }
942 
943 /* Validate the current endpoint's buffer */
944 static void udc_val_buffer_hwep(struct lpc32xx_udc *udc, u32 hwep)
945 {
946 	udc_select_hwep(udc, hwep);
947 	udc_protocol_cmd_w(udc, CMD_VALID_BUF);
948 }
949 
950 static inline u32 udc_clearep_getsts(struct lpc32xx_udc *udc, u32 hwep)
951 {
952 	/* Clear EP interrupt */
953 	uda_clear_hwepint(udc, hwep);
954 	return udc_selep_clrint(udc, hwep);
955 }
956 
957 /*
958  *
959  * USB EP DMA support
960  *
961  */
962 /* Allocate a DMA Descriptor */
963 static struct lpc32xx_usbd_dd_gad *udc_dd_alloc(struct lpc32xx_udc *udc)
964 {
965 	dma_addr_t			dma;
966 	struct lpc32xx_usbd_dd_gad	*dd;
967 
968 	dd = (struct lpc32xx_usbd_dd_gad *) dma_pool_alloc(
969 			udc->dd_cache, (GFP_KERNEL | GFP_DMA), &dma);
970 	if (dd)
971 		dd->this_dma = dma;
972 
973 	return dd;
974 }
975 
976 /* Free a DMA Descriptor */
977 static void udc_dd_free(struct lpc32xx_udc *udc, struct lpc32xx_usbd_dd_gad *dd)
978 {
979 	dma_pool_free(udc->dd_cache, dd, dd->this_dma);
980 }
981 
982 /*
983  *
984  * USB setup and shutdown functions
985  *
986  */
987 /* Enables or disables most of the USB system clocks when low power mode is
988  * needed. Clocks are typically started on a connection event, and disabled
989  * when a cable is disconnected */
990 static void udc_clk_set(struct lpc32xx_udc *udc, int enable)
991 {
992 	if (enable != 0) {
993 		if (udc->clocked)
994 			return;
995 
996 		udc->clocked = 1;
997 
998 		/* 48MHz PLL up */
999 		clk_enable(udc->usb_pll_clk);
1000 
1001 		/* Enable the USB device clock */
1002 		writel(readl(USB_CTRL) | USB_DEV_NEED_CLK_EN,
1003 			     USB_CTRL);
1004 
1005 		clk_enable(udc->usb_otg_clk);
1006 	} else {
1007 		if (!udc->clocked)
1008 			return;
1009 
1010 		udc->clocked = 0;
1011 
1012 		/* Never disable the USB_HCLK during normal operation */
1013 
1014 		/* 48MHz PLL dpwn */
1015 		clk_disable(udc->usb_pll_clk);
1016 
1017 		/* Disable the USB device clock */
1018 		writel(readl(USB_CTRL) & ~USB_DEV_NEED_CLK_EN,
1019 			     USB_CTRL);
1020 
1021 		clk_disable(udc->usb_otg_clk);
1022 	}
1023 }
1024 
1025 /* Set/reset USB device address */
1026 static void udc_set_address(struct lpc32xx_udc *udc, u32 addr)
1027 {
1028 	/* Address will be latched at the end of the status phase, or
1029 	   latched immediately if function is called twice */
1030 	udc_protocol_cmd_data_w(udc, CMD_SET_ADDR,
1031 				DAT_WR_BYTE(DEV_EN | addr));
1032 }
1033 
1034 /* Setup up a IN request for DMA transfer - this consists of determining the
1035  * list of DMA addresses for the transfer, allocating DMA Descriptors,
1036  * installing the DD into the UDCA, and then enabling the DMA for that EP */
1037 static int udc_ep_in_req_dma(struct lpc32xx_udc *udc, struct lpc32xx_ep *ep)
1038 {
1039 	struct lpc32xx_request *req;
1040 	u32 hwep = ep->hwep_num;
1041 
1042 	ep->req_pending = 1;
1043 
1044 	/* There will always be a request waiting here */
1045 	req = list_entry(ep->queue.next, struct lpc32xx_request, queue);
1046 
1047 	/* Place the DD Descriptor into the UDCA */
1048 	udc->udca_v_base[hwep] = req->dd_desc_ptr->this_dma;
1049 
1050 	/* Enable DMA and interrupt for the HW EP */
1051 	udc_ep_dma_enable(udc, hwep);
1052 
1053 	/* Clear ZLP if last packet is not of MAXP size */
1054 	if (req->req.length % ep->ep.maxpacket)
1055 		req->send_zlp = 0;
1056 
1057 	return 0;
1058 }
1059 
1060 /* Setup up a OUT request for DMA transfer - this consists of determining the
1061  * list of DMA addresses for the transfer, allocating DMA Descriptors,
1062  * installing the DD into the UDCA, and then enabling the DMA for that EP */
1063 static int udc_ep_out_req_dma(struct lpc32xx_udc *udc, struct lpc32xx_ep *ep)
1064 {
1065 	struct lpc32xx_request *req;
1066 	u32 hwep = ep->hwep_num;
1067 
1068 	ep->req_pending = 1;
1069 
1070 	/* There will always be a request waiting here */
1071 	req = list_entry(ep->queue.next, struct lpc32xx_request, queue);
1072 
1073 	/* Place the DD Descriptor into the UDCA */
1074 	udc->udca_v_base[hwep] = req->dd_desc_ptr->this_dma;
1075 
1076 	/* Enable DMA and interrupt for the HW EP */
1077 	udc_ep_dma_enable(udc, hwep);
1078 	return 0;
1079 }
1080 
1081 static void udc_disable(struct lpc32xx_udc *udc)
1082 {
1083 	u32 i;
1084 
1085 	/* Disable device */
1086 	udc_protocol_cmd_data_w(udc, CMD_CFG_DEV, DAT_WR_BYTE(0));
1087 	udc_protocol_cmd_data_w(udc, CMD_SET_DEV_STAT, DAT_WR_BYTE(0));
1088 
1089 	/* Disable all device interrupts (including EP0) */
1090 	uda_disable_devint(udc, 0x3FF);
1091 
1092 	/* Disable and reset all endpoint interrupts */
1093 	for (i = 0; i < 32; i++) {
1094 		uda_disable_hwepint(udc, i);
1095 		uda_clear_hwepint(udc, i);
1096 		udc_disable_hwep(udc, i);
1097 		udc_unrealize_hwep(udc, i);
1098 		udc->udca_v_base[i] = 0;
1099 
1100 		/* Disable and clear all interrupts and DMA */
1101 		udc_ep_dma_disable(udc, i);
1102 		writel((1 << i), USBD_EOTINTCLR(udc->udp_baseaddr));
1103 		writel((1 << i), USBD_NDDRTINTCLR(udc->udp_baseaddr));
1104 		writel((1 << i), USBD_SYSERRTINTCLR(udc->udp_baseaddr));
1105 		writel((1 << i), USBD_DMARCLR(udc->udp_baseaddr));
1106 	}
1107 
1108 	/* Disable DMA interrupts */
1109 	writel(0, USBD_DMAINTEN(udc->udp_baseaddr));
1110 
1111 	writel(0, USBD_UDCAH(udc->udp_baseaddr));
1112 }
1113 
1114 static void udc_enable(struct lpc32xx_udc *udc)
1115 {
1116 	u32 i;
1117 	struct lpc32xx_ep *ep = &udc->ep[0];
1118 
1119 	/* Start with known state */
1120 	udc_disable(udc);
1121 
1122 	/* Enable device */
1123 	udc_protocol_cmd_data_w(udc, CMD_SET_DEV_STAT, DAT_WR_BYTE(DEV_CON));
1124 
1125 	/* EP interrupts on high priority, FRAME interrupt on low priority */
1126 	writel(USBD_EP_FAST, USBD_DEVINTPRI(udc->udp_baseaddr));
1127 	writel(0xFFFF, USBD_EPINTPRI(udc->udp_baseaddr));
1128 
1129 	/* Clear any pending device interrupts */
1130 	writel(0x3FF, USBD_DEVINTCLR(udc->udp_baseaddr));
1131 
1132 	/* Setup UDCA - not yet used (DMA) */
1133 	writel(udc->udca_p_base, USBD_UDCAH(udc->udp_baseaddr));
1134 
1135 	/* Only enable EP0 in and out for now, EP0 only works in FIFO mode */
1136 	for (i = 0; i <= 1; i++) {
1137 		udc_realize_hwep(udc, i, ep->ep.maxpacket);
1138 		uda_enable_hwepint(udc, i);
1139 		udc_select_hwep(udc, i);
1140 		udc_clrstall_hwep(udc, i);
1141 		udc_clr_buffer_hwep(udc, i);
1142 	}
1143 
1144 	/* Device interrupt setup */
1145 	uda_clear_devint(udc, (USBD_ERR_INT | USBD_DEV_STAT | USBD_EP_SLOW |
1146 			       USBD_EP_FAST));
1147 	uda_enable_devint(udc, (USBD_ERR_INT | USBD_DEV_STAT | USBD_EP_SLOW |
1148 				USBD_EP_FAST));
1149 
1150 	/* Set device address to 0 - called twice to force a latch in the USB
1151 	   engine without the need of a setup packet status closure */
1152 	udc_set_address(udc, 0);
1153 	udc_set_address(udc, 0);
1154 
1155 	/* Enable master DMA interrupts */
1156 	writel((USBD_SYS_ERR_INT | USBD_EOT_INT),
1157 		     USBD_DMAINTEN(udc->udp_baseaddr));
1158 
1159 	udc->dev_status = 0;
1160 }
1161 
1162 /*
1163  *
1164  * USB device board specific events handled via callbacks
1165  *
1166  */
1167 /* Connection change event - notify board function of change */
1168 static void uda_power_event(struct lpc32xx_udc *udc, u32 conn)
1169 {
1170 	/* Just notify of a connection change event (optional) */
1171 	if (udc->board->conn_chgb != NULL)
1172 		udc->board->conn_chgb(conn);
1173 }
1174 
1175 /* Suspend/resume event - notify board function of change */
1176 static void uda_resm_susp_event(struct lpc32xx_udc *udc, u32 conn)
1177 {
1178 	/* Just notify of a Suspend/resume change event (optional) */
1179 	if (udc->board->susp_chgb != NULL)
1180 		udc->board->susp_chgb(conn);
1181 
1182 	if (conn)
1183 		udc->suspended = 0;
1184 	else
1185 		udc->suspended = 1;
1186 }
1187 
1188 /* Remote wakeup enable/disable - notify board function of change */
1189 static void uda_remwkp_cgh(struct lpc32xx_udc *udc)
1190 {
1191 	if (udc->board->rmwk_chgb != NULL)
1192 		udc->board->rmwk_chgb(udc->dev_status &
1193 				      (1 << USB_DEVICE_REMOTE_WAKEUP));
1194 }
1195 
1196 /* Reads data from FIFO, adjusts for alignment and data size */
1197 static void udc_pop_fifo(struct lpc32xx_udc *udc, u8 *data, u32 bytes)
1198 {
1199 	int n, i, bl;
1200 	u16 *p16;
1201 	u32 *p32, tmp, cbytes;
1202 
1203 	/* Use optimal data transfer method based on source address and size */
1204 	switch (((u32) data) & 0x3) {
1205 	case 0: /* 32-bit aligned */
1206 		p32 = (u32 *) data;
1207 		cbytes = (bytes & ~0x3);
1208 
1209 		/* Copy 32-bit aligned data first */
1210 		for (n = 0; n < cbytes; n += 4)
1211 			*p32++ = readl(USBD_RXDATA(udc->udp_baseaddr));
1212 
1213 		/* Handle any remaining bytes */
1214 		bl = bytes - cbytes;
1215 		if (bl) {
1216 			tmp = readl(USBD_RXDATA(udc->udp_baseaddr));
1217 			for (n = 0; n < bl; n++)
1218 				data[cbytes + n] = ((tmp >> (n * 8)) & 0xFF);
1219 
1220 		}
1221 		break;
1222 
1223 	case 1: /* 8-bit aligned */
1224 	case 3:
1225 		/* Each byte has to be handled independently */
1226 		for (n = 0; n < bytes; n += 4) {
1227 			tmp = readl(USBD_RXDATA(udc->udp_baseaddr));
1228 
1229 			bl = bytes - n;
1230 			if (bl > 3)
1231 				bl = 3;
1232 
1233 			for (i = 0; i < bl; i++)
1234 				data[n + i] = (u8) ((tmp >> (n * 8)) & 0xFF);
1235 		}
1236 		break;
1237 
1238 	case 2: /* 16-bit aligned */
1239 		p16 = (u16 *) data;
1240 		cbytes = (bytes & ~0x3);
1241 
1242 		/* Copy 32-bit sized objects first with 16-bit alignment */
1243 		for (n = 0; n < cbytes; n += 4) {
1244 			tmp = readl(USBD_RXDATA(udc->udp_baseaddr));
1245 			*p16++ = (u16)(tmp & 0xFFFF);
1246 			*p16++ = (u16)((tmp >> 16) & 0xFFFF);
1247 		}
1248 
1249 		/* Handle any remaining bytes */
1250 		bl = bytes - cbytes;
1251 		if (bl) {
1252 			tmp = readl(USBD_RXDATA(udc->udp_baseaddr));
1253 			for (n = 0; n < bl; n++)
1254 				data[cbytes + n] = ((tmp >> (n * 8)) & 0xFF);
1255 		}
1256 		break;
1257 	}
1258 }
1259 
1260 /* Read data from the FIFO for an endpoint. This function is for endpoints (such
1261  * as EP0) that don't use DMA. This function should only be called if a packet
1262  * is known to be ready to read for the endpoint. Note that the endpoint must
1263  * be selected in the protocol engine prior to this call. */
1264 static u32 udc_read_hwep(struct lpc32xx_udc *udc, u32 hwep, u32 *data,
1265 			 u32 bytes)
1266 {
1267 	u32 tmpv;
1268 	int to = 1000;
1269 	u32 tmp, hwrep = ((hwep & 0x1E) << 1) | CTRL_RD_EN;
1270 
1271 	/* Setup read of endpoint */
1272 	writel(hwrep, USBD_CTRL(udc->udp_baseaddr));
1273 
1274 	/* Wait until packet is ready */
1275 	while ((((tmpv = readl(USBD_RXPLEN(udc->udp_baseaddr))) &
1276 		 PKT_RDY) == 0)	&& (to > 0))
1277 		to--;
1278 	if (!to)
1279 		dev_dbg(udc->dev, "No packet ready on FIFO EP read\n");
1280 
1281 	/* Mask out count */
1282 	tmp = tmpv & PKT_LNGTH_MASK;
1283 	if (bytes < tmp)
1284 		tmp = bytes;
1285 
1286 	if ((tmp > 0) && (data != NULL))
1287 		udc_pop_fifo(udc, (u8 *) data, tmp);
1288 
1289 	writel(((hwep & 0x1E) << 1), USBD_CTRL(udc->udp_baseaddr));
1290 
1291 	/* Clear the buffer */
1292 	udc_clr_buffer_hwep(udc, hwep);
1293 
1294 	return tmp;
1295 }
1296 
1297 /* Stuffs data into the FIFO, adjusts for alignment and data size */
1298 static void udc_stuff_fifo(struct lpc32xx_udc *udc, u8 *data, u32 bytes)
1299 {
1300 	int n, i, bl;
1301 	u16 *p16;
1302 	u32 *p32, tmp, cbytes;
1303 
1304 	/* Use optimal data transfer method based on source address and size */
1305 	switch (((u32) data) & 0x3) {
1306 	case 0: /* 32-bit aligned */
1307 		p32 = (u32 *) data;
1308 		cbytes = (bytes & ~0x3);
1309 
1310 		/* Copy 32-bit aligned data first */
1311 		for (n = 0; n < cbytes; n += 4)
1312 			writel(*p32++, USBD_TXDATA(udc->udp_baseaddr));
1313 
1314 		/* Handle any remaining bytes */
1315 		bl = bytes - cbytes;
1316 		if (bl) {
1317 			tmp = 0;
1318 			for (n = 0; n < bl; n++)
1319 				tmp |= data[cbytes + n] << (n * 8);
1320 
1321 			writel(tmp, USBD_TXDATA(udc->udp_baseaddr));
1322 		}
1323 		break;
1324 
1325 	case 1: /* 8-bit aligned */
1326 	case 3:
1327 		/* Each byte has to be handled independently */
1328 		for (n = 0; n < bytes; n += 4) {
1329 			bl = bytes - n;
1330 			if (bl > 4)
1331 				bl = 4;
1332 
1333 			tmp = 0;
1334 			for (i = 0; i < bl; i++)
1335 				tmp |= data[n + i] << (i * 8);
1336 
1337 			writel(tmp, USBD_TXDATA(udc->udp_baseaddr));
1338 		}
1339 		break;
1340 
1341 	case 2: /* 16-bit aligned */
1342 		p16 = (u16 *) data;
1343 		cbytes = (bytes & ~0x3);
1344 
1345 		/* Copy 32-bit aligned data first */
1346 		for (n = 0; n < cbytes; n += 4) {
1347 			tmp = *p16++ & 0xFFFF;
1348 			tmp |= (*p16++ & 0xFFFF) << 16;
1349 			writel(tmp, USBD_TXDATA(udc->udp_baseaddr));
1350 		}
1351 
1352 		/* Handle any remaining bytes */
1353 		bl = bytes - cbytes;
1354 		if (bl) {
1355 			tmp = 0;
1356 			for (n = 0; n < bl; n++)
1357 				tmp |= data[cbytes + n] << (n * 8);
1358 
1359 			writel(tmp, USBD_TXDATA(udc->udp_baseaddr));
1360 		}
1361 		break;
1362 	}
1363 }
1364 
1365 /* Write data to the FIFO for an endpoint. This function is for endpoints (such
1366  * as EP0) that don't use DMA. Note that the endpoint must be selected in the
1367  * protocol engine prior to this call. */
1368 static void udc_write_hwep(struct lpc32xx_udc *udc, u32 hwep, u32 *data,
1369 			   u32 bytes)
1370 {
1371 	u32 hwwep = ((hwep & 0x1E) << 1) | CTRL_WR_EN;
1372 
1373 	if ((bytes > 0) && (data == NULL))
1374 		return;
1375 
1376 	/* Setup write of endpoint */
1377 	writel(hwwep, USBD_CTRL(udc->udp_baseaddr));
1378 
1379 	writel(bytes, USBD_TXPLEN(udc->udp_baseaddr));
1380 
1381 	/* Need at least 1 byte to trigger TX */
1382 	if (bytes == 0)
1383 		writel(0, USBD_TXDATA(udc->udp_baseaddr));
1384 	else
1385 		udc_stuff_fifo(udc, (u8 *) data, bytes);
1386 
1387 	writel(((hwep & 0x1E) << 1), USBD_CTRL(udc->udp_baseaddr));
1388 
1389 	udc_val_buffer_hwep(udc, hwep);
1390 }
1391 
1392 /* USB device reset - resets USB to a default state with just EP0
1393    enabled */
1394 static void uda_usb_reset(struct lpc32xx_udc *udc)
1395 {
1396 	u32 i = 0;
1397 	/* Re-init device controller and EP0 */
1398 	udc_enable(udc);
1399 	udc->gadget.speed = USB_SPEED_FULL;
1400 
1401 	for (i = 1; i < NUM_ENDPOINTS; i++) {
1402 		struct lpc32xx_ep *ep = &udc->ep[i];
1403 		ep->req_pending = 0;
1404 	}
1405 }
1406 
1407 /* Send a ZLP on EP0 */
1408 static void udc_ep0_send_zlp(struct lpc32xx_udc *udc)
1409 {
1410 	udc_write_hwep(udc, EP_IN, NULL, 0);
1411 }
1412 
1413 /* Get current frame number */
1414 static u16 udc_get_current_frame(struct lpc32xx_udc *udc)
1415 {
1416 	u16 flo, fhi;
1417 
1418 	udc_protocol_cmd_w(udc, CMD_RD_FRAME);
1419 	flo = (u16) udc_protocol_cmd_r(udc, DAT_RD_FRAME);
1420 	fhi = (u16) udc_protocol_cmd_r(udc, DAT_RD_FRAME);
1421 
1422 	return (fhi << 8) | flo;
1423 }
1424 
1425 /* Set the device as configured - enables all endpoints */
1426 static inline void udc_set_device_configured(struct lpc32xx_udc *udc)
1427 {
1428 	udc_protocol_cmd_data_w(udc, CMD_CFG_DEV, DAT_WR_BYTE(CONF_DVICE));
1429 }
1430 
1431 /* Set the device as unconfigured - disables all endpoints */
1432 static inline void udc_set_device_unconfigured(struct lpc32xx_udc *udc)
1433 {
1434 	udc_protocol_cmd_data_w(udc, CMD_CFG_DEV, DAT_WR_BYTE(0));
1435 }
1436 
1437 /* reinit == restore initial software state */
1438 static void udc_reinit(struct lpc32xx_udc *udc)
1439 {
1440 	u32 i;
1441 
1442 	INIT_LIST_HEAD(&udc->gadget.ep_list);
1443 	INIT_LIST_HEAD(&udc->gadget.ep0->ep_list);
1444 
1445 	for (i = 0; i < NUM_ENDPOINTS; i++) {
1446 		struct lpc32xx_ep *ep = &udc->ep[i];
1447 
1448 		if (i != 0)
1449 			list_add_tail(&ep->ep.ep_list, &udc->gadget.ep_list);
1450 		usb_ep_set_maxpacket_limit(&ep->ep, ep->maxpacket);
1451 		INIT_LIST_HEAD(&ep->queue);
1452 		ep->req_pending = 0;
1453 	}
1454 
1455 	udc->ep0state = WAIT_FOR_SETUP;
1456 }
1457 
1458 /* Must be called with lock */
1459 static void done(struct lpc32xx_ep *ep, struct lpc32xx_request *req, int status)
1460 {
1461 	struct lpc32xx_udc *udc = ep->udc;
1462 
1463 	list_del_init(&req->queue);
1464 	if (req->req.status == -EINPROGRESS)
1465 		req->req.status = status;
1466 	else
1467 		status = req->req.status;
1468 
1469 	if (ep->lep) {
1470 		usb_gadget_unmap_request(&udc->gadget, &req->req, ep->is_in);
1471 
1472 		/* Free DDs */
1473 		udc_dd_free(udc, req->dd_desc_ptr);
1474 	}
1475 
1476 	if (status && status != -ESHUTDOWN)
1477 		ep_dbg(ep, "%s done %p, status %d\n", ep->ep.name, req, status);
1478 
1479 	ep->req_pending = 0;
1480 	spin_unlock(&udc->lock);
1481 	usb_gadget_giveback_request(&ep->ep, &req->req);
1482 	spin_lock(&udc->lock);
1483 }
1484 
1485 /* Must be called with lock */
1486 static void nuke(struct lpc32xx_ep *ep, int status)
1487 {
1488 	struct lpc32xx_request *req;
1489 
1490 	while (!list_empty(&ep->queue)) {
1491 		req = list_entry(ep->queue.next, struct lpc32xx_request, queue);
1492 		done(ep, req, status);
1493 	}
1494 
1495 	if (status == -ESHUTDOWN) {
1496 		uda_disable_hwepint(ep->udc, ep->hwep_num);
1497 		udc_disable_hwep(ep->udc, ep->hwep_num);
1498 	}
1499 }
1500 
1501 /* IN endpoint 0 transfer */
1502 static int udc_ep0_in_req(struct lpc32xx_udc *udc)
1503 {
1504 	struct lpc32xx_request *req;
1505 	struct lpc32xx_ep *ep0 = &udc->ep[0];
1506 	u32 tsend, ts = 0;
1507 
1508 	if (list_empty(&ep0->queue))
1509 		/* Nothing to send */
1510 		return 0;
1511 	else
1512 		req = list_entry(ep0->queue.next, struct lpc32xx_request,
1513 				 queue);
1514 
1515 	tsend = ts = req->req.length - req->req.actual;
1516 	if (ts == 0) {
1517 		/* Send a ZLP */
1518 		udc_ep0_send_zlp(udc);
1519 		done(ep0, req, 0);
1520 		return 1;
1521 	} else if (ts > ep0->ep.maxpacket)
1522 		ts = ep0->ep.maxpacket; /* Just send what we can */
1523 
1524 	/* Write data to the EP0 FIFO and start transfer */
1525 	udc_write_hwep(udc, EP_IN, (req->req.buf + req->req.actual), ts);
1526 
1527 	/* Increment data pointer */
1528 	req->req.actual += ts;
1529 
1530 	if (tsend >= ep0->ep.maxpacket)
1531 		return 0; /* Stay in data transfer state */
1532 
1533 	/* Transfer request is complete */
1534 	udc->ep0state = WAIT_FOR_SETUP;
1535 	done(ep0, req, 0);
1536 	return 1;
1537 }
1538 
1539 /* OUT endpoint 0 transfer */
1540 static int udc_ep0_out_req(struct lpc32xx_udc *udc)
1541 {
1542 	struct lpc32xx_request *req;
1543 	struct lpc32xx_ep *ep0 = &udc->ep[0];
1544 	u32 tr, bufferspace;
1545 
1546 	if (list_empty(&ep0->queue))
1547 		return 0;
1548 	else
1549 		req = list_entry(ep0->queue.next, struct lpc32xx_request,
1550 				 queue);
1551 
1552 	if (req) {
1553 		if (req->req.length == 0) {
1554 			/* Just dequeue request */
1555 			done(ep0, req, 0);
1556 			udc->ep0state = WAIT_FOR_SETUP;
1557 			return 1;
1558 		}
1559 
1560 		/* Get data from FIFO */
1561 		bufferspace = req->req.length - req->req.actual;
1562 		if (bufferspace > ep0->ep.maxpacket)
1563 			bufferspace = ep0->ep.maxpacket;
1564 
1565 		/* Copy data to buffer */
1566 		prefetchw(req->req.buf + req->req.actual);
1567 		tr = udc_read_hwep(udc, EP_OUT, req->req.buf + req->req.actual,
1568 				   bufferspace);
1569 		req->req.actual += bufferspace;
1570 
1571 		if (tr < ep0->ep.maxpacket) {
1572 			/* This is the last packet */
1573 			done(ep0, req, 0);
1574 			udc->ep0state = WAIT_FOR_SETUP;
1575 			return 1;
1576 		}
1577 	}
1578 
1579 	return 0;
1580 }
1581 
1582 /* Must be called with lock */
1583 static void stop_activity(struct lpc32xx_udc *udc)
1584 {
1585 	struct usb_gadget_driver *driver = udc->driver;
1586 	int i;
1587 
1588 	if (udc->gadget.speed == USB_SPEED_UNKNOWN)
1589 		driver = NULL;
1590 
1591 	udc->gadget.speed = USB_SPEED_UNKNOWN;
1592 	udc->suspended = 0;
1593 
1594 	for (i = 0; i < NUM_ENDPOINTS; i++) {
1595 		struct lpc32xx_ep *ep = &udc->ep[i];
1596 		nuke(ep, -ESHUTDOWN);
1597 	}
1598 	if (driver) {
1599 		spin_unlock(&udc->lock);
1600 		driver->disconnect(&udc->gadget);
1601 		spin_lock(&udc->lock);
1602 	}
1603 
1604 	isp1301_pullup_enable(udc, 0, 0);
1605 	udc_disable(udc);
1606 	udc_reinit(udc);
1607 }
1608 
1609 /*
1610  * Activate or kill host pullup
1611  * Can be called with or without lock
1612  */
1613 static void pullup(struct lpc32xx_udc *udc, int is_on)
1614 {
1615 	if (!udc->clocked)
1616 		return;
1617 
1618 	if (!udc->enabled || !udc->vbus)
1619 		is_on = 0;
1620 
1621 	if (is_on != udc->pullup)
1622 		isp1301_pullup_enable(udc, is_on, 0);
1623 }
1624 
1625 /* Must be called without lock */
1626 static int lpc32xx_ep_disable(struct usb_ep *_ep)
1627 {
1628 	struct lpc32xx_ep *ep = container_of(_ep, struct lpc32xx_ep, ep);
1629 	struct lpc32xx_udc *udc = ep->udc;
1630 	unsigned long	flags;
1631 
1632 	if ((ep->hwep_num_base == 0) || (ep->hwep_num == 0))
1633 		return -EINVAL;
1634 	spin_lock_irqsave(&udc->lock, flags);
1635 
1636 	nuke(ep, -ESHUTDOWN);
1637 
1638 	/* Clear all DMA statuses for this EP */
1639 	udc_ep_dma_disable(udc, ep->hwep_num);
1640 	writel(1 << ep->hwep_num, USBD_EOTINTCLR(udc->udp_baseaddr));
1641 	writel(1 << ep->hwep_num, USBD_NDDRTINTCLR(udc->udp_baseaddr));
1642 	writel(1 << ep->hwep_num, USBD_SYSERRTINTCLR(udc->udp_baseaddr));
1643 	writel(1 << ep->hwep_num, USBD_DMARCLR(udc->udp_baseaddr));
1644 
1645 	/* Remove the DD pointer in the UDCA */
1646 	udc->udca_v_base[ep->hwep_num] = 0;
1647 
1648 	/* Disable and reset endpoint and interrupt */
1649 	uda_clear_hwepint(udc, ep->hwep_num);
1650 	udc_unrealize_hwep(udc, ep->hwep_num);
1651 
1652 	ep->hwep_num = 0;
1653 
1654 	spin_unlock_irqrestore(&udc->lock, flags);
1655 
1656 	atomic_dec(&udc->enabled_ep_cnt);
1657 	wake_up(&udc->ep_disable_wait_queue);
1658 
1659 	return 0;
1660 }
1661 
1662 /* Must be called without lock */
1663 static int lpc32xx_ep_enable(struct usb_ep *_ep,
1664 			     const struct usb_endpoint_descriptor *desc)
1665 {
1666 	struct lpc32xx_ep *ep = container_of(_ep, struct lpc32xx_ep, ep);
1667 	struct lpc32xx_udc *udc = ep->udc;
1668 	u16 maxpacket;
1669 	u32 tmp;
1670 	unsigned long flags;
1671 
1672 	/* Verify EP data */
1673 	if ((!_ep) || (!ep) || (!desc) ||
1674 	    (desc->bDescriptorType != USB_DT_ENDPOINT)) {
1675 		dev_dbg(udc->dev, "bad ep or descriptor\n");
1676 		return -EINVAL;
1677 	}
1678 	maxpacket = usb_endpoint_maxp(desc);
1679 	if ((maxpacket == 0) || (maxpacket > ep->maxpacket)) {
1680 		dev_dbg(udc->dev, "bad ep descriptor's packet size\n");
1681 		return -EINVAL;
1682 	}
1683 
1684 	/* Don't touch EP0 */
1685 	if (ep->hwep_num_base == 0) {
1686 		dev_dbg(udc->dev, "Can't re-enable EP0!!!\n");
1687 		return -EINVAL;
1688 	}
1689 
1690 	/* Is driver ready? */
1691 	if ((!udc->driver) || (udc->gadget.speed == USB_SPEED_UNKNOWN)) {
1692 		dev_dbg(udc->dev, "bogus device state\n");
1693 		return -ESHUTDOWN;
1694 	}
1695 
1696 	tmp = desc->bmAttributes & USB_ENDPOINT_XFERTYPE_MASK;
1697 	switch (tmp) {
1698 	case USB_ENDPOINT_XFER_CONTROL:
1699 		return -EINVAL;
1700 
1701 	case USB_ENDPOINT_XFER_INT:
1702 		if (maxpacket > ep->maxpacket) {
1703 			dev_dbg(udc->dev,
1704 				"Bad INT endpoint maxpacket %d\n", maxpacket);
1705 			return -EINVAL;
1706 		}
1707 		break;
1708 
1709 	case USB_ENDPOINT_XFER_BULK:
1710 		switch (maxpacket) {
1711 		case 8:
1712 		case 16:
1713 		case 32:
1714 		case 64:
1715 			break;
1716 
1717 		default:
1718 			dev_dbg(udc->dev,
1719 				"Bad BULK endpoint maxpacket %d\n", maxpacket);
1720 			return -EINVAL;
1721 		}
1722 		break;
1723 
1724 	case USB_ENDPOINT_XFER_ISOC:
1725 		break;
1726 	}
1727 	spin_lock_irqsave(&udc->lock, flags);
1728 
1729 	/* Initialize endpoint to match the selected descriptor */
1730 	ep->is_in = (desc->bEndpointAddress & USB_DIR_IN) != 0;
1731 	ep->ep.maxpacket = maxpacket;
1732 
1733 	/* Map hardware endpoint from base and direction */
1734 	if (ep->is_in)
1735 		/* IN endpoints are offset 1 from the OUT endpoint */
1736 		ep->hwep_num = ep->hwep_num_base + EP_IN;
1737 	else
1738 		ep->hwep_num = ep->hwep_num_base;
1739 
1740 	ep_dbg(ep, "EP enabled: %s, HW:%d, MP:%d IN:%d\n", ep->ep.name,
1741 	       ep->hwep_num, maxpacket, (ep->is_in == 1));
1742 
1743 	/* Realize the endpoint, interrupt is enabled later when
1744 	 * buffers are queued, IN EPs will NAK until buffers are ready */
1745 	udc_realize_hwep(udc, ep->hwep_num, ep->ep.maxpacket);
1746 	udc_clr_buffer_hwep(udc, ep->hwep_num);
1747 	uda_disable_hwepint(udc, ep->hwep_num);
1748 	udc_clrstall_hwep(udc, ep->hwep_num);
1749 
1750 	/* Clear all DMA statuses for this EP */
1751 	udc_ep_dma_disable(udc, ep->hwep_num);
1752 	writel(1 << ep->hwep_num, USBD_EOTINTCLR(udc->udp_baseaddr));
1753 	writel(1 << ep->hwep_num, USBD_NDDRTINTCLR(udc->udp_baseaddr));
1754 	writel(1 << ep->hwep_num, USBD_SYSERRTINTCLR(udc->udp_baseaddr));
1755 	writel(1 << ep->hwep_num, USBD_DMARCLR(udc->udp_baseaddr));
1756 
1757 	spin_unlock_irqrestore(&udc->lock, flags);
1758 
1759 	atomic_inc(&udc->enabled_ep_cnt);
1760 	return 0;
1761 }
1762 
1763 /*
1764  * Allocate a USB request list
1765  * Can be called with or without lock
1766  */
1767 static struct usb_request *lpc32xx_ep_alloc_request(struct usb_ep *_ep,
1768 						    gfp_t gfp_flags)
1769 {
1770 	struct lpc32xx_request *req;
1771 
1772 	req = kzalloc(sizeof(struct lpc32xx_request), gfp_flags);
1773 	if (!req)
1774 		return NULL;
1775 
1776 	INIT_LIST_HEAD(&req->queue);
1777 	return &req->req;
1778 }
1779 
1780 /*
1781  * De-allocate a USB request list
1782  * Can be called with or without lock
1783  */
1784 static void lpc32xx_ep_free_request(struct usb_ep *_ep,
1785 				    struct usb_request *_req)
1786 {
1787 	struct lpc32xx_request *req;
1788 
1789 	req = container_of(_req, struct lpc32xx_request, req);
1790 	BUG_ON(!list_empty(&req->queue));
1791 	kfree(req);
1792 }
1793 
1794 /* Must be called without lock */
1795 static int lpc32xx_ep_queue(struct usb_ep *_ep,
1796 			    struct usb_request *_req, gfp_t gfp_flags)
1797 {
1798 	struct lpc32xx_request *req;
1799 	struct lpc32xx_ep *ep;
1800 	struct lpc32xx_udc *udc;
1801 	unsigned long flags;
1802 	int status = 0;
1803 
1804 	req = container_of(_req, struct lpc32xx_request, req);
1805 	ep = container_of(_ep, struct lpc32xx_ep, ep);
1806 
1807 	if (!_req || !_req->complete || !_req->buf ||
1808 	    !list_empty(&req->queue))
1809 		return -EINVAL;
1810 
1811 	udc = ep->udc;
1812 
1813 	if (!_ep) {
1814 		dev_dbg(udc->dev, "invalid ep\n");
1815 		return -EINVAL;
1816 	}
1817 
1818 
1819 	if ((!udc) || (!udc->driver) ||
1820 	    (udc->gadget.speed == USB_SPEED_UNKNOWN)) {
1821 		dev_dbg(udc->dev, "invalid device\n");
1822 		return -EINVAL;
1823 	}
1824 
1825 	if (ep->lep) {
1826 		struct lpc32xx_usbd_dd_gad *dd;
1827 
1828 		status = usb_gadget_map_request(&udc->gadget, _req, ep->is_in);
1829 		if (status)
1830 			return status;
1831 
1832 		/* For the request, build a list of DDs */
1833 		dd = udc_dd_alloc(udc);
1834 		if (!dd) {
1835 			/* Error allocating DD */
1836 			return -ENOMEM;
1837 		}
1838 		req->dd_desc_ptr = dd;
1839 
1840 		/* Setup the DMA descriptor */
1841 		dd->dd_next_phy = dd->dd_next_v = 0;
1842 		dd->dd_buffer_addr = req->req.dma;
1843 		dd->dd_status = 0;
1844 
1845 		/* Special handling for ISO EPs */
1846 		if (ep->eptype == EP_ISO_TYPE) {
1847 			dd->dd_setup = DD_SETUP_ISO_EP |
1848 				DD_SETUP_PACKETLEN(0) |
1849 				DD_SETUP_DMALENBYTES(1);
1850 			dd->dd_iso_ps_mem_addr = dd->this_dma + 24;
1851 			if (ep->is_in)
1852 				dd->iso_status[0] = req->req.length;
1853 			else
1854 				dd->iso_status[0] = 0;
1855 		} else
1856 			dd->dd_setup = DD_SETUP_PACKETLEN(ep->ep.maxpacket) |
1857 				DD_SETUP_DMALENBYTES(req->req.length);
1858 	}
1859 
1860 	ep_dbg(ep, "%s queue req %p len %d buf %p (in=%d) z=%d\n", _ep->name,
1861 	       _req, _req->length, _req->buf, ep->is_in, _req->zero);
1862 
1863 	spin_lock_irqsave(&udc->lock, flags);
1864 
1865 	_req->status = -EINPROGRESS;
1866 	_req->actual = 0;
1867 	req->send_zlp = _req->zero;
1868 
1869 	/* Kickstart empty queues */
1870 	if (list_empty(&ep->queue)) {
1871 		list_add_tail(&req->queue, &ep->queue);
1872 
1873 		if (ep->hwep_num_base == 0) {
1874 			/* Handle expected data direction */
1875 			if (ep->is_in) {
1876 				/* IN packet to host */
1877 				udc->ep0state = DATA_IN;
1878 				status = udc_ep0_in_req(udc);
1879 			} else {
1880 				/* OUT packet from host */
1881 				udc->ep0state = DATA_OUT;
1882 				status = udc_ep0_out_req(udc);
1883 			}
1884 		} else if (ep->is_in) {
1885 			/* IN packet to host and kick off transfer */
1886 			if (!ep->req_pending)
1887 				udc_ep_in_req_dma(udc, ep);
1888 		} else
1889 			/* OUT packet from host and kick off list */
1890 			if (!ep->req_pending)
1891 				udc_ep_out_req_dma(udc, ep);
1892 	} else
1893 		list_add_tail(&req->queue, &ep->queue);
1894 
1895 	spin_unlock_irqrestore(&udc->lock, flags);
1896 
1897 	return (status < 0) ? status : 0;
1898 }
1899 
1900 /* Must be called without lock */
1901 static int lpc32xx_ep_dequeue(struct usb_ep *_ep, struct usb_request *_req)
1902 {
1903 	struct lpc32xx_ep *ep;
1904 	struct lpc32xx_request *req;
1905 	unsigned long flags;
1906 
1907 	ep = container_of(_ep, struct lpc32xx_ep, ep);
1908 	if (!_ep || ep->hwep_num_base == 0)
1909 		return -EINVAL;
1910 
1911 	spin_lock_irqsave(&ep->udc->lock, flags);
1912 
1913 	/* make sure it's actually queued on this endpoint */
1914 	list_for_each_entry(req, &ep->queue, queue) {
1915 		if (&req->req == _req)
1916 			break;
1917 	}
1918 	if (&req->req != _req) {
1919 		spin_unlock_irqrestore(&ep->udc->lock, flags);
1920 		return -EINVAL;
1921 	}
1922 
1923 	done(ep, req, -ECONNRESET);
1924 
1925 	spin_unlock_irqrestore(&ep->udc->lock, flags);
1926 
1927 	return 0;
1928 }
1929 
1930 /* Must be called without lock */
1931 static int lpc32xx_ep_set_halt(struct usb_ep *_ep, int value)
1932 {
1933 	struct lpc32xx_ep *ep = container_of(_ep, struct lpc32xx_ep, ep);
1934 	struct lpc32xx_udc *udc = ep->udc;
1935 	unsigned long flags;
1936 
1937 	if ((!ep) || (ep->hwep_num <= 1))
1938 		return -EINVAL;
1939 
1940 	/* Don't halt an IN EP */
1941 	if (ep->is_in)
1942 		return -EAGAIN;
1943 
1944 	spin_lock_irqsave(&udc->lock, flags);
1945 
1946 	if (value == 1) {
1947 		/* stall */
1948 		udc_protocol_cmd_data_w(udc, CMD_SET_EP_STAT(ep->hwep_num),
1949 					DAT_WR_BYTE(EP_STAT_ST));
1950 	} else {
1951 		/* End stall */
1952 		ep->wedge = 0;
1953 		udc_protocol_cmd_data_w(udc, CMD_SET_EP_STAT(ep->hwep_num),
1954 					DAT_WR_BYTE(0));
1955 	}
1956 
1957 	spin_unlock_irqrestore(&udc->lock, flags);
1958 
1959 	return 0;
1960 }
1961 
1962 /* set the halt feature and ignores clear requests */
1963 static int lpc32xx_ep_set_wedge(struct usb_ep *_ep)
1964 {
1965 	struct lpc32xx_ep *ep = container_of(_ep, struct lpc32xx_ep, ep);
1966 
1967 	if (!_ep || !ep->udc)
1968 		return -EINVAL;
1969 
1970 	ep->wedge = 1;
1971 
1972 	return usb_ep_set_halt(_ep);
1973 }
1974 
1975 static const struct usb_ep_ops lpc32xx_ep_ops = {
1976 	.enable		= lpc32xx_ep_enable,
1977 	.disable	= lpc32xx_ep_disable,
1978 	.alloc_request	= lpc32xx_ep_alloc_request,
1979 	.free_request	= lpc32xx_ep_free_request,
1980 	.queue		= lpc32xx_ep_queue,
1981 	.dequeue	= lpc32xx_ep_dequeue,
1982 	.set_halt	= lpc32xx_ep_set_halt,
1983 	.set_wedge	= lpc32xx_ep_set_wedge,
1984 };
1985 
1986 /* Send a ZLP on a non-0 IN EP */
1987 void udc_send_in_zlp(struct lpc32xx_udc *udc, struct lpc32xx_ep *ep)
1988 {
1989 	/* Clear EP status */
1990 	udc_clearep_getsts(udc, ep->hwep_num);
1991 
1992 	/* Send ZLP via FIFO mechanism */
1993 	udc_write_hwep(udc, ep->hwep_num, NULL, 0);
1994 }
1995 
1996 /*
1997  * Handle EP completion for ZLP
1998  * This function will only be called when a delayed ZLP needs to be sent out
1999  * after a DMA transfer has filled both buffers.
2000  */
2001 void udc_handle_eps(struct lpc32xx_udc *udc, struct lpc32xx_ep *ep)
2002 {
2003 	u32 epstatus;
2004 	struct lpc32xx_request *req;
2005 
2006 	if (ep->hwep_num <= 0)
2007 		return;
2008 
2009 	uda_clear_hwepint(udc, ep->hwep_num);
2010 
2011 	/* If this interrupt isn't enabled, return now */
2012 	if (!(udc->enabled_hwepints & (1 << ep->hwep_num)))
2013 		return;
2014 
2015 	/* Get endpoint status */
2016 	epstatus = udc_clearep_getsts(udc, ep->hwep_num);
2017 
2018 	/*
2019 	 * This should never happen, but protect against writing to the
2020 	 * buffer when full.
2021 	 */
2022 	if (epstatus & EP_SEL_F)
2023 		return;
2024 
2025 	if (ep->is_in) {
2026 		udc_send_in_zlp(udc, ep);
2027 		uda_disable_hwepint(udc, ep->hwep_num);
2028 	} else
2029 		return;
2030 
2031 	/* If there isn't a request waiting, something went wrong */
2032 	req = list_entry(ep->queue.next, struct lpc32xx_request, queue);
2033 	if (req) {
2034 		done(ep, req, 0);
2035 
2036 		/* Start another request if ready */
2037 		if (!list_empty(&ep->queue)) {
2038 			if (ep->is_in)
2039 				udc_ep_in_req_dma(udc, ep);
2040 			else
2041 				udc_ep_out_req_dma(udc, ep);
2042 		} else
2043 			ep->req_pending = 0;
2044 	}
2045 }
2046 
2047 
2048 /* DMA end of transfer completion */
2049 static void udc_handle_dma_ep(struct lpc32xx_udc *udc, struct lpc32xx_ep *ep)
2050 {
2051 	u32 status, epstatus;
2052 	struct lpc32xx_request *req;
2053 	struct lpc32xx_usbd_dd_gad *dd;
2054 
2055 #ifdef CONFIG_USB_GADGET_DEBUG_FILES
2056 	ep->totalints++;
2057 #endif
2058 
2059 	req = list_entry(ep->queue.next, struct lpc32xx_request, queue);
2060 	if (!req) {
2061 		ep_err(ep, "DMA interrupt on no req!\n");
2062 		return;
2063 	}
2064 	dd = req->dd_desc_ptr;
2065 
2066 	/* DMA descriptor should always be retired for this call */
2067 	if (!(dd->dd_status & DD_STATUS_DD_RETIRED))
2068 		ep_warn(ep, "DMA descriptor did not retire\n");
2069 
2070 	/* Disable DMA */
2071 	udc_ep_dma_disable(udc, ep->hwep_num);
2072 	writel((1 << ep->hwep_num), USBD_EOTINTCLR(udc->udp_baseaddr));
2073 	writel((1 << ep->hwep_num), USBD_NDDRTINTCLR(udc->udp_baseaddr));
2074 
2075 	/* System error? */
2076 	if (readl(USBD_SYSERRTINTST(udc->udp_baseaddr)) &
2077 	    (1 << ep->hwep_num)) {
2078 		writel((1 << ep->hwep_num),
2079 			     USBD_SYSERRTINTCLR(udc->udp_baseaddr));
2080 		ep_err(ep, "AHB critical error!\n");
2081 		ep->req_pending = 0;
2082 
2083 		/* The error could have occurred on a packet of a multipacket
2084 		 * transfer, so recovering the transfer is not possible. Close
2085 		 * the request with an error */
2086 		done(ep, req, -ECONNABORTED);
2087 		return;
2088 	}
2089 
2090 	/* Handle the current DD's status */
2091 	status = dd->dd_status;
2092 	switch (status & DD_STATUS_STS_MASK) {
2093 	case DD_STATUS_STS_NS:
2094 		/* DD not serviced? This shouldn't happen! */
2095 		ep->req_pending = 0;
2096 		ep_err(ep, "DMA critical EP error: DD not serviced (0x%x)!\n",
2097 		       status);
2098 
2099 		done(ep, req, -ECONNABORTED);
2100 		return;
2101 
2102 	case DD_STATUS_STS_BS:
2103 		/* Interrupt only fires on EOT - This shouldn't happen! */
2104 		ep->req_pending = 0;
2105 		ep_err(ep, "DMA critical EP error: EOT prior to service completion (0x%x)!\n",
2106 		       status);
2107 		done(ep, req, -ECONNABORTED);
2108 		return;
2109 
2110 	case DD_STATUS_STS_NC:
2111 	case DD_STATUS_STS_DUR:
2112 		/* Really just a short packet, not an underrun */
2113 		/* This is a good status and what we expect */
2114 		break;
2115 
2116 	default:
2117 		/* Data overrun, system error, or unknown */
2118 		ep->req_pending = 0;
2119 		ep_err(ep, "DMA critical EP error: System error (0x%x)!\n",
2120 		       status);
2121 		done(ep, req, -ECONNABORTED);
2122 		return;
2123 	}
2124 
2125 	/* ISO endpoints are handled differently */
2126 	if (ep->eptype == EP_ISO_TYPE) {
2127 		if (ep->is_in)
2128 			req->req.actual = req->req.length;
2129 		else
2130 			req->req.actual = dd->iso_status[0] & 0xFFFF;
2131 	} else
2132 		req->req.actual += DD_STATUS_CURDMACNT(status);
2133 
2134 	/* Send a ZLP if necessary. This will be done for non-int
2135 	 * packets which have a size that is a divisor of MAXP */
2136 	if (req->send_zlp) {
2137 		/*
2138 		 * If at least 1 buffer is available, send the ZLP now.
2139 		 * Otherwise, the ZLP send needs to be deferred until a
2140 		 * buffer is available.
2141 		 */
2142 		if (udc_clearep_getsts(udc, ep->hwep_num) & EP_SEL_F) {
2143 			udc_clearep_getsts(udc, ep->hwep_num);
2144 			uda_enable_hwepint(udc, ep->hwep_num);
2145 			epstatus = udc_clearep_getsts(udc, ep->hwep_num);
2146 
2147 			/* Let the EP interrupt handle the ZLP */
2148 			return;
2149 		} else
2150 			udc_send_in_zlp(udc, ep);
2151 	}
2152 
2153 	/* Transfer request is complete */
2154 	done(ep, req, 0);
2155 
2156 	/* Start another request if ready */
2157 	udc_clearep_getsts(udc, ep->hwep_num);
2158 	if (!list_empty((&ep->queue))) {
2159 		if (ep->is_in)
2160 			udc_ep_in_req_dma(udc, ep);
2161 		else
2162 			udc_ep_out_req_dma(udc, ep);
2163 	} else
2164 		ep->req_pending = 0;
2165 
2166 }
2167 
2168 /*
2169  *
2170  * Endpoint 0 functions
2171  *
2172  */
2173 static void udc_handle_dev(struct lpc32xx_udc *udc)
2174 {
2175 	u32 tmp;
2176 
2177 	udc_protocol_cmd_w(udc, CMD_GET_DEV_STAT);
2178 	tmp = udc_protocol_cmd_r(udc, DAT_GET_DEV_STAT);
2179 
2180 	if (tmp & DEV_RST)
2181 		uda_usb_reset(udc);
2182 	else if (tmp & DEV_CON_CH)
2183 		uda_power_event(udc, (tmp & DEV_CON));
2184 	else if (tmp & DEV_SUS_CH) {
2185 		if (tmp & DEV_SUS) {
2186 			if (udc->vbus == 0)
2187 				stop_activity(udc);
2188 			else if ((udc->gadget.speed != USB_SPEED_UNKNOWN) &&
2189 				 udc->driver) {
2190 				/* Power down transceiver */
2191 				udc->poweron = 0;
2192 				schedule_work(&udc->pullup_job);
2193 				uda_resm_susp_event(udc, 1);
2194 			}
2195 		} else if ((udc->gadget.speed != USB_SPEED_UNKNOWN) &&
2196 			   udc->driver && udc->vbus) {
2197 			uda_resm_susp_event(udc, 0);
2198 			/* Power up transceiver */
2199 			udc->poweron = 1;
2200 			schedule_work(&udc->pullup_job);
2201 		}
2202 	}
2203 }
2204 
2205 static int udc_get_status(struct lpc32xx_udc *udc, u16 reqtype, u16 wIndex)
2206 {
2207 	struct lpc32xx_ep *ep;
2208 	u32 ep0buff = 0, tmp;
2209 
2210 	switch (reqtype & USB_RECIP_MASK) {
2211 	case USB_RECIP_INTERFACE:
2212 		break; /* Not supported */
2213 
2214 	case USB_RECIP_DEVICE:
2215 		ep0buff = (udc->selfpowered << USB_DEVICE_SELF_POWERED);
2216 		if (udc->dev_status & (1 << USB_DEVICE_REMOTE_WAKEUP))
2217 			ep0buff |= (1 << USB_DEVICE_REMOTE_WAKEUP);
2218 		break;
2219 
2220 	case USB_RECIP_ENDPOINT:
2221 		tmp = wIndex & USB_ENDPOINT_NUMBER_MASK;
2222 		ep = &udc->ep[tmp];
2223 		if ((tmp == 0) || (tmp >= NUM_ENDPOINTS))
2224 			return -EOPNOTSUPP;
2225 
2226 		if (wIndex & USB_DIR_IN) {
2227 			if (!ep->is_in)
2228 				return -EOPNOTSUPP; /* Something's wrong */
2229 		} else if (ep->is_in)
2230 			return -EOPNOTSUPP; /* Not an IN endpoint */
2231 
2232 		/* Get status of the endpoint */
2233 		udc_protocol_cmd_w(udc, CMD_SEL_EP(ep->hwep_num));
2234 		tmp = udc_protocol_cmd_r(udc, DAT_SEL_EP(ep->hwep_num));
2235 
2236 		if (tmp & EP_SEL_ST)
2237 			ep0buff = (1 << USB_ENDPOINT_HALT);
2238 		else
2239 			ep0buff = 0;
2240 		break;
2241 
2242 	default:
2243 		break;
2244 	}
2245 
2246 	/* Return data */
2247 	udc_write_hwep(udc, EP_IN, &ep0buff, 2);
2248 
2249 	return 0;
2250 }
2251 
2252 static void udc_handle_ep0_setup(struct lpc32xx_udc *udc)
2253 {
2254 	struct lpc32xx_ep *ep, *ep0 = &udc->ep[0];
2255 	struct usb_ctrlrequest ctrlpkt;
2256 	int i, bytes;
2257 	u16 wIndex, wValue, wLength, reqtype, req, tmp;
2258 
2259 	/* Nuke previous transfers */
2260 	nuke(ep0, -EPROTO);
2261 
2262 	/* Get setup packet */
2263 	bytes = udc_read_hwep(udc, EP_OUT, (u32 *) &ctrlpkt, 8);
2264 	if (bytes != 8) {
2265 		ep_warn(ep0, "Incorrectly sized setup packet (s/b 8, is %d)!\n",
2266 			bytes);
2267 		return;
2268 	}
2269 
2270 	/* Native endianness */
2271 	wIndex = le16_to_cpu(ctrlpkt.wIndex);
2272 	wValue = le16_to_cpu(ctrlpkt.wValue);
2273 	wLength = le16_to_cpu(ctrlpkt.wLength);
2274 	reqtype = le16_to_cpu(ctrlpkt.bRequestType);
2275 
2276 	/* Set direction of EP0 */
2277 	if (likely(reqtype & USB_DIR_IN))
2278 		ep0->is_in = 1;
2279 	else
2280 		ep0->is_in = 0;
2281 
2282 	/* Handle SETUP packet */
2283 	req = le16_to_cpu(ctrlpkt.bRequest);
2284 	switch (req) {
2285 	case USB_REQ_CLEAR_FEATURE:
2286 	case USB_REQ_SET_FEATURE:
2287 		switch (reqtype) {
2288 		case (USB_TYPE_STANDARD | USB_RECIP_DEVICE):
2289 			if (wValue != USB_DEVICE_REMOTE_WAKEUP)
2290 				goto stall; /* Nothing else handled */
2291 
2292 			/* Tell board about event */
2293 			if (req == USB_REQ_CLEAR_FEATURE)
2294 				udc->dev_status &=
2295 					~(1 << USB_DEVICE_REMOTE_WAKEUP);
2296 			else
2297 				udc->dev_status |=
2298 					(1 << USB_DEVICE_REMOTE_WAKEUP);
2299 			uda_remwkp_cgh(udc);
2300 			goto zlp_send;
2301 
2302 		case (USB_TYPE_STANDARD | USB_RECIP_ENDPOINT):
2303 			tmp = wIndex & USB_ENDPOINT_NUMBER_MASK;
2304 			if ((wValue != USB_ENDPOINT_HALT) ||
2305 			    (tmp >= NUM_ENDPOINTS))
2306 				break;
2307 
2308 			/* Find hardware endpoint from logical endpoint */
2309 			ep = &udc->ep[tmp];
2310 			tmp = ep->hwep_num;
2311 			if (tmp == 0)
2312 				break;
2313 
2314 			if (req == USB_REQ_SET_FEATURE)
2315 				udc_stall_hwep(udc, tmp);
2316 			else if (!ep->wedge)
2317 				udc_clrstall_hwep(udc, tmp);
2318 
2319 			goto zlp_send;
2320 
2321 		default:
2322 			break;
2323 		}
2324 
2325 
2326 	case USB_REQ_SET_ADDRESS:
2327 		if (reqtype == (USB_TYPE_STANDARD | USB_RECIP_DEVICE)) {
2328 			udc_set_address(udc, wValue);
2329 			goto zlp_send;
2330 		}
2331 		break;
2332 
2333 	case USB_REQ_GET_STATUS:
2334 		udc_get_status(udc, reqtype, wIndex);
2335 		return;
2336 
2337 	default:
2338 		break; /* Let GadgetFS handle the descriptor instead */
2339 	}
2340 
2341 	if (likely(udc->driver)) {
2342 		/* device-2-host (IN) or no data setup command, process
2343 		 * immediately */
2344 		spin_unlock(&udc->lock);
2345 		i = udc->driver->setup(&udc->gadget, &ctrlpkt);
2346 
2347 		spin_lock(&udc->lock);
2348 		if (req == USB_REQ_SET_CONFIGURATION) {
2349 			/* Configuration is set after endpoints are realized */
2350 			if (wValue) {
2351 				/* Set configuration */
2352 				udc_set_device_configured(udc);
2353 
2354 				udc_protocol_cmd_data_w(udc, CMD_SET_MODE,
2355 							DAT_WR_BYTE(AP_CLK |
2356 							INAK_BI | INAK_II));
2357 			} else {
2358 				/* Clear configuration */
2359 				udc_set_device_unconfigured(udc);
2360 
2361 				/* Disable NAK interrupts */
2362 				udc_protocol_cmd_data_w(udc, CMD_SET_MODE,
2363 							DAT_WR_BYTE(AP_CLK));
2364 			}
2365 		}
2366 
2367 		if (i < 0) {
2368 			/* setup processing failed, force stall */
2369 			dev_dbg(udc->dev,
2370 				"req %02x.%02x protocol STALL; stat %d\n",
2371 				reqtype, req, i);
2372 			udc->ep0state = WAIT_FOR_SETUP;
2373 			goto stall;
2374 		}
2375 	}
2376 
2377 	if (!ep0->is_in)
2378 		udc_ep0_send_zlp(udc); /* ZLP IN packet on data phase */
2379 
2380 	return;
2381 
2382 stall:
2383 	udc_stall_hwep(udc, EP_IN);
2384 	return;
2385 
2386 zlp_send:
2387 	udc_ep0_send_zlp(udc);
2388 	return;
2389 }
2390 
2391 /* IN endpoint 0 transfer */
2392 static void udc_handle_ep0_in(struct lpc32xx_udc *udc)
2393 {
2394 	struct lpc32xx_ep *ep0 = &udc->ep[0];
2395 	u32 epstatus;
2396 
2397 	/* Clear EP interrupt */
2398 	epstatus = udc_clearep_getsts(udc, EP_IN);
2399 
2400 #ifdef CONFIG_USB_GADGET_DEBUG_FILES
2401 	ep0->totalints++;
2402 #endif
2403 
2404 	/* Stalled? Clear stall and reset buffers */
2405 	if (epstatus & EP_SEL_ST) {
2406 		udc_clrstall_hwep(udc, EP_IN);
2407 		nuke(ep0, -ECONNABORTED);
2408 		udc->ep0state = WAIT_FOR_SETUP;
2409 		return;
2410 	}
2411 
2412 	/* Is a buffer available? */
2413 	if (!(epstatus & EP_SEL_F)) {
2414 		/* Handle based on current state */
2415 		if (udc->ep0state == DATA_IN)
2416 			udc_ep0_in_req(udc);
2417 		else {
2418 			/* Unknown state for EP0 oe end of DATA IN phase */
2419 			nuke(ep0, -ECONNABORTED);
2420 			udc->ep0state = WAIT_FOR_SETUP;
2421 		}
2422 	}
2423 }
2424 
2425 /* OUT endpoint 0 transfer */
2426 static void udc_handle_ep0_out(struct lpc32xx_udc *udc)
2427 {
2428 	struct lpc32xx_ep *ep0 = &udc->ep[0];
2429 	u32 epstatus;
2430 
2431 	/* Clear EP interrupt */
2432 	epstatus = udc_clearep_getsts(udc, EP_OUT);
2433 
2434 
2435 #ifdef CONFIG_USB_GADGET_DEBUG_FILES
2436 	ep0->totalints++;
2437 #endif
2438 
2439 	/* Stalled? */
2440 	if (epstatus & EP_SEL_ST) {
2441 		udc_clrstall_hwep(udc, EP_OUT);
2442 		nuke(ep0, -ECONNABORTED);
2443 		udc->ep0state = WAIT_FOR_SETUP;
2444 		return;
2445 	}
2446 
2447 	/* A NAK may occur if a packet couldn't be received yet */
2448 	if (epstatus & EP_SEL_EPN)
2449 		return;
2450 	/* Setup packet incoming? */
2451 	if (epstatus & EP_SEL_STP) {
2452 		nuke(ep0, 0);
2453 		udc->ep0state = WAIT_FOR_SETUP;
2454 	}
2455 
2456 	/* Data available? */
2457 	if (epstatus & EP_SEL_F)
2458 		/* Handle based on current state */
2459 		switch (udc->ep0state) {
2460 		case WAIT_FOR_SETUP:
2461 			udc_handle_ep0_setup(udc);
2462 			break;
2463 
2464 		case DATA_OUT:
2465 			udc_ep0_out_req(udc);
2466 			break;
2467 
2468 		default:
2469 			/* Unknown state for EP0 */
2470 			nuke(ep0, -ECONNABORTED);
2471 			udc->ep0state = WAIT_FOR_SETUP;
2472 		}
2473 }
2474 
2475 /* Must be called without lock */
2476 static int lpc32xx_get_frame(struct usb_gadget *gadget)
2477 {
2478 	int frame;
2479 	unsigned long flags;
2480 	struct lpc32xx_udc *udc = to_udc(gadget);
2481 
2482 	if (!udc->clocked)
2483 		return -EINVAL;
2484 
2485 	spin_lock_irqsave(&udc->lock, flags);
2486 
2487 	frame = (int) udc_get_current_frame(udc);
2488 
2489 	spin_unlock_irqrestore(&udc->lock, flags);
2490 
2491 	return frame;
2492 }
2493 
2494 static int lpc32xx_wakeup(struct usb_gadget *gadget)
2495 {
2496 	return -ENOTSUPP;
2497 }
2498 
2499 static int lpc32xx_set_selfpowered(struct usb_gadget *gadget, int is_on)
2500 {
2501 	struct lpc32xx_udc *udc = to_udc(gadget);
2502 
2503 	/* Always self-powered */
2504 	udc->selfpowered = (is_on != 0);
2505 
2506 	return 0;
2507 }
2508 
2509 /*
2510  * vbus is here!  turn everything on that's ready
2511  * Must be called without lock
2512  */
2513 static int lpc32xx_vbus_session(struct usb_gadget *gadget, int is_active)
2514 {
2515 	unsigned long flags;
2516 	struct lpc32xx_udc *udc = to_udc(gadget);
2517 
2518 	spin_lock_irqsave(&udc->lock, flags);
2519 
2520 	/* Doesn't need lock */
2521 	if (udc->driver) {
2522 		udc_clk_set(udc, 1);
2523 		udc_enable(udc);
2524 		pullup(udc, is_active);
2525 	} else {
2526 		stop_activity(udc);
2527 		pullup(udc, 0);
2528 
2529 		spin_unlock_irqrestore(&udc->lock, flags);
2530 		/*
2531 		 *  Wait for all the endpoints to disable,
2532 		 *  before disabling clocks. Don't wait if
2533 		 *  endpoints are not enabled.
2534 		 */
2535 		if (atomic_read(&udc->enabled_ep_cnt))
2536 			wait_event_interruptible(udc->ep_disable_wait_queue,
2537 				 (atomic_read(&udc->enabled_ep_cnt) == 0));
2538 
2539 		spin_lock_irqsave(&udc->lock, flags);
2540 
2541 		udc_clk_set(udc, 0);
2542 	}
2543 
2544 	spin_unlock_irqrestore(&udc->lock, flags);
2545 
2546 	return 0;
2547 }
2548 
2549 /* Can be called with or without lock */
2550 static int lpc32xx_pullup(struct usb_gadget *gadget, int is_on)
2551 {
2552 	struct lpc32xx_udc *udc = to_udc(gadget);
2553 
2554 	/* Doesn't need lock */
2555 	pullup(udc, is_on);
2556 
2557 	return 0;
2558 }
2559 
2560 static int lpc32xx_start(struct usb_gadget *, struct usb_gadget_driver *);
2561 static int lpc32xx_stop(struct usb_gadget *);
2562 
2563 static const struct usb_gadget_ops lpc32xx_udc_ops = {
2564 	.get_frame		= lpc32xx_get_frame,
2565 	.wakeup			= lpc32xx_wakeup,
2566 	.set_selfpowered	= lpc32xx_set_selfpowered,
2567 	.vbus_session		= lpc32xx_vbus_session,
2568 	.pullup			= lpc32xx_pullup,
2569 	.udc_start		= lpc32xx_start,
2570 	.udc_stop		= lpc32xx_stop,
2571 };
2572 
2573 static void nop_release(struct device *dev)
2574 {
2575 	/* nothing to free */
2576 }
2577 
2578 static const struct lpc32xx_udc controller_template = {
2579 	.gadget = {
2580 		.ops	= &lpc32xx_udc_ops,
2581 		.name	= driver_name,
2582 		.dev	= {
2583 			.init_name = "gadget",
2584 			.release = nop_release,
2585 		}
2586 	},
2587 	.ep[0] = {
2588 		.ep = {
2589 			.name	= "ep0",
2590 			.ops	= &lpc32xx_ep_ops,
2591 		},
2592 		.maxpacket	= 64,
2593 		.hwep_num_base	= 0,
2594 		.hwep_num	= 0, /* Can be 0 or 1, has special handling */
2595 		.lep		= 0,
2596 		.eptype		= EP_CTL_TYPE,
2597 	},
2598 	.ep[1] = {
2599 		.ep = {
2600 			.name	= "ep1-int",
2601 			.ops	= &lpc32xx_ep_ops,
2602 		},
2603 		.maxpacket	= 64,
2604 		.hwep_num_base	= 2,
2605 		.hwep_num	= 0, /* 2 or 3, will be set later */
2606 		.lep		= 1,
2607 		.eptype		= EP_INT_TYPE,
2608 	},
2609 	.ep[2] = {
2610 		.ep = {
2611 			.name	= "ep2-bulk",
2612 			.ops	= &lpc32xx_ep_ops,
2613 		},
2614 		.maxpacket	= 64,
2615 		.hwep_num_base	= 4,
2616 		.hwep_num	= 0, /* 4 or 5, will be set later */
2617 		.lep		= 2,
2618 		.eptype		= EP_BLK_TYPE,
2619 	},
2620 	.ep[3] = {
2621 		.ep = {
2622 			.name	= "ep3-iso",
2623 			.ops	= &lpc32xx_ep_ops,
2624 		},
2625 		.maxpacket	= 1023,
2626 		.hwep_num_base	= 6,
2627 		.hwep_num	= 0, /* 6 or 7, will be set later */
2628 		.lep		= 3,
2629 		.eptype		= EP_ISO_TYPE,
2630 	},
2631 	.ep[4] = {
2632 		.ep = {
2633 			.name	= "ep4-int",
2634 			.ops	= &lpc32xx_ep_ops,
2635 		},
2636 		.maxpacket	= 64,
2637 		.hwep_num_base	= 8,
2638 		.hwep_num	= 0, /* 8 or 9, will be set later */
2639 		.lep		= 4,
2640 		.eptype		= EP_INT_TYPE,
2641 	},
2642 	.ep[5] = {
2643 		.ep = {
2644 			.name	= "ep5-bulk",
2645 			.ops	= &lpc32xx_ep_ops,
2646 		},
2647 		.maxpacket	= 64,
2648 		.hwep_num_base	= 10,
2649 		.hwep_num	= 0, /* 10 or 11, will be set later */
2650 		.lep		= 5,
2651 		.eptype		= EP_BLK_TYPE,
2652 	},
2653 	.ep[6] = {
2654 		.ep = {
2655 			.name	= "ep6-iso",
2656 			.ops	= &lpc32xx_ep_ops,
2657 		},
2658 		.maxpacket	= 1023,
2659 		.hwep_num_base	= 12,
2660 		.hwep_num	= 0, /* 12 or 13, will be set later */
2661 		.lep		= 6,
2662 		.eptype		= EP_ISO_TYPE,
2663 	},
2664 	.ep[7] = {
2665 		.ep = {
2666 			.name	= "ep7-int",
2667 			.ops	= &lpc32xx_ep_ops,
2668 		},
2669 		.maxpacket	= 64,
2670 		.hwep_num_base	= 14,
2671 		.hwep_num	= 0,
2672 		.lep		= 7,
2673 		.eptype		= EP_INT_TYPE,
2674 	},
2675 	.ep[8] = {
2676 		.ep = {
2677 			.name	= "ep8-bulk",
2678 			.ops	= &lpc32xx_ep_ops,
2679 		},
2680 		.maxpacket	= 64,
2681 		.hwep_num_base	= 16,
2682 		.hwep_num	= 0,
2683 		.lep		= 8,
2684 		.eptype		= EP_BLK_TYPE,
2685 	},
2686 	.ep[9] = {
2687 		.ep = {
2688 			.name	= "ep9-iso",
2689 			.ops	= &lpc32xx_ep_ops,
2690 		},
2691 		.maxpacket	= 1023,
2692 		.hwep_num_base	= 18,
2693 		.hwep_num	= 0,
2694 		.lep		= 9,
2695 		.eptype		= EP_ISO_TYPE,
2696 	},
2697 	.ep[10] = {
2698 		.ep = {
2699 			.name	= "ep10-int",
2700 			.ops	= &lpc32xx_ep_ops,
2701 		},
2702 		.maxpacket	= 64,
2703 		.hwep_num_base	= 20,
2704 		.hwep_num	= 0,
2705 		.lep		= 10,
2706 		.eptype		= EP_INT_TYPE,
2707 	},
2708 	.ep[11] = {
2709 		.ep = {
2710 			.name	= "ep11-bulk",
2711 			.ops	= &lpc32xx_ep_ops,
2712 		},
2713 		.maxpacket	= 64,
2714 		.hwep_num_base	= 22,
2715 		.hwep_num	= 0,
2716 		.lep		= 11,
2717 		.eptype		= EP_BLK_TYPE,
2718 	},
2719 	.ep[12] = {
2720 		.ep = {
2721 			.name	= "ep12-iso",
2722 			.ops	= &lpc32xx_ep_ops,
2723 		},
2724 		.maxpacket	= 1023,
2725 		.hwep_num_base	= 24,
2726 		.hwep_num	= 0,
2727 		.lep		= 12,
2728 		.eptype		= EP_ISO_TYPE,
2729 	},
2730 	.ep[13] = {
2731 		.ep = {
2732 			.name	= "ep13-int",
2733 			.ops	= &lpc32xx_ep_ops,
2734 		},
2735 		.maxpacket	= 64,
2736 		.hwep_num_base	= 26,
2737 		.hwep_num	= 0,
2738 		.lep		= 13,
2739 		.eptype		= EP_INT_TYPE,
2740 	},
2741 	.ep[14] = {
2742 		.ep = {
2743 			.name	= "ep14-bulk",
2744 			.ops	= &lpc32xx_ep_ops,
2745 		},
2746 		.maxpacket	= 64,
2747 		.hwep_num_base	= 28,
2748 		.hwep_num	= 0,
2749 		.lep		= 14,
2750 		.eptype		= EP_BLK_TYPE,
2751 	},
2752 	.ep[15] = {
2753 		.ep = {
2754 			.name	= "ep15-bulk",
2755 			.ops	= &lpc32xx_ep_ops,
2756 		},
2757 		.maxpacket	= 1023,
2758 		.hwep_num_base	= 30,
2759 		.hwep_num	= 0,
2760 		.lep		= 15,
2761 		.eptype		= EP_BLK_TYPE,
2762 	},
2763 };
2764 
2765 /* ISO and status interrupts */
2766 static irqreturn_t lpc32xx_usb_lp_irq(int irq, void *_udc)
2767 {
2768 	u32 tmp, devstat;
2769 	struct lpc32xx_udc *udc = _udc;
2770 
2771 	spin_lock(&udc->lock);
2772 
2773 	/* Read the device status register */
2774 	devstat = readl(USBD_DEVINTST(udc->udp_baseaddr));
2775 
2776 	devstat &= ~USBD_EP_FAST;
2777 	writel(devstat, USBD_DEVINTCLR(udc->udp_baseaddr));
2778 	devstat = devstat & udc->enabled_devints;
2779 
2780 	/* Device specific handling needed? */
2781 	if (devstat & USBD_DEV_STAT)
2782 		udc_handle_dev(udc);
2783 
2784 	/* Start of frame? (devstat & FRAME_INT):
2785 	 * The frame interrupt isn't really needed for ISO support,
2786 	 * as the driver will queue the necessary packets */
2787 
2788 	/* Error? */
2789 	if (devstat & ERR_INT) {
2790 		/* All types of errors, from cable removal during transfer to
2791 		 * misc protocol and bit errors. These are mostly for just info,
2792 		 * as the USB hardware will work around these. If these errors
2793 		 * happen alot, something is wrong. */
2794 		udc_protocol_cmd_w(udc, CMD_RD_ERR_STAT);
2795 		tmp = udc_protocol_cmd_r(udc, DAT_RD_ERR_STAT);
2796 		dev_dbg(udc->dev, "Device error (0x%x)!\n", tmp);
2797 	}
2798 
2799 	spin_unlock(&udc->lock);
2800 
2801 	return IRQ_HANDLED;
2802 }
2803 
2804 /* EP interrupts */
2805 static irqreturn_t lpc32xx_usb_hp_irq(int irq, void *_udc)
2806 {
2807 	u32 tmp;
2808 	struct lpc32xx_udc *udc = _udc;
2809 
2810 	spin_lock(&udc->lock);
2811 
2812 	/* Read the device status register */
2813 	writel(USBD_EP_FAST, USBD_DEVINTCLR(udc->udp_baseaddr));
2814 
2815 	/* Endpoints */
2816 	tmp = readl(USBD_EPINTST(udc->udp_baseaddr));
2817 
2818 	/* Special handling for EP0 */
2819 	if (tmp & (EP_MASK_SEL(0, EP_OUT) | EP_MASK_SEL(0, EP_IN))) {
2820 		/* Handle EP0 IN */
2821 		if (tmp & (EP_MASK_SEL(0, EP_IN)))
2822 			udc_handle_ep0_in(udc);
2823 
2824 		/* Handle EP0 OUT */
2825 		if (tmp & (EP_MASK_SEL(0, EP_OUT)))
2826 			udc_handle_ep0_out(udc);
2827 	}
2828 
2829 	/* All other EPs */
2830 	if (tmp & ~(EP_MASK_SEL(0, EP_OUT) | EP_MASK_SEL(0, EP_IN))) {
2831 		int i;
2832 
2833 		/* Handle other EP interrupts */
2834 		for (i = 1; i < NUM_ENDPOINTS; i++) {
2835 			if (tmp & (1 << udc->ep[i].hwep_num))
2836 				udc_handle_eps(udc, &udc->ep[i]);
2837 		}
2838 	}
2839 
2840 	spin_unlock(&udc->lock);
2841 
2842 	return IRQ_HANDLED;
2843 }
2844 
2845 static irqreturn_t lpc32xx_usb_devdma_irq(int irq, void *_udc)
2846 {
2847 	struct lpc32xx_udc *udc = _udc;
2848 
2849 	int i;
2850 	u32 tmp;
2851 
2852 	spin_lock(&udc->lock);
2853 
2854 	/* Handle EP DMA EOT interrupts */
2855 	tmp = readl(USBD_EOTINTST(udc->udp_baseaddr)) |
2856 		(readl(USBD_EPDMAST(udc->udp_baseaddr)) &
2857 		 readl(USBD_NDDRTINTST(udc->udp_baseaddr))) |
2858 		readl(USBD_SYSERRTINTST(udc->udp_baseaddr));
2859 	for (i = 1; i < NUM_ENDPOINTS; i++) {
2860 		if (tmp & (1 << udc->ep[i].hwep_num))
2861 			udc_handle_dma_ep(udc, &udc->ep[i]);
2862 	}
2863 
2864 	spin_unlock(&udc->lock);
2865 
2866 	return IRQ_HANDLED;
2867 }
2868 
2869 /*
2870  *
2871  * VBUS detection, pullup handler, and Gadget cable state notification
2872  *
2873  */
2874 static void vbus_work(struct work_struct *work)
2875 {
2876 	u8 value;
2877 	struct lpc32xx_udc *udc = container_of(work, struct lpc32xx_udc,
2878 					       vbus_job);
2879 
2880 	if (udc->enabled != 0) {
2881 		/* Discharge VBUS real quick */
2882 		i2c_smbus_write_byte_data(udc->isp1301_i2c_client,
2883 			ISP1301_I2C_OTG_CONTROL_1, OTG1_VBUS_DISCHRG);
2884 
2885 		/* Give VBUS some time (100mS) to discharge */
2886 		msleep(100);
2887 
2888 		/* Disable VBUS discharge resistor */
2889 		i2c_smbus_write_byte_data(udc->isp1301_i2c_client,
2890 			ISP1301_I2C_OTG_CONTROL_1 | ISP1301_I2C_REG_CLEAR_ADDR,
2891 			OTG1_VBUS_DISCHRG);
2892 
2893 		/* Clear interrupt */
2894 		i2c_smbus_write_byte_data(udc->isp1301_i2c_client,
2895 			ISP1301_I2C_INTERRUPT_LATCH |
2896 			ISP1301_I2C_REG_CLEAR_ADDR, ~0);
2897 
2898 		/* Get the VBUS status from the transceiver */
2899 		value = i2c_smbus_read_byte_data(udc->isp1301_i2c_client,
2900 						 ISP1301_I2C_INTERRUPT_SOURCE);
2901 
2902 		/* VBUS on or off? */
2903 		if (value & INT_SESS_VLD)
2904 			udc->vbus = 1;
2905 		else
2906 			udc->vbus = 0;
2907 
2908 		/* VBUS changed? */
2909 		if (udc->last_vbus != udc->vbus) {
2910 			udc->last_vbus = udc->vbus;
2911 			lpc32xx_vbus_session(&udc->gadget, udc->vbus);
2912 		}
2913 	}
2914 
2915 	/* Re-enable after completion */
2916 	enable_irq(udc->udp_irq[IRQ_USB_ATX]);
2917 }
2918 
2919 static irqreturn_t lpc32xx_usb_vbus_irq(int irq, void *_udc)
2920 {
2921 	struct lpc32xx_udc *udc = _udc;
2922 
2923 	/* Defer handling of VBUS IRQ to work queue */
2924 	disable_irq_nosync(udc->udp_irq[IRQ_USB_ATX]);
2925 	schedule_work(&udc->vbus_job);
2926 
2927 	return IRQ_HANDLED;
2928 }
2929 
2930 static int lpc32xx_start(struct usb_gadget *gadget,
2931 			 struct usb_gadget_driver *driver)
2932 {
2933 	struct lpc32xx_udc *udc = to_udc(gadget);
2934 	int i;
2935 
2936 	if (!driver || driver->max_speed < USB_SPEED_FULL || !driver->setup) {
2937 		dev_err(udc->dev, "bad parameter.\n");
2938 		return -EINVAL;
2939 	}
2940 
2941 	if (udc->driver) {
2942 		dev_err(udc->dev, "UDC already has a gadget driver\n");
2943 		return -EBUSY;
2944 	}
2945 
2946 	udc->driver = driver;
2947 	udc->gadget.dev.of_node = udc->dev->of_node;
2948 	udc->enabled = 1;
2949 	udc->selfpowered = 1;
2950 	udc->vbus = 0;
2951 
2952 	/* Force VBUS process once to check for cable insertion */
2953 	udc->last_vbus = udc->vbus = 0;
2954 	schedule_work(&udc->vbus_job);
2955 
2956 	/* Do not re-enable ATX IRQ (3) */
2957 	for (i = IRQ_USB_LP; i < IRQ_USB_ATX; i++)
2958 		enable_irq(udc->udp_irq[i]);
2959 
2960 	return 0;
2961 }
2962 
2963 static int lpc32xx_stop(struct usb_gadget *gadget)
2964 {
2965 	int i;
2966 	struct lpc32xx_udc *udc = to_udc(gadget);
2967 
2968 	for (i = IRQ_USB_LP; i <= IRQ_USB_ATX; i++)
2969 		disable_irq(udc->udp_irq[i]);
2970 
2971 	if (udc->clocked) {
2972 		spin_lock(&udc->lock);
2973 		stop_activity(udc);
2974 		spin_unlock(&udc->lock);
2975 
2976 		/*
2977 		 *  Wait for all the endpoints to disable,
2978 		 *  before disabling clocks. Don't wait if
2979 		 *  endpoints are not enabled.
2980 		 */
2981 		if (atomic_read(&udc->enabled_ep_cnt))
2982 			wait_event_interruptible(udc->ep_disable_wait_queue,
2983 				(atomic_read(&udc->enabled_ep_cnt) == 0));
2984 
2985 		spin_lock(&udc->lock);
2986 		udc_clk_set(udc, 0);
2987 		spin_unlock(&udc->lock);
2988 	}
2989 
2990 	udc->enabled = 0;
2991 	udc->driver = NULL;
2992 
2993 	return 0;
2994 }
2995 
2996 static void lpc32xx_udc_shutdown(struct platform_device *dev)
2997 {
2998 	/* Force disconnect on reboot */
2999 	struct lpc32xx_udc *udc = platform_get_drvdata(dev);
3000 
3001 	pullup(udc, 0);
3002 }
3003 
3004 /*
3005  * Callbacks to be overridden by options passed via OF (TODO)
3006  */
3007 
3008 static void lpc32xx_usbd_conn_chg(int conn)
3009 {
3010 	/* Do nothing, it might be nice to enable an LED
3011 	 * based on conn state being !0 */
3012 }
3013 
3014 static void lpc32xx_usbd_susp_chg(int susp)
3015 {
3016 	/* Device suspend if susp != 0 */
3017 }
3018 
3019 static void lpc32xx_rmwkup_chg(int remote_wakup_enable)
3020 {
3021 	/* Enable or disable USB remote wakeup */
3022 }
3023 
3024 struct lpc32xx_usbd_cfg lpc32xx_usbddata = {
3025 	.vbus_drv_pol = 0,
3026 	.conn_chgb = &lpc32xx_usbd_conn_chg,
3027 	.susp_chgb = &lpc32xx_usbd_susp_chg,
3028 	.rmwk_chgb = &lpc32xx_rmwkup_chg,
3029 };
3030 
3031 
3032 static u64 lpc32xx_usbd_dmamask = ~(u32) 0x7F;
3033 
3034 static int lpc32xx_udc_probe(struct platform_device *pdev)
3035 {
3036 	struct device *dev = &pdev->dev;
3037 	struct lpc32xx_udc *udc;
3038 	int retval, i;
3039 	struct resource *res;
3040 	dma_addr_t dma_handle;
3041 	struct device_node *isp1301_node;
3042 
3043 	udc = kmemdup(&controller_template, sizeof(*udc), GFP_KERNEL);
3044 	if (!udc)
3045 		return -ENOMEM;
3046 
3047 	for (i = 0; i <= 15; i++)
3048 		udc->ep[i].udc = udc;
3049 	udc->gadget.ep0 = &udc->ep[0].ep;
3050 
3051 	/* init software state */
3052 	udc->gadget.dev.parent = dev;
3053 	udc->pdev = pdev;
3054 	udc->dev = &pdev->dev;
3055 	udc->enabled = 0;
3056 
3057 	if (pdev->dev.of_node) {
3058 		isp1301_node = of_parse_phandle(pdev->dev.of_node,
3059 						"transceiver", 0);
3060 	} else {
3061 		isp1301_node = NULL;
3062 	}
3063 
3064 	udc->isp1301_i2c_client = isp1301_get_client(isp1301_node);
3065 	if (!udc->isp1301_i2c_client) {
3066 		retval = -EPROBE_DEFER;
3067 		goto phy_fail;
3068 	}
3069 
3070 	dev_info(udc->dev, "ISP1301 I2C device at address 0x%x\n",
3071 		 udc->isp1301_i2c_client->addr);
3072 
3073 	pdev->dev.dma_mask = &lpc32xx_usbd_dmamask;
3074 	retval = dma_set_coherent_mask(&pdev->dev, DMA_BIT_MASK(32));
3075 	if (retval)
3076 		goto resource_fail;
3077 
3078 	udc->board = &lpc32xx_usbddata;
3079 
3080 	/*
3081 	 * Resources are mapped as follows:
3082 	 *  IORESOURCE_MEM, base address and size of USB space
3083 	 *  IORESOURCE_IRQ, USB device low priority interrupt number
3084 	 *  IORESOURCE_IRQ, USB device high priority interrupt number
3085 	 *  IORESOURCE_IRQ, USB device interrupt number
3086 	 *  IORESOURCE_IRQ, USB transceiver interrupt number
3087 	 */
3088 	res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
3089 	if (!res) {
3090 		retval = -ENXIO;
3091 		goto resource_fail;
3092 	}
3093 
3094 	spin_lock_init(&udc->lock);
3095 
3096 	/* Get IRQs */
3097 	for (i = 0; i < 4; i++) {
3098 		udc->udp_irq[i] = platform_get_irq(pdev, i);
3099 		if (udc->udp_irq[i] < 0) {
3100 			dev_err(udc->dev,
3101 				"irq resource %d not available!\n", i);
3102 			retval = udc->udp_irq[i];
3103 			goto irq_fail;
3104 		}
3105 	}
3106 
3107 	udc->io_p_start = res->start;
3108 	udc->io_p_size = resource_size(res);
3109 	if (!request_mem_region(udc->io_p_start, udc->io_p_size, driver_name)) {
3110 		dev_err(udc->dev, "someone's using UDC memory\n");
3111 		retval = -EBUSY;
3112 		goto request_mem_region_fail;
3113 	}
3114 
3115 	udc->udp_baseaddr = ioremap(udc->io_p_start, udc->io_p_size);
3116 	if (!udc->udp_baseaddr) {
3117 		retval = -ENOMEM;
3118 		dev_err(udc->dev, "IO map failure\n");
3119 		goto io_map_fail;
3120 	}
3121 
3122 	/* Enable AHB slave USB clock, needed for further USB clock control */
3123 	writel(USB_SLAVE_HCLK_EN | (1 << 19), USB_CTRL);
3124 
3125 	/* Get required clocks */
3126 	udc->usb_pll_clk = clk_get(&pdev->dev, "ck_pll5");
3127 	if (IS_ERR(udc->usb_pll_clk)) {
3128 		dev_err(udc->dev, "failed to acquire USB PLL\n");
3129 		retval = PTR_ERR(udc->usb_pll_clk);
3130 		goto pll_get_fail;
3131 	}
3132 	udc->usb_slv_clk = clk_get(&pdev->dev, "ck_usbd");
3133 	if (IS_ERR(udc->usb_slv_clk)) {
3134 		dev_err(udc->dev, "failed to acquire USB device clock\n");
3135 		retval = PTR_ERR(udc->usb_slv_clk);
3136 		goto usb_clk_get_fail;
3137 	}
3138 	udc->usb_otg_clk = clk_get(&pdev->dev, "ck_usb_otg");
3139 	if (IS_ERR(udc->usb_otg_clk)) {
3140 		dev_err(udc->dev, "failed to acquire USB otg clock\n");
3141 		retval = PTR_ERR(udc->usb_otg_clk);
3142 		goto usb_otg_clk_get_fail;
3143 	}
3144 
3145 	/* Setup PLL clock to 48MHz */
3146 	retval = clk_enable(udc->usb_pll_clk);
3147 	if (retval < 0) {
3148 		dev_err(udc->dev, "failed to start USB PLL\n");
3149 		goto pll_enable_fail;
3150 	}
3151 
3152 	retval = clk_set_rate(udc->usb_pll_clk, 48000);
3153 	if (retval < 0) {
3154 		dev_err(udc->dev, "failed to set USB clock rate\n");
3155 		goto pll_set_fail;
3156 	}
3157 
3158 	writel(readl(USB_CTRL) | USB_DEV_NEED_CLK_EN, USB_CTRL);
3159 
3160 	/* Enable USB device clock */
3161 	retval = clk_enable(udc->usb_slv_clk);
3162 	if (retval < 0) {
3163 		dev_err(udc->dev, "failed to start USB device clock\n");
3164 		goto usb_clk_enable_fail;
3165 	}
3166 
3167 	/* Enable USB OTG clock */
3168 	retval = clk_enable(udc->usb_otg_clk);
3169 	if (retval < 0) {
3170 		dev_err(udc->dev, "failed to start USB otg clock\n");
3171 		goto usb_otg_clk_enable_fail;
3172 	}
3173 
3174 	/* Setup deferred workqueue data */
3175 	udc->poweron = udc->pullup = 0;
3176 	INIT_WORK(&udc->pullup_job, pullup_work);
3177 	INIT_WORK(&udc->vbus_job, vbus_work);
3178 #ifdef CONFIG_PM
3179 	INIT_WORK(&udc->power_job, power_work);
3180 #endif
3181 
3182 	/* All clocks are now on */
3183 	udc->clocked = 1;
3184 
3185 	isp1301_udc_configure(udc);
3186 	/* Allocate memory for the UDCA */
3187 	udc->udca_v_base = dma_alloc_coherent(&pdev->dev, UDCA_BUFF_SIZE,
3188 					      &dma_handle,
3189 					      (GFP_KERNEL | GFP_DMA));
3190 	if (!udc->udca_v_base) {
3191 		dev_err(udc->dev, "error getting UDCA region\n");
3192 		retval = -ENOMEM;
3193 		goto i2c_fail;
3194 	}
3195 	udc->udca_p_base = dma_handle;
3196 	dev_dbg(udc->dev, "DMA buffer(0x%x bytes), P:0x%08x, V:0x%p\n",
3197 		UDCA_BUFF_SIZE, udc->udca_p_base, udc->udca_v_base);
3198 
3199 	/* Setup the DD DMA memory pool */
3200 	udc->dd_cache = dma_pool_create("udc_dd", udc->dev,
3201 					sizeof(struct lpc32xx_usbd_dd_gad),
3202 					sizeof(u32), 0);
3203 	if (!udc->dd_cache) {
3204 		dev_err(udc->dev, "error getting DD DMA region\n");
3205 		retval = -ENOMEM;
3206 		goto dma_alloc_fail;
3207 	}
3208 
3209 	/* Clear USB peripheral and initialize gadget endpoints */
3210 	udc_disable(udc);
3211 	udc_reinit(udc);
3212 
3213 	/* Request IRQs - low and high priority USB device IRQs are routed to
3214 	 * the same handler, while the DMA interrupt is routed elsewhere */
3215 	retval = request_irq(udc->udp_irq[IRQ_USB_LP], lpc32xx_usb_lp_irq,
3216 			     0, "udc_lp", udc);
3217 	if (retval < 0) {
3218 		dev_err(udc->dev, "LP request irq %d failed\n",
3219 			udc->udp_irq[IRQ_USB_LP]);
3220 		goto irq_lp_fail;
3221 	}
3222 	retval = request_irq(udc->udp_irq[IRQ_USB_HP], lpc32xx_usb_hp_irq,
3223 			     0, "udc_hp", udc);
3224 	if (retval < 0) {
3225 		dev_err(udc->dev, "HP request irq %d failed\n",
3226 			udc->udp_irq[IRQ_USB_HP]);
3227 		goto irq_hp_fail;
3228 	}
3229 
3230 	retval = request_irq(udc->udp_irq[IRQ_USB_DEVDMA],
3231 			     lpc32xx_usb_devdma_irq, 0, "udc_dma", udc);
3232 	if (retval < 0) {
3233 		dev_err(udc->dev, "DEV request irq %d failed\n",
3234 			udc->udp_irq[IRQ_USB_DEVDMA]);
3235 		goto irq_dev_fail;
3236 	}
3237 
3238 	/* The transceiver interrupt is used for VBUS detection and will
3239 	   kick off the VBUS handler function */
3240 	retval = request_irq(udc->udp_irq[IRQ_USB_ATX], lpc32xx_usb_vbus_irq,
3241 			     0, "udc_otg", udc);
3242 	if (retval < 0) {
3243 		dev_err(udc->dev, "VBUS request irq %d failed\n",
3244 			udc->udp_irq[IRQ_USB_ATX]);
3245 		goto irq_xcvr_fail;
3246 	}
3247 
3248 	/* Initialize wait queue */
3249 	init_waitqueue_head(&udc->ep_disable_wait_queue);
3250 	atomic_set(&udc->enabled_ep_cnt, 0);
3251 
3252 	/* Keep all IRQs disabled until GadgetFS starts up */
3253 	for (i = IRQ_USB_LP; i <= IRQ_USB_ATX; i++)
3254 		disable_irq(udc->udp_irq[i]);
3255 
3256 	retval = usb_add_gadget_udc(dev, &udc->gadget);
3257 	if (retval < 0)
3258 		goto add_gadget_fail;
3259 
3260 	dev_set_drvdata(dev, udc);
3261 	device_init_wakeup(dev, 1);
3262 	create_debug_file(udc);
3263 
3264 	/* Disable clocks for now */
3265 	udc_clk_set(udc, 0);
3266 
3267 	dev_info(udc->dev, "%s version %s\n", driver_name, DRIVER_VERSION);
3268 	return 0;
3269 
3270 add_gadget_fail:
3271 	free_irq(udc->udp_irq[IRQ_USB_ATX], udc);
3272 irq_xcvr_fail:
3273 	free_irq(udc->udp_irq[IRQ_USB_DEVDMA], udc);
3274 irq_dev_fail:
3275 	free_irq(udc->udp_irq[IRQ_USB_HP], udc);
3276 irq_hp_fail:
3277 	free_irq(udc->udp_irq[IRQ_USB_LP], udc);
3278 irq_lp_fail:
3279 	dma_pool_destroy(udc->dd_cache);
3280 dma_alloc_fail:
3281 	dma_free_coherent(&pdev->dev, UDCA_BUFF_SIZE,
3282 			  udc->udca_v_base, udc->udca_p_base);
3283 i2c_fail:
3284 	clk_disable(udc->usb_otg_clk);
3285 usb_otg_clk_enable_fail:
3286 	clk_disable(udc->usb_slv_clk);
3287 usb_clk_enable_fail:
3288 pll_set_fail:
3289 	clk_disable(udc->usb_pll_clk);
3290 pll_enable_fail:
3291 	clk_put(udc->usb_otg_clk);
3292 usb_otg_clk_get_fail:
3293 	clk_put(udc->usb_slv_clk);
3294 usb_clk_get_fail:
3295 	clk_put(udc->usb_pll_clk);
3296 pll_get_fail:
3297 	iounmap(udc->udp_baseaddr);
3298 io_map_fail:
3299 	release_mem_region(udc->io_p_start, udc->io_p_size);
3300 	dev_err(udc->dev, "%s probe failed, %d\n", driver_name, retval);
3301 request_mem_region_fail:
3302 irq_fail:
3303 resource_fail:
3304 phy_fail:
3305 	kfree(udc);
3306 	return retval;
3307 }
3308 
3309 static int lpc32xx_udc_remove(struct platform_device *pdev)
3310 {
3311 	struct lpc32xx_udc *udc = platform_get_drvdata(pdev);
3312 
3313 	usb_del_gadget_udc(&udc->gadget);
3314 	if (udc->driver)
3315 		return -EBUSY;
3316 
3317 	udc_clk_set(udc, 1);
3318 	udc_disable(udc);
3319 	pullup(udc, 0);
3320 
3321 	free_irq(udc->udp_irq[IRQ_USB_ATX], udc);
3322 
3323 	device_init_wakeup(&pdev->dev, 0);
3324 	remove_debug_file(udc);
3325 
3326 	dma_pool_destroy(udc->dd_cache);
3327 	dma_free_coherent(&pdev->dev, UDCA_BUFF_SIZE,
3328 			  udc->udca_v_base, udc->udca_p_base);
3329 	free_irq(udc->udp_irq[IRQ_USB_DEVDMA], udc);
3330 	free_irq(udc->udp_irq[IRQ_USB_HP], udc);
3331 	free_irq(udc->udp_irq[IRQ_USB_LP], udc);
3332 
3333 	clk_disable(udc->usb_otg_clk);
3334 	clk_put(udc->usb_otg_clk);
3335 	clk_disable(udc->usb_slv_clk);
3336 	clk_put(udc->usb_slv_clk);
3337 	clk_disable(udc->usb_pll_clk);
3338 	clk_put(udc->usb_pll_clk);
3339 	iounmap(udc->udp_baseaddr);
3340 	release_mem_region(udc->io_p_start, udc->io_p_size);
3341 	kfree(udc);
3342 
3343 	return 0;
3344 }
3345 
3346 #ifdef CONFIG_PM
3347 static int lpc32xx_udc_suspend(struct platform_device *pdev, pm_message_t mesg)
3348 {
3349 	struct lpc32xx_udc *udc = platform_get_drvdata(pdev);
3350 
3351 	if (udc->clocked) {
3352 		/* Power down ISP */
3353 		udc->poweron = 0;
3354 		isp1301_set_powerstate(udc, 0);
3355 
3356 		/* Disable clocking */
3357 		udc_clk_set(udc, 0);
3358 
3359 		/* Keep clock flag on, so we know to re-enable clocks
3360 		   on resume */
3361 		udc->clocked = 1;
3362 
3363 		/* Kill global USB clock */
3364 		clk_disable(udc->usb_slv_clk);
3365 	}
3366 
3367 	return 0;
3368 }
3369 
3370 static int lpc32xx_udc_resume(struct platform_device *pdev)
3371 {
3372 	struct lpc32xx_udc *udc = platform_get_drvdata(pdev);
3373 
3374 	if (udc->clocked) {
3375 		/* Enable global USB clock */
3376 		clk_enable(udc->usb_slv_clk);
3377 
3378 		/* Enable clocking */
3379 		udc_clk_set(udc, 1);
3380 
3381 		/* ISP back to normal power mode */
3382 		udc->poweron = 1;
3383 		isp1301_set_powerstate(udc, 1);
3384 	}
3385 
3386 	return 0;
3387 }
3388 #else
3389 #define	lpc32xx_udc_suspend	NULL
3390 #define	lpc32xx_udc_resume	NULL
3391 #endif
3392 
3393 #ifdef CONFIG_OF
3394 static const struct of_device_id lpc32xx_udc_of_match[] = {
3395 	{ .compatible = "nxp,lpc3220-udc", },
3396 	{ },
3397 };
3398 MODULE_DEVICE_TABLE(of, lpc32xx_udc_of_match);
3399 #endif
3400 
3401 static struct platform_driver lpc32xx_udc_driver = {
3402 	.remove		= lpc32xx_udc_remove,
3403 	.shutdown	= lpc32xx_udc_shutdown,
3404 	.suspend	= lpc32xx_udc_suspend,
3405 	.resume		= lpc32xx_udc_resume,
3406 	.driver		= {
3407 		.name	= (char *) driver_name,
3408 		.of_match_table = of_match_ptr(lpc32xx_udc_of_match),
3409 	},
3410 };
3411 
3412 module_platform_driver_probe(lpc32xx_udc_driver, lpc32xx_udc_probe);
3413 
3414 MODULE_DESCRIPTION("LPC32XX udc driver");
3415 MODULE_AUTHOR("Kevin Wells <kevin.wells@nxp.com>");
3416 MODULE_AUTHOR("Roland Stigge <stigge@antcom.de>");
3417 MODULE_LICENSE("GPL");
3418 MODULE_ALIAS("platform:lpc32xx_udc");
3419