1 // SPDX-License-Identifier: GPL-2.0+ 2 /* 3 * USB Gadget driver for LPC32xx 4 * 5 * Authors: 6 * Kevin Wells <kevin.wells@nxp.com> 7 * Mike James 8 * Roland Stigge <stigge@antcom.de> 9 * 10 * Copyright (C) 2006 Philips Semiconductors 11 * Copyright (C) 2009 NXP Semiconductors 12 * Copyright (C) 2012 Roland Stigge 13 * 14 * Note: This driver is based on original work done by Mike James for 15 * the LPC3180. 16 */ 17 18 #include <linux/clk.h> 19 #include <linux/delay.h> 20 #include <linux/dma-mapping.h> 21 #include <linux/dmapool.h> 22 #include <linux/i2c.h> 23 #include <linux/interrupt.h> 24 #include <linux/module.h> 25 #include <linux/of.h> 26 #include <linux/platform_device.h> 27 #include <linux/proc_fs.h> 28 #include <linux/slab.h> 29 #include <linux/usb/ch9.h> 30 #include <linux/usb/gadget.h> 31 #include <linux/usb/isp1301.h> 32 33 #ifdef CONFIG_USB_GADGET_DEBUG_FILES 34 #include <linux/debugfs.h> 35 #include <linux/seq_file.h> 36 #endif 37 38 #include <mach/hardware.h> 39 40 /* 41 * USB device configuration structure 42 */ 43 typedef void (*usc_chg_event)(int); 44 struct lpc32xx_usbd_cfg { 45 int vbus_drv_pol; /* 0=active low drive for VBUS via ISP1301 */ 46 usc_chg_event conn_chgb; /* Connection change event (optional) */ 47 usc_chg_event susp_chgb; /* Suspend/resume event (optional) */ 48 usc_chg_event rmwk_chgb; /* Enable/disable remote wakeup */ 49 }; 50 51 /* 52 * controller driver data structures 53 */ 54 55 /* 16 endpoints (not to be confused with 32 hardware endpoints) */ 56 #define NUM_ENDPOINTS 16 57 58 /* 59 * IRQ indices make reading the code a little easier 60 */ 61 #define IRQ_USB_LP 0 62 #define IRQ_USB_HP 1 63 #define IRQ_USB_DEVDMA 2 64 #define IRQ_USB_ATX 3 65 66 #define EP_OUT 0 /* RX (from host) */ 67 #define EP_IN 1 /* TX (to host) */ 68 69 /* Returns the interrupt mask for the selected hardware endpoint */ 70 #define EP_MASK_SEL(ep, dir) (1 << (((ep) * 2) + dir)) 71 72 #define EP_INT_TYPE 0 73 #define EP_ISO_TYPE 1 74 #define EP_BLK_TYPE 2 75 #define EP_CTL_TYPE 3 76 77 /* EP0 states */ 78 #define WAIT_FOR_SETUP 0 /* Wait for setup packet */ 79 #define DATA_IN 1 /* Expect dev->host transfer */ 80 #define DATA_OUT 2 /* Expect host->dev transfer */ 81 82 /* DD (DMA Descriptor) structure, requires word alignment, this is already 83 * defined in the LPC32XX USB device header file, but this version is slightly 84 * modified to tag some work data with each DMA descriptor. */ 85 struct lpc32xx_usbd_dd_gad { 86 u32 dd_next_phy; 87 u32 dd_setup; 88 u32 dd_buffer_addr; 89 u32 dd_status; 90 u32 dd_iso_ps_mem_addr; 91 u32 this_dma; 92 u32 iso_status[6]; /* 5 spare */ 93 u32 dd_next_v; 94 }; 95 96 /* 97 * Logical endpoint structure 98 */ 99 struct lpc32xx_ep { 100 struct usb_ep ep; 101 struct list_head queue; 102 struct lpc32xx_udc *udc; 103 104 u32 hwep_num_base; /* Physical hardware EP */ 105 u32 hwep_num; /* Maps to hardware endpoint */ 106 u32 maxpacket; 107 u32 lep; 108 109 bool is_in; 110 bool req_pending; 111 u32 eptype; 112 113 u32 totalints; 114 115 bool wedge; 116 }; 117 118 enum atx_type { 119 ISP1301, 120 STOTG04, 121 }; 122 123 /* 124 * Common UDC structure 125 */ 126 struct lpc32xx_udc { 127 struct usb_gadget gadget; 128 struct usb_gadget_driver *driver; 129 struct platform_device *pdev; 130 struct device *dev; 131 struct dentry *pde; 132 spinlock_t lock; 133 struct i2c_client *isp1301_i2c_client; 134 135 /* Board and device specific */ 136 struct lpc32xx_usbd_cfg *board; 137 void __iomem *udp_baseaddr; 138 int udp_irq[4]; 139 struct clk *usb_slv_clk; 140 141 /* DMA support */ 142 u32 *udca_v_base; 143 u32 udca_p_base; 144 struct dma_pool *dd_cache; 145 146 /* Common EP and control data */ 147 u32 enabled_devints; 148 u32 enabled_hwepints; 149 u32 dev_status; 150 u32 realized_eps; 151 152 /* VBUS detection, pullup, and power flags */ 153 u8 vbus; 154 u8 last_vbus; 155 int pullup; 156 int poweron; 157 enum atx_type atx; 158 159 /* Work queues related to I2C support */ 160 struct work_struct pullup_job; 161 struct work_struct power_job; 162 163 /* USB device peripheral - various */ 164 struct lpc32xx_ep ep[NUM_ENDPOINTS]; 165 bool enabled; 166 bool clocked; 167 bool suspended; 168 int ep0state; 169 atomic_t enabled_ep_cnt; 170 wait_queue_head_t ep_disable_wait_queue; 171 }; 172 173 /* 174 * Endpoint request 175 */ 176 struct lpc32xx_request { 177 struct usb_request req; 178 struct list_head queue; 179 struct lpc32xx_usbd_dd_gad *dd_desc_ptr; 180 bool mapped; 181 bool send_zlp; 182 }; 183 184 static inline struct lpc32xx_udc *to_udc(struct usb_gadget *g) 185 { 186 return container_of(g, struct lpc32xx_udc, gadget); 187 } 188 189 #define ep_dbg(epp, fmt, arg...) \ 190 dev_dbg(epp->udc->dev, "%s: " fmt, __func__, ## arg) 191 #define ep_err(epp, fmt, arg...) \ 192 dev_err(epp->udc->dev, "%s: " fmt, __func__, ## arg) 193 #define ep_info(epp, fmt, arg...) \ 194 dev_info(epp->udc->dev, "%s: " fmt, __func__, ## arg) 195 #define ep_warn(epp, fmt, arg...) \ 196 dev_warn(epp->udc->dev, "%s:" fmt, __func__, ## arg) 197 198 #define UDCA_BUFF_SIZE (128) 199 200 /********************************************************************** 201 * USB device controller register offsets 202 **********************************************************************/ 203 204 #define USBD_DEVINTST(x) ((x) + 0x200) 205 #define USBD_DEVINTEN(x) ((x) + 0x204) 206 #define USBD_DEVINTCLR(x) ((x) + 0x208) 207 #define USBD_DEVINTSET(x) ((x) + 0x20C) 208 #define USBD_CMDCODE(x) ((x) + 0x210) 209 #define USBD_CMDDATA(x) ((x) + 0x214) 210 #define USBD_RXDATA(x) ((x) + 0x218) 211 #define USBD_TXDATA(x) ((x) + 0x21C) 212 #define USBD_RXPLEN(x) ((x) + 0x220) 213 #define USBD_TXPLEN(x) ((x) + 0x224) 214 #define USBD_CTRL(x) ((x) + 0x228) 215 #define USBD_DEVINTPRI(x) ((x) + 0x22C) 216 #define USBD_EPINTST(x) ((x) + 0x230) 217 #define USBD_EPINTEN(x) ((x) + 0x234) 218 #define USBD_EPINTCLR(x) ((x) + 0x238) 219 #define USBD_EPINTSET(x) ((x) + 0x23C) 220 #define USBD_EPINTPRI(x) ((x) + 0x240) 221 #define USBD_REEP(x) ((x) + 0x244) 222 #define USBD_EPIND(x) ((x) + 0x248) 223 #define USBD_EPMAXPSIZE(x) ((x) + 0x24C) 224 /* DMA support registers only below */ 225 /* Set, clear, or get enabled state of the DMA request status. If 226 * enabled, an IN or OUT token will start a DMA transfer for the EP */ 227 #define USBD_DMARST(x) ((x) + 0x250) 228 #define USBD_DMARCLR(x) ((x) + 0x254) 229 #define USBD_DMARSET(x) ((x) + 0x258) 230 /* DMA UDCA head pointer */ 231 #define USBD_UDCAH(x) ((x) + 0x280) 232 /* EP DMA status, enable, and disable. This is used to specifically 233 * enabled or disable DMA for a specific EP */ 234 #define USBD_EPDMAST(x) ((x) + 0x284) 235 #define USBD_EPDMAEN(x) ((x) + 0x288) 236 #define USBD_EPDMADIS(x) ((x) + 0x28C) 237 /* DMA master interrupts enable and pending interrupts */ 238 #define USBD_DMAINTST(x) ((x) + 0x290) 239 #define USBD_DMAINTEN(x) ((x) + 0x294) 240 /* DMA end of transfer interrupt enable, disable, status */ 241 #define USBD_EOTINTST(x) ((x) + 0x2A0) 242 #define USBD_EOTINTCLR(x) ((x) + 0x2A4) 243 #define USBD_EOTINTSET(x) ((x) + 0x2A8) 244 /* New DD request interrupt enable, disable, status */ 245 #define USBD_NDDRTINTST(x) ((x) + 0x2AC) 246 #define USBD_NDDRTINTCLR(x) ((x) + 0x2B0) 247 #define USBD_NDDRTINTSET(x) ((x) + 0x2B4) 248 /* DMA error interrupt enable, disable, status */ 249 #define USBD_SYSERRTINTST(x) ((x) + 0x2B8) 250 #define USBD_SYSERRTINTCLR(x) ((x) + 0x2BC) 251 #define USBD_SYSERRTINTSET(x) ((x) + 0x2C0) 252 253 /********************************************************************** 254 * USBD_DEVINTST/USBD_DEVINTEN/USBD_DEVINTCLR/USBD_DEVINTSET/ 255 * USBD_DEVINTPRI register definitions 256 **********************************************************************/ 257 #define USBD_ERR_INT (1 << 9) 258 #define USBD_EP_RLZED (1 << 8) 259 #define USBD_TXENDPKT (1 << 7) 260 #define USBD_RXENDPKT (1 << 6) 261 #define USBD_CDFULL (1 << 5) 262 #define USBD_CCEMPTY (1 << 4) 263 #define USBD_DEV_STAT (1 << 3) 264 #define USBD_EP_SLOW (1 << 2) 265 #define USBD_EP_FAST (1 << 1) 266 #define USBD_FRAME (1 << 0) 267 268 /********************************************************************** 269 * USBD_EPINTST/USBD_EPINTEN/USBD_EPINTCLR/USBD_EPINTSET/ 270 * USBD_EPINTPRI register definitions 271 **********************************************************************/ 272 /* End point selection macro (RX) */ 273 #define USBD_RX_EP_SEL(e) (1 << ((e) << 1)) 274 275 /* End point selection macro (TX) */ 276 #define USBD_TX_EP_SEL(e) (1 << (((e) << 1) + 1)) 277 278 /********************************************************************** 279 * USBD_REEP/USBD_DMARST/USBD_DMARCLR/USBD_DMARSET/USBD_EPDMAST/ 280 * USBD_EPDMAEN/USBD_EPDMADIS/ 281 * USBD_NDDRTINTST/USBD_NDDRTINTCLR/USBD_NDDRTINTSET/ 282 * USBD_EOTINTST/USBD_EOTINTCLR/USBD_EOTINTSET/ 283 * USBD_SYSERRTINTST/USBD_SYSERRTINTCLR/USBD_SYSERRTINTSET 284 * register definitions 285 **********************************************************************/ 286 /* Endpoint selection macro */ 287 #define USBD_EP_SEL(e) (1 << (e)) 288 289 /********************************************************************** 290 * SBD_DMAINTST/USBD_DMAINTEN 291 **********************************************************************/ 292 #define USBD_SYS_ERR_INT (1 << 2) 293 #define USBD_NEW_DD_INT (1 << 1) 294 #define USBD_EOT_INT (1 << 0) 295 296 /********************************************************************** 297 * USBD_RXPLEN register definitions 298 **********************************************************************/ 299 #define USBD_PKT_RDY (1 << 11) 300 #define USBD_DV (1 << 10) 301 #define USBD_PK_LEN_MASK 0x3FF 302 303 /********************************************************************** 304 * USBD_CTRL register definitions 305 **********************************************************************/ 306 #define USBD_LOG_ENDPOINT(e) ((e) << 2) 307 #define USBD_WR_EN (1 << 1) 308 #define USBD_RD_EN (1 << 0) 309 310 /********************************************************************** 311 * USBD_CMDCODE register definitions 312 **********************************************************************/ 313 #define USBD_CMD_CODE(c) ((c) << 16) 314 #define USBD_CMD_PHASE(p) ((p) << 8) 315 316 /********************************************************************** 317 * USBD_DMARST/USBD_DMARCLR/USBD_DMARSET register definitions 318 **********************************************************************/ 319 #define USBD_DMAEP(e) (1 << (e)) 320 321 /* DD (DMA Descriptor) structure, requires word alignment */ 322 struct lpc32xx_usbd_dd { 323 u32 *dd_next; 324 u32 dd_setup; 325 u32 dd_buffer_addr; 326 u32 dd_status; 327 u32 dd_iso_ps_mem_addr; 328 }; 329 330 /* dd_setup bit defines */ 331 #define DD_SETUP_ATLE_DMA_MODE 0x01 332 #define DD_SETUP_NEXT_DD_VALID 0x04 333 #define DD_SETUP_ISO_EP 0x10 334 #define DD_SETUP_PACKETLEN(n) (((n) & 0x7FF) << 5) 335 #define DD_SETUP_DMALENBYTES(n) (((n) & 0xFFFF) << 16) 336 337 /* dd_status bit defines */ 338 #define DD_STATUS_DD_RETIRED 0x01 339 #define DD_STATUS_STS_MASK 0x1E 340 #define DD_STATUS_STS_NS 0x00 /* Not serviced */ 341 #define DD_STATUS_STS_BS 0x02 /* Being serviced */ 342 #define DD_STATUS_STS_NC 0x04 /* Normal completion */ 343 #define DD_STATUS_STS_DUR 0x06 /* Data underrun (short packet) */ 344 #define DD_STATUS_STS_DOR 0x08 /* Data overrun */ 345 #define DD_STATUS_STS_SE 0x12 /* System error */ 346 #define DD_STATUS_PKT_VAL 0x20 /* Packet valid */ 347 #define DD_STATUS_LSB_EX 0x40 /* LS byte extracted (ATLE) */ 348 #define DD_STATUS_MSB_EX 0x80 /* MS byte extracted (ATLE) */ 349 #define DD_STATUS_MLEN(n) (((n) >> 8) & 0x3F) 350 #define DD_STATUS_CURDMACNT(n) (((n) >> 16) & 0xFFFF) 351 352 /* 353 * 354 * Protocol engine bits below 355 * 356 */ 357 /* Device Interrupt Bit Definitions */ 358 #define FRAME_INT 0x00000001 359 #define EP_FAST_INT 0x00000002 360 #define EP_SLOW_INT 0x00000004 361 #define DEV_STAT_INT 0x00000008 362 #define CCEMTY_INT 0x00000010 363 #define CDFULL_INT 0x00000020 364 #define RxENDPKT_INT 0x00000040 365 #define TxENDPKT_INT 0x00000080 366 #define EP_RLZED_INT 0x00000100 367 #define ERR_INT 0x00000200 368 369 /* Rx & Tx Packet Length Definitions */ 370 #define PKT_LNGTH_MASK 0x000003FF 371 #define PKT_DV 0x00000400 372 #define PKT_RDY 0x00000800 373 374 /* USB Control Definitions */ 375 #define CTRL_RD_EN 0x00000001 376 #define CTRL_WR_EN 0x00000002 377 378 /* Command Codes */ 379 #define CMD_SET_ADDR 0x00D00500 380 #define CMD_CFG_DEV 0x00D80500 381 #define CMD_SET_MODE 0x00F30500 382 #define CMD_RD_FRAME 0x00F50500 383 #define DAT_RD_FRAME 0x00F50200 384 #define CMD_RD_TEST 0x00FD0500 385 #define DAT_RD_TEST 0x00FD0200 386 #define CMD_SET_DEV_STAT 0x00FE0500 387 #define CMD_GET_DEV_STAT 0x00FE0500 388 #define DAT_GET_DEV_STAT 0x00FE0200 389 #define CMD_GET_ERR_CODE 0x00FF0500 390 #define DAT_GET_ERR_CODE 0x00FF0200 391 #define CMD_RD_ERR_STAT 0x00FB0500 392 #define DAT_RD_ERR_STAT 0x00FB0200 393 #define DAT_WR_BYTE(x) (0x00000100 | ((x) << 16)) 394 #define CMD_SEL_EP(x) (0x00000500 | ((x) << 16)) 395 #define DAT_SEL_EP(x) (0x00000200 | ((x) << 16)) 396 #define CMD_SEL_EP_CLRI(x) (0x00400500 | ((x) << 16)) 397 #define DAT_SEL_EP_CLRI(x) (0x00400200 | ((x) << 16)) 398 #define CMD_SET_EP_STAT(x) (0x00400500 | ((x) << 16)) 399 #define CMD_CLR_BUF 0x00F20500 400 #define DAT_CLR_BUF 0x00F20200 401 #define CMD_VALID_BUF 0x00FA0500 402 403 /* Device Address Register Definitions */ 404 #define DEV_ADDR_MASK 0x7F 405 #define DEV_EN 0x80 406 407 /* Device Configure Register Definitions */ 408 #define CONF_DVICE 0x01 409 410 /* Device Mode Register Definitions */ 411 #define AP_CLK 0x01 412 #define INAK_CI 0x02 413 #define INAK_CO 0x04 414 #define INAK_II 0x08 415 #define INAK_IO 0x10 416 #define INAK_BI 0x20 417 #define INAK_BO 0x40 418 419 /* Device Status Register Definitions */ 420 #define DEV_CON 0x01 421 #define DEV_CON_CH 0x02 422 #define DEV_SUS 0x04 423 #define DEV_SUS_CH 0x08 424 #define DEV_RST 0x10 425 426 /* Error Code Register Definitions */ 427 #define ERR_EC_MASK 0x0F 428 #define ERR_EA 0x10 429 430 /* Error Status Register Definitions */ 431 #define ERR_PID 0x01 432 #define ERR_UEPKT 0x02 433 #define ERR_DCRC 0x04 434 #define ERR_TIMOUT 0x08 435 #define ERR_EOP 0x10 436 #define ERR_B_OVRN 0x20 437 #define ERR_BTSTF 0x40 438 #define ERR_TGL 0x80 439 440 /* Endpoint Select Register Definitions */ 441 #define EP_SEL_F 0x01 442 #define EP_SEL_ST 0x02 443 #define EP_SEL_STP 0x04 444 #define EP_SEL_PO 0x08 445 #define EP_SEL_EPN 0x10 446 #define EP_SEL_B_1_FULL 0x20 447 #define EP_SEL_B_2_FULL 0x40 448 449 /* Endpoint Status Register Definitions */ 450 #define EP_STAT_ST 0x01 451 #define EP_STAT_DA 0x20 452 #define EP_STAT_RF_MO 0x40 453 #define EP_STAT_CND_ST 0x80 454 455 /* Clear Buffer Register Definitions */ 456 #define CLR_BUF_PO 0x01 457 458 /* DMA Interrupt Bit Definitions */ 459 #define EOT_INT 0x01 460 #define NDD_REQ_INT 0x02 461 #define SYS_ERR_INT 0x04 462 463 #define DRIVER_VERSION "1.03" 464 static const char driver_name[] = "lpc32xx_udc"; 465 466 /* 467 * 468 * proc interface support 469 * 470 */ 471 #ifdef CONFIG_USB_GADGET_DEBUG_FILES 472 static char *epnames[] = {"INT", "ISO", "BULK", "CTRL"}; 473 static const char debug_filename[] = "driver/udc"; 474 475 static void proc_ep_show(struct seq_file *s, struct lpc32xx_ep *ep) 476 { 477 struct lpc32xx_request *req; 478 479 seq_printf(s, "\n"); 480 seq_printf(s, "%12s, maxpacket %4d %3s", 481 ep->ep.name, ep->ep.maxpacket, 482 ep->is_in ? "in" : "out"); 483 seq_printf(s, " type %4s", epnames[ep->eptype]); 484 seq_printf(s, " ints: %12d", ep->totalints); 485 486 if (list_empty(&ep->queue)) 487 seq_printf(s, "\t(queue empty)\n"); 488 else { 489 list_for_each_entry(req, &ep->queue, queue) { 490 u32 length = req->req.actual; 491 492 seq_printf(s, "\treq %p len %d/%d buf %p\n", 493 &req->req, length, 494 req->req.length, req->req.buf); 495 } 496 } 497 } 498 499 static int proc_udc_show(struct seq_file *s, void *unused) 500 { 501 struct lpc32xx_udc *udc = s->private; 502 struct lpc32xx_ep *ep; 503 unsigned long flags; 504 505 seq_printf(s, "%s: version %s\n", driver_name, DRIVER_VERSION); 506 507 spin_lock_irqsave(&udc->lock, flags); 508 509 seq_printf(s, "vbus %s, pullup %s, %s powered%s, gadget %s\n\n", 510 udc->vbus ? "present" : "off", 511 udc->enabled ? (udc->vbus ? "active" : "enabled") : 512 "disabled", 513 udc->gadget.is_selfpowered ? "self" : "VBUS", 514 udc->suspended ? ", suspended" : "", 515 udc->driver ? udc->driver->driver.name : "(none)"); 516 517 if (udc->enabled && udc->vbus) { 518 proc_ep_show(s, &udc->ep[0]); 519 list_for_each_entry(ep, &udc->gadget.ep_list, ep.ep_list) 520 proc_ep_show(s, ep); 521 } 522 523 spin_unlock_irqrestore(&udc->lock, flags); 524 525 return 0; 526 } 527 528 static int proc_udc_open(struct inode *inode, struct file *file) 529 { 530 return single_open(file, proc_udc_show, PDE_DATA(inode)); 531 } 532 533 static const struct file_operations proc_ops = { 534 .owner = THIS_MODULE, 535 .open = proc_udc_open, 536 .read = seq_read, 537 .llseek = seq_lseek, 538 .release = single_release, 539 }; 540 541 static void create_debug_file(struct lpc32xx_udc *udc) 542 { 543 udc->pde = debugfs_create_file(debug_filename, 0, NULL, udc, &proc_ops); 544 } 545 546 static void remove_debug_file(struct lpc32xx_udc *udc) 547 { 548 debugfs_remove(udc->pde); 549 } 550 551 #else 552 static inline void create_debug_file(struct lpc32xx_udc *udc) {} 553 static inline void remove_debug_file(struct lpc32xx_udc *udc) {} 554 #endif 555 556 /* Primary initialization sequence for the ISP1301 transceiver */ 557 static void isp1301_udc_configure(struct lpc32xx_udc *udc) 558 { 559 u8 value; 560 s32 vendor, product; 561 562 vendor = i2c_smbus_read_word_data(udc->isp1301_i2c_client, 0x00); 563 product = i2c_smbus_read_word_data(udc->isp1301_i2c_client, 0x02); 564 565 if (vendor == 0x0483 && product == 0xa0c4) 566 udc->atx = STOTG04; 567 568 /* LPC32XX only supports DAT_SE0 USB mode */ 569 /* This sequence is important */ 570 571 /* Disable transparent UART mode first */ 572 i2c_smbus_write_byte_data(udc->isp1301_i2c_client, 573 (ISP1301_I2C_MODE_CONTROL_1 | ISP1301_I2C_REG_CLEAR_ADDR), 574 MC1_UART_EN); 575 576 /* Set full speed and SE0 mode */ 577 i2c_smbus_write_byte_data(udc->isp1301_i2c_client, 578 (ISP1301_I2C_MODE_CONTROL_1 | ISP1301_I2C_REG_CLEAR_ADDR), ~0); 579 i2c_smbus_write_byte_data(udc->isp1301_i2c_client, 580 ISP1301_I2C_MODE_CONTROL_1, (MC1_SPEED_REG | MC1_DAT_SE0)); 581 582 /* 583 * The PSW_OE enable bit state is reversed in the ISP1301 User's Guide 584 */ 585 i2c_smbus_write_byte_data(udc->isp1301_i2c_client, 586 (ISP1301_I2C_MODE_CONTROL_2 | ISP1301_I2C_REG_CLEAR_ADDR), ~0); 587 588 value = MC2_BI_DI; 589 if (udc->atx != STOTG04) 590 value |= MC2_SPD_SUSP_CTRL; 591 i2c_smbus_write_byte_data(udc->isp1301_i2c_client, 592 ISP1301_I2C_MODE_CONTROL_2, value); 593 594 /* Driver VBUS_DRV high or low depending on board setup */ 595 if (udc->board->vbus_drv_pol != 0) 596 i2c_smbus_write_byte_data(udc->isp1301_i2c_client, 597 ISP1301_I2C_OTG_CONTROL_1, OTG1_VBUS_DRV); 598 else 599 i2c_smbus_write_byte_data(udc->isp1301_i2c_client, 600 ISP1301_I2C_OTG_CONTROL_1 | ISP1301_I2C_REG_CLEAR_ADDR, 601 OTG1_VBUS_DRV); 602 603 /* Bi-directional mode with suspend control 604 * Enable both pulldowns for now - the pullup will be enable when VBUS 605 * is detected */ 606 i2c_smbus_write_byte_data(udc->isp1301_i2c_client, 607 (ISP1301_I2C_OTG_CONTROL_1 | ISP1301_I2C_REG_CLEAR_ADDR), ~0); 608 i2c_smbus_write_byte_data(udc->isp1301_i2c_client, 609 ISP1301_I2C_OTG_CONTROL_1, 610 (0 | OTG1_DM_PULLDOWN | OTG1_DP_PULLDOWN)); 611 612 /* Discharge VBUS (just in case) */ 613 i2c_smbus_write_byte_data(udc->isp1301_i2c_client, 614 ISP1301_I2C_OTG_CONTROL_1, OTG1_VBUS_DISCHRG); 615 msleep(1); 616 i2c_smbus_write_byte_data(udc->isp1301_i2c_client, 617 (ISP1301_I2C_OTG_CONTROL_1 | ISP1301_I2C_REG_CLEAR_ADDR), 618 OTG1_VBUS_DISCHRG); 619 620 i2c_smbus_write_byte_data(udc->isp1301_i2c_client, 621 ISP1301_I2C_INTERRUPT_LATCH | ISP1301_I2C_REG_CLEAR_ADDR, ~0); 622 623 i2c_smbus_write_byte_data(udc->isp1301_i2c_client, 624 ISP1301_I2C_INTERRUPT_FALLING | ISP1301_I2C_REG_CLEAR_ADDR, ~0); 625 i2c_smbus_write_byte_data(udc->isp1301_i2c_client, 626 ISP1301_I2C_INTERRUPT_RISING | ISP1301_I2C_REG_CLEAR_ADDR, ~0); 627 628 dev_info(udc->dev, "ISP1301 Vendor ID : 0x%04x\n", vendor); 629 dev_info(udc->dev, "ISP1301 Product ID : 0x%04x\n", product); 630 dev_info(udc->dev, "ISP1301 Version ID : 0x%04x\n", 631 i2c_smbus_read_word_data(udc->isp1301_i2c_client, 0x14)); 632 633 } 634 635 /* Enables or disables the USB device pullup via the ISP1301 transceiver */ 636 static void isp1301_pullup_set(struct lpc32xx_udc *udc) 637 { 638 if (udc->pullup) 639 /* Enable pullup for bus signalling */ 640 i2c_smbus_write_byte_data(udc->isp1301_i2c_client, 641 ISP1301_I2C_OTG_CONTROL_1, OTG1_DP_PULLUP); 642 else 643 /* Enable pullup for bus signalling */ 644 i2c_smbus_write_byte_data(udc->isp1301_i2c_client, 645 ISP1301_I2C_OTG_CONTROL_1 | ISP1301_I2C_REG_CLEAR_ADDR, 646 OTG1_DP_PULLUP); 647 } 648 649 static void pullup_work(struct work_struct *work) 650 { 651 struct lpc32xx_udc *udc = 652 container_of(work, struct lpc32xx_udc, pullup_job); 653 654 isp1301_pullup_set(udc); 655 } 656 657 static void isp1301_pullup_enable(struct lpc32xx_udc *udc, int en_pullup, 658 int block) 659 { 660 if (en_pullup == udc->pullup) 661 return; 662 663 udc->pullup = en_pullup; 664 if (block) 665 isp1301_pullup_set(udc); 666 else 667 /* defer slow i2c pull up setting */ 668 schedule_work(&udc->pullup_job); 669 } 670 671 #ifdef CONFIG_PM 672 /* Powers up or down the ISP1301 transceiver */ 673 static void isp1301_set_powerstate(struct lpc32xx_udc *udc, int enable) 674 { 675 /* There is no "global power down" register for stotg04 */ 676 if (udc->atx == STOTG04) 677 return; 678 679 if (enable != 0) 680 /* Power up ISP1301 - this ISP1301 will automatically wakeup 681 when VBUS is detected */ 682 i2c_smbus_write_byte_data(udc->isp1301_i2c_client, 683 ISP1301_I2C_MODE_CONTROL_2 | ISP1301_I2C_REG_CLEAR_ADDR, 684 MC2_GLOBAL_PWR_DN); 685 else 686 /* Power down ISP1301 */ 687 i2c_smbus_write_byte_data(udc->isp1301_i2c_client, 688 ISP1301_I2C_MODE_CONTROL_2, MC2_GLOBAL_PWR_DN); 689 } 690 691 static void power_work(struct work_struct *work) 692 { 693 struct lpc32xx_udc *udc = 694 container_of(work, struct lpc32xx_udc, power_job); 695 696 isp1301_set_powerstate(udc, udc->poweron); 697 } 698 #endif 699 700 /* 701 * 702 * USB protocol engine command/data read/write helper functions 703 * 704 */ 705 /* Issues a single command to the USB device state machine */ 706 static void udc_protocol_cmd_w(struct lpc32xx_udc *udc, u32 cmd) 707 { 708 u32 pass = 0; 709 int to; 710 711 /* EP may lock on CLRI if this read isn't done */ 712 u32 tmp = readl(USBD_DEVINTST(udc->udp_baseaddr)); 713 (void) tmp; 714 715 while (pass == 0) { 716 writel(USBD_CCEMPTY, USBD_DEVINTCLR(udc->udp_baseaddr)); 717 718 /* Write command code */ 719 writel(cmd, USBD_CMDCODE(udc->udp_baseaddr)); 720 to = 10000; 721 while (((readl(USBD_DEVINTST(udc->udp_baseaddr)) & 722 USBD_CCEMPTY) == 0) && (to > 0)) { 723 to--; 724 } 725 726 if (to > 0) 727 pass = 1; 728 729 cpu_relax(); 730 } 731 } 732 733 /* Issues 2 commands (or command and data) to the USB device state machine */ 734 static inline void udc_protocol_cmd_data_w(struct lpc32xx_udc *udc, u32 cmd, 735 u32 data) 736 { 737 udc_protocol_cmd_w(udc, cmd); 738 udc_protocol_cmd_w(udc, data); 739 } 740 741 /* Issues a single command to the USB device state machine and reads 742 * response data */ 743 static u32 udc_protocol_cmd_r(struct lpc32xx_udc *udc, u32 cmd) 744 { 745 u32 tmp; 746 int to = 1000; 747 748 /* Write a command and read data from the protocol engine */ 749 writel((USBD_CDFULL | USBD_CCEMPTY), 750 USBD_DEVINTCLR(udc->udp_baseaddr)); 751 752 /* Write command code */ 753 udc_protocol_cmd_w(udc, cmd); 754 755 tmp = readl(USBD_DEVINTST(udc->udp_baseaddr)); 756 while ((!(readl(USBD_DEVINTST(udc->udp_baseaddr)) & USBD_CDFULL)) 757 && (to > 0)) 758 to--; 759 if (!to) 760 dev_dbg(udc->dev, 761 "Protocol engine didn't receive response (CDFULL)\n"); 762 763 return readl(USBD_CMDDATA(udc->udp_baseaddr)); 764 } 765 766 /* 767 * 768 * USB device interrupt mask support functions 769 * 770 */ 771 /* Enable one or more USB device interrupts */ 772 static inline void uda_enable_devint(struct lpc32xx_udc *udc, u32 devmask) 773 { 774 udc->enabled_devints |= devmask; 775 writel(udc->enabled_devints, USBD_DEVINTEN(udc->udp_baseaddr)); 776 } 777 778 /* Disable one or more USB device interrupts */ 779 static inline void uda_disable_devint(struct lpc32xx_udc *udc, u32 mask) 780 { 781 udc->enabled_devints &= ~mask; 782 writel(udc->enabled_devints, USBD_DEVINTEN(udc->udp_baseaddr)); 783 } 784 785 /* Clear one or more USB device interrupts */ 786 static inline void uda_clear_devint(struct lpc32xx_udc *udc, u32 mask) 787 { 788 writel(mask, USBD_DEVINTCLR(udc->udp_baseaddr)); 789 } 790 791 /* 792 * 793 * Endpoint interrupt disable/enable functions 794 * 795 */ 796 /* Enable one or more USB endpoint interrupts */ 797 static void uda_enable_hwepint(struct lpc32xx_udc *udc, u32 hwep) 798 { 799 udc->enabled_hwepints |= (1 << hwep); 800 writel(udc->enabled_hwepints, USBD_EPINTEN(udc->udp_baseaddr)); 801 } 802 803 /* Disable one or more USB endpoint interrupts */ 804 static void uda_disable_hwepint(struct lpc32xx_udc *udc, u32 hwep) 805 { 806 udc->enabled_hwepints &= ~(1 << hwep); 807 writel(udc->enabled_hwepints, USBD_EPINTEN(udc->udp_baseaddr)); 808 } 809 810 /* Clear one or more USB endpoint interrupts */ 811 static inline void uda_clear_hwepint(struct lpc32xx_udc *udc, u32 hwep) 812 { 813 writel((1 << hwep), USBD_EPINTCLR(udc->udp_baseaddr)); 814 } 815 816 /* Enable DMA for the HW channel */ 817 static inline void udc_ep_dma_enable(struct lpc32xx_udc *udc, u32 hwep) 818 { 819 writel((1 << hwep), USBD_EPDMAEN(udc->udp_baseaddr)); 820 } 821 822 /* Disable DMA for the HW channel */ 823 static inline void udc_ep_dma_disable(struct lpc32xx_udc *udc, u32 hwep) 824 { 825 writel((1 << hwep), USBD_EPDMADIS(udc->udp_baseaddr)); 826 } 827 828 /* 829 * 830 * Endpoint realize/unrealize functions 831 * 832 */ 833 /* Before an endpoint can be used, it needs to be realized 834 * in the USB protocol engine - this realizes the endpoint. 835 * The interrupt (FIFO or DMA) is not enabled with this function */ 836 static void udc_realize_hwep(struct lpc32xx_udc *udc, u32 hwep, 837 u32 maxpacket) 838 { 839 int to = 1000; 840 841 writel(USBD_EP_RLZED, USBD_DEVINTCLR(udc->udp_baseaddr)); 842 writel(hwep, USBD_EPIND(udc->udp_baseaddr)); 843 udc->realized_eps |= (1 << hwep); 844 writel(udc->realized_eps, USBD_REEP(udc->udp_baseaddr)); 845 writel(maxpacket, USBD_EPMAXPSIZE(udc->udp_baseaddr)); 846 847 /* Wait until endpoint is realized in hardware */ 848 while ((!(readl(USBD_DEVINTST(udc->udp_baseaddr)) & 849 USBD_EP_RLZED)) && (to > 0)) 850 to--; 851 if (!to) 852 dev_dbg(udc->dev, "EP not correctly realized in hardware\n"); 853 854 writel(USBD_EP_RLZED, USBD_DEVINTCLR(udc->udp_baseaddr)); 855 } 856 857 /* Unrealize an EP */ 858 static void udc_unrealize_hwep(struct lpc32xx_udc *udc, u32 hwep) 859 { 860 udc->realized_eps &= ~(1 << hwep); 861 writel(udc->realized_eps, USBD_REEP(udc->udp_baseaddr)); 862 } 863 864 /* 865 * 866 * Endpoint support functions 867 * 868 */ 869 /* Select and clear endpoint interrupt */ 870 static u32 udc_selep_clrint(struct lpc32xx_udc *udc, u32 hwep) 871 { 872 udc_protocol_cmd_w(udc, CMD_SEL_EP_CLRI(hwep)); 873 return udc_protocol_cmd_r(udc, DAT_SEL_EP_CLRI(hwep)); 874 } 875 876 /* Disables the endpoint in the USB protocol engine */ 877 static void udc_disable_hwep(struct lpc32xx_udc *udc, u32 hwep) 878 { 879 udc_protocol_cmd_data_w(udc, CMD_SET_EP_STAT(hwep), 880 DAT_WR_BYTE(EP_STAT_DA)); 881 } 882 883 /* Stalls the endpoint - endpoint will return STALL */ 884 static void udc_stall_hwep(struct lpc32xx_udc *udc, u32 hwep) 885 { 886 udc_protocol_cmd_data_w(udc, CMD_SET_EP_STAT(hwep), 887 DAT_WR_BYTE(EP_STAT_ST)); 888 } 889 890 /* Clear stall or reset endpoint */ 891 static void udc_clrstall_hwep(struct lpc32xx_udc *udc, u32 hwep) 892 { 893 udc_protocol_cmd_data_w(udc, CMD_SET_EP_STAT(hwep), 894 DAT_WR_BYTE(0)); 895 } 896 897 /* Select an endpoint for endpoint status, clear, validate */ 898 static void udc_select_hwep(struct lpc32xx_udc *udc, u32 hwep) 899 { 900 udc_protocol_cmd_w(udc, CMD_SEL_EP(hwep)); 901 } 902 903 /* 904 * 905 * Endpoint buffer management functions 906 * 907 */ 908 /* Clear the current endpoint's buffer */ 909 static void udc_clr_buffer_hwep(struct lpc32xx_udc *udc, u32 hwep) 910 { 911 udc_select_hwep(udc, hwep); 912 udc_protocol_cmd_w(udc, CMD_CLR_BUF); 913 } 914 915 /* Validate the current endpoint's buffer */ 916 static void udc_val_buffer_hwep(struct lpc32xx_udc *udc, u32 hwep) 917 { 918 udc_select_hwep(udc, hwep); 919 udc_protocol_cmd_w(udc, CMD_VALID_BUF); 920 } 921 922 static inline u32 udc_clearep_getsts(struct lpc32xx_udc *udc, u32 hwep) 923 { 924 /* Clear EP interrupt */ 925 uda_clear_hwepint(udc, hwep); 926 return udc_selep_clrint(udc, hwep); 927 } 928 929 /* 930 * 931 * USB EP DMA support 932 * 933 */ 934 /* Allocate a DMA Descriptor */ 935 static struct lpc32xx_usbd_dd_gad *udc_dd_alloc(struct lpc32xx_udc *udc) 936 { 937 dma_addr_t dma; 938 struct lpc32xx_usbd_dd_gad *dd; 939 940 dd = (struct lpc32xx_usbd_dd_gad *) dma_pool_alloc( 941 udc->dd_cache, (GFP_KERNEL | GFP_DMA), &dma); 942 if (dd) 943 dd->this_dma = dma; 944 945 return dd; 946 } 947 948 /* Free a DMA Descriptor */ 949 static void udc_dd_free(struct lpc32xx_udc *udc, struct lpc32xx_usbd_dd_gad *dd) 950 { 951 dma_pool_free(udc->dd_cache, dd, dd->this_dma); 952 } 953 954 /* 955 * 956 * USB setup and shutdown functions 957 * 958 */ 959 /* Enables or disables most of the USB system clocks when low power mode is 960 * needed. Clocks are typically started on a connection event, and disabled 961 * when a cable is disconnected */ 962 static void udc_clk_set(struct lpc32xx_udc *udc, int enable) 963 { 964 if (enable != 0) { 965 if (udc->clocked) 966 return; 967 968 udc->clocked = 1; 969 clk_prepare_enable(udc->usb_slv_clk); 970 } else { 971 if (!udc->clocked) 972 return; 973 974 udc->clocked = 0; 975 clk_disable_unprepare(udc->usb_slv_clk); 976 } 977 } 978 979 /* Set/reset USB device address */ 980 static void udc_set_address(struct lpc32xx_udc *udc, u32 addr) 981 { 982 /* Address will be latched at the end of the status phase, or 983 latched immediately if function is called twice */ 984 udc_protocol_cmd_data_w(udc, CMD_SET_ADDR, 985 DAT_WR_BYTE(DEV_EN | addr)); 986 } 987 988 /* Setup up a IN request for DMA transfer - this consists of determining the 989 * list of DMA addresses for the transfer, allocating DMA Descriptors, 990 * installing the DD into the UDCA, and then enabling the DMA for that EP */ 991 static int udc_ep_in_req_dma(struct lpc32xx_udc *udc, struct lpc32xx_ep *ep) 992 { 993 struct lpc32xx_request *req; 994 u32 hwep = ep->hwep_num; 995 996 ep->req_pending = 1; 997 998 /* There will always be a request waiting here */ 999 req = list_entry(ep->queue.next, struct lpc32xx_request, queue); 1000 1001 /* Place the DD Descriptor into the UDCA */ 1002 udc->udca_v_base[hwep] = req->dd_desc_ptr->this_dma; 1003 1004 /* Enable DMA and interrupt for the HW EP */ 1005 udc_ep_dma_enable(udc, hwep); 1006 1007 /* Clear ZLP if last packet is not of MAXP size */ 1008 if (req->req.length % ep->ep.maxpacket) 1009 req->send_zlp = 0; 1010 1011 return 0; 1012 } 1013 1014 /* Setup up a OUT request for DMA transfer - this consists of determining the 1015 * list of DMA addresses for the transfer, allocating DMA Descriptors, 1016 * installing the DD into the UDCA, and then enabling the DMA for that EP */ 1017 static int udc_ep_out_req_dma(struct lpc32xx_udc *udc, struct lpc32xx_ep *ep) 1018 { 1019 struct lpc32xx_request *req; 1020 u32 hwep = ep->hwep_num; 1021 1022 ep->req_pending = 1; 1023 1024 /* There will always be a request waiting here */ 1025 req = list_entry(ep->queue.next, struct lpc32xx_request, queue); 1026 1027 /* Place the DD Descriptor into the UDCA */ 1028 udc->udca_v_base[hwep] = req->dd_desc_ptr->this_dma; 1029 1030 /* Enable DMA and interrupt for the HW EP */ 1031 udc_ep_dma_enable(udc, hwep); 1032 return 0; 1033 } 1034 1035 static void udc_disable(struct lpc32xx_udc *udc) 1036 { 1037 u32 i; 1038 1039 /* Disable device */ 1040 udc_protocol_cmd_data_w(udc, CMD_CFG_DEV, DAT_WR_BYTE(0)); 1041 udc_protocol_cmd_data_w(udc, CMD_SET_DEV_STAT, DAT_WR_BYTE(0)); 1042 1043 /* Disable all device interrupts (including EP0) */ 1044 uda_disable_devint(udc, 0x3FF); 1045 1046 /* Disable and reset all endpoint interrupts */ 1047 for (i = 0; i < 32; i++) { 1048 uda_disable_hwepint(udc, i); 1049 uda_clear_hwepint(udc, i); 1050 udc_disable_hwep(udc, i); 1051 udc_unrealize_hwep(udc, i); 1052 udc->udca_v_base[i] = 0; 1053 1054 /* Disable and clear all interrupts and DMA */ 1055 udc_ep_dma_disable(udc, i); 1056 writel((1 << i), USBD_EOTINTCLR(udc->udp_baseaddr)); 1057 writel((1 << i), USBD_NDDRTINTCLR(udc->udp_baseaddr)); 1058 writel((1 << i), USBD_SYSERRTINTCLR(udc->udp_baseaddr)); 1059 writel((1 << i), USBD_DMARCLR(udc->udp_baseaddr)); 1060 } 1061 1062 /* Disable DMA interrupts */ 1063 writel(0, USBD_DMAINTEN(udc->udp_baseaddr)); 1064 1065 writel(0, USBD_UDCAH(udc->udp_baseaddr)); 1066 } 1067 1068 static void udc_enable(struct lpc32xx_udc *udc) 1069 { 1070 u32 i; 1071 struct lpc32xx_ep *ep = &udc->ep[0]; 1072 1073 /* Start with known state */ 1074 udc_disable(udc); 1075 1076 /* Enable device */ 1077 udc_protocol_cmd_data_w(udc, CMD_SET_DEV_STAT, DAT_WR_BYTE(DEV_CON)); 1078 1079 /* EP interrupts on high priority, FRAME interrupt on low priority */ 1080 writel(USBD_EP_FAST, USBD_DEVINTPRI(udc->udp_baseaddr)); 1081 writel(0xFFFF, USBD_EPINTPRI(udc->udp_baseaddr)); 1082 1083 /* Clear any pending device interrupts */ 1084 writel(0x3FF, USBD_DEVINTCLR(udc->udp_baseaddr)); 1085 1086 /* Setup UDCA - not yet used (DMA) */ 1087 writel(udc->udca_p_base, USBD_UDCAH(udc->udp_baseaddr)); 1088 1089 /* Only enable EP0 in and out for now, EP0 only works in FIFO mode */ 1090 for (i = 0; i <= 1; i++) { 1091 udc_realize_hwep(udc, i, ep->ep.maxpacket); 1092 uda_enable_hwepint(udc, i); 1093 udc_select_hwep(udc, i); 1094 udc_clrstall_hwep(udc, i); 1095 udc_clr_buffer_hwep(udc, i); 1096 } 1097 1098 /* Device interrupt setup */ 1099 uda_clear_devint(udc, (USBD_ERR_INT | USBD_DEV_STAT | USBD_EP_SLOW | 1100 USBD_EP_FAST)); 1101 uda_enable_devint(udc, (USBD_ERR_INT | USBD_DEV_STAT | USBD_EP_SLOW | 1102 USBD_EP_FAST)); 1103 1104 /* Set device address to 0 - called twice to force a latch in the USB 1105 engine without the need of a setup packet status closure */ 1106 udc_set_address(udc, 0); 1107 udc_set_address(udc, 0); 1108 1109 /* Enable master DMA interrupts */ 1110 writel((USBD_SYS_ERR_INT | USBD_EOT_INT), 1111 USBD_DMAINTEN(udc->udp_baseaddr)); 1112 1113 udc->dev_status = 0; 1114 } 1115 1116 /* 1117 * 1118 * USB device board specific events handled via callbacks 1119 * 1120 */ 1121 /* Connection change event - notify board function of change */ 1122 static void uda_power_event(struct lpc32xx_udc *udc, u32 conn) 1123 { 1124 /* Just notify of a connection change event (optional) */ 1125 if (udc->board->conn_chgb != NULL) 1126 udc->board->conn_chgb(conn); 1127 } 1128 1129 /* Suspend/resume event - notify board function of change */ 1130 static void uda_resm_susp_event(struct lpc32xx_udc *udc, u32 conn) 1131 { 1132 /* Just notify of a Suspend/resume change event (optional) */ 1133 if (udc->board->susp_chgb != NULL) 1134 udc->board->susp_chgb(conn); 1135 1136 if (conn) 1137 udc->suspended = 0; 1138 else 1139 udc->suspended = 1; 1140 } 1141 1142 /* Remote wakeup enable/disable - notify board function of change */ 1143 static void uda_remwkp_cgh(struct lpc32xx_udc *udc) 1144 { 1145 if (udc->board->rmwk_chgb != NULL) 1146 udc->board->rmwk_chgb(udc->dev_status & 1147 (1 << USB_DEVICE_REMOTE_WAKEUP)); 1148 } 1149 1150 /* Reads data from FIFO, adjusts for alignment and data size */ 1151 static void udc_pop_fifo(struct lpc32xx_udc *udc, u8 *data, u32 bytes) 1152 { 1153 int n, i, bl; 1154 u16 *p16; 1155 u32 *p32, tmp, cbytes; 1156 1157 /* Use optimal data transfer method based on source address and size */ 1158 switch (((u32) data) & 0x3) { 1159 case 0: /* 32-bit aligned */ 1160 p32 = (u32 *) data; 1161 cbytes = (bytes & ~0x3); 1162 1163 /* Copy 32-bit aligned data first */ 1164 for (n = 0; n < cbytes; n += 4) 1165 *p32++ = readl(USBD_RXDATA(udc->udp_baseaddr)); 1166 1167 /* Handle any remaining bytes */ 1168 bl = bytes - cbytes; 1169 if (bl) { 1170 tmp = readl(USBD_RXDATA(udc->udp_baseaddr)); 1171 for (n = 0; n < bl; n++) 1172 data[cbytes + n] = ((tmp >> (n * 8)) & 0xFF); 1173 1174 } 1175 break; 1176 1177 case 1: /* 8-bit aligned */ 1178 case 3: 1179 /* Each byte has to be handled independently */ 1180 for (n = 0; n < bytes; n += 4) { 1181 tmp = readl(USBD_RXDATA(udc->udp_baseaddr)); 1182 1183 bl = bytes - n; 1184 if (bl > 3) 1185 bl = 3; 1186 1187 for (i = 0; i < bl; i++) 1188 data[n + i] = (u8) ((tmp >> (n * 8)) & 0xFF); 1189 } 1190 break; 1191 1192 case 2: /* 16-bit aligned */ 1193 p16 = (u16 *) data; 1194 cbytes = (bytes & ~0x3); 1195 1196 /* Copy 32-bit sized objects first with 16-bit alignment */ 1197 for (n = 0; n < cbytes; n += 4) { 1198 tmp = readl(USBD_RXDATA(udc->udp_baseaddr)); 1199 *p16++ = (u16)(tmp & 0xFFFF); 1200 *p16++ = (u16)((tmp >> 16) & 0xFFFF); 1201 } 1202 1203 /* Handle any remaining bytes */ 1204 bl = bytes - cbytes; 1205 if (bl) { 1206 tmp = readl(USBD_RXDATA(udc->udp_baseaddr)); 1207 for (n = 0; n < bl; n++) 1208 data[cbytes + n] = ((tmp >> (n * 8)) & 0xFF); 1209 } 1210 break; 1211 } 1212 } 1213 1214 /* Read data from the FIFO for an endpoint. This function is for endpoints (such 1215 * as EP0) that don't use DMA. This function should only be called if a packet 1216 * is known to be ready to read for the endpoint. Note that the endpoint must 1217 * be selected in the protocol engine prior to this call. */ 1218 static u32 udc_read_hwep(struct lpc32xx_udc *udc, u32 hwep, u32 *data, 1219 u32 bytes) 1220 { 1221 u32 tmpv; 1222 int to = 1000; 1223 u32 tmp, hwrep = ((hwep & 0x1E) << 1) | CTRL_RD_EN; 1224 1225 /* Setup read of endpoint */ 1226 writel(hwrep, USBD_CTRL(udc->udp_baseaddr)); 1227 1228 /* Wait until packet is ready */ 1229 while ((((tmpv = readl(USBD_RXPLEN(udc->udp_baseaddr))) & 1230 PKT_RDY) == 0) && (to > 0)) 1231 to--; 1232 if (!to) 1233 dev_dbg(udc->dev, "No packet ready on FIFO EP read\n"); 1234 1235 /* Mask out count */ 1236 tmp = tmpv & PKT_LNGTH_MASK; 1237 if (bytes < tmp) 1238 tmp = bytes; 1239 1240 if ((tmp > 0) && (data != NULL)) 1241 udc_pop_fifo(udc, (u8 *) data, tmp); 1242 1243 writel(((hwep & 0x1E) << 1), USBD_CTRL(udc->udp_baseaddr)); 1244 1245 /* Clear the buffer */ 1246 udc_clr_buffer_hwep(udc, hwep); 1247 1248 return tmp; 1249 } 1250 1251 /* Stuffs data into the FIFO, adjusts for alignment and data size */ 1252 static void udc_stuff_fifo(struct lpc32xx_udc *udc, u8 *data, u32 bytes) 1253 { 1254 int n, i, bl; 1255 u16 *p16; 1256 u32 *p32, tmp, cbytes; 1257 1258 /* Use optimal data transfer method based on source address and size */ 1259 switch (((u32) data) & 0x3) { 1260 case 0: /* 32-bit aligned */ 1261 p32 = (u32 *) data; 1262 cbytes = (bytes & ~0x3); 1263 1264 /* Copy 32-bit aligned data first */ 1265 for (n = 0; n < cbytes; n += 4) 1266 writel(*p32++, USBD_TXDATA(udc->udp_baseaddr)); 1267 1268 /* Handle any remaining bytes */ 1269 bl = bytes - cbytes; 1270 if (bl) { 1271 tmp = 0; 1272 for (n = 0; n < bl; n++) 1273 tmp |= data[cbytes + n] << (n * 8); 1274 1275 writel(tmp, USBD_TXDATA(udc->udp_baseaddr)); 1276 } 1277 break; 1278 1279 case 1: /* 8-bit aligned */ 1280 case 3: 1281 /* Each byte has to be handled independently */ 1282 for (n = 0; n < bytes; n += 4) { 1283 bl = bytes - n; 1284 if (bl > 4) 1285 bl = 4; 1286 1287 tmp = 0; 1288 for (i = 0; i < bl; i++) 1289 tmp |= data[n + i] << (i * 8); 1290 1291 writel(tmp, USBD_TXDATA(udc->udp_baseaddr)); 1292 } 1293 break; 1294 1295 case 2: /* 16-bit aligned */ 1296 p16 = (u16 *) data; 1297 cbytes = (bytes & ~0x3); 1298 1299 /* Copy 32-bit aligned data first */ 1300 for (n = 0; n < cbytes; n += 4) { 1301 tmp = *p16++ & 0xFFFF; 1302 tmp |= (*p16++ & 0xFFFF) << 16; 1303 writel(tmp, USBD_TXDATA(udc->udp_baseaddr)); 1304 } 1305 1306 /* Handle any remaining bytes */ 1307 bl = bytes - cbytes; 1308 if (bl) { 1309 tmp = 0; 1310 for (n = 0; n < bl; n++) 1311 tmp |= data[cbytes + n] << (n * 8); 1312 1313 writel(tmp, USBD_TXDATA(udc->udp_baseaddr)); 1314 } 1315 break; 1316 } 1317 } 1318 1319 /* Write data to the FIFO for an endpoint. This function is for endpoints (such 1320 * as EP0) that don't use DMA. Note that the endpoint must be selected in the 1321 * protocol engine prior to this call. */ 1322 static void udc_write_hwep(struct lpc32xx_udc *udc, u32 hwep, u32 *data, 1323 u32 bytes) 1324 { 1325 u32 hwwep = ((hwep & 0x1E) << 1) | CTRL_WR_EN; 1326 1327 if ((bytes > 0) && (data == NULL)) 1328 return; 1329 1330 /* Setup write of endpoint */ 1331 writel(hwwep, USBD_CTRL(udc->udp_baseaddr)); 1332 1333 writel(bytes, USBD_TXPLEN(udc->udp_baseaddr)); 1334 1335 /* Need at least 1 byte to trigger TX */ 1336 if (bytes == 0) 1337 writel(0, USBD_TXDATA(udc->udp_baseaddr)); 1338 else 1339 udc_stuff_fifo(udc, (u8 *) data, bytes); 1340 1341 writel(((hwep & 0x1E) << 1), USBD_CTRL(udc->udp_baseaddr)); 1342 1343 udc_val_buffer_hwep(udc, hwep); 1344 } 1345 1346 /* USB device reset - resets USB to a default state with just EP0 1347 enabled */ 1348 static void uda_usb_reset(struct lpc32xx_udc *udc) 1349 { 1350 u32 i = 0; 1351 /* Re-init device controller and EP0 */ 1352 udc_enable(udc); 1353 udc->gadget.speed = USB_SPEED_FULL; 1354 1355 for (i = 1; i < NUM_ENDPOINTS; i++) { 1356 struct lpc32xx_ep *ep = &udc->ep[i]; 1357 ep->req_pending = 0; 1358 } 1359 } 1360 1361 /* Send a ZLP on EP0 */ 1362 static void udc_ep0_send_zlp(struct lpc32xx_udc *udc) 1363 { 1364 udc_write_hwep(udc, EP_IN, NULL, 0); 1365 } 1366 1367 /* Get current frame number */ 1368 static u16 udc_get_current_frame(struct lpc32xx_udc *udc) 1369 { 1370 u16 flo, fhi; 1371 1372 udc_protocol_cmd_w(udc, CMD_RD_FRAME); 1373 flo = (u16) udc_protocol_cmd_r(udc, DAT_RD_FRAME); 1374 fhi = (u16) udc_protocol_cmd_r(udc, DAT_RD_FRAME); 1375 1376 return (fhi << 8) | flo; 1377 } 1378 1379 /* Set the device as configured - enables all endpoints */ 1380 static inline void udc_set_device_configured(struct lpc32xx_udc *udc) 1381 { 1382 udc_protocol_cmd_data_w(udc, CMD_CFG_DEV, DAT_WR_BYTE(CONF_DVICE)); 1383 } 1384 1385 /* Set the device as unconfigured - disables all endpoints */ 1386 static inline void udc_set_device_unconfigured(struct lpc32xx_udc *udc) 1387 { 1388 udc_protocol_cmd_data_w(udc, CMD_CFG_DEV, DAT_WR_BYTE(0)); 1389 } 1390 1391 /* reinit == restore initial software state */ 1392 static void udc_reinit(struct lpc32xx_udc *udc) 1393 { 1394 u32 i; 1395 1396 INIT_LIST_HEAD(&udc->gadget.ep_list); 1397 INIT_LIST_HEAD(&udc->gadget.ep0->ep_list); 1398 1399 for (i = 0; i < NUM_ENDPOINTS; i++) { 1400 struct lpc32xx_ep *ep = &udc->ep[i]; 1401 1402 if (i != 0) 1403 list_add_tail(&ep->ep.ep_list, &udc->gadget.ep_list); 1404 usb_ep_set_maxpacket_limit(&ep->ep, ep->maxpacket); 1405 INIT_LIST_HEAD(&ep->queue); 1406 ep->req_pending = 0; 1407 } 1408 1409 udc->ep0state = WAIT_FOR_SETUP; 1410 } 1411 1412 /* Must be called with lock */ 1413 static void done(struct lpc32xx_ep *ep, struct lpc32xx_request *req, int status) 1414 { 1415 struct lpc32xx_udc *udc = ep->udc; 1416 1417 list_del_init(&req->queue); 1418 if (req->req.status == -EINPROGRESS) 1419 req->req.status = status; 1420 else 1421 status = req->req.status; 1422 1423 if (ep->lep) { 1424 usb_gadget_unmap_request(&udc->gadget, &req->req, ep->is_in); 1425 1426 /* Free DDs */ 1427 udc_dd_free(udc, req->dd_desc_ptr); 1428 } 1429 1430 if (status && status != -ESHUTDOWN) 1431 ep_dbg(ep, "%s done %p, status %d\n", ep->ep.name, req, status); 1432 1433 ep->req_pending = 0; 1434 spin_unlock(&udc->lock); 1435 usb_gadget_giveback_request(&ep->ep, &req->req); 1436 spin_lock(&udc->lock); 1437 } 1438 1439 /* Must be called with lock */ 1440 static void nuke(struct lpc32xx_ep *ep, int status) 1441 { 1442 struct lpc32xx_request *req; 1443 1444 while (!list_empty(&ep->queue)) { 1445 req = list_entry(ep->queue.next, struct lpc32xx_request, queue); 1446 done(ep, req, status); 1447 } 1448 1449 if (status == -ESHUTDOWN) { 1450 uda_disable_hwepint(ep->udc, ep->hwep_num); 1451 udc_disable_hwep(ep->udc, ep->hwep_num); 1452 } 1453 } 1454 1455 /* IN endpoint 0 transfer */ 1456 static int udc_ep0_in_req(struct lpc32xx_udc *udc) 1457 { 1458 struct lpc32xx_request *req; 1459 struct lpc32xx_ep *ep0 = &udc->ep[0]; 1460 u32 tsend, ts = 0; 1461 1462 if (list_empty(&ep0->queue)) 1463 /* Nothing to send */ 1464 return 0; 1465 else 1466 req = list_entry(ep0->queue.next, struct lpc32xx_request, 1467 queue); 1468 1469 tsend = ts = req->req.length - req->req.actual; 1470 if (ts == 0) { 1471 /* Send a ZLP */ 1472 udc_ep0_send_zlp(udc); 1473 done(ep0, req, 0); 1474 return 1; 1475 } else if (ts > ep0->ep.maxpacket) 1476 ts = ep0->ep.maxpacket; /* Just send what we can */ 1477 1478 /* Write data to the EP0 FIFO and start transfer */ 1479 udc_write_hwep(udc, EP_IN, (req->req.buf + req->req.actual), ts); 1480 1481 /* Increment data pointer */ 1482 req->req.actual += ts; 1483 1484 if (tsend >= ep0->ep.maxpacket) 1485 return 0; /* Stay in data transfer state */ 1486 1487 /* Transfer request is complete */ 1488 udc->ep0state = WAIT_FOR_SETUP; 1489 done(ep0, req, 0); 1490 return 1; 1491 } 1492 1493 /* OUT endpoint 0 transfer */ 1494 static int udc_ep0_out_req(struct lpc32xx_udc *udc) 1495 { 1496 struct lpc32xx_request *req; 1497 struct lpc32xx_ep *ep0 = &udc->ep[0]; 1498 u32 tr, bufferspace; 1499 1500 if (list_empty(&ep0->queue)) 1501 return 0; 1502 else 1503 req = list_entry(ep0->queue.next, struct lpc32xx_request, 1504 queue); 1505 1506 if (req) { 1507 if (req->req.length == 0) { 1508 /* Just dequeue request */ 1509 done(ep0, req, 0); 1510 udc->ep0state = WAIT_FOR_SETUP; 1511 return 1; 1512 } 1513 1514 /* Get data from FIFO */ 1515 bufferspace = req->req.length - req->req.actual; 1516 if (bufferspace > ep0->ep.maxpacket) 1517 bufferspace = ep0->ep.maxpacket; 1518 1519 /* Copy data to buffer */ 1520 prefetchw(req->req.buf + req->req.actual); 1521 tr = udc_read_hwep(udc, EP_OUT, req->req.buf + req->req.actual, 1522 bufferspace); 1523 req->req.actual += bufferspace; 1524 1525 if (tr < ep0->ep.maxpacket) { 1526 /* This is the last packet */ 1527 done(ep0, req, 0); 1528 udc->ep0state = WAIT_FOR_SETUP; 1529 return 1; 1530 } 1531 } 1532 1533 return 0; 1534 } 1535 1536 /* Must be called with lock */ 1537 static void stop_activity(struct lpc32xx_udc *udc) 1538 { 1539 struct usb_gadget_driver *driver = udc->driver; 1540 int i; 1541 1542 if (udc->gadget.speed == USB_SPEED_UNKNOWN) 1543 driver = NULL; 1544 1545 udc->gadget.speed = USB_SPEED_UNKNOWN; 1546 udc->suspended = 0; 1547 1548 for (i = 0; i < NUM_ENDPOINTS; i++) { 1549 struct lpc32xx_ep *ep = &udc->ep[i]; 1550 nuke(ep, -ESHUTDOWN); 1551 } 1552 if (driver) { 1553 spin_unlock(&udc->lock); 1554 driver->disconnect(&udc->gadget); 1555 spin_lock(&udc->lock); 1556 } 1557 1558 isp1301_pullup_enable(udc, 0, 0); 1559 udc_disable(udc); 1560 udc_reinit(udc); 1561 } 1562 1563 /* 1564 * Activate or kill host pullup 1565 * Can be called with or without lock 1566 */ 1567 static void pullup(struct lpc32xx_udc *udc, int is_on) 1568 { 1569 if (!udc->clocked) 1570 return; 1571 1572 if (!udc->enabled || !udc->vbus) 1573 is_on = 0; 1574 1575 if (is_on != udc->pullup) 1576 isp1301_pullup_enable(udc, is_on, 0); 1577 } 1578 1579 /* Must be called without lock */ 1580 static int lpc32xx_ep_disable(struct usb_ep *_ep) 1581 { 1582 struct lpc32xx_ep *ep = container_of(_ep, struct lpc32xx_ep, ep); 1583 struct lpc32xx_udc *udc = ep->udc; 1584 unsigned long flags; 1585 1586 if ((ep->hwep_num_base == 0) || (ep->hwep_num == 0)) 1587 return -EINVAL; 1588 spin_lock_irqsave(&udc->lock, flags); 1589 1590 nuke(ep, -ESHUTDOWN); 1591 1592 /* Clear all DMA statuses for this EP */ 1593 udc_ep_dma_disable(udc, ep->hwep_num); 1594 writel(1 << ep->hwep_num, USBD_EOTINTCLR(udc->udp_baseaddr)); 1595 writel(1 << ep->hwep_num, USBD_NDDRTINTCLR(udc->udp_baseaddr)); 1596 writel(1 << ep->hwep_num, USBD_SYSERRTINTCLR(udc->udp_baseaddr)); 1597 writel(1 << ep->hwep_num, USBD_DMARCLR(udc->udp_baseaddr)); 1598 1599 /* Remove the DD pointer in the UDCA */ 1600 udc->udca_v_base[ep->hwep_num] = 0; 1601 1602 /* Disable and reset endpoint and interrupt */ 1603 uda_clear_hwepint(udc, ep->hwep_num); 1604 udc_unrealize_hwep(udc, ep->hwep_num); 1605 1606 ep->hwep_num = 0; 1607 1608 spin_unlock_irqrestore(&udc->lock, flags); 1609 1610 atomic_dec(&udc->enabled_ep_cnt); 1611 wake_up(&udc->ep_disable_wait_queue); 1612 1613 return 0; 1614 } 1615 1616 /* Must be called without lock */ 1617 static int lpc32xx_ep_enable(struct usb_ep *_ep, 1618 const struct usb_endpoint_descriptor *desc) 1619 { 1620 struct lpc32xx_ep *ep = container_of(_ep, struct lpc32xx_ep, ep); 1621 struct lpc32xx_udc *udc = ep->udc; 1622 u16 maxpacket; 1623 u32 tmp; 1624 unsigned long flags; 1625 1626 /* Verify EP data */ 1627 if ((!_ep) || (!ep) || (!desc) || 1628 (desc->bDescriptorType != USB_DT_ENDPOINT)) { 1629 dev_dbg(udc->dev, "bad ep or descriptor\n"); 1630 return -EINVAL; 1631 } 1632 maxpacket = usb_endpoint_maxp(desc); 1633 if ((maxpacket == 0) || (maxpacket > ep->maxpacket)) { 1634 dev_dbg(udc->dev, "bad ep descriptor's packet size\n"); 1635 return -EINVAL; 1636 } 1637 1638 /* Don't touch EP0 */ 1639 if (ep->hwep_num_base == 0) { 1640 dev_dbg(udc->dev, "Can't re-enable EP0!!!\n"); 1641 return -EINVAL; 1642 } 1643 1644 /* Is driver ready? */ 1645 if ((!udc->driver) || (udc->gadget.speed == USB_SPEED_UNKNOWN)) { 1646 dev_dbg(udc->dev, "bogus device state\n"); 1647 return -ESHUTDOWN; 1648 } 1649 1650 tmp = desc->bmAttributes & USB_ENDPOINT_XFERTYPE_MASK; 1651 switch (tmp) { 1652 case USB_ENDPOINT_XFER_CONTROL: 1653 return -EINVAL; 1654 1655 case USB_ENDPOINT_XFER_INT: 1656 if (maxpacket > ep->maxpacket) { 1657 dev_dbg(udc->dev, 1658 "Bad INT endpoint maxpacket %d\n", maxpacket); 1659 return -EINVAL; 1660 } 1661 break; 1662 1663 case USB_ENDPOINT_XFER_BULK: 1664 switch (maxpacket) { 1665 case 8: 1666 case 16: 1667 case 32: 1668 case 64: 1669 break; 1670 1671 default: 1672 dev_dbg(udc->dev, 1673 "Bad BULK endpoint maxpacket %d\n", maxpacket); 1674 return -EINVAL; 1675 } 1676 break; 1677 1678 case USB_ENDPOINT_XFER_ISOC: 1679 break; 1680 } 1681 spin_lock_irqsave(&udc->lock, flags); 1682 1683 /* Initialize endpoint to match the selected descriptor */ 1684 ep->is_in = (desc->bEndpointAddress & USB_DIR_IN) != 0; 1685 ep->ep.maxpacket = maxpacket; 1686 1687 /* Map hardware endpoint from base and direction */ 1688 if (ep->is_in) 1689 /* IN endpoints are offset 1 from the OUT endpoint */ 1690 ep->hwep_num = ep->hwep_num_base + EP_IN; 1691 else 1692 ep->hwep_num = ep->hwep_num_base; 1693 1694 ep_dbg(ep, "EP enabled: %s, HW:%d, MP:%d IN:%d\n", ep->ep.name, 1695 ep->hwep_num, maxpacket, (ep->is_in == 1)); 1696 1697 /* Realize the endpoint, interrupt is enabled later when 1698 * buffers are queued, IN EPs will NAK until buffers are ready */ 1699 udc_realize_hwep(udc, ep->hwep_num, ep->ep.maxpacket); 1700 udc_clr_buffer_hwep(udc, ep->hwep_num); 1701 uda_disable_hwepint(udc, ep->hwep_num); 1702 udc_clrstall_hwep(udc, ep->hwep_num); 1703 1704 /* Clear all DMA statuses for this EP */ 1705 udc_ep_dma_disable(udc, ep->hwep_num); 1706 writel(1 << ep->hwep_num, USBD_EOTINTCLR(udc->udp_baseaddr)); 1707 writel(1 << ep->hwep_num, USBD_NDDRTINTCLR(udc->udp_baseaddr)); 1708 writel(1 << ep->hwep_num, USBD_SYSERRTINTCLR(udc->udp_baseaddr)); 1709 writel(1 << ep->hwep_num, USBD_DMARCLR(udc->udp_baseaddr)); 1710 1711 spin_unlock_irqrestore(&udc->lock, flags); 1712 1713 atomic_inc(&udc->enabled_ep_cnt); 1714 return 0; 1715 } 1716 1717 /* 1718 * Allocate a USB request list 1719 * Can be called with or without lock 1720 */ 1721 static struct usb_request *lpc32xx_ep_alloc_request(struct usb_ep *_ep, 1722 gfp_t gfp_flags) 1723 { 1724 struct lpc32xx_request *req; 1725 1726 req = kzalloc(sizeof(struct lpc32xx_request), gfp_flags); 1727 if (!req) 1728 return NULL; 1729 1730 INIT_LIST_HEAD(&req->queue); 1731 return &req->req; 1732 } 1733 1734 /* 1735 * De-allocate a USB request list 1736 * Can be called with or without lock 1737 */ 1738 static void lpc32xx_ep_free_request(struct usb_ep *_ep, 1739 struct usb_request *_req) 1740 { 1741 struct lpc32xx_request *req; 1742 1743 req = container_of(_req, struct lpc32xx_request, req); 1744 BUG_ON(!list_empty(&req->queue)); 1745 kfree(req); 1746 } 1747 1748 /* Must be called without lock */ 1749 static int lpc32xx_ep_queue(struct usb_ep *_ep, 1750 struct usb_request *_req, gfp_t gfp_flags) 1751 { 1752 struct lpc32xx_request *req; 1753 struct lpc32xx_ep *ep; 1754 struct lpc32xx_udc *udc; 1755 unsigned long flags; 1756 int status = 0; 1757 1758 req = container_of(_req, struct lpc32xx_request, req); 1759 ep = container_of(_ep, struct lpc32xx_ep, ep); 1760 1761 if (!_ep || !_req || !_req->complete || !_req->buf || 1762 !list_empty(&req->queue)) 1763 return -EINVAL; 1764 1765 udc = ep->udc; 1766 1767 if (udc->gadget.speed == USB_SPEED_UNKNOWN) 1768 return -EPIPE; 1769 1770 if (ep->lep) { 1771 struct lpc32xx_usbd_dd_gad *dd; 1772 1773 status = usb_gadget_map_request(&udc->gadget, _req, ep->is_in); 1774 if (status) 1775 return status; 1776 1777 /* For the request, build a list of DDs */ 1778 dd = udc_dd_alloc(udc); 1779 if (!dd) { 1780 /* Error allocating DD */ 1781 return -ENOMEM; 1782 } 1783 req->dd_desc_ptr = dd; 1784 1785 /* Setup the DMA descriptor */ 1786 dd->dd_next_phy = dd->dd_next_v = 0; 1787 dd->dd_buffer_addr = req->req.dma; 1788 dd->dd_status = 0; 1789 1790 /* Special handling for ISO EPs */ 1791 if (ep->eptype == EP_ISO_TYPE) { 1792 dd->dd_setup = DD_SETUP_ISO_EP | 1793 DD_SETUP_PACKETLEN(0) | 1794 DD_SETUP_DMALENBYTES(1); 1795 dd->dd_iso_ps_mem_addr = dd->this_dma + 24; 1796 if (ep->is_in) 1797 dd->iso_status[0] = req->req.length; 1798 else 1799 dd->iso_status[0] = 0; 1800 } else 1801 dd->dd_setup = DD_SETUP_PACKETLEN(ep->ep.maxpacket) | 1802 DD_SETUP_DMALENBYTES(req->req.length); 1803 } 1804 1805 ep_dbg(ep, "%s queue req %p len %d buf %p (in=%d) z=%d\n", _ep->name, 1806 _req, _req->length, _req->buf, ep->is_in, _req->zero); 1807 1808 spin_lock_irqsave(&udc->lock, flags); 1809 1810 _req->status = -EINPROGRESS; 1811 _req->actual = 0; 1812 req->send_zlp = _req->zero; 1813 1814 /* Kickstart empty queues */ 1815 if (list_empty(&ep->queue)) { 1816 list_add_tail(&req->queue, &ep->queue); 1817 1818 if (ep->hwep_num_base == 0) { 1819 /* Handle expected data direction */ 1820 if (ep->is_in) { 1821 /* IN packet to host */ 1822 udc->ep0state = DATA_IN; 1823 status = udc_ep0_in_req(udc); 1824 } else { 1825 /* OUT packet from host */ 1826 udc->ep0state = DATA_OUT; 1827 status = udc_ep0_out_req(udc); 1828 } 1829 } else if (ep->is_in) { 1830 /* IN packet to host and kick off transfer */ 1831 if (!ep->req_pending) 1832 udc_ep_in_req_dma(udc, ep); 1833 } else 1834 /* OUT packet from host and kick off list */ 1835 if (!ep->req_pending) 1836 udc_ep_out_req_dma(udc, ep); 1837 } else 1838 list_add_tail(&req->queue, &ep->queue); 1839 1840 spin_unlock_irqrestore(&udc->lock, flags); 1841 1842 return (status < 0) ? status : 0; 1843 } 1844 1845 /* Must be called without lock */ 1846 static int lpc32xx_ep_dequeue(struct usb_ep *_ep, struct usb_request *_req) 1847 { 1848 struct lpc32xx_ep *ep; 1849 struct lpc32xx_request *req; 1850 unsigned long flags; 1851 1852 ep = container_of(_ep, struct lpc32xx_ep, ep); 1853 if (!_ep || ep->hwep_num_base == 0) 1854 return -EINVAL; 1855 1856 spin_lock_irqsave(&ep->udc->lock, flags); 1857 1858 /* make sure it's actually queued on this endpoint */ 1859 list_for_each_entry(req, &ep->queue, queue) { 1860 if (&req->req == _req) 1861 break; 1862 } 1863 if (&req->req != _req) { 1864 spin_unlock_irqrestore(&ep->udc->lock, flags); 1865 return -EINVAL; 1866 } 1867 1868 done(ep, req, -ECONNRESET); 1869 1870 spin_unlock_irqrestore(&ep->udc->lock, flags); 1871 1872 return 0; 1873 } 1874 1875 /* Must be called without lock */ 1876 static int lpc32xx_ep_set_halt(struct usb_ep *_ep, int value) 1877 { 1878 struct lpc32xx_ep *ep = container_of(_ep, struct lpc32xx_ep, ep); 1879 struct lpc32xx_udc *udc = ep->udc; 1880 unsigned long flags; 1881 1882 if ((!ep) || (ep->hwep_num <= 1)) 1883 return -EINVAL; 1884 1885 /* Don't halt an IN EP */ 1886 if (ep->is_in) 1887 return -EAGAIN; 1888 1889 spin_lock_irqsave(&udc->lock, flags); 1890 1891 if (value == 1) { 1892 /* stall */ 1893 udc_protocol_cmd_data_w(udc, CMD_SET_EP_STAT(ep->hwep_num), 1894 DAT_WR_BYTE(EP_STAT_ST)); 1895 } else { 1896 /* End stall */ 1897 ep->wedge = 0; 1898 udc_protocol_cmd_data_w(udc, CMD_SET_EP_STAT(ep->hwep_num), 1899 DAT_WR_BYTE(0)); 1900 } 1901 1902 spin_unlock_irqrestore(&udc->lock, flags); 1903 1904 return 0; 1905 } 1906 1907 /* set the halt feature and ignores clear requests */ 1908 static int lpc32xx_ep_set_wedge(struct usb_ep *_ep) 1909 { 1910 struct lpc32xx_ep *ep = container_of(_ep, struct lpc32xx_ep, ep); 1911 1912 if (!_ep || !ep->udc) 1913 return -EINVAL; 1914 1915 ep->wedge = 1; 1916 1917 return usb_ep_set_halt(_ep); 1918 } 1919 1920 static const struct usb_ep_ops lpc32xx_ep_ops = { 1921 .enable = lpc32xx_ep_enable, 1922 .disable = lpc32xx_ep_disable, 1923 .alloc_request = lpc32xx_ep_alloc_request, 1924 .free_request = lpc32xx_ep_free_request, 1925 .queue = lpc32xx_ep_queue, 1926 .dequeue = lpc32xx_ep_dequeue, 1927 .set_halt = lpc32xx_ep_set_halt, 1928 .set_wedge = lpc32xx_ep_set_wedge, 1929 }; 1930 1931 /* Send a ZLP on a non-0 IN EP */ 1932 void udc_send_in_zlp(struct lpc32xx_udc *udc, struct lpc32xx_ep *ep) 1933 { 1934 /* Clear EP status */ 1935 udc_clearep_getsts(udc, ep->hwep_num); 1936 1937 /* Send ZLP via FIFO mechanism */ 1938 udc_write_hwep(udc, ep->hwep_num, NULL, 0); 1939 } 1940 1941 /* 1942 * Handle EP completion for ZLP 1943 * This function will only be called when a delayed ZLP needs to be sent out 1944 * after a DMA transfer has filled both buffers. 1945 */ 1946 void udc_handle_eps(struct lpc32xx_udc *udc, struct lpc32xx_ep *ep) 1947 { 1948 u32 epstatus; 1949 struct lpc32xx_request *req; 1950 1951 if (ep->hwep_num <= 0) 1952 return; 1953 1954 uda_clear_hwepint(udc, ep->hwep_num); 1955 1956 /* If this interrupt isn't enabled, return now */ 1957 if (!(udc->enabled_hwepints & (1 << ep->hwep_num))) 1958 return; 1959 1960 /* Get endpoint status */ 1961 epstatus = udc_clearep_getsts(udc, ep->hwep_num); 1962 1963 /* 1964 * This should never happen, but protect against writing to the 1965 * buffer when full. 1966 */ 1967 if (epstatus & EP_SEL_F) 1968 return; 1969 1970 if (ep->is_in) { 1971 udc_send_in_zlp(udc, ep); 1972 uda_disable_hwepint(udc, ep->hwep_num); 1973 } else 1974 return; 1975 1976 /* If there isn't a request waiting, something went wrong */ 1977 req = list_entry(ep->queue.next, struct lpc32xx_request, queue); 1978 if (req) { 1979 done(ep, req, 0); 1980 1981 /* Start another request if ready */ 1982 if (!list_empty(&ep->queue)) { 1983 if (ep->is_in) 1984 udc_ep_in_req_dma(udc, ep); 1985 else 1986 udc_ep_out_req_dma(udc, ep); 1987 } else 1988 ep->req_pending = 0; 1989 } 1990 } 1991 1992 1993 /* DMA end of transfer completion */ 1994 static void udc_handle_dma_ep(struct lpc32xx_udc *udc, struct lpc32xx_ep *ep) 1995 { 1996 u32 status, epstatus; 1997 struct lpc32xx_request *req; 1998 struct lpc32xx_usbd_dd_gad *dd; 1999 2000 #ifdef CONFIG_USB_GADGET_DEBUG_FILES 2001 ep->totalints++; 2002 #endif 2003 2004 req = list_entry(ep->queue.next, struct lpc32xx_request, queue); 2005 if (!req) { 2006 ep_err(ep, "DMA interrupt on no req!\n"); 2007 return; 2008 } 2009 dd = req->dd_desc_ptr; 2010 2011 /* DMA descriptor should always be retired for this call */ 2012 if (!(dd->dd_status & DD_STATUS_DD_RETIRED)) 2013 ep_warn(ep, "DMA descriptor did not retire\n"); 2014 2015 /* Disable DMA */ 2016 udc_ep_dma_disable(udc, ep->hwep_num); 2017 writel((1 << ep->hwep_num), USBD_EOTINTCLR(udc->udp_baseaddr)); 2018 writel((1 << ep->hwep_num), USBD_NDDRTINTCLR(udc->udp_baseaddr)); 2019 2020 /* System error? */ 2021 if (readl(USBD_SYSERRTINTST(udc->udp_baseaddr)) & 2022 (1 << ep->hwep_num)) { 2023 writel((1 << ep->hwep_num), 2024 USBD_SYSERRTINTCLR(udc->udp_baseaddr)); 2025 ep_err(ep, "AHB critical error!\n"); 2026 ep->req_pending = 0; 2027 2028 /* The error could have occurred on a packet of a multipacket 2029 * transfer, so recovering the transfer is not possible. Close 2030 * the request with an error */ 2031 done(ep, req, -ECONNABORTED); 2032 return; 2033 } 2034 2035 /* Handle the current DD's status */ 2036 status = dd->dd_status; 2037 switch (status & DD_STATUS_STS_MASK) { 2038 case DD_STATUS_STS_NS: 2039 /* DD not serviced? This shouldn't happen! */ 2040 ep->req_pending = 0; 2041 ep_err(ep, "DMA critical EP error: DD not serviced (0x%x)!\n", 2042 status); 2043 2044 done(ep, req, -ECONNABORTED); 2045 return; 2046 2047 case DD_STATUS_STS_BS: 2048 /* Interrupt only fires on EOT - This shouldn't happen! */ 2049 ep->req_pending = 0; 2050 ep_err(ep, "DMA critical EP error: EOT prior to service completion (0x%x)!\n", 2051 status); 2052 done(ep, req, -ECONNABORTED); 2053 return; 2054 2055 case DD_STATUS_STS_NC: 2056 case DD_STATUS_STS_DUR: 2057 /* Really just a short packet, not an underrun */ 2058 /* This is a good status and what we expect */ 2059 break; 2060 2061 default: 2062 /* Data overrun, system error, or unknown */ 2063 ep->req_pending = 0; 2064 ep_err(ep, "DMA critical EP error: System error (0x%x)!\n", 2065 status); 2066 done(ep, req, -ECONNABORTED); 2067 return; 2068 } 2069 2070 /* ISO endpoints are handled differently */ 2071 if (ep->eptype == EP_ISO_TYPE) { 2072 if (ep->is_in) 2073 req->req.actual = req->req.length; 2074 else 2075 req->req.actual = dd->iso_status[0] & 0xFFFF; 2076 } else 2077 req->req.actual += DD_STATUS_CURDMACNT(status); 2078 2079 /* Send a ZLP if necessary. This will be done for non-int 2080 * packets which have a size that is a divisor of MAXP */ 2081 if (req->send_zlp) { 2082 /* 2083 * If at least 1 buffer is available, send the ZLP now. 2084 * Otherwise, the ZLP send needs to be deferred until a 2085 * buffer is available. 2086 */ 2087 if (udc_clearep_getsts(udc, ep->hwep_num) & EP_SEL_F) { 2088 udc_clearep_getsts(udc, ep->hwep_num); 2089 uda_enable_hwepint(udc, ep->hwep_num); 2090 epstatus = udc_clearep_getsts(udc, ep->hwep_num); 2091 2092 /* Let the EP interrupt handle the ZLP */ 2093 return; 2094 } else 2095 udc_send_in_zlp(udc, ep); 2096 } 2097 2098 /* Transfer request is complete */ 2099 done(ep, req, 0); 2100 2101 /* Start another request if ready */ 2102 udc_clearep_getsts(udc, ep->hwep_num); 2103 if (!list_empty((&ep->queue))) { 2104 if (ep->is_in) 2105 udc_ep_in_req_dma(udc, ep); 2106 else 2107 udc_ep_out_req_dma(udc, ep); 2108 } else 2109 ep->req_pending = 0; 2110 2111 } 2112 2113 /* 2114 * 2115 * Endpoint 0 functions 2116 * 2117 */ 2118 static void udc_handle_dev(struct lpc32xx_udc *udc) 2119 { 2120 u32 tmp; 2121 2122 udc_protocol_cmd_w(udc, CMD_GET_DEV_STAT); 2123 tmp = udc_protocol_cmd_r(udc, DAT_GET_DEV_STAT); 2124 2125 if (tmp & DEV_RST) 2126 uda_usb_reset(udc); 2127 else if (tmp & DEV_CON_CH) 2128 uda_power_event(udc, (tmp & DEV_CON)); 2129 else if (tmp & DEV_SUS_CH) { 2130 if (tmp & DEV_SUS) { 2131 if (udc->vbus == 0) 2132 stop_activity(udc); 2133 else if ((udc->gadget.speed != USB_SPEED_UNKNOWN) && 2134 udc->driver) { 2135 /* Power down transceiver */ 2136 udc->poweron = 0; 2137 schedule_work(&udc->pullup_job); 2138 uda_resm_susp_event(udc, 1); 2139 } 2140 } else if ((udc->gadget.speed != USB_SPEED_UNKNOWN) && 2141 udc->driver && udc->vbus) { 2142 uda_resm_susp_event(udc, 0); 2143 /* Power up transceiver */ 2144 udc->poweron = 1; 2145 schedule_work(&udc->pullup_job); 2146 } 2147 } 2148 } 2149 2150 static int udc_get_status(struct lpc32xx_udc *udc, u16 reqtype, u16 wIndex) 2151 { 2152 struct lpc32xx_ep *ep; 2153 u32 ep0buff = 0, tmp; 2154 2155 switch (reqtype & USB_RECIP_MASK) { 2156 case USB_RECIP_INTERFACE: 2157 break; /* Not supported */ 2158 2159 case USB_RECIP_DEVICE: 2160 ep0buff = udc->gadget.is_selfpowered; 2161 if (udc->dev_status & (1 << USB_DEVICE_REMOTE_WAKEUP)) 2162 ep0buff |= (1 << USB_DEVICE_REMOTE_WAKEUP); 2163 break; 2164 2165 case USB_RECIP_ENDPOINT: 2166 tmp = wIndex & USB_ENDPOINT_NUMBER_MASK; 2167 ep = &udc->ep[tmp]; 2168 if ((tmp == 0) || (tmp >= NUM_ENDPOINTS)) 2169 return -EOPNOTSUPP; 2170 2171 if (wIndex & USB_DIR_IN) { 2172 if (!ep->is_in) 2173 return -EOPNOTSUPP; /* Something's wrong */ 2174 } else if (ep->is_in) 2175 return -EOPNOTSUPP; /* Not an IN endpoint */ 2176 2177 /* Get status of the endpoint */ 2178 udc_protocol_cmd_w(udc, CMD_SEL_EP(ep->hwep_num)); 2179 tmp = udc_protocol_cmd_r(udc, DAT_SEL_EP(ep->hwep_num)); 2180 2181 if (tmp & EP_SEL_ST) 2182 ep0buff = (1 << USB_ENDPOINT_HALT); 2183 else 2184 ep0buff = 0; 2185 break; 2186 2187 default: 2188 break; 2189 } 2190 2191 /* Return data */ 2192 udc_write_hwep(udc, EP_IN, &ep0buff, 2); 2193 2194 return 0; 2195 } 2196 2197 static void udc_handle_ep0_setup(struct lpc32xx_udc *udc) 2198 { 2199 struct lpc32xx_ep *ep, *ep0 = &udc->ep[0]; 2200 struct usb_ctrlrequest ctrlpkt; 2201 int i, bytes; 2202 u16 wIndex, wValue, wLength, reqtype, req, tmp; 2203 2204 /* Nuke previous transfers */ 2205 nuke(ep0, -EPROTO); 2206 2207 /* Get setup packet */ 2208 bytes = udc_read_hwep(udc, EP_OUT, (u32 *) &ctrlpkt, 8); 2209 if (bytes != 8) { 2210 ep_warn(ep0, "Incorrectly sized setup packet (s/b 8, is %d)!\n", 2211 bytes); 2212 return; 2213 } 2214 2215 /* Native endianness */ 2216 wIndex = le16_to_cpu(ctrlpkt.wIndex); 2217 wValue = le16_to_cpu(ctrlpkt.wValue); 2218 wLength = le16_to_cpu(ctrlpkt.wLength); 2219 reqtype = le16_to_cpu(ctrlpkt.bRequestType); 2220 2221 /* Set direction of EP0 */ 2222 if (likely(reqtype & USB_DIR_IN)) 2223 ep0->is_in = 1; 2224 else 2225 ep0->is_in = 0; 2226 2227 /* Handle SETUP packet */ 2228 req = le16_to_cpu(ctrlpkt.bRequest); 2229 switch (req) { 2230 case USB_REQ_CLEAR_FEATURE: 2231 case USB_REQ_SET_FEATURE: 2232 switch (reqtype) { 2233 case (USB_TYPE_STANDARD | USB_RECIP_DEVICE): 2234 if (wValue != USB_DEVICE_REMOTE_WAKEUP) 2235 goto stall; /* Nothing else handled */ 2236 2237 /* Tell board about event */ 2238 if (req == USB_REQ_CLEAR_FEATURE) 2239 udc->dev_status &= 2240 ~(1 << USB_DEVICE_REMOTE_WAKEUP); 2241 else 2242 udc->dev_status |= 2243 (1 << USB_DEVICE_REMOTE_WAKEUP); 2244 uda_remwkp_cgh(udc); 2245 goto zlp_send; 2246 2247 case (USB_TYPE_STANDARD | USB_RECIP_ENDPOINT): 2248 tmp = wIndex & USB_ENDPOINT_NUMBER_MASK; 2249 if ((wValue != USB_ENDPOINT_HALT) || 2250 (tmp >= NUM_ENDPOINTS)) 2251 break; 2252 2253 /* Find hardware endpoint from logical endpoint */ 2254 ep = &udc->ep[tmp]; 2255 tmp = ep->hwep_num; 2256 if (tmp == 0) 2257 break; 2258 2259 if (req == USB_REQ_SET_FEATURE) 2260 udc_stall_hwep(udc, tmp); 2261 else if (!ep->wedge) 2262 udc_clrstall_hwep(udc, tmp); 2263 2264 goto zlp_send; 2265 2266 default: 2267 break; 2268 } 2269 2270 2271 case USB_REQ_SET_ADDRESS: 2272 if (reqtype == (USB_TYPE_STANDARD | USB_RECIP_DEVICE)) { 2273 udc_set_address(udc, wValue); 2274 goto zlp_send; 2275 } 2276 break; 2277 2278 case USB_REQ_GET_STATUS: 2279 udc_get_status(udc, reqtype, wIndex); 2280 return; 2281 2282 default: 2283 break; /* Let GadgetFS handle the descriptor instead */ 2284 } 2285 2286 if (likely(udc->driver)) { 2287 /* device-2-host (IN) or no data setup command, process 2288 * immediately */ 2289 spin_unlock(&udc->lock); 2290 i = udc->driver->setup(&udc->gadget, &ctrlpkt); 2291 2292 spin_lock(&udc->lock); 2293 if (req == USB_REQ_SET_CONFIGURATION) { 2294 /* Configuration is set after endpoints are realized */ 2295 if (wValue) { 2296 /* Set configuration */ 2297 udc_set_device_configured(udc); 2298 2299 udc_protocol_cmd_data_w(udc, CMD_SET_MODE, 2300 DAT_WR_BYTE(AP_CLK | 2301 INAK_BI | INAK_II)); 2302 } else { 2303 /* Clear configuration */ 2304 udc_set_device_unconfigured(udc); 2305 2306 /* Disable NAK interrupts */ 2307 udc_protocol_cmd_data_w(udc, CMD_SET_MODE, 2308 DAT_WR_BYTE(AP_CLK)); 2309 } 2310 } 2311 2312 if (i < 0) { 2313 /* setup processing failed, force stall */ 2314 dev_dbg(udc->dev, 2315 "req %02x.%02x protocol STALL; stat %d\n", 2316 reqtype, req, i); 2317 udc->ep0state = WAIT_FOR_SETUP; 2318 goto stall; 2319 } 2320 } 2321 2322 if (!ep0->is_in) 2323 udc_ep0_send_zlp(udc); /* ZLP IN packet on data phase */ 2324 2325 return; 2326 2327 stall: 2328 udc_stall_hwep(udc, EP_IN); 2329 return; 2330 2331 zlp_send: 2332 udc_ep0_send_zlp(udc); 2333 return; 2334 } 2335 2336 /* IN endpoint 0 transfer */ 2337 static void udc_handle_ep0_in(struct lpc32xx_udc *udc) 2338 { 2339 struct lpc32xx_ep *ep0 = &udc->ep[0]; 2340 u32 epstatus; 2341 2342 /* Clear EP interrupt */ 2343 epstatus = udc_clearep_getsts(udc, EP_IN); 2344 2345 #ifdef CONFIG_USB_GADGET_DEBUG_FILES 2346 ep0->totalints++; 2347 #endif 2348 2349 /* Stalled? Clear stall and reset buffers */ 2350 if (epstatus & EP_SEL_ST) { 2351 udc_clrstall_hwep(udc, EP_IN); 2352 nuke(ep0, -ECONNABORTED); 2353 udc->ep0state = WAIT_FOR_SETUP; 2354 return; 2355 } 2356 2357 /* Is a buffer available? */ 2358 if (!(epstatus & EP_SEL_F)) { 2359 /* Handle based on current state */ 2360 if (udc->ep0state == DATA_IN) 2361 udc_ep0_in_req(udc); 2362 else { 2363 /* Unknown state for EP0 oe end of DATA IN phase */ 2364 nuke(ep0, -ECONNABORTED); 2365 udc->ep0state = WAIT_FOR_SETUP; 2366 } 2367 } 2368 } 2369 2370 /* OUT endpoint 0 transfer */ 2371 static void udc_handle_ep0_out(struct lpc32xx_udc *udc) 2372 { 2373 struct lpc32xx_ep *ep0 = &udc->ep[0]; 2374 u32 epstatus; 2375 2376 /* Clear EP interrupt */ 2377 epstatus = udc_clearep_getsts(udc, EP_OUT); 2378 2379 2380 #ifdef CONFIG_USB_GADGET_DEBUG_FILES 2381 ep0->totalints++; 2382 #endif 2383 2384 /* Stalled? */ 2385 if (epstatus & EP_SEL_ST) { 2386 udc_clrstall_hwep(udc, EP_OUT); 2387 nuke(ep0, -ECONNABORTED); 2388 udc->ep0state = WAIT_FOR_SETUP; 2389 return; 2390 } 2391 2392 /* A NAK may occur if a packet couldn't be received yet */ 2393 if (epstatus & EP_SEL_EPN) 2394 return; 2395 /* Setup packet incoming? */ 2396 if (epstatus & EP_SEL_STP) { 2397 nuke(ep0, 0); 2398 udc->ep0state = WAIT_FOR_SETUP; 2399 } 2400 2401 /* Data available? */ 2402 if (epstatus & EP_SEL_F) 2403 /* Handle based on current state */ 2404 switch (udc->ep0state) { 2405 case WAIT_FOR_SETUP: 2406 udc_handle_ep0_setup(udc); 2407 break; 2408 2409 case DATA_OUT: 2410 udc_ep0_out_req(udc); 2411 break; 2412 2413 default: 2414 /* Unknown state for EP0 */ 2415 nuke(ep0, -ECONNABORTED); 2416 udc->ep0state = WAIT_FOR_SETUP; 2417 } 2418 } 2419 2420 /* Must be called without lock */ 2421 static int lpc32xx_get_frame(struct usb_gadget *gadget) 2422 { 2423 int frame; 2424 unsigned long flags; 2425 struct lpc32xx_udc *udc = to_udc(gadget); 2426 2427 if (!udc->clocked) 2428 return -EINVAL; 2429 2430 spin_lock_irqsave(&udc->lock, flags); 2431 2432 frame = (int) udc_get_current_frame(udc); 2433 2434 spin_unlock_irqrestore(&udc->lock, flags); 2435 2436 return frame; 2437 } 2438 2439 static int lpc32xx_wakeup(struct usb_gadget *gadget) 2440 { 2441 return -ENOTSUPP; 2442 } 2443 2444 static int lpc32xx_set_selfpowered(struct usb_gadget *gadget, int is_on) 2445 { 2446 gadget->is_selfpowered = (is_on != 0); 2447 2448 return 0; 2449 } 2450 2451 /* 2452 * vbus is here! turn everything on that's ready 2453 * Must be called without lock 2454 */ 2455 static int lpc32xx_vbus_session(struct usb_gadget *gadget, int is_active) 2456 { 2457 unsigned long flags; 2458 struct lpc32xx_udc *udc = to_udc(gadget); 2459 2460 spin_lock_irqsave(&udc->lock, flags); 2461 2462 /* Doesn't need lock */ 2463 if (udc->driver) { 2464 udc_clk_set(udc, 1); 2465 udc_enable(udc); 2466 pullup(udc, is_active); 2467 } else { 2468 stop_activity(udc); 2469 pullup(udc, 0); 2470 2471 spin_unlock_irqrestore(&udc->lock, flags); 2472 /* 2473 * Wait for all the endpoints to disable, 2474 * before disabling clocks. Don't wait if 2475 * endpoints are not enabled. 2476 */ 2477 if (atomic_read(&udc->enabled_ep_cnt)) 2478 wait_event_interruptible(udc->ep_disable_wait_queue, 2479 (atomic_read(&udc->enabled_ep_cnt) == 0)); 2480 2481 spin_lock_irqsave(&udc->lock, flags); 2482 2483 udc_clk_set(udc, 0); 2484 } 2485 2486 spin_unlock_irqrestore(&udc->lock, flags); 2487 2488 return 0; 2489 } 2490 2491 /* Can be called with or without lock */ 2492 static int lpc32xx_pullup(struct usb_gadget *gadget, int is_on) 2493 { 2494 struct lpc32xx_udc *udc = to_udc(gadget); 2495 2496 /* Doesn't need lock */ 2497 pullup(udc, is_on); 2498 2499 return 0; 2500 } 2501 2502 static int lpc32xx_start(struct usb_gadget *, struct usb_gadget_driver *); 2503 static int lpc32xx_stop(struct usb_gadget *); 2504 2505 static const struct usb_gadget_ops lpc32xx_udc_ops = { 2506 .get_frame = lpc32xx_get_frame, 2507 .wakeup = lpc32xx_wakeup, 2508 .set_selfpowered = lpc32xx_set_selfpowered, 2509 .vbus_session = lpc32xx_vbus_session, 2510 .pullup = lpc32xx_pullup, 2511 .udc_start = lpc32xx_start, 2512 .udc_stop = lpc32xx_stop, 2513 }; 2514 2515 static void nop_release(struct device *dev) 2516 { 2517 /* nothing to free */ 2518 } 2519 2520 static const struct lpc32xx_udc controller_template = { 2521 .gadget = { 2522 .ops = &lpc32xx_udc_ops, 2523 .name = driver_name, 2524 .dev = { 2525 .init_name = "gadget", 2526 .release = nop_release, 2527 } 2528 }, 2529 .ep[0] = { 2530 .ep = { 2531 .name = "ep0", 2532 .ops = &lpc32xx_ep_ops, 2533 .caps = USB_EP_CAPS(USB_EP_CAPS_TYPE_CONTROL, 2534 USB_EP_CAPS_DIR_ALL), 2535 }, 2536 .maxpacket = 64, 2537 .hwep_num_base = 0, 2538 .hwep_num = 0, /* Can be 0 or 1, has special handling */ 2539 .lep = 0, 2540 .eptype = EP_CTL_TYPE, 2541 }, 2542 .ep[1] = { 2543 .ep = { 2544 .name = "ep1-int", 2545 .ops = &lpc32xx_ep_ops, 2546 .caps = USB_EP_CAPS(USB_EP_CAPS_TYPE_INT, 2547 USB_EP_CAPS_DIR_ALL), 2548 }, 2549 .maxpacket = 64, 2550 .hwep_num_base = 2, 2551 .hwep_num = 0, /* 2 or 3, will be set later */ 2552 .lep = 1, 2553 .eptype = EP_INT_TYPE, 2554 }, 2555 .ep[2] = { 2556 .ep = { 2557 .name = "ep2-bulk", 2558 .ops = &lpc32xx_ep_ops, 2559 .caps = USB_EP_CAPS(USB_EP_CAPS_TYPE_BULK, 2560 USB_EP_CAPS_DIR_ALL), 2561 }, 2562 .maxpacket = 64, 2563 .hwep_num_base = 4, 2564 .hwep_num = 0, /* 4 or 5, will be set later */ 2565 .lep = 2, 2566 .eptype = EP_BLK_TYPE, 2567 }, 2568 .ep[3] = { 2569 .ep = { 2570 .name = "ep3-iso", 2571 .ops = &lpc32xx_ep_ops, 2572 .caps = USB_EP_CAPS(USB_EP_CAPS_TYPE_ISO, 2573 USB_EP_CAPS_DIR_ALL), 2574 }, 2575 .maxpacket = 1023, 2576 .hwep_num_base = 6, 2577 .hwep_num = 0, /* 6 or 7, will be set later */ 2578 .lep = 3, 2579 .eptype = EP_ISO_TYPE, 2580 }, 2581 .ep[4] = { 2582 .ep = { 2583 .name = "ep4-int", 2584 .ops = &lpc32xx_ep_ops, 2585 .caps = USB_EP_CAPS(USB_EP_CAPS_TYPE_INT, 2586 USB_EP_CAPS_DIR_ALL), 2587 }, 2588 .maxpacket = 64, 2589 .hwep_num_base = 8, 2590 .hwep_num = 0, /* 8 or 9, will be set later */ 2591 .lep = 4, 2592 .eptype = EP_INT_TYPE, 2593 }, 2594 .ep[5] = { 2595 .ep = { 2596 .name = "ep5-bulk", 2597 .ops = &lpc32xx_ep_ops, 2598 .caps = USB_EP_CAPS(USB_EP_CAPS_TYPE_BULK, 2599 USB_EP_CAPS_DIR_ALL), 2600 }, 2601 .maxpacket = 64, 2602 .hwep_num_base = 10, 2603 .hwep_num = 0, /* 10 or 11, will be set later */ 2604 .lep = 5, 2605 .eptype = EP_BLK_TYPE, 2606 }, 2607 .ep[6] = { 2608 .ep = { 2609 .name = "ep6-iso", 2610 .ops = &lpc32xx_ep_ops, 2611 .caps = USB_EP_CAPS(USB_EP_CAPS_TYPE_ISO, 2612 USB_EP_CAPS_DIR_ALL), 2613 }, 2614 .maxpacket = 1023, 2615 .hwep_num_base = 12, 2616 .hwep_num = 0, /* 12 or 13, will be set later */ 2617 .lep = 6, 2618 .eptype = EP_ISO_TYPE, 2619 }, 2620 .ep[7] = { 2621 .ep = { 2622 .name = "ep7-int", 2623 .ops = &lpc32xx_ep_ops, 2624 .caps = USB_EP_CAPS(USB_EP_CAPS_TYPE_INT, 2625 USB_EP_CAPS_DIR_ALL), 2626 }, 2627 .maxpacket = 64, 2628 .hwep_num_base = 14, 2629 .hwep_num = 0, 2630 .lep = 7, 2631 .eptype = EP_INT_TYPE, 2632 }, 2633 .ep[8] = { 2634 .ep = { 2635 .name = "ep8-bulk", 2636 .ops = &lpc32xx_ep_ops, 2637 .caps = USB_EP_CAPS(USB_EP_CAPS_TYPE_BULK, 2638 USB_EP_CAPS_DIR_ALL), 2639 }, 2640 .maxpacket = 64, 2641 .hwep_num_base = 16, 2642 .hwep_num = 0, 2643 .lep = 8, 2644 .eptype = EP_BLK_TYPE, 2645 }, 2646 .ep[9] = { 2647 .ep = { 2648 .name = "ep9-iso", 2649 .ops = &lpc32xx_ep_ops, 2650 .caps = USB_EP_CAPS(USB_EP_CAPS_TYPE_ISO, 2651 USB_EP_CAPS_DIR_ALL), 2652 }, 2653 .maxpacket = 1023, 2654 .hwep_num_base = 18, 2655 .hwep_num = 0, 2656 .lep = 9, 2657 .eptype = EP_ISO_TYPE, 2658 }, 2659 .ep[10] = { 2660 .ep = { 2661 .name = "ep10-int", 2662 .ops = &lpc32xx_ep_ops, 2663 .caps = USB_EP_CAPS(USB_EP_CAPS_TYPE_INT, 2664 USB_EP_CAPS_DIR_ALL), 2665 }, 2666 .maxpacket = 64, 2667 .hwep_num_base = 20, 2668 .hwep_num = 0, 2669 .lep = 10, 2670 .eptype = EP_INT_TYPE, 2671 }, 2672 .ep[11] = { 2673 .ep = { 2674 .name = "ep11-bulk", 2675 .ops = &lpc32xx_ep_ops, 2676 .caps = USB_EP_CAPS(USB_EP_CAPS_TYPE_BULK, 2677 USB_EP_CAPS_DIR_ALL), 2678 }, 2679 .maxpacket = 64, 2680 .hwep_num_base = 22, 2681 .hwep_num = 0, 2682 .lep = 11, 2683 .eptype = EP_BLK_TYPE, 2684 }, 2685 .ep[12] = { 2686 .ep = { 2687 .name = "ep12-iso", 2688 .ops = &lpc32xx_ep_ops, 2689 .caps = USB_EP_CAPS(USB_EP_CAPS_TYPE_ISO, 2690 USB_EP_CAPS_DIR_ALL), 2691 }, 2692 .maxpacket = 1023, 2693 .hwep_num_base = 24, 2694 .hwep_num = 0, 2695 .lep = 12, 2696 .eptype = EP_ISO_TYPE, 2697 }, 2698 .ep[13] = { 2699 .ep = { 2700 .name = "ep13-int", 2701 .ops = &lpc32xx_ep_ops, 2702 .caps = USB_EP_CAPS(USB_EP_CAPS_TYPE_INT, 2703 USB_EP_CAPS_DIR_ALL), 2704 }, 2705 .maxpacket = 64, 2706 .hwep_num_base = 26, 2707 .hwep_num = 0, 2708 .lep = 13, 2709 .eptype = EP_INT_TYPE, 2710 }, 2711 .ep[14] = { 2712 .ep = { 2713 .name = "ep14-bulk", 2714 .ops = &lpc32xx_ep_ops, 2715 .caps = USB_EP_CAPS(USB_EP_CAPS_TYPE_BULK, 2716 USB_EP_CAPS_DIR_ALL), 2717 }, 2718 .maxpacket = 64, 2719 .hwep_num_base = 28, 2720 .hwep_num = 0, 2721 .lep = 14, 2722 .eptype = EP_BLK_TYPE, 2723 }, 2724 .ep[15] = { 2725 .ep = { 2726 .name = "ep15-bulk", 2727 .ops = &lpc32xx_ep_ops, 2728 .caps = USB_EP_CAPS(USB_EP_CAPS_TYPE_BULK, 2729 USB_EP_CAPS_DIR_ALL), 2730 }, 2731 .maxpacket = 1023, 2732 .hwep_num_base = 30, 2733 .hwep_num = 0, 2734 .lep = 15, 2735 .eptype = EP_BLK_TYPE, 2736 }, 2737 }; 2738 2739 /* ISO and status interrupts */ 2740 static irqreturn_t lpc32xx_usb_lp_irq(int irq, void *_udc) 2741 { 2742 u32 tmp, devstat; 2743 struct lpc32xx_udc *udc = _udc; 2744 2745 spin_lock(&udc->lock); 2746 2747 /* Read the device status register */ 2748 devstat = readl(USBD_DEVINTST(udc->udp_baseaddr)); 2749 2750 devstat &= ~USBD_EP_FAST; 2751 writel(devstat, USBD_DEVINTCLR(udc->udp_baseaddr)); 2752 devstat = devstat & udc->enabled_devints; 2753 2754 /* Device specific handling needed? */ 2755 if (devstat & USBD_DEV_STAT) 2756 udc_handle_dev(udc); 2757 2758 /* Start of frame? (devstat & FRAME_INT): 2759 * The frame interrupt isn't really needed for ISO support, 2760 * as the driver will queue the necessary packets */ 2761 2762 /* Error? */ 2763 if (devstat & ERR_INT) { 2764 /* All types of errors, from cable removal during transfer to 2765 * misc protocol and bit errors. These are mostly for just info, 2766 * as the USB hardware will work around these. If these errors 2767 * happen alot, something is wrong. */ 2768 udc_protocol_cmd_w(udc, CMD_RD_ERR_STAT); 2769 tmp = udc_protocol_cmd_r(udc, DAT_RD_ERR_STAT); 2770 dev_dbg(udc->dev, "Device error (0x%x)!\n", tmp); 2771 } 2772 2773 spin_unlock(&udc->lock); 2774 2775 return IRQ_HANDLED; 2776 } 2777 2778 /* EP interrupts */ 2779 static irqreturn_t lpc32xx_usb_hp_irq(int irq, void *_udc) 2780 { 2781 u32 tmp; 2782 struct lpc32xx_udc *udc = _udc; 2783 2784 spin_lock(&udc->lock); 2785 2786 /* Read the device status register */ 2787 writel(USBD_EP_FAST, USBD_DEVINTCLR(udc->udp_baseaddr)); 2788 2789 /* Endpoints */ 2790 tmp = readl(USBD_EPINTST(udc->udp_baseaddr)); 2791 2792 /* Special handling for EP0 */ 2793 if (tmp & (EP_MASK_SEL(0, EP_OUT) | EP_MASK_SEL(0, EP_IN))) { 2794 /* Handle EP0 IN */ 2795 if (tmp & (EP_MASK_SEL(0, EP_IN))) 2796 udc_handle_ep0_in(udc); 2797 2798 /* Handle EP0 OUT */ 2799 if (tmp & (EP_MASK_SEL(0, EP_OUT))) 2800 udc_handle_ep0_out(udc); 2801 } 2802 2803 /* All other EPs */ 2804 if (tmp & ~(EP_MASK_SEL(0, EP_OUT) | EP_MASK_SEL(0, EP_IN))) { 2805 int i; 2806 2807 /* Handle other EP interrupts */ 2808 for (i = 1; i < NUM_ENDPOINTS; i++) { 2809 if (tmp & (1 << udc->ep[i].hwep_num)) 2810 udc_handle_eps(udc, &udc->ep[i]); 2811 } 2812 } 2813 2814 spin_unlock(&udc->lock); 2815 2816 return IRQ_HANDLED; 2817 } 2818 2819 static irqreturn_t lpc32xx_usb_devdma_irq(int irq, void *_udc) 2820 { 2821 struct lpc32xx_udc *udc = _udc; 2822 2823 int i; 2824 u32 tmp; 2825 2826 spin_lock(&udc->lock); 2827 2828 /* Handle EP DMA EOT interrupts */ 2829 tmp = readl(USBD_EOTINTST(udc->udp_baseaddr)) | 2830 (readl(USBD_EPDMAST(udc->udp_baseaddr)) & 2831 readl(USBD_NDDRTINTST(udc->udp_baseaddr))) | 2832 readl(USBD_SYSERRTINTST(udc->udp_baseaddr)); 2833 for (i = 1; i < NUM_ENDPOINTS; i++) { 2834 if (tmp & (1 << udc->ep[i].hwep_num)) 2835 udc_handle_dma_ep(udc, &udc->ep[i]); 2836 } 2837 2838 spin_unlock(&udc->lock); 2839 2840 return IRQ_HANDLED; 2841 } 2842 2843 /* 2844 * 2845 * VBUS detection, pullup handler, and Gadget cable state notification 2846 * 2847 */ 2848 static void vbus_work(struct lpc32xx_udc *udc) 2849 { 2850 u8 value; 2851 2852 if (udc->enabled != 0) { 2853 /* Discharge VBUS real quick */ 2854 i2c_smbus_write_byte_data(udc->isp1301_i2c_client, 2855 ISP1301_I2C_OTG_CONTROL_1, OTG1_VBUS_DISCHRG); 2856 2857 /* Give VBUS some time (100mS) to discharge */ 2858 msleep(100); 2859 2860 /* Disable VBUS discharge resistor */ 2861 i2c_smbus_write_byte_data(udc->isp1301_i2c_client, 2862 ISP1301_I2C_OTG_CONTROL_1 | ISP1301_I2C_REG_CLEAR_ADDR, 2863 OTG1_VBUS_DISCHRG); 2864 2865 /* Clear interrupt */ 2866 i2c_smbus_write_byte_data(udc->isp1301_i2c_client, 2867 ISP1301_I2C_INTERRUPT_LATCH | 2868 ISP1301_I2C_REG_CLEAR_ADDR, ~0); 2869 2870 /* Get the VBUS status from the transceiver */ 2871 value = i2c_smbus_read_byte_data(udc->isp1301_i2c_client, 2872 ISP1301_I2C_INTERRUPT_SOURCE); 2873 2874 /* VBUS on or off? */ 2875 if (value & INT_SESS_VLD) 2876 udc->vbus = 1; 2877 else 2878 udc->vbus = 0; 2879 2880 /* VBUS changed? */ 2881 if (udc->last_vbus != udc->vbus) { 2882 udc->last_vbus = udc->vbus; 2883 lpc32xx_vbus_session(&udc->gadget, udc->vbus); 2884 } 2885 } 2886 } 2887 2888 static irqreturn_t lpc32xx_usb_vbus_irq(int irq, void *_udc) 2889 { 2890 struct lpc32xx_udc *udc = _udc; 2891 2892 vbus_work(udc); 2893 2894 return IRQ_HANDLED; 2895 } 2896 2897 static int lpc32xx_start(struct usb_gadget *gadget, 2898 struct usb_gadget_driver *driver) 2899 { 2900 struct lpc32xx_udc *udc = to_udc(gadget); 2901 2902 if (!driver || driver->max_speed < USB_SPEED_FULL || !driver->setup) { 2903 dev_err(udc->dev, "bad parameter.\n"); 2904 return -EINVAL; 2905 } 2906 2907 if (udc->driver) { 2908 dev_err(udc->dev, "UDC already has a gadget driver\n"); 2909 return -EBUSY; 2910 } 2911 2912 udc->driver = driver; 2913 udc->gadget.dev.of_node = udc->dev->of_node; 2914 udc->enabled = 1; 2915 udc->gadget.is_selfpowered = 1; 2916 udc->vbus = 0; 2917 2918 /* Force VBUS process once to check for cable insertion */ 2919 udc->last_vbus = udc->vbus = 0; 2920 vbus_work(udc); 2921 2922 /* enable interrupts */ 2923 i2c_smbus_write_byte_data(udc->isp1301_i2c_client, 2924 ISP1301_I2C_INTERRUPT_FALLING, INT_SESS_VLD | INT_VBUS_VLD); 2925 i2c_smbus_write_byte_data(udc->isp1301_i2c_client, 2926 ISP1301_I2C_INTERRUPT_RISING, INT_SESS_VLD | INT_VBUS_VLD); 2927 2928 return 0; 2929 } 2930 2931 static int lpc32xx_stop(struct usb_gadget *gadget) 2932 { 2933 struct lpc32xx_udc *udc = to_udc(gadget); 2934 2935 i2c_smbus_write_byte_data(udc->isp1301_i2c_client, 2936 ISP1301_I2C_INTERRUPT_FALLING | ISP1301_I2C_REG_CLEAR_ADDR, ~0); 2937 i2c_smbus_write_byte_data(udc->isp1301_i2c_client, 2938 ISP1301_I2C_INTERRUPT_RISING | ISP1301_I2C_REG_CLEAR_ADDR, ~0); 2939 2940 if (udc->clocked) { 2941 spin_lock(&udc->lock); 2942 stop_activity(udc); 2943 spin_unlock(&udc->lock); 2944 2945 /* 2946 * Wait for all the endpoints to disable, 2947 * before disabling clocks. Don't wait if 2948 * endpoints are not enabled. 2949 */ 2950 if (atomic_read(&udc->enabled_ep_cnt)) 2951 wait_event_interruptible(udc->ep_disable_wait_queue, 2952 (atomic_read(&udc->enabled_ep_cnt) == 0)); 2953 2954 spin_lock(&udc->lock); 2955 udc_clk_set(udc, 0); 2956 spin_unlock(&udc->lock); 2957 } 2958 2959 udc->enabled = 0; 2960 udc->driver = NULL; 2961 2962 return 0; 2963 } 2964 2965 static void lpc32xx_udc_shutdown(struct platform_device *dev) 2966 { 2967 /* Force disconnect on reboot */ 2968 struct lpc32xx_udc *udc = platform_get_drvdata(dev); 2969 2970 pullup(udc, 0); 2971 } 2972 2973 /* 2974 * Callbacks to be overridden by options passed via OF (TODO) 2975 */ 2976 2977 static void lpc32xx_usbd_conn_chg(int conn) 2978 { 2979 /* Do nothing, it might be nice to enable an LED 2980 * based on conn state being !0 */ 2981 } 2982 2983 static void lpc32xx_usbd_susp_chg(int susp) 2984 { 2985 /* Device suspend if susp != 0 */ 2986 } 2987 2988 static void lpc32xx_rmwkup_chg(int remote_wakup_enable) 2989 { 2990 /* Enable or disable USB remote wakeup */ 2991 } 2992 2993 struct lpc32xx_usbd_cfg lpc32xx_usbddata = { 2994 .vbus_drv_pol = 0, 2995 .conn_chgb = &lpc32xx_usbd_conn_chg, 2996 .susp_chgb = &lpc32xx_usbd_susp_chg, 2997 .rmwk_chgb = &lpc32xx_rmwkup_chg, 2998 }; 2999 3000 3001 static u64 lpc32xx_usbd_dmamask = ~(u32) 0x7F; 3002 3003 static int lpc32xx_udc_probe(struct platform_device *pdev) 3004 { 3005 struct device *dev = &pdev->dev; 3006 struct lpc32xx_udc *udc; 3007 int retval, i; 3008 struct resource *res; 3009 dma_addr_t dma_handle; 3010 struct device_node *isp1301_node; 3011 3012 udc = devm_kmemdup(dev, &controller_template, sizeof(*udc), GFP_KERNEL); 3013 if (!udc) 3014 return -ENOMEM; 3015 3016 for (i = 0; i <= 15; i++) 3017 udc->ep[i].udc = udc; 3018 udc->gadget.ep0 = &udc->ep[0].ep; 3019 3020 /* init software state */ 3021 udc->gadget.dev.parent = dev; 3022 udc->pdev = pdev; 3023 udc->dev = &pdev->dev; 3024 udc->enabled = 0; 3025 3026 if (pdev->dev.of_node) { 3027 isp1301_node = of_parse_phandle(pdev->dev.of_node, 3028 "transceiver", 0); 3029 } else { 3030 isp1301_node = NULL; 3031 } 3032 3033 udc->isp1301_i2c_client = isp1301_get_client(isp1301_node); 3034 if (!udc->isp1301_i2c_client) { 3035 return -EPROBE_DEFER; 3036 } 3037 3038 dev_info(udc->dev, "ISP1301 I2C device at address 0x%x\n", 3039 udc->isp1301_i2c_client->addr); 3040 3041 pdev->dev.dma_mask = &lpc32xx_usbd_dmamask; 3042 retval = dma_set_coherent_mask(&pdev->dev, DMA_BIT_MASK(32)); 3043 if (retval) 3044 return retval; 3045 3046 udc->board = &lpc32xx_usbddata; 3047 3048 /* 3049 * Resources are mapped as follows: 3050 * IORESOURCE_MEM, base address and size of USB space 3051 * IORESOURCE_IRQ, USB device low priority interrupt number 3052 * IORESOURCE_IRQ, USB device high priority interrupt number 3053 * IORESOURCE_IRQ, USB device interrupt number 3054 * IORESOURCE_IRQ, USB transceiver interrupt number 3055 */ 3056 res = platform_get_resource(pdev, IORESOURCE_MEM, 0); 3057 if (!res) 3058 return -ENXIO; 3059 3060 spin_lock_init(&udc->lock); 3061 3062 /* Get IRQs */ 3063 for (i = 0; i < 4; i++) { 3064 udc->udp_irq[i] = platform_get_irq(pdev, i); 3065 if (udc->udp_irq[i] < 0) { 3066 dev_err(udc->dev, 3067 "irq resource %d not available!\n", i); 3068 return udc->udp_irq[i]; 3069 } 3070 } 3071 3072 udc->udp_baseaddr = devm_ioremap_resource(dev, res); 3073 if (!udc->udp_baseaddr) { 3074 dev_err(udc->dev, "IO map failure\n"); 3075 return -ENOMEM; 3076 } 3077 3078 /* Get USB device clock */ 3079 udc->usb_slv_clk = devm_clk_get(&pdev->dev, NULL); 3080 if (IS_ERR(udc->usb_slv_clk)) { 3081 dev_err(udc->dev, "failed to acquire USB device clock\n"); 3082 return PTR_ERR(udc->usb_slv_clk); 3083 } 3084 3085 /* Enable USB device clock */ 3086 retval = clk_prepare_enable(udc->usb_slv_clk); 3087 if (retval < 0) { 3088 dev_err(udc->dev, "failed to start USB device clock\n"); 3089 return retval; 3090 } 3091 3092 /* Setup deferred workqueue data */ 3093 udc->poweron = udc->pullup = 0; 3094 INIT_WORK(&udc->pullup_job, pullup_work); 3095 #ifdef CONFIG_PM 3096 INIT_WORK(&udc->power_job, power_work); 3097 #endif 3098 3099 /* All clocks are now on */ 3100 udc->clocked = 1; 3101 3102 isp1301_udc_configure(udc); 3103 /* Allocate memory for the UDCA */ 3104 udc->udca_v_base = dma_alloc_coherent(&pdev->dev, UDCA_BUFF_SIZE, 3105 &dma_handle, 3106 (GFP_KERNEL | GFP_DMA)); 3107 if (!udc->udca_v_base) { 3108 dev_err(udc->dev, "error getting UDCA region\n"); 3109 retval = -ENOMEM; 3110 goto i2c_fail; 3111 } 3112 udc->udca_p_base = dma_handle; 3113 dev_dbg(udc->dev, "DMA buffer(0x%x bytes), P:0x%08x, V:0x%p\n", 3114 UDCA_BUFF_SIZE, udc->udca_p_base, udc->udca_v_base); 3115 3116 /* Setup the DD DMA memory pool */ 3117 udc->dd_cache = dma_pool_create("udc_dd", udc->dev, 3118 sizeof(struct lpc32xx_usbd_dd_gad), 3119 sizeof(u32), 0); 3120 if (!udc->dd_cache) { 3121 dev_err(udc->dev, "error getting DD DMA region\n"); 3122 retval = -ENOMEM; 3123 goto dma_alloc_fail; 3124 } 3125 3126 /* Clear USB peripheral and initialize gadget endpoints */ 3127 udc_disable(udc); 3128 udc_reinit(udc); 3129 3130 /* Request IRQs - low and high priority USB device IRQs are routed to 3131 * the same handler, while the DMA interrupt is routed elsewhere */ 3132 retval = devm_request_irq(dev, udc->udp_irq[IRQ_USB_LP], 3133 lpc32xx_usb_lp_irq, 0, "udc_lp", udc); 3134 if (retval < 0) { 3135 dev_err(udc->dev, "LP request irq %d failed\n", 3136 udc->udp_irq[IRQ_USB_LP]); 3137 goto irq_req_fail; 3138 } 3139 retval = devm_request_irq(dev, udc->udp_irq[IRQ_USB_HP], 3140 lpc32xx_usb_hp_irq, 0, "udc_hp", udc); 3141 if (retval < 0) { 3142 dev_err(udc->dev, "HP request irq %d failed\n", 3143 udc->udp_irq[IRQ_USB_HP]); 3144 goto irq_req_fail; 3145 } 3146 3147 retval = devm_request_irq(dev, udc->udp_irq[IRQ_USB_DEVDMA], 3148 lpc32xx_usb_devdma_irq, 0, "udc_dma", udc); 3149 if (retval < 0) { 3150 dev_err(udc->dev, "DEV request irq %d failed\n", 3151 udc->udp_irq[IRQ_USB_DEVDMA]); 3152 goto irq_req_fail; 3153 } 3154 3155 /* The transceiver interrupt is used for VBUS detection and will 3156 kick off the VBUS handler function */ 3157 retval = devm_request_threaded_irq(dev, udc->udp_irq[IRQ_USB_ATX], NULL, 3158 lpc32xx_usb_vbus_irq, IRQF_ONESHOT, 3159 "udc_otg", udc); 3160 if (retval < 0) { 3161 dev_err(udc->dev, "VBUS request irq %d failed\n", 3162 udc->udp_irq[IRQ_USB_ATX]); 3163 goto irq_req_fail; 3164 } 3165 3166 /* Initialize wait queue */ 3167 init_waitqueue_head(&udc->ep_disable_wait_queue); 3168 atomic_set(&udc->enabled_ep_cnt, 0); 3169 3170 retval = usb_add_gadget_udc(dev, &udc->gadget); 3171 if (retval < 0) 3172 goto add_gadget_fail; 3173 3174 dev_set_drvdata(dev, udc); 3175 device_init_wakeup(dev, 1); 3176 create_debug_file(udc); 3177 3178 /* Disable clocks for now */ 3179 udc_clk_set(udc, 0); 3180 3181 dev_info(udc->dev, "%s version %s\n", driver_name, DRIVER_VERSION); 3182 return 0; 3183 3184 add_gadget_fail: 3185 irq_req_fail: 3186 dma_pool_destroy(udc->dd_cache); 3187 dma_alloc_fail: 3188 dma_free_coherent(&pdev->dev, UDCA_BUFF_SIZE, 3189 udc->udca_v_base, udc->udca_p_base); 3190 i2c_fail: 3191 clk_disable_unprepare(udc->usb_slv_clk); 3192 dev_err(udc->dev, "%s probe failed, %d\n", driver_name, retval); 3193 3194 return retval; 3195 } 3196 3197 static int lpc32xx_udc_remove(struct platform_device *pdev) 3198 { 3199 struct lpc32xx_udc *udc = platform_get_drvdata(pdev); 3200 3201 usb_del_gadget_udc(&udc->gadget); 3202 if (udc->driver) 3203 return -EBUSY; 3204 3205 udc_clk_set(udc, 1); 3206 udc_disable(udc); 3207 pullup(udc, 0); 3208 3209 device_init_wakeup(&pdev->dev, 0); 3210 remove_debug_file(udc); 3211 3212 dma_pool_destroy(udc->dd_cache); 3213 dma_free_coherent(&pdev->dev, UDCA_BUFF_SIZE, 3214 udc->udca_v_base, udc->udca_p_base); 3215 3216 clk_disable_unprepare(udc->usb_slv_clk); 3217 3218 return 0; 3219 } 3220 3221 #ifdef CONFIG_PM 3222 static int lpc32xx_udc_suspend(struct platform_device *pdev, pm_message_t mesg) 3223 { 3224 struct lpc32xx_udc *udc = platform_get_drvdata(pdev); 3225 3226 if (udc->clocked) { 3227 /* Power down ISP */ 3228 udc->poweron = 0; 3229 isp1301_set_powerstate(udc, 0); 3230 3231 /* Disable clocking */ 3232 udc_clk_set(udc, 0); 3233 3234 /* Keep clock flag on, so we know to re-enable clocks 3235 on resume */ 3236 udc->clocked = 1; 3237 3238 /* Kill global USB clock */ 3239 clk_disable_unprepare(udc->usb_slv_clk); 3240 } 3241 3242 return 0; 3243 } 3244 3245 static int lpc32xx_udc_resume(struct platform_device *pdev) 3246 { 3247 struct lpc32xx_udc *udc = platform_get_drvdata(pdev); 3248 3249 if (udc->clocked) { 3250 /* Enable global USB clock */ 3251 clk_prepare_enable(udc->usb_slv_clk); 3252 3253 /* Enable clocking */ 3254 udc_clk_set(udc, 1); 3255 3256 /* ISP back to normal power mode */ 3257 udc->poweron = 1; 3258 isp1301_set_powerstate(udc, 1); 3259 } 3260 3261 return 0; 3262 } 3263 #else 3264 #define lpc32xx_udc_suspend NULL 3265 #define lpc32xx_udc_resume NULL 3266 #endif 3267 3268 #ifdef CONFIG_OF 3269 static const struct of_device_id lpc32xx_udc_of_match[] = { 3270 { .compatible = "nxp,lpc3220-udc", }, 3271 { }, 3272 }; 3273 MODULE_DEVICE_TABLE(of, lpc32xx_udc_of_match); 3274 #endif 3275 3276 static struct platform_driver lpc32xx_udc_driver = { 3277 .remove = lpc32xx_udc_remove, 3278 .shutdown = lpc32xx_udc_shutdown, 3279 .suspend = lpc32xx_udc_suspend, 3280 .resume = lpc32xx_udc_resume, 3281 .driver = { 3282 .name = (char *) driver_name, 3283 .of_match_table = of_match_ptr(lpc32xx_udc_of_match), 3284 }, 3285 }; 3286 3287 module_platform_driver_probe(lpc32xx_udc_driver, lpc32xx_udc_probe); 3288 3289 MODULE_DESCRIPTION("LPC32XX udc driver"); 3290 MODULE_AUTHOR("Kevin Wells <kevin.wells@nxp.com>"); 3291 MODULE_AUTHOR("Roland Stigge <stigge@antcom.de>"); 3292 MODULE_LICENSE("GPL"); 3293 MODULE_ALIAS("platform:lpc32xx_udc"); 3294