1 /* SPDX-License-Identifier: GPL-2.0 */ 2 /* 3 * USBHS-DEV device controller driver header file 4 * 5 * Copyright (C) 2023 Cadence. 6 * 7 * Author: Pawel Laszczak <pawell@cadence.com> 8 */ 9 10 #ifndef __LINUX_CDNS2_GADGET 11 #define __LINUX_CDNS2_GADGET 12 13 #include <linux/usb/gadget.h> 14 #include <linux/dma-direction.h> 15 16 /* 17 * USBHS register interface. 18 * This corresponds to the USBHS Device Controller Interface. 19 */ 20 21 /** 22 * struct cdns2_ep0_regs - endpoint 0 related registers. 23 * @rxbc: receive (OUT) 0 endpoint byte count register. 24 * @txbc: transmit (IN) 0 endpoint byte count register. 25 * @cs: 0 endpoint control and status register. 26 * @reserved1: reserved. 27 * @fifo: 0 endpoint fifo register. 28 * @reserved2: reserved. 29 * @setupdat: SETUP data register. 30 * @reserved4: reserved. 31 * @maxpack: 0 endpoint max packet size. 32 */ 33 struct cdns2_ep0_regs { 34 __u8 rxbc; 35 __u8 txbc; 36 __u8 cs; 37 __u8 reserved1[4]; 38 __u8 fifo; 39 __le32 reserved2[94]; 40 __u8 setupdat[8]; 41 __u8 reserved4[88]; 42 __u8 maxpack; 43 } __packed __aligned(4); 44 45 /* EP0CS - bitmasks. */ 46 /* Endpoint 0 stall bit for status stage. */ 47 #define EP0CS_STALL BIT(0) 48 /* HSNAK bit. */ 49 #define EP0CS_HSNAK BIT(1) 50 /* IN 0 endpoint busy bit. */ 51 #define EP0CS_TXBSY_MSK BIT(2) 52 /* OUT 0 endpoint busy bit. */ 53 #define EP0CS_RXBSY_MSK BIT(3) 54 /* Send STALL in the data stage phase. */ 55 #define EP0CS_DSTALL BIT(4) 56 /* SETUP buffer content was changed. */ 57 #define EP0CS_CHGSET BIT(7) 58 59 /* EP0FIFO - bitmasks. */ 60 /* Direction. */ 61 #define EP0_FIFO_IO_TX BIT(4) 62 /* FIFO auto bit. */ 63 #define EP0_FIFO_AUTO BIT(5) 64 /* FIFO commit bit. */ 65 #define EP0_FIFO_COMMIT BIT(6) 66 /* FIFO access bit. */ 67 #define EP0_FIFO_ACCES BIT(7) 68 69 /** 70 * struct cdns2_epx_base - base endpoint registers. 71 * @rxbc: OUT endpoint byte count register. 72 * @rxcon: OUT endpoint control register. 73 * @rxcs: OUT endpoint control and status register. 74 * @txbc: IN endpoint byte count register. 75 * @txcon: IN endpoint control register. 76 * @txcs: IN endpoint control and status register. 77 */ 78 struct cdns2_epx_base { 79 __le16 rxbc; 80 __u8 rxcon; 81 __u8 rxcs; 82 __le16 txbc; 83 __u8 txcon; 84 __u8 txcs; 85 } __packed __aligned(4); 86 87 /* rxcon/txcon - endpoint control register bitmasks. */ 88 /* Endpoint buffering: 0 - single buffering ... 3 - quad buffering. */ 89 #define EPX_CON_BUF GENMASK(1, 0) 90 /* Endpoint type. */ 91 #define EPX_CON_TYPE GENMASK(3, 2) 92 /* Endpoint type: isochronous. */ 93 #define EPX_CON_TYPE_ISOC 0x4 94 /* Endpoint type: bulk. */ 95 #define EPX_CON_TYPE_BULK 0x8 96 /* Endpoint type: interrupt. */ 97 #define EPX_CON_TYPE_INT 0xC 98 /* Number of packets per microframe. */ 99 #define EPX_CON_ISOD GENMASK(5, 4) 100 #define EPX_CON_ISOD_SHIFT 0x4 101 /* Endpoint stall bit. */ 102 #define EPX_CON_STALL BIT(6) 103 /* Endpoint enable bit.*/ 104 #define EPX_CON_VAL BIT(7) 105 106 /* rxcs/txcs - endpoint control and status bitmasks. */ 107 /* Data sequence error for the ISO endpoint. */ 108 #define EPX_CS_ERR(p) ((p) & BIT(0)) 109 110 /** 111 * struct cdns2_epx_regs - endpoint 1..15 related registers. 112 * @reserved: reserved. 113 * @ep: none control endpoints array. 114 * @reserved2: reserved. 115 * @endprst: endpoint reset register. 116 * @reserved3: reserved. 117 * @isoautoarm: ISO auto-arm register. 118 * @reserved4: reserved. 119 * @isodctrl: ISO control register. 120 * @reserved5: reserved. 121 * @isoautodump: ISO auto dump enable register. 122 * @reserved6: reserved. 123 * @rxmaxpack: receive (OUT) Max packet size register. 124 * @reserved7: reserved. 125 * @rxstaddr: receive (OUT) start address endpoint buffer register. 126 * @reserved8: reserved. 127 * @txstaddr: transmit (IN) start address endpoint buffer register. 128 * @reserved9: reserved. 129 * @txmaxpack: transmit (IN) Max packet size register. 130 */ 131 struct cdns2_epx_regs { 132 __le32 reserved[2]; 133 struct cdns2_epx_base ep[15]; 134 __u8 reserved2[290]; 135 __u8 endprst; 136 __u8 reserved3[41]; 137 __le16 isoautoarm; 138 __u8 reserved4[10]; 139 __le16 isodctrl; 140 __le16 reserved5; 141 __le16 isoautodump; 142 __le32 reserved6; 143 __le16 rxmaxpack[15]; 144 __le32 reserved7[65]; 145 __le32 rxstaddr[15]; 146 __u8 reserved8[4]; 147 __le32 txstaddr[15]; 148 __u8 reserved9[98]; 149 __le16 txmaxpack[15]; 150 } __packed __aligned(4); 151 152 /* ENDPRST - bitmasks. */ 153 /* Endpoint number. */ 154 #define ENDPRST_EP GENMASK(3, 0) 155 /* IN direction bit. */ 156 #define ENDPRST_IO_TX BIT(4) 157 /* Toggle reset bit. */ 158 #define ENDPRST_TOGRST BIT(5) 159 /* FIFO reset bit. */ 160 #define ENDPRST_FIFORST BIT(6) 161 /* Toggle status and reset bit. */ 162 #define ENDPRST_TOGSETQ BIT(7) 163 164 /** 165 * struct cdns2_interrupt_regs - USB interrupt related registers. 166 * @reserved: reserved. 167 * @usbirq: USB interrupt request register. 168 * @extirq: external interrupt request register. 169 * @rxpngirq: external interrupt request register. 170 * @reserved1: reserved. 171 * @usbien: USB interrupt enable register. 172 * @extien: external interrupt enable register. 173 * @reserved2: reserved. 174 * @usbivect: USB interrupt vector register. 175 */ 176 struct cdns2_interrupt_regs { 177 __u8 reserved[396]; 178 __u8 usbirq; 179 __u8 extirq; 180 __le16 rxpngirq; 181 __le16 reserved1[4]; 182 __u8 usbien; 183 __u8 extien; 184 __le16 reserved2[3]; 185 __u8 usbivect; 186 } __packed __aligned(4); 187 188 /* EXTIRQ and EXTIEN - bitmasks. */ 189 /* VBUS fault fall interrupt. */ 190 #define EXTIRQ_VBUSFAULT_FALL BIT(0) 191 /* VBUS fault fall interrupt. */ 192 #define EXTIRQ_VBUSFAULT_RISE BIT(1) 193 /* Wake up interrupt bit. */ 194 #define EXTIRQ_WAKEUP BIT(7) 195 196 /* USBIEN and USBIRQ - bitmasks. */ 197 /* SETUP data valid interrupt bit.*/ 198 #define USBIRQ_SUDAV BIT(0) 199 /* Start-of-frame interrupt bit. */ 200 #define USBIRQ_SOF BIT(1) 201 /* SETUP token interrupt bit. */ 202 #define USBIRQ_SUTOK BIT(2) 203 /* USB suspend interrupt bit. */ 204 #define USBIRQ_SUSPEND BIT(3) 205 /* USB reset interrupt bit. */ 206 #define USBIRQ_URESET BIT(4) 207 /* USB high-speed mode interrupt bit. */ 208 #define USBIRQ_HSPEED BIT(5) 209 /* Link Power Management interrupt bit. */ 210 #define USBIRQ_LPM BIT(7) 211 212 #define USB_IEN_INIT (USBIRQ_SUDAV | USBIRQ_SUSPEND | USBIRQ_URESET \ 213 | USBIRQ_HSPEED | USBIRQ_LPM) 214 /** 215 * struct cdns2_usb_regs - USB controller registers. 216 * @reserved: reserved. 217 * @lpmctrl: LPM control register. 218 * @lpmclock: LPM clock register. 219 * @reserved2: reserved. 220 * @endprst: endpoint reset register. 221 * @usbcs: USB control and status register. 222 * @frmnr: USB frame counter register. 223 * @fnaddr: function Address register. 224 * @clkgate: clock gate register. 225 * @fifoctrl: FIFO control register. 226 * @speedctrl: speed Control register. 227 * @sleep_clkgate: sleep Clock Gate register. 228 * @reserved3: reserved. 229 * @cpuctrl: microprocessor control register. 230 */ 231 struct cdns2_usb_regs { 232 __u8 reserved[4]; 233 __u16 lpmctrl; 234 __u8 lpmclock; 235 __u8 reserved2[411]; 236 __u8 endprst; 237 __u8 usbcs; 238 __le16 frmnr; 239 __u8 fnaddr; 240 __u8 clkgate; 241 __u8 fifoctrl; 242 __u8 speedctrl; 243 __u8 sleep_clkgate; 244 __u8 reserved3[533]; 245 __u8 cpuctrl; 246 } __packed __aligned(4); 247 248 /* LPMCTRL - bitmasks. */ 249 /* BESL (Best Effort Service Latency). */ 250 #define LPMCTRLLL_HIRD GENMASK(7, 4) 251 /* Last received Remote Wakeup field from LPM Extended Token packet. */ 252 #define LPMCTRLLH_BREMOTEWAKEUP BIT(8) 253 /* Reflects value of the lpmnyet bit located in the usbcs[1] register. */ 254 #define LPMCTRLLH_LPMNYET BIT(16) 255 256 /* LPMCLOCK - bitmasks. */ 257 /* 258 * If bit is 1 the controller automatically turns off clock 259 * (utmisleepm goes to low), else the microprocessor should use 260 * sleep clock gate register to turn off clock. 261 */ 262 #define LPMCLOCK_SLEEP_ENTRY BIT(7) 263 264 /* USBCS - bitmasks. */ 265 /* Send NYET handshake for the LPM transaction. */ 266 #define USBCS_LPMNYET BIT(2) 267 /* Remote wake-up bit. */ 268 #define USBCS_SIGRSUME BIT(5) 269 /* Software disconnect bit. */ 270 #define USBCS_DISCON BIT(6) 271 /* Indicates that a wakeup pin resumed the controller. */ 272 #define USBCS_WAKESRC BIT(7) 273 274 /* FIFOCTRL - bitmasks. */ 275 /* Endpoint number. */ 276 #define FIFOCTRL_EP GENMASK(3, 0) 277 /* Direction bit. */ 278 #define FIFOCTRL_IO_TX BIT(4) 279 /* FIFO auto bit. */ 280 #define FIFOCTRL_FIFOAUTO BIT(5) 281 /* FIFO commit bit. */ 282 #define FIFOCTRL_FIFOCMIT BIT(6) 283 /* FIFO access bit. */ 284 #define FIFOCTRL_FIFOACC BIT(7) 285 286 /* SPEEDCTRL - bitmasks. */ 287 /* Device works in Full Speed. */ 288 #define SPEEDCTRL_FS BIT(1) 289 /* Device works in High Speed. */ 290 #define SPEEDCTRL_HS BIT(2) 291 /* Force FS mode. */ 292 #define SPEEDCTRL_HSDISABLE BIT(7) 293 294 /* CPUCTRL- bitmasks. */ 295 /* UP clock enable */ 296 #define CPUCTRL_UPCLK BIT(0) 297 /* Controller reset bit. */ 298 #define CPUCTRL_SW_RST BIT(1) 299 /** 300 * If the wuen bit is ‘1’, the upclken is automatically set to ‘1’ after 301 * detecting rising edge of wuintereq interrupt. If the wuen bit is ‘0’, 302 * the wuintereq interrupt is ignored. 303 */ 304 #define CPUCTRL_WUEN BIT(7) 305 306 307 /** 308 * struct cdns2_adma_regs - ADMA controller registers. 309 * @conf: DMA global configuration register. 310 * @sts: DMA global Status register. 311 * @reserved1: reserved. 312 * @ep_sel: DMA endpoint select register. 313 * @ep_traddr: DMA endpoint transfer ring address register. 314 * @ep_cfg: DMA endpoint configuration register. 315 * @ep_cmd: DMA endpoint command register. 316 * @ep_sts: DMA endpoint status register. 317 * @reserved2: reserved. 318 * @ep_sts_en: DMA endpoint status enable register. 319 * @drbl: DMA doorbell register. 320 * @ep_ien: DMA endpoint interrupt enable register. 321 * @ep_ists: DMA endpoint interrupt status register. 322 * @axim_ctrl: AXI Master Control register. 323 * @axim_id: AXI Master ID register. 324 * @reserved3: reserved. 325 * @axim_cap: AXI Master Wrapper Extended Capability. 326 * @reserved4: reserved. 327 * @axim_ctrl0: AXI Master Wrapper Extended Capability Control Register 0. 328 * @axim_ctrl1: AXI Master Wrapper Extended Capability Control Register 1. 329 */ 330 struct cdns2_adma_regs { 331 __le32 conf; 332 __le32 sts; 333 __le32 reserved1[5]; 334 __le32 ep_sel; 335 __le32 ep_traddr; 336 __le32 ep_cfg; 337 __le32 ep_cmd; 338 __le32 ep_sts; 339 __le32 reserved2; 340 __le32 ep_sts_en; 341 __le32 drbl; 342 __le32 ep_ien; 343 __le32 ep_ists; 344 __le32 axim_ctrl; 345 __le32 axim_id; 346 __le32 reserved3; 347 __le32 axim_cap; 348 __le32 reserved4; 349 __le32 axim_ctrl0; 350 __le32 axim_ctrl1; 351 }; 352 353 #define CDNS2_ADMA_REGS_OFFSET 0x400 354 355 /* DMA_CONF - bitmasks. */ 356 /* Reset USB device configuration. */ 357 #define DMA_CONF_CFGRST BIT(0) 358 /* Singular DMA transfer mode.*/ 359 #define DMA_CONF_DSING BIT(8) 360 /* Multiple DMA transfers mode.*/ 361 #define DMA_CONF_DMULT BIT(9) 362 363 /* DMA_EP_CFG - bitmasks. */ 364 /* Endpoint enable. */ 365 #define DMA_EP_CFG_ENABLE BIT(0) 366 367 /* DMA_EP_CMD - bitmasks. */ 368 /* Endpoint reset. */ 369 #define DMA_EP_CMD_EPRST BIT(0) 370 /* Transfer descriptor ready. */ 371 #define DMA_EP_CMD_DRDY BIT(6) 372 /* Data flush. */ 373 #define DMA_EP_CMD_DFLUSH BIT(7) 374 375 /* DMA_EP_STS - bitmasks. */ 376 /* Interrupt On Complete. */ 377 #define DMA_EP_STS_IOC BIT(2) 378 /* Interrupt on Short Packet. */ 379 #define DMA_EP_STS_ISP BIT(3) 380 /* Transfer descriptor missing. */ 381 #define DMA_EP_STS_DESCMIS BIT(4) 382 /* TRB error. */ 383 #define DMA_EP_STS_TRBERR BIT(7) 384 /* DMA busy bit. */ 385 #define DMA_EP_STS_DBUSY BIT(9) 386 /* Current Cycle Status. */ 387 #define DMA_EP_STS_CCS(p) ((p) & BIT(11)) 388 /* OUT size mismatch. */ 389 #define DMA_EP_STS_OUTSMM BIT(14) 390 /* ISO transmission error. */ 391 #define DMA_EP_STS_ISOERR BIT(15) 392 393 /* DMA_EP_STS_EN - bitmasks. */ 394 /* OUT transfer missing descriptor enable. */ 395 #define DMA_EP_STS_EN_DESCMISEN BIT(4) 396 /* TRB enable. */ 397 #define DMA_EP_STS_EN_TRBERREN BIT(7) 398 /* OUT size mismatch enable. */ 399 #define DMA_EP_STS_EN_OUTSMMEN BIT(14) 400 /* ISO transmission error enable. */ 401 #define DMA_EP_STS_EN_ISOERREN BIT(15) 402 403 /* DMA_EP_IEN - bitmasks. */ 404 #define DMA_EP_IEN(index) (1 << (index)) 405 #define DMA_EP_IEN_EP_OUT0 BIT(0) 406 #define DMA_EP_IEN_EP_IN0 BIT(16) 407 408 /* DMA_EP_ISTS - bitmasks. */ 409 #define DMA_EP_ISTS(index) (1 << (index)) 410 #define DMA_EP_ISTS_EP_OUT0 BIT(0) 411 #define DMA_EP_ISTS_EP_IN0 BIT(16) 412 413 #define gadget_to_cdns2_device(g) (container_of(g, struct cdns2_device, gadget)) 414 #define ep_to_cdns2_ep(ep) (container_of(ep, struct cdns2_endpoint, endpoint)) 415 416 /*-------------------------------------------------------------------------*/ 417 #define TRBS_PER_SEGMENT 600 418 #define ISO_MAX_INTERVAL 8 419 #define MAX_TRB_LENGTH BIT(16) 420 #define MAX_ISO_SIZE 3076 421 /* 422 * To improve performance the TRB buffer pointers can't cross 423 * 4KB boundaries. 424 */ 425 #define TRB_MAX_ISO_BUFF_SHIFT 12 426 #define TRB_MAX_ISO_BUFF_SIZE BIT(TRB_MAX_ISO_BUFF_SHIFT) 427 /* How much data is left before the 4KB boundary? */ 428 #define TRB_BUFF_LEN_UP_TO_BOUNDARY(addr) (TRB_MAX_ISO_BUFF_SIZE - \ 429 ((addr) & (TRB_MAX_ISO_BUFF_SIZE - 1))) 430 431 #if TRBS_PER_SEGMENT < 2 432 #error "Incorrect TRBS_PER_SEGMENT. Minimal Transfer Ring size is 2." 433 #endif 434 435 /** 436 * struct cdns2_trb - represent Transfer Descriptor block. 437 * @buffer: pointer to buffer data. 438 * @length: length of data. 439 * @control: control flags. 440 * 441 * This structure describes transfer block handled by DMA module. 442 */ 443 struct cdns2_trb { 444 __le32 buffer; 445 __le32 length; 446 __le32 control; 447 }; 448 449 #define TRB_SIZE (sizeof(struct cdns2_trb)) 450 /* 451 * These two extra TRBs are reserved for isochronous transfer 452 * to inject 0 length packet and extra LINK TRB to synchronize the ISO transfer. 453 */ 454 #define TRB_ISO_RESERVED 2 455 #define TR_SEG_SIZE (TRB_SIZE * (TRBS_PER_SEGMENT + TRB_ISO_RESERVED)) 456 457 /* TRB bit mask. */ 458 #define TRB_TYPE_BITMASK GENMASK(15, 10) 459 #define TRB_TYPE(p) ((p) << 10) 460 #define TRB_FIELD_TO_TYPE(p) (((p) & TRB_TYPE_BITMASK) >> 10) 461 462 /* TRB type IDs. */ 463 /* Used for Bulk, Interrupt, ISOC, and control data stage. */ 464 #define TRB_NORMAL 1 465 /* TRB for linking ring segments. */ 466 #define TRB_LINK 6 467 468 /* Cycle bit - indicates TRB ownership by driver or hw. */ 469 #define TRB_CYCLE BIT(0) 470 /* 471 * When set to '1', the device will toggle its interpretation of the Cycle bit. 472 */ 473 #define TRB_TOGGLE BIT(1) 474 /* Interrupt on short packet. */ 475 #define TRB_ISP BIT(2) 476 /* Chain bit associate this TRB with next one TRB. */ 477 #define TRB_CHAIN BIT(4) 478 /* Interrupt on completion. */ 479 #define TRB_IOC BIT(5) 480 481 /* Transfer_len bitmasks. */ 482 #define TRB_LEN(p) ((p) & GENMASK(16, 0)) 483 #define TRB_BURST(p) (((p) << 24) & GENMASK(31, 24)) 484 #define TRB_FIELD_TO_BURST(p) (((p) & GENMASK(31, 24)) >> 24) 485 486 /* Data buffer pointer bitmasks. */ 487 #define TRB_BUFFER(p) ((p) & GENMASK(31, 0)) 488 489 /*-------------------------------------------------------------------------*/ 490 /* Driver numeric constants. */ 491 492 /* Maximum address that can be assigned to device. */ 493 #define USB_DEVICE_MAX_ADDRESS 127 494 495 /* One control and 15 IN and 15 OUT endpoints. */ 496 #define CDNS2_ENDPOINTS_NUM 31 497 498 #define CDNS2_EP_ZLP_BUF_SIZE 512 499 500 /*-------------------------------------------------------------------------*/ 501 /* Used structures. */ 502 503 struct cdns2_device; 504 505 /** 506 * struct cdns2_ring - transfer ring representation. 507 * @trbs: pointer to transfer ring. 508 * @dma: dma address of transfer ring. 509 * @free_trbs: number of free TRBs in transfer ring. 510 * @pcs: producer cycle state. 511 * @ccs: consumer cycle state. 512 * @enqueue: enqueue index in transfer ring. 513 * @dequeue: dequeue index in transfer ring. 514 */ 515 struct cdns2_ring { 516 struct cdns2_trb *trbs; 517 dma_addr_t dma; 518 int free_trbs; 519 u8 pcs; 520 u8 ccs; 521 int enqueue; 522 int dequeue; 523 }; 524 525 /** 526 * struct cdns2_endpoint - extended device side representation of USB endpoint. 527 * @endpoint: usb endpoint. 528 * @pending_list: list of requests queuing on transfer ring. 529 * @deferred_list: list of requests waiting for queuing on transfer ring. 530 * @pdev: device associated with endpoint. 531 * @name: a human readable name e.g. ep1out. 532 * @ring: transfer ring associated with endpoint. 533 * @ep_state: state of endpoint. 534 * @idx: index of endpoint in pdev->eps table. 535 * @dir: endpoint direction. 536 * @num: endpoint number (1 - 15). 537 * @type: set to bmAttributes & USB_ENDPOINT_XFERTYPE_MASK. 538 * @interval: interval between packets used for ISOC and Interrupt endpoint. 539 * @buffering: on-chip buffers assigned to endpoint. 540 * @trb_burst_size: number of burst used in TRB. 541 * @skip: Sometimes the controller cannot process isochronous endpoint ring 542 * quickly enough and it will miss some isoc tds on the ring and 543 * generate ISO transmition error. 544 * Driver sets skip flag when receive a ISO transmition error and 545 * process the missed TDs on the endpoint ring. 546 * @wa1_set: use WA1. 547 * @wa1_trb: TRB assigned to WA1. 548 * @wa1_trb_index: TRB index for WA1. 549 * @wa1_cycle_bit: correct cycle bit for WA1. 550 */ 551 struct cdns2_endpoint { 552 struct usb_ep endpoint; 553 struct list_head pending_list; 554 struct list_head deferred_list; 555 556 struct cdns2_device *pdev; 557 char name[20]; 558 559 struct cdns2_ring ring; 560 561 #define EP_ENABLED BIT(0) 562 #define EP_STALLED BIT(1) 563 #define EP_STALL_PENDING BIT(2) 564 #define EP_WEDGE BIT(3) 565 #define EP_CLAIMED BIT(4) 566 #define EP_RING_FULL BIT(5) 567 #define EP_DEFERRED_DRDY BIT(6) 568 569 u32 ep_state; 570 571 u8 idx; 572 u8 dir; 573 u8 num; 574 u8 type; 575 int interval; 576 u8 buffering; 577 u8 trb_burst_size; 578 bool skip; 579 580 unsigned int wa1_set:1; 581 struct cdns2_trb *wa1_trb; 582 unsigned int wa1_trb_index; 583 unsigned int wa1_cycle_bit:1; 584 }; 585 586 /** 587 * struct cdns2_request - extended device side representation of usb_request 588 * object. 589 * @request: generic usb_request object describing single I/O request. 590 * @pep: extended representation of usb_ep object. 591 * @trb: the first TRB association with this request. 592 * @start_trb: number of the first TRB in transfer ring. 593 * @end_trb: number of the last TRB in transfer ring. 594 * @list: used for queuing request in lists. 595 * @finished_trb: number of trb has already finished per request. 596 * @num_of_trb: how many trbs are associated with request. 597 */ 598 struct cdns2_request { 599 struct usb_request request; 600 struct cdns2_endpoint *pep; 601 struct cdns2_trb *trb; 602 int start_trb; 603 int end_trb; 604 struct list_head list; 605 int finished_trb; 606 int num_of_trb; 607 }; 608 609 #define to_cdns2_request(r) (container_of(r, struct cdns2_request, request)) 610 611 /* Stages used during enumeration process.*/ 612 #define CDNS2_SETUP_STAGE 0x0 613 #define CDNS2_DATA_STAGE 0x1 614 #define CDNS2_STATUS_STAGE 0x2 615 616 /** 617 * struct cdns2_device - represent USB device. 618 * @dev: pointer to device structure associated whit this controller. 619 * @gadget: device side representation of the peripheral controller. 620 * @gadget_driver: pointer to the gadget driver. 621 * @lock: for synchronizing. 622 * @irq: interrupt line number. 623 * @regs: base address for registers 624 * @usb_regs: base address for common USB registers. 625 * @ep0_regs: base address for endpoint 0 related registers. 626 * @epx_regs: base address for all none control endpoint registers. 627 * @interrupt_regs: base address for interrupt handling related registers. 628 * @adma_regs: base address for ADMA registers. 629 * @eps_dma_pool: endpoint Transfer Ring pool. 630 * @setup: used while processing usb control requests. 631 * @ep0_preq: private request used while handling EP0. 632 * @ep0_stage: ep0 stage during enumeration process. 633 * @zlp_buf: zlp buffer. 634 * @dev_address: device address assigned by host. 635 * @eps: array of objects describing endpoints. 636 * @selected_ep: actually selected endpoint. It's used only to improve 637 * performance by limiting access to dma_ep_sel register. 638 * @is_selfpowered: device is self powered. 639 * @may_wakeup: allows device to remote wakeup the host. 640 * @status_completion_no_call: indicate that driver is waiting for status 641 * stage completion. It's used in deferred SET_CONFIGURATION request. 642 * @in_lpm: indicate the controller is in low power mode. 643 * @pending_status_wq: workqueue handling status stage for deferred requests. 644 * @pending_status_request: request for which status stage was deferred. 645 * @eps_supported: endpoints supported by controller in form: 646 * bit: 0 - ep0, 1 - epOut1, 2 - epIn1, 3 - epOut2 ... 647 * @burst_opt: array with the best burst size value for different TRB size. 648 * @onchip_tx_buf: size of transmit on-chip buffer in KB. 649 * @onchip_rx_buf: size of receive on-chip buffer in KB. 650 */ 651 struct cdns2_device { 652 struct device *dev; 653 struct usb_gadget gadget; 654 struct usb_gadget_driver *gadget_driver; 655 656 /* generic spin-lock for drivers */ 657 spinlock_t lock; 658 int irq; 659 void __iomem *regs; 660 struct cdns2_usb_regs __iomem *usb_regs; 661 struct cdns2_ep0_regs __iomem *ep0_regs; 662 struct cdns2_epx_regs __iomem *epx_regs; 663 struct cdns2_interrupt_regs __iomem *interrupt_regs; 664 struct cdns2_adma_regs __iomem *adma_regs; 665 struct dma_pool *eps_dma_pool; 666 struct usb_ctrlrequest setup; 667 struct cdns2_request ep0_preq; 668 u8 ep0_stage; 669 void *zlp_buf; 670 u8 dev_address; 671 struct cdns2_endpoint eps[CDNS2_ENDPOINTS_NUM]; 672 u32 selected_ep; 673 bool is_selfpowered; 674 bool may_wakeup; 675 bool status_completion_no_call; 676 bool in_lpm; 677 struct work_struct pending_status_wq; 678 struct usb_request *pending_status_request; 679 u32 eps_supported; 680 u8 burst_opt[MAX_ISO_SIZE + 1]; 681 682 /*in KB */ 683 u16 onchip_tx_buf; 684 u16 onchip_rx_buf; 685 }; 686 687 #define CDNS2_IF_EP_EXIST(pdev, ep_num, dir) \ 688 ((pdev)->eps_supported & \ 689 (BIT(ep_num) << ((dir) ? 0 : 16))) 690 691 dma_addr_t cdns2_trb_virt_to_dma(struct cdns2_endpoint *pep, 692 struct cdns2_trb *trb); 693 void cdns2_pending_setup_status_handler(struct work_struct *work); 694 void cdns2_select_ep(struct cdns2_device *pdev, u32 ep); 695 struct cdns2_request *cdns2_next_preq(struct list_head *list); 696 struct usb_request *cdns2_gadget_ep_alloc_request(struct usb_ep *ep, 697 gfp_t gfp_flags); 698 void cdns2_gadget_ep_free_request(struct usb_ep *ep, 699 struct usb_request *request); 700 int cdns2_gadget_ep_dequeue(struct usb_ep *ep, struct usb_request *request); 701 void cdns2_gadget_giveback(struct cdns2_endpoint *pep, 702 struct cdns2_request *priv_req, 703 int status); 704 void cdns2_init_ep0(struct cdns2_device *pdev, struct cdns2_endpoint *pep); 705 void cdns2_ep0_config(struct cdns2_device *pdev); 706 void cdns2_handle_ep0_interrupt(struct cdns2_device *pdev, int dir); 707 void cdns2_handle_setup_packet(struct cdns2_device *pdev); 708 int cdns2_gadget_resume(struct cdns2_device *pdev, bool hibernated); 709 int cdns2_gadget_suspend(struct cdns2_device *pdev); 710 void cdns2_gadget_remove(struct cdns2_device *pdev); 711 int cdns2_gadget_init(struct cdns2_device *pdev); 712 void set_reg_bit_8(void __iomem *ptr, u8 mask); 713 int cdns2_halt_endpoint(struct cdns2_device *pdev, struct cdns2_endpoint *pep, 714 int value); 715 716 #endif /* __LINUX_CDNS2_GADGET */ 717