1 // SPDX-License-Identifier: GPL-2.0 2 /* 3 * Driver for the Atmel USBA high speed USB device controller 4 * 5 * Copyright (C) 2005-2007 Atmel Corporation 6 */ 7 #include <linux/clk.h> 8 #include <linux/clk/at91_pmc.h> 9 #include <linux/module.h> 10 #include <linux/init.h> 11 #include <linux/interrupt.h> 12 #include <linux/io.h> 13 #include <linux/slab.h> 14 #include <linux/device.h> 15 #include <linux/dma-mapping.h> 16 #include <linux/list.h> 17 #include <linux/mfd/syscon.h> 18 #include <linux/platform_device.h> 19 #include <linux/regmap.h> 20 #include <linux/ctype.h> 21 #include <linux/usb.h> 22 #include <linux/usb/ch9.h> 23 #include <linux/usb/gadget.h> 24 #include <linux/delay.h> 25 #include <linux/of.h> 26 #include <linux/irq.h> 27 #include <linux/gpio/consumer.h> 28 29 #include "atmel_usba_udc.h" 30 #define USBA_VBUS_IRQFLAGS (IRQF_ONESHOT \ 31 | IRQF_TRIGGER_FALLING | IRQF_TRIGGER_RISING) 32 33 #ifdef CONFIG_USB_GADGET_DEBUG_FS 34 #include <linux/debugfs.h> 35 #include <linux/uaccess.h> 36 37 static int queue_dbg_open(struct inode *inode, struct file *file) 38 { 39 struct usba_ep *ep = inode->i_private; 40 struct usba_request *req, *req_copy; 41 struct list_head *queue_data; 42 43 queue_data = kmalloc(sizeof(*queue_data), GFP_KERNEL); 44 if (!queue_data) 45 return -ENOMEM; 46 INIT_LIST_HEAD(queue_data); 47 48 spin_lock_irq(&ep->udc->lock); 49 list_for_each_entry(req, &ep->queue, queue) { 50 req_copy = kmemdup(req, sizeof(*req_copy), GFP_ATOMIC); 51 if (!req_copy) 52 goto fail; 53 list_add_tail(&req_copy->queue, queue_data); 54 } 55 spin_unlock_irq(&ep->udc->lock); 56 57 file->private_data = queue_data; 58 return 0; 59 60 fail: 61 spin_unlock_irq(&ep->udc->lock); 62 list_for_each_entry_safe(req, req_copy, queue_data, queue) { 63 list_del(&req->queue); 64 kfree(req); 65 } 66 kfree(queue_data); 67 return -ENOMEM; 68 } 69 70 /* 71 * bbbbbbbb llllllll IZS sssss nnnn FDL\n\0 72 * 73 * b: buffer address 74 * l: buffer length 75 * I/i: interrupt/no interrupt 76 * Z/z: zero/no zero 77 * S/s: short ok/short not ok 78 * s: status 79 * n: nr_packets 80 * F/f: submitted/not submitted to FIFO 81 * D/d: using/not using DMA 82 * L/l: last transaction/not last transaction 83 */ 84 static ssize_t queue_dbg_read(struct file *file, char __user *buf, 85 size_t nbytes, loff_t *ppos) 86 { 87 struct list_head *queue = file->private_data; 88 struct usba_request *req, *tmp_req; 89 size_t len, remaining, actual = 0; 90 char tmpbuf[38]; 91 92 if (!access_ok(buf, nbytes)) 93 return -EFAULT; 94 95 inode_lock(file_inode(file)); 96 list_for_each_entry_safe(req, tmp_req, queue, queue) { 97 len = snprintf(tmpbuf, sizeof(tmpbuf), 98 "%8p %08x %c%c%c %5d %c%c%c\n", 99 req->req.buf, req->req.length, 100 req->req.no_interrupt ? 'i' : 'I', 101 req->req.zero ? 'Z' : 'z', 102 req->req.short_not_ok ? 's' : 'S', 103 req->req.status, 104 req->submitted ? 'F' : 'f', 105 req->using_dma ? 'D' : 'd', 106 req->last_transaction ? 'L' : 'l'); 107 len = min(len, sizeof(tmpbuf)); 108 if (len > nbytes) 109 break; 110 111 list_del(&req->queue); 112 kfree(req); 113 114 remaining = __copy_to_user(buf, tmpbuf, len); 115 actual += len - remaining; 116 if (remaining) 117 break; 118 119 nbytes -= len; 120 buf += len; 121 } 122 inode_unlock(file_inode(file)); 123 124 return actual; 125 } 126 127 static int queue_dbg_release(struct inode *inode, struct file *file) 128 { 129 struct list_head *queue_data = file->private_data; 130 struct usba_request *req, *tmp_req; 131 132 list_for_each_entry_safe(req, tmp_req, queue_data, queue) { 133 list_del(&req->queue); 134 kfree(req); 135 } 136 kfree(queue_data); 137 return 0; 138 } 139 140 static int regs_dbg_open(struct inode *inode, struct file *file) 141 { 142 struct usba_udc *udc; 143 unsigned int i; 144 u32 *data; 145 int ret = -ENOMEM; 146 147 inode_lock(inode); 148 udc = inode->i_private; 149 data = kmalloc(inode->i_size, GFP_KERNEL); 150 if (!data) 151 goto out; 152 153 spin_lock_irq(&udc->lock); 154 for (i = 0; i < inode->i_size / 4; i++) 155 data[i] = readl_relaxed(udc->regs + i * 4); 156 spin_unlock_irq(&udc->lock); 157 158 file->private_data = data; 159 ret = 0; 160 161 out: 162 inode_unlock(inode); 163 164 return ret; 165 } 166 167 static ssize_t regs_dbg_read(struct file *file, char __user *buf, 168 size_t nbytes, loff_t *ppos) 169 { 170 struct inode *inode = file_inode(file); 171 int ret; 172 173 inode_lock(inode); 174 ret = simple_read_from_buffer(buf, nbytes, ppos, 175 file->private_data, 176 file_inode(file)->i_size); 177 inode_unlock(inode); 178 179 return ret; 180 } 181 182 static int regs_dbg_release(struct inode *inode, struct file *file) 183 { 184 kfree(file->private_data); 185 return 0; 186 } 187 188 static const struct file_operations queue_dbg_fops = { 189 .owner = THIS_MODULE, 190 .open = queue_dbg_open, 191 .llseek = no_llseek, 192 .read = queue_dbg_read, 193 .release = queue_dbg_release, 194 }; 195 196 static const struct file_operations regs_dbg_fops = { 197 .owner = THIS_MODULE, 198 .open = regs_dbg_open, 199 .llseek = generic_file_llseek, 200 .read = regs_dbg_read, 201 .release = regs_dbg_release, 202 }; 203 204 static void usba_ep_init_debugfs(struct usba_udc *udc, 205 struct usba_ep *ep) 206 { 207 struct dentry *ep_root; 208 209 ep_root = debugfs_create_dir(ep->ep.name, udc->debugfs_root); 210 ep->debugfs_dir = ep_root; 211 212 debugfs_create_file("queue", 0400, ep_root, ep, &queue_dbg_fops); 213 if (ep->can_dma) 214 debugfs_create_u32("dma_status", 0400, ep_root, 215 &ep->last_dma_status); 216 if (ep_is_control(ep)) 217 debugfs_create_u32("state", 0400, ep_root, &ep->state); 218 } 219 220 static void usba_ep_cleanup_debugfs(struct usba_ep *ep) 221 { 222 debugfs_remove_recursive(ep->debugfs_dir); 223 } 224 225 static void usba_init_debugfs(struct usba_udc *udc) 226 { 227 struct dentry *root; 228 struct resource *regs_resource; 229 230 root = debugfs_create_dir(udc->gadget.name, usb_debug_root); 231 udc->debugfs_root = root; 232 233 regs_resource = platform_get_resource(udc->pdev, IORESOURCE_MEM, 234 CTRL_IOMEM_ID); 235 236 if (regs_resource) { 237 debugfs_create_file_size("regs", 0400, root, udc, 238 ®s_dbg_fops, 239 resource_size(regs_resource)); 240 } 241 242 usba_ep_init_debugfs(udc, to_usba_ep(udc->gadget.ep0)); 243 } 244 245 static void usba_cleanup_debugfs(struct usba_udc *udc) 246 { 247 usba_ep_cleanup_debugfs(to_usba_ep(udc->gadget.ep0)); 248 debugfs_remove_recursive(udc->debugfs_root); 249 } 250 #else 251 static inline void usba_ep_init_debugfs(struct usba_udc *udc, 252 struct usba_ep *ep) 253 { 254 255 } 256 257 static inline void usba_ep_cleanup_debugfs(struct usba_ep *ep) 258 { 259 260 } 261 262 static inline void usba_init_debugfs(struct usba_udc *udc) 263 { 264 265 } 266 267 static inline void usba_cleanup_debugfs(struct usba_udc *udc) 268 { 269 270 } 271 #endif 272 273 static ushort fifo_mode; 274 275 module_param(fifo_mode, ushort, 0x0); 276 MODULE_PARM_DESC(fifo_mode, "Endpoint configuration mode"); 277 278 /* mode 0 - uses autoconfig */ 279 280 /* mode 1 - fits in 8KB, generic max fifo configuration */ 281 static struct usba_fifo_cfg mode_1_cfg[] = { 282 { .hw_ep_num = 0, .fifo_size = 64, .nr_banks = 1, }, 283 { .hw_ep_num = 1, .fifo_size = 1024, .nr_banks = 2, }, 284 { .hw_ep_num = 2, .fifo_size = 1024, .nr_banks = 1, }, 285 { .hw_ep_num = 3, .fifo_size = 1024, .nr_banks = 1, }, 286 { .hw_ep_num = 4, .fifo_size = 1024, .nr_banks = 1, }, 287 { .hw_ep_num = 5, .fifo_size = 1024, .nr_banks = 1, }, 288 { .hw_ep_num = 6, .fifo_size = 1024, .nr_banks = 1, }, 289 }; 290 291 /* mode 2 - fits in 8KB, performance max fifo configuration */ 292 static struct usba_fifo_cfg mode_2_cfg[] = { 293 { .hw_ep_num = 0, .fifo_size = 64, .nr_banks = 1, }, 294 { .hw_ep_num = 1, .fifo_size = 1024, .nr_banks = 3, }, 295 { .hw_ep_num = 2, .fifo_size = 1024, .nr_banks = 2, }, 296 { .hw_ep_num = 3, .fifo_size = 1024, .nr_banks = 2, }, 297 }; 298 299 /* mode 3 - fits in 8KB, mixed fifo configuration */ 300 static struct usba_fifo_cfg mode_3_cfg[] = { 301 { .hw_ep_num = 0, .fifo_size = 64, .nr_banks = 1, }, 302 { .hw_ep_num = 1, .fifo_size = 1024, .nr_banks = 2, }, 303 { .hw_ep_num = 2, .fifo_size = 512, .nr_banks = 2, }, 304 { .hw_ep_num = 3, .fifo_size = 512, .nr_banks = 2, }, 305 { .hw_ep_num = 4, .fifo_size = 512, .nr_banks = 2, }, 306 { .hw_ep_num = 5, .fifo_size = 512, .nr_banks = 2, }, 307 { .hw_ep_num = 6, .fifo_size = 512, .nr_banks = 2, }, 308 }; 309 310 /* mode 4 - fits in 8KB, custom fifo configuration */ 311 static struct usba_fifo_cfg mode_4_cfg[] = { 312 { .hw_ep_num = 0, .fifo_size = 64, .nr_banks = 1, }, 313 { .hw_ep_num = 1, .fifo_size = 512, .nr_banks = 2, }, 314 { .hw_ep_num = 2, .fifo_size = 512, .nr_banks = 2, }, 315 { .hw_ep_num = 3, .fifo_size = 8, .nr_banks = 2, }, 316 { .hw_ep_num = 4, .fifo_size = 512, .nr_banks = 2, }, 317 { .hw_ep_num = 5, .fifo_size = 512, .nr_banks = 2, }, 318 { .hw_ep_num = 6, .fifo_size = 16, .nr_banks = 2, }, 319 { .hw_ep_num = 7, .fifo_size = 8, .nr_banks = 2, }, 320 { .hw_ep_num = 8, .fifo_size = 8, .nr_banks = 2, }, 321 }; 322 /* Add additional configurations here */ 323 324 static int usba_config_fifo_table(struct usba_udc *udc) 325 { 326 int n; 327 328 switch (fifo_mode) { 329 default: 330 fifo_mode = 0; 331 fallthrough; 332 case 0: 333 udc->fifo_cfg = NULL; 334 n = 0; 335 break; 336 case 1: 337 udc->fifo_cfg = mode_1_cfg; 338 n = ARRAY_SIZE(mode_1_cfg); 339 break; 340 case 2: 341 udc->fifo_cfg = mode_2_cfg; 342 n = ARRAY_SIZE(mode_2_cfg); 343 break; 344 case 3: 345 udc->fifo_cfg = mode_3_cfg; 346 n = ARRAY_SIZE(mode_3_cfg); 347 break; 348 case 4: 349 udc->fifo_cfg = mode_4_cfg; 350 n = ARRAY_SIZE(mode_4_cfg); 351 break; 352 } 353 DBG(DBG_HW, "Setup fifo_mode %d\n", fifo_mode); 354 355 return n; 356 } 357 358 static inline u32 usba_int_enb_get(struct usba_udc *udc) 359 { 360 return udc->int_enb_cache; 361 } 362 363 static inline void usba_int_enb_set(struct usba_udc *udc, u32 mask) 364 { 365 u32 val; 366 367 val = udc->int_enb_cache | mask; 368 usba_writel(udc, INT_ENB, val); 369 udc->int_enb_cache = val; 370 } 371 372 static inline void usba_int_enb_clear(struct usba_udc *udc, u32 mask) 373 { 374 u32 val; 375 376 val = udc->int_enb_cache & ~mask; 377 usba_writel(udc, INT_ENB, val); 378 udc->int_enb_cache = val; 379 } 380 381 static int vbus_is_present(struct usba_udc *udc) 382 { 383 if (udc->vbus_pin) 384 return gpiod_get_value(udc->vbus_pin); 385 386 /* No Vbus detection: Assume always present */ 387 return 1; 388 } 389 390 static void toggle_bias(struct usba_udc *udc, int is_on) 391 { 392 if (udc->errata && udc->errata->toggle_bias) 393 udc->errata->toggle_bias(udc, is_on); 394 } 395 396 static void generate_bias_pulse(struct usba_udc *udc) 397 { 398 if (!udc->bias_pulse_needed) 399 return; 400 401 if (udc->errata && udc->errata->pulse_bias) 402 udc->errata->pulse_bias(udc); 403 404 udc->bias_pulse_needed = false; 405 } 406 407 static void next_fifo_transaction(struct usba_ep *ep, struct usba_request *req) 408 { 409 unsigned int transaction_len; 410 411 transaction_len = req->req.length - req->req.actual; 412 req->last_transaction = 1; 413 if (transaction_len > ep->ep.maxpacket) { 414 transaction_len = ep->ep.maxpacket; 415 req->last_transaction = 0; 416 } else if (transaction_len == ep->ep.maxpacket && req->req.zero) 417 req->last_transaction = 0; 418 419 DBG(DBG_QUEUE, "%s: submit_transaction, req %p (length %d)%s\n", 420 ep->ep.name, req, transaction_len, 421 req->last_transaction ? ", done" : ""); 422 423 memcpy_toio(ep->fifo, req->req.buf + req->req.actual, transaction_len); 424 usba_ep_writel(ep, SET_STA, USBA_TX_PK_RDY); 425 req->req.actual += transaction_len; 426 } 427 428 static void submit_request(struct usba_ep *ep, struct usba_request *req) 429 { 430 DBG(DBG_QUEUE, "%s: submit_request: req %p (length %d)\n", 431 ep->ep.name, req, req->req.length); 432 433 req->req.actual = 0; 434 req->submitted = 1; 435 436 if (req->using_dma) { 437 if (req->req.length == 0) { 438 usba_ep_writel(ep, CTL_ENB, USBA_TX_PK_RDY); 439 return; 440 } 441 442 if (req->req.zero) 443 usba_ep_writel(ep, CTL_ENB, USBA_SHORT_PACKET); 444 else 445 usba_ep_writel(ep, CTL_DIS, USBA_SHORT_PACKET); 446 447 usba_dma_writel(ep, ADDRESS, req->req.dma); 448 usba_dma_writel(ep, CONTROL, req->ctrl); 449 } else { 450 next_fifo_transaction(ep, req); 451 if (req->last_transaction) { 452 usba_ep_writel(ep, CTL_DIS, USBA_TX_PK_RDY); 453 if (ep_is_control(ep)) 454 usba_ep_writel(ep, CTL_ENB, USBA_TX_COMPLETE); 455 } else { 456 if (ep_is_control(ep)) 457 usba_ep_writel(ep, CTL_DIS, USBA_TX_COMPLETE); 458 usba_ep_writel(ep, CTL_ENB, USBA_TX_PK_RDY); 459 } 460 } 461 } 462 463 static void submit_next_request(struct usba_ep *ep) 464 { 465 struct usba_request *req; 466 467 if (list_empty(&ep->queue)) { 468 usba_ep_writel(ep, CTL_DIS, USBA_TX_PK_RDY | USBA_RX_BK_RDY); 469 return; 470 } 471 472 req = list_entry(ep->queue.next, struct usba_request, queue); 473 if (!req->submitted) 474 submit_request(ep, req); 475 } 476 477 static void send_status(struct usba_udc *udc, struct usba_ep *ep) 478 { 479 ep->state = STATUS_STAGE_IN; 480 usba_ep_writel(ep, SET_STA, USBA_TX_PK_RDY); 481 usba_ep_writel(ep, CTL_ENB, USBA_TX_COMPLETE); 482 } 483 484 static void receive_data(struct usba_ep *ep) 485 { 486 struct usba_udc *udc = ep->udc; 487 struct usba_request *req; 488 unsigned long status; 489 unsigned int bytecount, nr_busy; 490 int is_complete = 0; 491 492 status = usba_ep_readl(ep, STA); 493 nr_busy = USBA_BFEXT(BUSY_BANKS, status); 494 495 DBG(DBG_QUEUE, "receive data: nr_busy=%u\n", nr_busy); 496 497 while (nr_busy > 0) { 498 if (list_empty(&ep->queue)) { 499 usba_ep_writel(ep, CTL_DIS, USBA_RX_BK_RDY); 500 break; 501 } 502 req = list_entry(ep->queue.next, 503 struct usba_request, queue); 504 505 bytecount = USBA_BFEXT(BYTE_COUNT, status); 506 507 if (status & (1 << 31)) 508 is_complete = 1; 509 if (req->req.actual + bytecount >= req->req.length) { 510 is_complete = 1; 511 bytecount = req->req.length - req->req.actual; 512 } 513 514 memcpy_fromio(req->req.buf + req->req.actual, 515 ep->fifo, bytecount); 516 req->req.actual += bytecount; 517 518 usba_ep_writel(ep, CLR_STA, USBA_RX_BK_RDY); 519 520 if (is_complete) { 521 DBG(DBG_QUEUE, "%s: request done\n", ep->ep.name); 522 req->req.status = 0; 523 list_del_init(&req->queue); 524 usba_ep_writel(ep, CTL_DIS, USBA_RX_BK_RDY); 525 spin_unlock(&udc->lock); 526 usb_gadget_giveback_request(&ep->ep, &req->req); 527 spin_lock(&udc->lock); 528 } 529 530 status = usba_ep_readl(ep, STA); 531 nr_busy = USBA_BFEXT(BUSY_BANKS, status); 532 533 if (is_complete && ep_is_control(ep)) { 534 send_status(udc, ep); 535 break; 536 } 537 } 538 } 539 540 static void 541 request_complete(struct usba_ep *ep, struct usba_request *req, int status) 542 { 543 struct usba_udc *udc = ep->udc; 544 545 WARN_ON(!list_empty(&req->queue)); 546 547 if (req->req.status == -EINPROGRESS) 548 req->req.status = status; 549 550 if (req->using_dma) 551 usb_gadget_unmap_request(&udc->gadget, &req->req, ep->is_in); 552 553 DBG(DBG_GADGET | DBG_REQ, 554 "%s: req %p complete: status %d, actual %u\n", 555 ep->ep.name, req, req->req.status, req->req.actual); 556 557 spin_unlock(&udc->lock); 558 usb_gadget_giveback_request(&ep->ep, &req->req); 559 spin_lock(&udc->lock); 560 } 561 562 static void 563 request_complete_list(struct usba_ep *ep, struct list_head *list, int status) 564 { 565 struct usba_request *req, *tmp_req; 566 567 list_for_each_entry_safe(req, tmp_req, list, queue) { 568 list_del_init(&req->queue); 569 request_complete(ep, req, status); 570 } 571 } 572 573 static int 574 usba_ep_enable(struct usb_ep *_ep, const struct usb_endpoint_descriptor *desc) 575 { 576 struct usba_ep *ep = to_usba_ep(_ep); 577 struct usba_udc *udc = ep->udc; 578 unsigned long flags, maxpacket; 579 unsigned int nr_trans; 580 581 DBG(DBG_GADGET, "%s: ep_enable: desc=%p\n", ep->ep.name, desc); 582 583 maxpacket = usb_endpoint_maxp(desc); 584 585 if (((desc->bEndpointAddress & USB_ENDPOINT_NUMBER_MASK) != ep->index) 586 || ep->index == 0 587 || desc->bDescriptorType != USB_DT_ENDPOINT 588 || maxpacket == 0 589 || maxpacket > ep->fifo_size) { 590 DBG(DBG_ERR, "ep_enable: Invalid argument"); 591 return -EINVAL; 592 } 593 594 ep->is_isoc = 0; 595 ep->is_in = 0; 596 597 DBG(DBG_ERR, "%s: EPT_CFG = 0x%lx (maxpacket = %lu)\n", 598 ep->ep.name, ep->ept_cfg, maxpacket); 599 600 if (usb_endpoint_dir_in(desc)) { 601 ep->is_in = 1; 602 ep->ept_cfg |= USBA_EPT_DIR_IN; 603 } 604 605 switch (usb_endpoint_type(desc)) { 606 case USB_ENDPOINT_XFER_CONTROL: 607 ep->ept_cfg |= USBA_BF(EPT_TYPE, USBA_EPT_TYPE_CONTROL); 608 break; 609 case USB_ENDPOINT_XFER_ISOC: 610 if (!ep->can_isoc) { 611 DBG(DBG_ERR, "ep_enable: %s is not isoc capable\n", 612 ep->ep.name); 613 return -EINVAL; 614 } 615 616 /* 617 * Bits 11:12 specify number of _additional_ 618 * transactions per microframe. 619 */ 620 nr_trans = usb_endpoint_maxp_mult(desc); 621 if (nr_trans > 3) 622 return -EINVAL; 623 624 ep->is_isoc = 1; 625 ep->ept_cfg |= USBA_BF(EPT_TYPE, USBA_EPT_TYPE_ISO); 626 ep->ept_cfg |= USBA_BF(NB_TRANS, nr_trans); 627 628 break; 629 case USB_ENDPOINT_XFER_BULK: 630 ep->ept_cfg |= USBA_BF(EPT_TYPE, USBA_EPT_TYPE_BULK); 631 break; 632 case USB_ENDPOINT_XFER_INT: 633 ep->ept_cfg |= USBA_BF(EPT_TYPE, USBA_EPT_TYPE_INT); 634 break; 635 } 636 637 spin_lock_irqsave(&ep->udc->lock, flags); 638 639 ep->ep.desc = desc; 640 ep->ep.maxpacket = maxpacket; 641 642 usba_ep_writel(ep, CFG, ep->ept_cfg); 643 usba_ep_writel(ep, CTL_ENB, USBA_EPT_ENABLE); 644 645 if (ep->can_dma) { 646 u32 ctrl; 647 648 usba_int_enb_set(udc, USBA_BF(EPT_INT, 1 << ep->index) | 649 USBA_BF(DMA_INT, 1 << ep->index)); 650 ctrl = USBA_AUTO_VALID | USBA_INTDIS_DMA; 651 usba_ep_writel(ep, CTL_ENB, ctrl); 652 } else { 653 usba_int_enb_set(udc, USBA_BF(EPT_INT, 1 << ep->index)); 654 } 655 656 spin_unlock_irqrestore(&udc->lock, flags); 657 658 DBG(DBG_HW, "EPT_CFG%d after init: %#08lx\n", ep->index, 659 (unsigned long)usba_ep_readl(ep, CFG)); 660 DBG(DBG_HW, "INT_ENB after init: %#08lx\n", 661 (unsigned long)usba_int_enb_get(udc)); 662 663 return 0; 664 } 665 666 static int usba_ep_disable(struct usb_ep *_ep) 667 { 668 struct usba_ep *ep = to_usba_ep(_ep); 669 struct usba_udc *udc = ep->udc; 670 LIST_HEAD(req_list); 671 unsigned long flags; 672 673 DBG(DBG_GADGET, "ep_disable: %s\n", ep->ep.name); 674 675 spin_lock_irqsave(&udc->lock, flags); 676 677 if (!ep->ep.desc) { 678 spin_unlock_irqrestore(&udc->lock, flags); 679 DBG(DBG_ERR, "ep_disable: %s not enabled\n", ep->ep.name); 680 return -EINVAL; 681 } 682 ep->ep.desc = NULL; 683 684 list_splice_init(&ep->queue, &req_list); 685 if (ep->can_dma) { 686 usba_dma_writel(ep, CONTROL, 0); 687 usba_dma_writel(ep, ADDRESS, 0); 688 usba_dma_readl(ep, STATUS); 689 } 690 usba_ep_writel(ep, CTL_DIS, USBA_EPT_ENABLE); 691 usba_int_enb_clear(udc, USBA_BF(EPT_INT, 1 << ep->index)); 692 693 request_complete_list(ep, &req_list, -ESHUTDOWN); 694 695 spin_unlock_irqrestore(&udc->lock, flags); 696 697 return 0; 698 } 699 700 static struct usb_request * 701 usba_ep_alloc_request(struct usb_ep *_ep, gfp_t gfp_flags) 702 { 703 struct usba_request *req; 704 705 DBG(DBG_GADGET, "ep_alloc_request: %p, 0x%x\n", _ep, gfp_flags); 706 707 req = kzalloc(sizeof(*req), gfp_flags); 708 if (!req) 709 return NULL; 710 711 INIT_LIST_HEAD(&req->queue); 712 713 return &req->req; 714 } 715 716 static void 717 usba_ep_free_request(struct usb_ep *_ep, struct usb_request *_req) 718 { 719 struct usba_request *req = to_usba_req(_req); 720 721 DBG(DBG_GADGET, "ep_free_request: %p, %p\n", _ep, _req); 722 723 kfree(req); 724 } 725 726 static int queue_dma(struct usba_udc *udc, struct usba_ep *ep, 727 struct usba_request *req, gfp_t gfp_flags) 728 { 729 unsigned long flags; 730 int ret; 731 732 DBG(DBG_DMA, "%s: req l/%u d/%pad %c%c%c\n", 733 ep->ep.name, req->req.length, &req->req.dma, 734 req->req.zero ? 'Z' : 'z', 735 req->req.short_not_ok ? 'S' : 's', 736 req->req.no_interrupt ? 'I' : 'i'); 737 738 if (req->req.length > 0x10000) { 739 /* Lengths from 0 to 65536 (inclusive) are supported */ 740 DBG(DBG_ERR, "invalid request length %u\n", req->req.length); 741 return -EINVAL; 742 } 743 744 ret = usb_gadget_map_request(&udc->gadget, &req->req, ep->is_in); 745 if (ret) 746 return ret; 747 748 req->using_dma = 1; 749 req->ctrl = USBA_BF(DMA_BUF_LEN, req->req.length) 750 | USBA_DMA_CH_EN | USBA_DMA_END_BUF_IE 751 | USBA_DMA_END_BUF_EN; 752 753 if (!ep->is_in) 754 req->ctrl |= USBA_DMA_END_TR_EN | USBA_DMA_END_TR_IE; 755 756 /* 757 * Add this request to the queue and submit for DMA if 758 * possible. Check if we're still alive first -- we may have 759 * received a reset since last time we checked. 760 */ 761 ret = -ESHUTDOWN; 762 spin_lock_irqsave(&udc->lock, flags); 763 if (ep->ep.desc) { 764 if (list_empty(&ep->queue)) 765 submit_request(ep, req); 766 767 list_add_tail(&req->queue, &ep->queue); 768 ret = 0; 769 } 770 spin_unlock_irqrestore(&udc->lock, flags); 771 772 return ret; 773 } 774 775 static int 776 usba_ep_queue(struct usb_ep *_ep, struct usb_request *_req, gfp_t gfp_flags) 777 { 778 struct usba_request *req = to_usba_req(_req); 779 struct usba_ep *ep = to_usba_ep(_ep); 780 struct usba_udc *udc = ep->udc; 781 unsigned long flags; 782 int ret; 783 784 DBG(DBG_GADGET | DBG_QUEUE | DBG_REQ, "%s: queue req %p, len %u\n", 785 ep->ep.name, req, _req->length); 786 787 if (!udc->driver || udc->gadget.speed == USB_SPEED_UNKNOWN || 788 !ep->ep.desc) 789 return -ESHUTDOWN; 790 791 req->submitted = 0; 792 req->using_dma = 0; 793 req->last_transaction = 0; 794 795 _req->status = -EINPROGRESS; 796 _req->actual = 0; 797 798 if (ep->can_dma) 799 return queue_dma(udc, ep, req, gfp_flags); 800 801 /* May have received a reset since last time we checked */ 802 ret = -ESHUTDOWN; 803 spin_lock_irqsave(&udc->lock, flags); 804 if (ep->ep.desc) { 805 list_add_tail(&req->queue, &ep->queue); 806 807 if ((!ep_is_control(ep) && ep->is_in) || 808 (ep_is_control(ep) 809 && (ep->state == DATA_STAGE_IN 810 || ep->state == STATUS_STAGE_IN))) 811 usba_ep_writel(ep, CTL_ENB, USBA_TX_PK_RDY); 812 else 813 usba_ep_writel(ep, CTL_ENB, USBA_RX_BK_RDY); 814 ret = 0; 815 } 816 spin_unlock_irqrestore(&udc->lock, flags); 817 818 return ret; 819 } 820 821 static void 822 usba_update_req(struct usba_ep *ep, struct usba_request *req, u32 status) 823 { 824 req->req.actual = req->req.length - USBA_BFEXT(DMA_BUF_LEN, status); 825 } 826 827 static int stop_dma(struct usba_ep *ep, u32 *pstatus) 828 { 829 unsigned int timeout; 830 u32 status; 831 832 /* 833 * Stop the DMA controller. When writing both CH_EN 834 * and LINK to 0, the other bits are not affected. 835 */ 836 usba_dma_writel(ep, CONTROL, 0); 837 838 /* Wait for the FIFO to empty */ 839 for (timeout = 40; timeout; --timeout) { 840 status = usba_dma_readl(ep, STATUS); 841 if (!(status & USBA_DMA_CH_EN)) 842 break; 843 udelay(1); 844 } 845 846 if (pstatus) 847 *pstatus = status; 848 849 if (timeout == 0) { 850 dev_err(&ep->udc->pdev->dev, 851 "%s: timed out waiting for DMA FIFO to empty\n", 852 ep->ep.name); 853 return -ETIMEDOUT; 854 } 855 856 return 0; 857 } 858 859 static int usba_ep_dequeue(struct usb_ep *_ep, struct usb_request *_req) 860 { 861 struct usba_ep *ep = to_usba_ep(_ep); 862 struct usba_udc *udc = ep->udc; 863 struct usba_request *req; 864 unsigned long flags; 865 u32 status; 866 867 DBG(DBG_GADGET | DBG_QUEUE, "ep_dequeue: %s, req %p\n", 868 ep->ep.name, _req); 869 870 spin_lock_irqsave(&udc->lock, flags); 871 872 list_for_each_entry(req, &ep->queue, queue) { 873 if (&req->req == _req) 874 break; 875 } 876 877 if (&req->req != _req) { 878 spin_unlock_irqrestore(&udc->lock, flags); 879 return -EINVAL; 880 } 881 882 if (req->using_dma) { 883 /* 884 * If this request is currently being transferred, 885 * stop the DMA controller and reset the FIFO. 886 */ 887 if (ep->queue.next == &req->queue) { 888 status = usba_dma_readl(ep, STATUS); 889 if (status & USBA_DMA_CH_EN) 890 stop_dma(ep, &status); 891 892 #ifdef CONFIG_USB_GADGET_DEBUG_FS 893 ep->last_dma_status = status; 894 #endif 895 896 usba_writel(udc, EPT_RST, 1 << ep->index); 897 898 usba_update_req(ep, req, status); 899 } 900 } 901 902 /* 903 * Errors should stop the queue from advancing until the 904 * completion function returns. 905 */ 906 list_del_init(&req->queue); 907 908 request_complete(ep, req, -ECONNRESET); 909 910 /* Process the next request if any */ 911 submit_next_request(ep); 912 spin_unlock_irqrestore(&udc->lock, flags); 913 914 return 0; 915 } 916 917 static int usba_ep_set_halt(struct usb_ep *_ep, int value) 918 { 919 struct usba_ep *ep = to_usba_ep(_ep); 920 struct usba_udc *udc = ep->udc; 921 unsigned long flags; 922 int ret = 0; 923 924 DBG(DBG_GADGET, "endpoint %s: %s HALT\n", ep->ep.name, 925 value ? "set" : "clear"); 926 927 if (!ep->ep.desc) { 928 DBG(DBG_ERR, "Attempted to halt uninitialized ep %s\n", 929 ep->ep.name); 930 return -ENODEV; 931 } 932 if (ep->is_isoc) { 933 DBG(DBG_ERR, "Attempted to halt isochronous ep %s\n", 934 ep->ep.name); 935 return -ENOTTY; 936 } 937 938 spin_lock_irqsave(&udc->lock, flags); 939 940 /* 941 * We can't halt IN endpoints while there are still data to be 942 * transferred 943 */ 944 if (!list_empty(&ep->queue) 945 || ((value && ep->is_in && (usba_ep_readl(ep, STA) 946 & USBA_BF(BUSY_BANKS, -1L))))) { 947 ret = -EAGAIN; 948 } else { 949 if (value) 950 usba_ep_writel(ep, SET_STA, USBA_FORCE_STALL); 951 else 952 usba_ep_writel(ep, CLR_STA, 953 USBA_FORCE_STALL | USBA_TOGGLE_CLR); 954 usba_ep_readl(ep, STA); 955 } 956 957 spin_unlock_irqrestore(&udc->lock, flags); 958 959 return ret; 960 } 961 962 static int usba_ep_fifo_status(struct usb_ep *_ep) 963 { 964 struct usba_ep *ep = to_usba_ep(_ep); 965 966 return USBA_BFEXT(BYTE_COUNT, usba_ep_readl(ep, STA)); 967 } 968 969 static void usba_ep_fifo_flush(struct usb_ep *_ep) 970 { 971 struct usba_ep *ep = to_usba_ep(_ep); 972 struct usba_udc *udc = ep->udc; 973 974 usba_writel(udc, EPT_RST, 1 << ep->index); 975 } 976 977 static const struct usb_ep_ops usba_ep_ops = { 978 .enable = usba_ep_enable, 979 .disable = usba_ep_disable, 980 .alloc_request = usba_ep_alloc_request, 981 .free_request = usba_ep_free_request, 982 .queue = usba_ep_queue, 983 .dequeue = usba_ep_dequeue, 984 .set_halt = usba_ep_set_halt, 985 .fifo_status = usba_ep_fifo_status, 986 .fifo_flush = usba_ep_fifo_flush, 987 }; 988 989 static int usba_udc_get_frame(struct usb_gadget *gadget) 990 { 991 struct usba_udc *udc = to_usba_udc(gadget); 992 993 return USBA_BFEXT(FRAME_NUMBER, usba_readl(udc, FNUM)); 994 } 995 996 static int usba_udc_wakeup(struct usb_gadget *gadget) 997 { 998 struct usba_udc *udc = to_usba_udc(gadget); 999 unsigned long flags; 1000 u32 ctrl; 1001 int ret = -EINVAL; 1002 1003 spin_lock_irqsave(&udc->lock, flags); 1004 if (udc->devstatus & (1 << USB_DEVICE_REMOTE_WAKEUP)) { 1005 ctrl = usba_readl(udc, CTRL); 1006 usba_writel(udc, CTRL, ctrl | USBA_REMOTE_WAKE_UP); 1007 ret = 0; 1008 } 1009 spin_unlock_irqrestore(&udc->lock, flags); 1010 1011 return ret; 1012 } 1013 1014 static int 1015 usba_udc_set_selfpowered(struct usb_gadget *gadget, int is_selfpowered) 1016 { 1017 struct usba_udc *udc = to_usba_udc(gadget); 1018 unsigned long flags; 1019 1020 gadget->is_selfpowered = (is_selfpowered != 0); 1021 spin_lock_irqsave(&udc->lock, flags); 1022 if (is_selfpowered) 1023 udc->devstatus |= 1 << USB_DEVICE_SELF_POWERED; 1024 else 1025 udc->devstatus &= ~(1 << USB_DEVICE_SELF_POWERED); 1026 spin_unlock_irqrestore(&udc->lock, flags); 1027 1028 return 0; 1029 } 1030 1031 static int atmel_usba_pullup(struct usb_gadget *gadget, int is_on); 1032 static int atmel_usba_start(struct usb_gadget *gadget, 1033 struct usb_gadget_driver *driver); 1034 static int atmel_usba_stop(struct usb_gadget *gadget); 1035 1036 static struct usb_ep *atmel_usba_match_ep(struct usb_gadget *gadget, 1037 struct usb_endpoint_descriptor *desc, 1038 struct usb_ss_ep_comp_descriptor *ep_comp) 1039 { 1040 struct usb_ep *_ep; 1041 struct usba_ep *ep; 1042 1043 /* Look at endpoints until an unclaimed one looks usable */ 1044 list_for_each_entry(_ep, &gadget->ep_list, ep_list) { 1045 if (usb_gadget_ep_match_desc(gadget, _ep, desc, ep_comp)) 1046 goto found_ep; 1047 } 1048 /* Fail */ 1049 return NULL; 1050 1051 found_ep: 1052 1053 if (fifo_mode == 0) { 1054 /* Optimize hw fifo size based on ep type and other info */ 1055 ep = to_usba_ep(_ep); 1056 1057 switch (usb_endpoint_type(desc)) { 1058 case USB_ENDPOINT_XFER_CONTROL: 1059 ep->nr_banks = 1; 1060 break; 1061 1062 case USB_ENDPOINT_XFER_ISOC: 1063 ep->fifo_size = 1024; 1064 if (ep->udc->ep_prealloc) 1065 ep->nr_banks = 2; 1066 break; 1067 1068 case USB_ENDPOINT_XFER_BULK: 1069 ep->fifo_size = 512; 1070 if (ep->udc->ep_prealloc) 1071 ep->nr_banks = 1; 1072 break; 1073 1074 case USB_ENDPOINT_XFER_INT: 1075 if (desc->wMaxPacketSize == 0) 1076 ep->fifo_size = 1077 roundup_pow_of_two(_ep->maxpacket_limit); 1078 else 1079 ep->fifo_size = 1080 roundup_pow_of_two(le16_to_cpu(desc->wMaxPacketSize)); 1081 if (ep->udc->ep_prealloc) 1082 ep->nr_banks = 1; 1083 break; 1084 } 1085 1086 /* It might be a little bit late to set this */ 1087 usb_ep_set_maxpacket_limit(&ep->ep, ep->fifo_size); 1088 1089 /* Generate ept_cfg basd on FIFO size and number of banks */ 1090 if (ep->fifo_size <= 8) 1091 ep->ept_cfg = USBA_BF(EPT_SIZE, USBA_EPT_SIZE_8); 1092 else 1093 /* LSB is bit 1, not 0 */ 1094 ep->ept_cfg = 1095 USBA_BF(EPT_SIZE, fls(ep->fifo_size - 1) - 3); 1096 1097 ep->ept_cfg |= USBA_BF(BK_NUMBER, ep->nr_banks); 1098 } 1099 1100 return _ep; 1101 } 1102 1103 static const struct usb_gadget_ops usba_udc_ops = { 1104 .get_frame = usba_udc_get_frame, 1105 .wakeup = usba_udc_wakeup, 1106 .set_selfpowered = usba_udc_set_selfpowered, 1107 .pullup = atmel_usba_pullup, 1108 .udc_start = atmel_usba_start, 1109 .udc_stop = atmel_usba_stop, 1110 .match_ep = atmel_usba_match_ep, 1111 }; 1112 1113 static struct usb_endpoint_descriptor usba_ep0_desc = { 1114 .bLength = USB_DT_ENDPOINT_SIZE, 1115 .bDescriptorType = USB_DT_ENDPOINT, 1116 .bEndpointAddress = 0, 1117 .bmAttributes = USB_ENDPOINT_XFER_CONTROL, 1118 .wMaxPacketSize = cpu_to_le16(64), 1119 /* FIXME: I have no idea what to put here */ 1120 .bInterval = 1, 1121 }; 1122 1123 static const struct usb_gadget usba_gadget_template = { 1124 .ops = &usba_udc_ops, 1125 .max_speed = USB_SPEED_HIGH, 1126 .name = "atmel_usba_udc", 1127 }; 1128 1129 /* 1130 * Called with interrupts disabled and udc->lock held. 1131 */ 1132 static void reset_all_endpoints(struct usba_udc *udc) 1133 { 1134 struct usba_ep *ep; 1135 struct usba_request *req, *tmp_req; 1136 1137 usba_writel(udc, EPT_RST, ~0UL); 1138 1139 ep = to_usba_ep(udc->gadget.ep0); 1140 list_for_each_entry_safe(req, tmp_req, &ep->queue, queue) { 1141 list_del_init(&req->queue); 1142 request_complete(ep, req, -ECONNRESET); 1143 } 1144 } 1145 1146 static struct usba_ep *get_ep_by_addr(struct usba_udc *udc, u16 wIndex) 1147 { 1148 struct usba_ep *ep; 1149 1150 if ((wIndex & USB_ENDPOINT_NUMBER_MASK) == 0) 1151 return to_usba_ep(udc->gadget.ep0); 1152 1153 list_for_each_entry (ep, &udc->gadget.ep_list, ep.ep_list) { 1154 u8 bEndpointAddress; 1155 1156 if (!ep->ep.desc) 1157 continue; 1158 bEndpointAddress = ep->ep.desc->bEndpointAddress; 1159 if ((wIndex ^ bEndpointAddress) & USB_DIR_IN) 1160 continue; 1161 if ((bEndpointAddress & USB_ENDPOINT_NUMBER_MASK) 1162 == (wIndex & USB_ENDPOINT_NUMBER_MASK)) 1163 return ep; 1164 } 1165 1166 return NULL; 1167 } 1168 1169 /* Called with interrupts disabled and udc->lock held */ 1170 static inline void set_protocol_stall(struct usba_udc *udc, struct usba_ep *ep) 1171 { 1172 usba_ep_writel(ep, SET_STA, USBA_FORCE_STALL); 1173 ep->state = WAIT_FOR_SETUP; 1174 } 1175 1176 static inline int is_stalled(struct usba_udc *udc, struct usba_ep *ep) 1177 { 1178 if (usba_ep_readl(ep, STA) & USBA_FORCE_STALL) 1179 return 1; 1180 return 0; 1181 } 1182 1183 static inline void set_address(struct usba_udc *udc, unsigned int addr) 1184 { 1185 u32 regval; 1186 1187 DBG(DBG_BUS, "setting address %u...\n", addr); 1188 regval = usba_readl(udc, CTRL); 1189 regval = USBA_BFINS(DEV_ADDR, addr, regval); 1190 usba_writel(udc, CTRL, regval); 1191 } 1192 1193 static int do_test_mode(struct usba_udc *udc) 1194 { 1195 static const char test_packet_buffer[] = { 1196 /* JKJKJKJK * 9 */ 1197 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 1198 /* JJKKJJKK * 8 */ 1199 0xAA, 0xAA, 0xAA, 0xAA, 0xAA, 0xAA, 0xAA, 0xAA, 1200 /* JJKKJJKK * 8 */ 1201 0xEE, 0xEE, 0xEE, 0xEE, 0xEE, 0xEE, 0xEE, 0xEE, 1202 /* JJJJJJJKKKKKKK * 8 */ 1203 0xFE, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 1204 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 1205 /* JJJJJJJK * 8 */ 1206 0x7F, 0xBF, 0xDF, 0xEF, 0xF7, 0xFB, 0xFD, 1207 /* {JKKKKKKK * 10}, JK */ 1208 0xFC, 0x7E, 0xBF, 0xDF, 0xEF, 0xF7, 0xFB, 0xFD, 0x7E 1209 }; 1210 struct usba_ep *ep; 1211 struct device *dev = &udc->pdev->dev; 1212 int test_mode; 1213 1214 test_mode = udc->test_mode; 1215 1216 /* Start from a clean slate */ 1217 reset_all_endpoints(udc); 1218 1219 switch (test_mode) { 1220 case 0x0100: 1221 /* Test_J */ 1222 usba_writel(udc, TST, USBA_TST_J_MODE); 1223 dev_info(dev, "Entering Test_J mode...\n"); 1224 break; 1225 case 0x0200: 1226 /* Test_K */ 1227 usba_writel(udc, TST, USBA_TST_K_MODE); 1228 dev_info(dev, "Entering Test_K mode...\n"); 1229 break; 1230 case 0x0300: 1231 /* 1232 * Test_SE0_NAK: Force high-speed mode and set up ep0 1233 * for Bulk IN transfers 1234 */ 1235 ep = &udc->usba_ep[0]; 1236 usba_writel(udc, TST, 1237 USBA_BF(SPEED_CFG, USBA_SPEED_CFG_FORCE_HIGH)); 1238 usba_ep_writel(ep, CFG, 1239 USBA_BF(EPT_SIZE, USBA_EPT_SIZE_64) 1240 | USBA_EPT_DIR_IN 1241 | USBA_BF(EPT_TYPE, USBA_EPT_TYPE_BULK) 1242 | USBA_BF(BK_NUMBER, 1)); 1243 if (!(usba_ep_readl(ep, CFG) & USBA_EPT_MAPPED)) { 1244 set_protocol_stall(udc, ep); 1245 dev_err(dev, "Test_SE0_NAK: ep0 not mapped\n"); 1246 } else { 1247 usba_ep_writel(ep, CTL_ENB, USBA_EPT_ENABLE); 1248 dev_info(dev, "Entering Test_SE0_NAK mode...\n"); 1249 } 1250 break; 1251 case 0x0400: 1252 /* Test_Packet */ 1253 ep = &udc->usba_ep[0]; 1254 usba_ep_writel(ep, CFG, 1255 USBA_BF(EPT_SIZE, USBA_EPT_SIZE_64) 1256 | USBA_EPT_DIR_IN 1257 | USBA_BF(EPT_TYPE, USBA_EPT_TYPE_BULK) 1258 | USBA_BF(BK_NUMBER, 1)); 1259 if (!(usba_ep_readl(ep, CFG) & USBA_EPT_MAPPED)) { 1260 set_protocol_stall(udc, ep); 1261 dev_err(dev, "Test_Packet: ep0 not mapped\n"); 1262 } else { 1263 usba_ep_writel(ep, CTL_ENB, USBA_EPT_ENABLE); 1264 usba_writel(udc, TST, USBA_TST_PKT_MODE); 1265 memcpy_toio(ep->fifo, test_packet_buffer, 1266 sizeof(test_packet_buffer)); 1267 usba_ep_writel(ep, SET_STA, USBA_TX_PK_RDY); 1268 dev_info(dev, "Entering Test_Packet mode...\n"); 1269 } 1270 break; 1271 default: 1272 dev_err(dev, "Invalid test mode: 0x%04x\n", test_mode); 1273 return -EINVAL; 1274 } 1275 1276 return 0; 1277 } 1278 1279 /* Avoid overly long expressions */ 1280 static inline bool feature_is_dev_remote_wakeup(struct usb_ctrlrequest *crq) 1281 { 1282 if (crq->wValue == cpu_to_le16(USB_DEVICE_REMOTE_WAKEUP)) 1283 return true; 1284 return false; 1285 } 1286 1287 static inline bool feature_is_dev_test_mode(struct usb_ctrlrequest *crq) 1288 { 1289 if (crq->wValue == cpu_to_le16(USB_DEVICE_TEST_MODE)) 1290 return true; 1291 return false; 1292 } 1293 1294 static inline bool feature_is_ep_halt(struct usb_ctrlrequest *crq) 1295 { 1296 if (crq->wValue == cpu_to_le16(USB_ENDPOINT_HALT)) 1297 return true; 1298 return false; 1299 } 1300 1301 static int handle_ep0_setup(struct usba_udc *udc, struct usba_ep *ep, 1302 struct usb_ctrlrequest *crq) 1303 { 1304 int retval = 0; 1305 1306 switch (crq->bRequest) { 1307 case USB_REQ_GET_STATUS: { 1308 u16 status; 1309 1310 if (crq->bRequestType == (USB_DIR_IN | USB_RECIP_DEVICE)) { 1311 status = cpu_to_le16(udc->devstatus); 1312 } else if (crq->bRequestType 1313 == (USB_DIR_IN | USB_RECIP_INTERFACE)) { 1314 status = cpu_to_le16(0); 1315 } else if (crq->bRequestType 1316 == (USB_DIR_IN | USB_RECIP_ENDPOINT)) { 1317 struct usba_ep *target; 1318 1319 target = get_ep_by_addr(udc, le16_to_cpu(crq->wIndex)); 1320 if (!target) 1321 goto stall; 1322 1323 status = 0; 1324 if (is_stalled(udc, target)) 1325 status |= cpu_to_le16(1); 1326 } else 1327 goto delegate; 1328 1329 /* Write directly to the FIFO. No queueing is done. */ 1330 if (crq->wLength != cpu_to_le16(sizeof(status))) 1331 goto stall; 1332 ep->state = DATA_STAGE_IN; 1333 writew_relaxed(status, ep->fifo); 1334 usba_ep_writel(ep, SET_STA, USBA_TX_PK_RDY); 1335 break; 1336 } 1337 1338 case USB_REQ_CLEAR_FEATURE: { 1339 if (crq->bRequestType == USB_RECIP_DEVICE) { 1340 if (feature_is_dev_remote_wakeup(crq)) 1341 udc->devstatus 1342 &= ~(1 << USB_DEVICE_REMOTE_WAKEUP); 1343 else 1344 /* Can't CLEAR_FEATURE TEST_MODE */ 1345 goto stall; 1346 } else if (crq->bRequestType == USB_RECIP_ENDPOINT) { 1347 struct usba_ep *target; 1348 1349 if (crq->wLength != cpu_to_le16(0) 1350 || !feature_is_ep_halt(crq)) 1351 goto stall; 1352 target = get_ep_by_addr(udc, le16_to_cpu(crq->wIndex)); 1353 if (!target) 1354 goto stall; 1355 1356 usba_ep_writel(target, CLR_STA, USBA_FORCE_STALL); 1357 if (target->index != 0) 1358 usba_ep_writel(target, CLR_STA, 1359 USBA_TOGGLE_CLR); 1360 } else { 1361 goto delegate; 1362 } 1363 1364 send_status(udc, ep); 1365 break; 1366 } 1367 1368 case USB_REQ_SET_FEATURE: { 1369 if (crq->bRequestType == USB_RECIP_DEVICE) { 1370 if (feature_is_dev_test_mode(crq)) { 1371 send_status(udc, ep); 1372 ep->state = STATUS_STAGE_TEST; 1373 udc->test_mode = le16_to_cpu(crq->wIndex); 1374 return 0; 1375 } else if (feature_is_dev_remote_wakeup(crq)) { 1376 udc->devstatus |= 1 << USB_DEVICE_REMOTE_WAKEUP; 1377 } else { 1378 goto stall; 1379 } 1380 } else if (crq->bRequestType == USB_RECIP_ENDPOINT) { 1381 struct usba_ep *target; 1382 1383 if (crq->wLength != cpu_to_le16(0) 1384 || !feature_is_ep_halt(crq)) 1385 goto stall; 1386 1387 target = get_ep_by_addr(udc, le16_to_cpu(crq->wIndex)); 1388 if (!target) 1389 goto stall; 1390 1391 usba_ep_writel(target, SET_STA, USBA_FORCE_STALL); 1392 } else 1393 goto delegate; 1394 1395 send_status(udc, ep); 1396 break; 1397 } 1398 1399 case USB_REQ_SET_ADDRESS: 1400 if (crq->bRequestType != (USB_DIR_OUT | USB_RECIP_DEVICE)) 1401 goto delegate; 1402 1403 set_address(udc, le16_to_cpu(crq->wValue)); 1404 send_status(udc, ep); 1405 ep->state = STATUS_STAGE_ADDR; 1406 break; 1407 1408 default: 1409 delegate: 1410 spin_unlock(&udc->lock); 1411 retval = udc->driver->setup(&udc->gadget, crq); 1412 spin_lock(&udc->lock); 1413 } 1414 1415 return retval; 1416 1417 stall: 1418 pr_err("udc: %s: Invalid setup request: %02x.%02x v%04x i%04x l%d, " 1419 "halting endpoint...\n", 1420 ep->ep.name, crq->bRequestType, crq->bRequest, 1421 le16_to_cpu(crq->wValue), le16_to_cpu(crq->wIndex), 1422 le16_to_cpu(crq->wLength)); 1423 set_protocol_stall(udc, ep); 1424 return -1; 1425 } 1426 1427 static void usba_control_irq(struct usba_udc *udc, struct usba_ep *ep) 1428 { 1429 struct usba_request *req; 1430 u32 epstatus; 1431 u32 epctrl; 1432 1433 restart: 1434 epstatus = usba_ep_readl(ep, STA); 1435 epctrl = usba_ep_readl(ep, CTL); 1436 1437 DBG(DBG_INT, "%s [%d]: s/%08x c/%08x\n", 1438 ep->ep.name, ep->state, epstatus, epctrl); 1439 1440 req = NULL; 1441 if (!list_empty(&ep->queue)) 1442 req = list_entry(ep->queue.next, 1443 struct usba_request, queue); 1444 1445 if ((epctrl & USBA_TX_PK_RDY) && !(epstatus & USBA_TX_PK_RDY)) { 1446 if (req->submitted) 1447 next_fifo_transaction(ep, req); 1448 else 1449 submit_request(ep, req); 1450 1451 if (req->last_transaction) { 1452 usba_ep_writel(ep, CTL_DIS, USBA_TX_PK_RDY); 1453 usba_ep_writel(ep, CTL_ENB, USBA_TX_COMPLETE); 1454 } 1455 goto restart; 1456 } 1457 if ((epstatus & epctrl) & USBA_TX_COMPLETE) { 1458 usba_ep_writel(ep, CLR_STA, USBA_TX_COMPLETE); 1459 1460 switch (ep->state) { 1461 case DATA_STAGE_IN: 1462 usba_ep_writel(ep, CTL_ENB, USBA_RX_BK_RDY); 1463 usba_ep_writel(ep, CTL_DIS, USBA_TX_COMPLETE); 1464 ep->state = STATUS_STAGE_OUT; 1465 break; 1466 case STATUS_STAGE_ADDR: 1467 /* Activate our new address */ 1468 usba_writel(udc, CTRL, (usba_readl(udc, CTRL) 1469 | USBA_FADDR_EN)); 1470 usba_ep_writel(ep, CTL_DIS, USBA_TX_COMPLETE); 1471 ep->state = WAIT_FOR_SETUP; 1472 break; 1473 case STATUS_STAGE_IN: 1474 if (req) { 1475 list_del_init(&req->queue); 1476 request_complete(ep, req, 0); 1477 submit_next_request(ep); 1478 } 1479 usba_ep_writel(ep, CTL_DIS, USBA_TX_COMPLETE); 1480 ep->state = WAIT_FOR_SETUP; 1481 break; 1482 case STATUS_STAGE_TEST: 1483 usba_ep_writel(ep, CTL_DIS, USBA_TX_COMPLETE); 1484 ep->state = WAIT_FOR_SETUP; 1485 if (do_test_mode(udc)) 1486 set_protocol_stall(udc, ep); 1487 break; 1488 default: 1489 pr_err("udc: %s: TXCOMP: Invalid endpoint state %d, " 1490 "halting endpoint...\n", 1491 ep->ep.name, ep->state); 1492 set_protocol_stall(udc, ep); 1493 break; 1494 } 1495 1496 goto restart; 1497 } 1498 if ((epstatus & epctrl) & USBA_RX_BK_RDY) { 1499 switch (ep->state) { 1500 case STATUS_STAGE_OUT: 1501 usba_ep_writel(ep, CLR_STA, USBA_RX_BK_RDY); 1502 usba_ep_writel(ep, CTL_DIS, USBA_RX_BK_RDY); 1503 1504 if (req) { 1505 list_del_init(&req->queue); 1506 request_complete(ep, req, 0); 1507 } 1508 ep->state = WAIT_FOR_SETUP; 1509 break; 1510 1511 case DATA_STAGE_OUT: 1512 receive_data(ep); 1513 break; 1514 1515 default: 1516 usba_ep_writel(ep, CLR_STA, USBA_RX_BK_RDY); 1517 usba_ep_writel(ep, CTL_DIS, USBA_RX_BK_RDY); 1518 pr_err("udc: %s: RXRDY: Invalid endpoint state %d, " 1519 "halting endpoint...\n", 1520 ep->ep.name, ep->state); 1521 set_protocol_stall(udc, ep); 1522 break; 1523 } 1524 1525 goto restart; 1526 } 1527 if (epstatus & USBA_RX_SETUP) { 1528 union { 1529 struct usb_ctrlrequest crq; 1530 unsigned long data[2]; 1531 } crq; 1532 unsigned int pkt_len; 1533 int ret; 1534 1535 if (ep->state != WAIT_FOR_SETUP) { 1536 /* 1537 * Didn't expect a SETUP packet at this 1538 * point. Clean up any pending requests (which 1539 * may be successful). 1540 */ 1541 int status = -EPROTO; 1542 1543 /* 1544 * RXRDY and TXCOMP are dropped when SETUP 1545 * packets arrive. Just pretend we received 1546 * the status packet. 1547 */ 1548 if (ep->state == STATUS_STAGE_OUT 1549 || ep->state == STATUS_STAGE_IN) { 1550 usba_ep_writel(ep, CTL_DIS, USBA_RX_BK_RDY); 1551 status = 0; 1552 } 1553 1554 if (req) { 1555 list_del_init(&req->queue); 1556 request_complete(ep, req, status); 1557 } 1558 } 1559 1560 pkt_len = USBA_BFEXT(BYTE_COUNT, usba_ep_readl(ep, STA)); 1561 DBG(DBG_HW, "Packet length: %u\n", pkt_len); 1562 if (pkt_len != sizeof(crq)) { 1563 pr_warn("udc: Invalid packet length %u (expected %zu)\n", 1564 pkt_len, sizeof(crq)); 1565 set_protocol_stall(udc, ep); 1566 return; 1567 } 1568 1569 DBG(DBG_FIFO, "Copying ctrl request from 0x%p:\n", ep->fifo); 1570 memcpy_fromio(crq.data, ep->fifo, sizeof(crq)); 1571 1572 /* Free up one bank in the FIFO so that we can 1573 * generate or receive a reply right away. */ 1574 usba_ep_writel(ep, CLR_STA, USBA_RX_SETUP); 1575 1576 /* printk(KERN_DEBUG "setup: %d: %02x.%02x\n", 1577 ep->state, crq.crq.bRequestType, 1578 crq.crq.bRequest); */ 1579 1580 if (crq.crq.bRequestType & USB_DIR_IN) { 1581 /* 1582 * The USB 2.0 spec states that "if wLength is 1583 * zero, there is no data transfer phase." 1584 * However, testusb #14 seems to actually 1585 * expect a data phase even if wLength = 0... 1586 */ 1587 ep->state = DATA_STAGE_IN; 1588 } else { 1589 if (crq.crq.wLength != cpu_to_le16(0)) 1590 ep->state = DATA_STAGE_OUT; 1591 else 1592 ep->state = STATUS_STAGE_IN; 1593 } 1594 1595 ret = -1; 1596 if (ep->index == 0) 1597 ret = handle_ep0_setup(udc, ep, &crq.crq); 1598 else { 1599 spin_unlock(&udc->lock); 1600 ret = udc->driver->setup(&udc->gadget, &crq.crq); 1601 spin_lock(&udc->lock); 1602 } 1603 1604 DBG(DBG_BUS, "req %02x.%02x, length %d, state %d, ret %d\n", 1605 crq.crq.bRequestType, crq.crq.bRequest, 1606 le16_to_cpu(crq.crq.wLength), ep->state, ret); 1607 1608 if (ret < 0) { 1609 /* Let the host know that we failed */ 1610 set_protocol_stall(udc, ep); 1611 } 1612 } 1613 } 1614 1615 static void usba_ep_irq(struct usba_udc *udc, struct usba_ep *ep) 1616 { 1617 struct usba_request *req; 1618 u32 epstatus; 1619 u32 epctrl; 1620 1621 epstatus = usba_ep_readl(ep, STA); 1622 epctrl = usba_ep_readl(ep, CTL); 1623 1624 DBG(DBG_INT, "%s: interrupt, status: 0x%08x\n", ep->ep.name, epstatus); 1625 1626 while ((epctrl & USBA_TX_PK_RDY) && !(epstatus & USBA_TX_PK_RDY)) { 1627 DBG(DBG_BUS, "%s: TX PK ready\n", ep->ep.name); 1628 1629 if (list_empty(&ep->queue)) { 1630 dev_warn(&udc->pdev->dev, "ep_irq: queue empty\n"); 1631 usba_ep_writel(ep, CTL_DIS, USBA_TX_PK_RDY); 1632 return; 1633 } 1634 1635 req = list_entry(ep->queue.next, struct usba_request, queue); 1636 1637 if (req->using_dma) { 1638 /* Send a zero-length packet */ 1639 usba_ep_writel(ep, SET_STA, 1640 USBA_TX_PK_RDY); 1641 usba_ep_writel(ep, CTL_DIS, 1642 USBA_TX_PK_RDY); 1643 list_del_init(&req->queue); 1644 submit_next_request(ep); 1645 request_complete(ep, req, 0); 1646 } else { 1647 if (req->submitted) 1648 next_fifo_transaction(ep, req); 1649 else 1650 submit_request(ep, req); 1651 1652 if (req->last_transaction) { 1653 list_del_init(&req->queue); 1654 submit_next_request(ep); 1655 request_complete(ep, req, 0); 1656 } 1657 } 1658 1659 epstatus = usba_ep_readl(ep, STA); 1660 epctrl = usba_ep_readl(ep, CTL); 1661 } 1662 if ((epstatus & epctrl) & USBA_RX_BK_RDY) { 1663 DBG(DBG_BUS, "%s: RX data ready\n", ep->ep.name); 1664 receive_data(ep); 1665 } 1666 } 1667 1668 static void usba_dma_irq(struct usba_udc *udc, struct usba_ep *ep) 1669 { 1670 struct usba_request *req; 1671 u32 status, control, pending; 1672 1673 status = usba_dma_readl(ep, STATUS); 1674 control = usba_dma_readl(ep, CONTROL); 1675 #ifdef CONFIG_USB_GADGET_DEBUG_FS 1676 ep->last_dma_status = status; 1677 #endif 1678 pending = status & control; 1679 DBG(DBG_INT | DBG_DMA, "dma irq, s/%#08x, c/%#08x\n", status, control); 1680 1681 if (status & USBA_DMA_CH_EN) { 1682 dev_err(&udc->pdev->dev, 1683 "DMA_CH_EN is set after transfer is finished!\n"); 1684 dev_err(&udc->pdev->dev, 1685 "status=%#08x, pending=%#08x, control=%#08x\n", 1686 status, pending, control); 1687 1688 /* 1689 * try to pretend nothing happened. We might have to 1690 * do something here... 1691 */ 1692 } 1693 1694 if (list_empty(&ep->queue)) 1695 /* Might happen if a reset comes along at the right moment */ 1696 return; 1697 1698 if (pending & (USBA_DMA_END_TR_ST | USBA_DMA_END_BUF_ST)) { 1699 req = list_entry(ep->queue.next, struct usba_request, queue); 1700 usba_update_req(ep, req, status); 1701 1702 list_del_init(&req->queue); 1703 submit_next_request(ep); 1704 request_complete(ep, req, 0); 1705 } 1706 } 1707 1708 static int start_clock(struct usba_udc *udc); 1709 static void stop_clock(struct usba_udc *udc); 1710 1711 static irqreturn_t usba_udc_irq(int irq, void *devid) 1712 { 1713 struct usba_udc *udc = devid; 1714 u32 status, int_enb; 1715 u32 dma_status; 1716 u32 ep_status; 1717 1718 spin_lock(&udc->lock); 1719 1720 int_enb = usba_int_enb_get(udc); 1721 status = usba_readl(udc, INT_STA) & (int_enb | USBA_HIGH_SPEED); 1722 DBG(DBG_INT, "irq, status=%#08x\n", status); 1723 1724 if (status & USBA_DET_SUSPEND) { 1725 usba_writel(udc, INT_CLR, USBA_DET_SUSPEND|USBA_WAKE_UP); 1726 usba_int_enb_set(udc, USBA_WAKE_UP); 1727 usba_int_enb_clear(udc, USBA_DET_SUSPEND); 1728 udc->suspended = true; 1729 toggle_bias(udc, 0); 1730 udc->bias_pulse_needed = true; 1731 stop_clock(udc); 1732 DBG(DBG_BUS, "Suspend detected\n"); 1733 if (udc->gadget.speed != USB_SPEED_UNKNOWN 1734 && udc->driver && udc->driver->suspend) { 1735 spin_unlock(&udc->lock); 1736 udc->driver->suspend(&udc->gadget); 1737 spin_lock(&udc->lock); 1738 } 1739 } 1740 1741 if (status & USBA_WAKE_UP) { 1742 start_clock(udc); 1743 toggle_bias(udc, 1); 1744 usba_writel(udc, INT_CLR, USBA_WAKE_UP); 1745 DBG(DBG_BUS, "Wake Up CPU detected\n"); 1746 } 1747 1748 if (status & USBA_END_OF_RESUME) { 1749 udc->suspended = false; 1750 usba_writel(udc, INT_CLR, USBA_END_OF_RESUME); 1751 usba_int_enb_clear(udc, USBA_WAKE_UP); 1752 usba_int_enb_set(udc, USBA_DET_SUSPEND); 1753 generate_bias_pulse(udc); 1754 DBG(DBG_BUS, "Resume detected\n"); 1755 if (udc->gadget.speed != USB_SPEED_UNKNOWN 1756 && udc->driver && udc->driver->resume) { 1757 spin_unlock(&udc->lock); 1758 udc->driver->resume(&udc->gadget); 1759 spin_lock(&udc->lock); 1760 } 1761 } 1762 1763 dma_status = USBA_BFEXT(DMA_INT, status); 1764 if (dma_status) { 1765 int i; 1766 1767 usba_int_enb_set(udc, USBA_DET_SUSPEND); 1768 1769 for (i = 1; i <= USBA_NR_DMAS; i++) 1770 if (dma_status & (1 << i)) 1771 usba_dma_irq(udc, &udc->usba_ep[i]); 1772 } 1773 1774 ep_status = USBA_BFEXT(EPT_INT, status); 1775 if (ep_status) { 1776 int i; 1777 1778 usba_int_enb_set(udc, USBA_DET_SUSPEND); 1779 1780 for (i = 0; i < udc->num_ep; i++) 1781 if (ep_status & (1 << i)) { 1782 if (ep_is_control(&udc->usba_ep[i])) 1783 usba_control_irq(udc, &udc->usba_ep[i]); 1784 else 1785 usba_ep_irq(udc, &udc->usba_ep[i]); 1786 } 1787 } 1788 1789 if (status & USBA_END_OF_RESET) { 1790 struct usba_ep *ep0, *ep; 1791 int i; 1792 1793 usba_writel(udc, INT_CLR, 1794 USBA_END_OF_RESET|USBA_END_OF_RESUME 1795 |USBA_DET_SUSPEND|USBA_WAKE_UP); 1796 generate_bias_pulse(udc); 1797 reset_all_endpoints(udc); 1798 1799 if (udc->gadget.speed != USB_SPEED_UNKNOWN && udc->driver) { 1800 udc->gadget.speed = USB_SPEED_UNKNOWN; 1801 spin_unlock(&udc->lock); 1802 usb_gadget_udc_reset(&udc->gadget, udc->driver); 1803 spin_lock(&udc->lock); 1804 } 1805 1806 if (status & USBA_HIGH_SPEED) 1807 udc->gadget.speed = USB_SPEED_HIGH; 1808 else 1809 udc->gadget.speed = USB_SPEED_FULL; 1810 DBG(DBG_BUS, "%s bus reset detected\n", 1811 usb_speed_string(udc->gadget.speed)); 1812 1813 ep0 = &udc->usba_ep[0]; 1814 ep0->ep.desc = &usba_ep0_desc; 1815 ep0->state = WAIT_FOR_SETUP; 1816 usba_ep_writel(ep0, CFG, 1817 (USBA_BF(EPT_SIZE, EP0_EPT_SIZE) 1818 | USBA_BF(EPT_TYPE, USBA_EPT_TYPE_CONTROL) 1819 | USBA_BF(BK_NUMBER, USBA_BK_NUMBER_ONE))); 1820 usba_ep_writel(ep0, CTL_ENB, 1821 USBA_EPT_ENABLE | USBA_RX_SETUP); 1822 1823 /* If we get reset while suspended... */ 1824 udc->suspended = false; 1825 usba_int_enb_clear(udc, USBA_WAKE_UP); 1826 1827 usba_int_enb_set(udc, USBA_BF(EPT_INT, 1) | 1828 USBA_DET_SUSPEND | USBA_END_OF_RESUME); 1829 1830 /* 1831 * Unclear why we hit this irregularly, e.g. in usbtest, 1832 * but it's clearly harmless... 1833 */ 1834 if (!(usba_ep_readl(ep0, CFG) & USBA_EPT_MAPPED)) 1835 dev_err(&udc->pdev->dev, 1836 "ODD: EP0 configuration is invalid!\n"); 1837 1838 /* Preallocate other endpoints */ 1839 for (i = 1; i < udc->num_ep; i++) { 1840 ep = &udc->usba_ep[i]; 1841 if (ep->ep.claimed) { 1842 usba_ep_writel(ep, CFG, ep->ept_cfg); 1843 if (!(usba_ep_readl(ep, CFG) & USBA_EPT_MAPPED)) 1844 dev_err(&udc->pdev->dev, 1845 "ODD: EP%d configuration is invalid!\n", i); 1846 } 1847 } 1848 } 1849 1850 spin_unlock(&udc->lock); 1851 1852 return IRQ_HANDLED; 1853 } 1854 1855 static int start_clock(struct usba_udc *udc) 1856 { 1857 int ret; 1858 1859 if (udc->clocked) 1860 return 0; 1861 1862 pm_stay_awake(&udc->pdev->dev); 1863 1864 ret = clk_prepare_enable(udc->pclk); 1865 if (ret) 1866 return ret; 1867 ret = clk_prepare_enable(udc->hclk); 1868 if (ret) { 1869 clk_disable_unprepare(udc->pclk); 1870 return ret; 1871 } 1872 1873 udc->clocked = true; 1874 return 0; 1875 } 1876 1877 static void stop_clock(struct usba_udc *udc) 1878 { 1879 if (!udc->clocked) 1880 return; 1881 1882 clk_disable_unprepare(udc->hclk); 1883 clk_disable_unprepare(udc->pclk); 1884 1885 udc->clocked = false; 1886 1887 pm_relax(&udc->pdev->dev); 1888 } 1889 1890 static int usba_start(struct usba_udc *udc) 1891 { 1892 unsigned long flags; 1893 int ret; 1894 1895 ret = start_clock(udc); 1896 if (ret) 1897 return ret; 1898 1899 if (udc->suspended) 1900 return 0; 1901 1902 spin_lock_irqsave(&udc->lock, flags); 1903 toggle_bias(udc, 1); 1904 usba_writel(udc, CTRL, USBA_ENABLE_MASK); 1905 /* Clear all requested and pending interrupts... */ 1906 usba_writel(udc, INT_ENB, 0); 1907 udc->int_enb_cache = 0; 1908 usba_writel(udc, INT_CLR, 1909 USBA_END_OF_RESET|USBA_END_OF_RESUME 1910 |USBA_DET_SUSPEND|USBA_WAKE_UP); 1911 /* ...and enable just 'reset' IRQ to get us started */ 1912 usba_int_enb_set(udc, USBA_END_OF_RESET); 1913 spin_unlock_irqrestore(&udc->lock, flags); 1914 1915 return 0; 1916 } 1917 1918 static void usba_stop(struct usba_udc *udc) 1919 { 1920 unsigned long flags; 1921 1922 if (udc->suspended) 1923 return; 1924 1925 spin_lock_irqsave(&udc->lock, flags); 1926 udc->gadget.speed = USB_SPEED_UNKNOWN; 1927 reset_all_endpoints(udc); 1928 1929 /* This will also disable the DP pullup */ 1930 toggle_bias(udc, 0); 1931 usba_writel(udc, CTRL, USBA_DISABLE_MASK); 1932 spin_unlock_irqrestore(&udc->lock, flags); 1933 1934 stop_clock(udc); 1935 } 1936 1937 static irqreturn_t usba_vbus_irq_thread(int irq, void *devid) 1938 { 1939 struct usba_udc *udc = devid; 1940 int vbus; 1941 1942 /* debounce */ 1943 udelay(10); 1944 1945 mutex_lock(&udc->vbus_mutex); 1946 1947 vbus = vbus_is_present(udc); 1948 if (vbus != udc->vbus_prev) { 1949 if (vbus) { 1950 usba_start(udc); 1951 } else { 1952 udc->suspended = false; 1953 if (udc->driver->disconnect) 1954 udc->driver->disconnect(&udc->gadget); 1955 1956 usba_stop(udc); 1957 } 1958 udc->vbus_prev = vbus; 1959 } 1960 1961 mutex_unlock(&udc->vbus_mutex); 1962 return IRQ_HANDLED; 1963 } 1964 1965 static int atmel_usba_pullup(struct usb_gadget *gadget, int is_on) 1966 { 1967 struct usba_udc *udc = container_of(gadget, struct usba_udc, gadget); 1968 unsigned long flags; 1969 u32 ctrl; 1970 1971 spin_lock_irqsave(&udc->lock, flags); 1972 ctrl = usba_readl(udc, CTRL); 1973 if (is_on) 1974 ctrl &= ~USBA_DETACH; 1975 else 1976 ctrl |= USBA_DETACH; 1977 usba_writel(udc, CTRL, ctrl); 1978 spin_unlock_irqrestore(&udc->lock, flags); 1979 1980 return 0; 1981 } 1982 1983 static int atmel_usba_start(struct usb_gadget *gadget, 1984 struct usb_gadget_driver *driver) 1985 { 1986 int ret; 1987 struct usba_udc *udc = container_of(gadget, struct usba_udc, gadget); 1988 unsigned long flags; 1989 1990 spin_lock_irqsave(&udc->lock, flags); 1991 udc->devstatus = 1 << USB_DEVICE_SELF_POWERED; 1992 udc->driver = driver; 1993 spin_unlock_irqrestore(&udc->lock, flags); 1994 1995 mutex_lock(&udc->vbus_mutex); 1996 1997 if (udc->vbus_pin) 1998 enable_irq(gpiod_to_irq(udc->vbus_pin)); 1999 2000 /* If Vbus is present, enable the controller and wait for reset */ 2001 udc->vbus_prev = vbus_is_present(udc); 2002 if (udc->vbus_prev) { 2003 ret = usba_start(udc); 2004 if (ret) 2005 goto err; 2006 } 2007 2008 mutex_unlock(&udc->vbus_mutex); 2009 return 0; 2010 2011 err: 2012 if (udc->vbus_pin) 2013 disable_irq(gpiod_to_irq(udc->vbus_pin)); 2014 2015 mutex_unlock(&udc->vbus_mutex); 2016 2017 spin_lock_irqsave(&udc->lock, flags); 2018 udc->devstatus &= ~(1 << USB_DEVICE_SELF_POWERED); 2019 udc->driver = NULL; 2020 spin_unlock_irqrestore(&udc->lock, flags); 2021 return ret; 2022 } 2023 2024 static int atmel_usba_stop(struct usb_gadget *gadget) 2025 { 2026 struct usba_udc *udc = container_of(gadget, struct usba_udc, gadget); 2027 2028 if (udc->vbus_pin) 2029 disable_irq(gpiod_to_irq(udc->vbus_pin)); 2030 2031 udc->suspended = false; 2032 usba_stop(udc); 2033 2034 udc->driver = NULL; 2035 2036 return 0; 2037 } 2038 2039 static void at91sam9rl_toggle_bias(struct usba_udc *udc, int is_on) 2040 { 2041 regmap_update_bits(udc->pmc, AT91_CKGR_UCKR, AT91_PMC_BIASEN, 2042 is_on ? AT91_PMC_BIASEN : 0); 2043 } 2044 2045 static void at91sam9g45_pulse_bias(struct usba_udc *udc) 2046 { 2047 regmap_update_bits(udc->pmc, AT91_CKGR_UCKR, AT91_PMC_BIASEN, 0); 2048 regmap_update_bits(udc->pmc, AT91_CKGR_UCKR, AT91_PMC_BIASEN, 2049 AT91_PMC_BIASEN); 2050 } 2051 2052 static const struct usba_udc_errata at91sam9rl_errata = { 2053 .toggle_bias = at91sam9rl_toggle_bias, 2054 }; 2055 2056 static const struct usba_udc_errata at91sam9g45_errata = { 2057 .pulse_bias = at91sam9g45_pulse_bias, 2058 }; 2059 2060 static const struct usba_ep_config ep_config_sam9[] __initconst = { 2061 { .nr_banks = 1 }, /* ep 0 */ 2062 { .nr_banks = 2, .can_dma = 1, .can_isoc = 1 }, /* ep 1 */ 2063 { .nr_banks = 2, .can_dma = 1, .can_isoc = 1 }, /* ep 2 */ 2064 { .nr_banks = 3, .can_dma = 1 }, /* ep 3 */ 2065 { .nr_banks = 3, .can_dma = 1 }, /* ep 4 */ 2066 { .nr_banks = 3, .can_dma = 1, .can_isoc = 1 }, /* ep 5 */ 2067 { .nr_banks = 3, .can_dma = 1, .can_isoc = 1 }, /* ep 6 */ 2068 }; 2069 2070 static const struct usba_ep_config ep_config_sama5[] __initconst = { 2071 { .nr_banks = 1 }, /* ep 0 */ 2072 { .nr_banks = 3, .can_dma = 1, .can_isoc = 1 }, /* ep 1 */ 2073 { .nr_banks = 3, .can_dma = 1, .can_isoc = 1 }, /* ep 2 */ 2074 { .nr_banks = 2, .can_dma = 1, .can_isoc = 1 }, /* ep 3 */ 2075 { .nr_banks = 2, .can_dma = 1, .can_isoc = 1 }, /* ep 4 */ 2076 { .nr_banks = 2, .can_dma = 1, .can_isoc = 1 }, /* ep 5 */ 2077 { .nr_banks = 2, .can_dma = 1, .can_isoc = 1 }, /* ep 6 */ 2078 { .nr_banks = 2, .can_dma = 1, .can_isoc = 1 }, /* ep 7 */ 2079 { .nr_banks = 2, .can_isoc = 1 }, /* ep 8 */ 2080 { .nr_banks = 2, .can_isoc = 1 }, /* ep 9 */ 2081 { .nr_banks = 2, .can_isoc = 1 }, /* ep 10 */ 2082 { .nr_banks = 2, .can_isoc = 1 }, /* ep 11 */ 2083 { .nr_banks = 2, .can_isoc = 1 }, /* ep 12 */ 2084 { .nr_banks = 2, .can_isoc = 1 }, /* ep 13 */ 2085 { .nr_banks = 2, .can_isoc = 1 }, /* ep 14 */ 2086 { .nr_banks = 2, .can_isoc = 1 }, /* ep 15 */ 2087 }; 2088 2089 static const struct usba_udc_config udc_at91sam9rl_cfg = { 2090 .errata = &at91sam9rl_errata, 2091 .config = ep_config_sam9, 2092 .num_ep = ARRAY_SIZE(ep_config_sam9), 2093 .ep_prealloc = true, 2094 }; 2095 2096 static const struct usba_udc_config udc_at91sam9g45_cfg = { 2097 .errata = &at91sam9g45_errata, 2098 .config = ep_config_sam9, 2099 .num_ep = ARRAY_SIZE(ep_config_sam9), 2100 .ep_prealloc = true, 2101 }; 2102 2103 static const struct usba_udc_config udc_sama5d3_cfg = { 2104 .config = ep_config_sama5, 2105 .num_ep = ARRAY_SIZE(ep_config_sama5), 2106 .ep_prealloc = true, 2107 }; 2108 2109 static const struct usba_udc_config udc_sam9x60_cfg = { 2110 .num_ep = ARRAY_SIZE(ep_config_sam9), 2111 .config = ep_config_sam9, 2112 .ep_prealloc = false, 2113 }; 2114 2115 static const struct of_device_id atmel_udc_dt_ids[] = { 2116 { .compatible = "atmel,at91sam9rl-udc", .data = &udc_at91sam9rl_cfg }, 2117 { .compatible = "atmel,at91sam9g45-udc", .data = &udc_at91sam9g45_cfg }, 2118 { .compatible = "atmel,sama5d3-udc", .data = &udc_sama5d3_cfg }, 2119 { .compatible = "microchip,sam9x60-udc", .data = &udc_sam9x60_cfg }, 2120 { /* sentinel */ } 2121 }; 2122 2123 MODULE_DEVICE_TABLE(of, atmel_udc_dt_ids); 2124 2125 static const struct of_device_id atmel_pmc_dt_ids[] = { 2126 { .compatible = "atmel,at91sam9g45-pmc" }, 2127 { .compatible = "atmel,at91sam9rl-pmc" }, 2128 { .compatible = "atmel,at91sam9x5-pmc" }, 2129 { /* sentinel */ } 2130 }; 2131 2132 static struct usba_ep * atmel_udc_of_init(struct platform_device *pdev, 2133 struct usba_udc *udc) 2134 { 2135 struct device_node *np = pdev->dev.of_node; 2136 const struct of_device_id *match; 2137 struct device_node *pp; 2138 int i, ret; 2139 struct usba_ep *eps, *ep; 2140 const struct usba_udc_config *udc_config; 2141 2142 match = of_match_node(atmel_udc_dt_ids, np); 2143 if (!match) 2144 return ERR_PTR(-EINVAL); 2145 2146 udc_config = match->data; 2147 udc->ep_prealloc = udc_config->ep_prealloc; 2148 udc->errata = udc_config->errata; 2149 if (udc->errata) { 2150 pp = of_find_matching_node_and_match(NULL, atmel_pmc_dt_ids, 2151 NULL); 2152 if (!pp) 2153 return ERR_PTR(-ENODEV); 2154 2155 udc->pmc = syscon_node_to_regmap(pp); 2156 of_node_put(pp); 2157 if (IS_ERR(udc->pmc)) 2158 return ERR_CAST(udc->pmc); 2159 } 2160 2161 udc->num_ep = 0; 2162 2163 udc->vbus_pin = devm_gpiod_get_optional(&pdev->dev, "atmel,vbus", 2164 GPIOD_IN); 2165 2166 if (fifo_mode == 0) { 2167 udc->num_ep = udc_config->num_ep; 2168 } else { 2169 udc->num_ep = usba_config_fifo_table(udc); 2170 } 2171 2172 eps = devm_kcalloc(&pdev->dev, udc->num_ep, sizeof(struct usba_ep), 2173 GFP_KERNEL); 2174 if (!eps) 2175 return ERR_PTR(-ENOMEM); 2176 2177 udc->gadget.ep0 = &eps[0].ep; 2178 2179 INIT_LIST_HEAD(&eps[0].ep.ep_list); 2180 2181 i = 0; 2182 while (i < udc->num_ep) { 2183 const struct usba_ep_config *ep_cfg = &udc_config->config[i]; 2184 2185 ep = &eps[i]; 2186 2187 ep->index = fifo_mode ? udc->fifo_cfg[i].hw_ep_num : i; 2188 2189 /* Only the first EP is 64 bytes */ 2190 if (ep->index == 0) 2191 ep->fifo_size = 64; 2192 else 2193 ep->fifo_size = 1024; 2194 2195 if (fifo_mode) { 2196 if (ep->fifo_size < udc->fifo_cfg[i].fifo_size) 2197 dev_warn(&pdev->dev, 2198 "Using default max fifo-size value\n"); 2199 else 2200 ep->fifo_size = udc->fifo_cfg[i].fifo_size; 2201 } 2202 2203 ep->nr_banks = ep_cfg->nr_banks; 2204 if (fifo_mode) { 2205 if (ep->nr_banks < udc->fifo_cfg[i].nr_banks) 2206 dev_warn(&pdev->dev, 2207 "Using default max nb-banks value\n"); 2208 else 2209 ep->nr_banks = udc->fifo_cfg[i].nr_banks; 2210 } 2211 2212 ep->can_dma = ep_cfg->can_dma; 2213 ep->can_isoc = ep_cfg->can_isoc; 2214 2215 sprintf(ep->name, "ep%d", ep->index); 2216 ep->ep.name = ep->name; 2217 2218 ep->ep_regs = udc->regs + USBA_EPT_BASE(i); 2219 ep->dma_regs = udc->regs + USBA_DMA_BASE(i); 2220 ep->fifo = udc->fifo + USBA_FIFO_BASE(i); 2221 ep->ep.ops = &usba_ep_ops; 2222 usb_ep_set_maxpacket_limit(&ep->ep, ep->fifo_size); 2223 ep->udc = udc; 2224 INIT_LIST_HEAD(&ep->queue); 2225 2226 if (ep->index == 0) { 2227 ep->ep.caps.type_control = true; 2228 } else { 2229 ep->ep.caps.type_iso = ep->can_isoc; 2230 ep->ep.caps.type_bulk = true; 2231 ep->ep.caps.type_int = true; 2232 } 2233 2234 ep->ep.caps.dir_in = true; 2235 ep->ep.caps.dir_out = true; 2236 2237 if (fifo_mode != 0) { 2238 /* 2239 * Generate ept_cfg based on FIFO size and 2240 * banks number 2241 */ 2242 if (ep->fifo_size <= 8) 2243 ep->ept_cfg = USBA_BF(EPT_SIZE, USBA_EPT_SIZE_8); 2244 else 2245 /* LSB is bit 1, not 0 */ 2246 ep->ept_cfg = 2247 USBA_BF(EPT_SIZE, fls(ep->fifo_size - 1) - 3); 2248 2249 ep->ept_cfg |= USBA_BF(BK_NUMBER, ep->nr_banks); 2250 } 2251 2252 if (i) 2253 list_add_tail(&ep->ep.ep_list, &udc->gadget.ep_list); 2254 2255 i++; 2256 } 2257 2258 if (i == 0) { 2259 dev_err(&pdev->dev, "of_probe: no endpoint specified\n"); 2260 ret = -EINVAL; 2261 goto err; 2262 } 2263 2264 return eps; 2265 err: 2266 return ERR_PTR(ret); 2267 } 2268 2269 static int usba_udc_probe(struct platform_device *pdev) 2270 { 2271 struct resource *res; 2272 struct clk *pclk, *hclk; 2273 struct usba_udc *udc; 2274 int irq, ret, i; 2275 2276 udc = devm_kzalloc(&pdev->dev, sizeof(*udc), GFP_KERNEL); 2277 if (!udc) 2278 return -ENOMEM; 2279 2280 udc->gadget = usba_gadget_template; 2281 INIT_LIST_HEAD(&udc->gadget.ep_list); 2282 2283 res = platform_get_resource(pdev, IORESOURCE_MEM, CTRL_IOMEM_ID); 2284 udc->regs = devm_ioremap_resource(&pdev->dev, res); 2285 if (IS_ERR(udc->regs)) 2286 return PTR_ERR(udc->regs); 2287 dev_info(&pdev->dev, "MMIO registers at %pR mapped at %p\n", 2288 res, udc->regs); 2289 2290 res = platform_get_resource(pdev, IORESOURCE_MEM, FIFO_IOMEM_ID); 2291 udc->fifo = devm_ioremap_resource(&pdev->dev, res); 2292 if (IS_ERR(udc->fifo)) 2293 return PTR_ERR(udc->fifo); 2294 dev_info(&pdev->dev, "FIFO at %pR mapped at %p\n", res, udc->fifo); 2295 2296 irq = platform_get_irq(pdev, 0); 2297 if (irq < 0) 2298 return irq; 2299 2300 pclk = devm_clk_get(&pdev->dev, "pclk"); 2301 if (IS_ERR(pclk)) 2302 return PTR_ERR(pclk); 2303 hclk = devm_clk_get(&pdev->dev, "hclk"); 2304 if (IS_ERR(hclk)) 2305 return PTR_ERR(hclk); 2306 2307 spin_lock_init(&udc->lock); 2308 mutex_init(&udc->vbus_mutex); 2309 udc->pdev = pdev; 2310 udc->pclk = pclk; 2311 udc->hclk = hclk; 2312 2313 platform_set_drvdata(pdev, udc); 2314 2315 /* Make sure we start from a clean slate */ 2316 ret = clk_prepare_enable(pclk); 2317 if (ret) { 2318 dev_err(&pdev->dev, "Unable to enable pclk, aborting.\n"); 2319 return ret; 2320 } 2321 2322 usba_writel(udc, CTRL, USBA_DISABLE_MASK); 2323 clk_disable_unprepare(pclk); 2324 2325 udc->usba_ep = atmel_udc_of_init(pdev, udc); 2326 2327 toggle_bias(udc, 0); 2328 2329 if (IS_ERR(udc->usba_ep)) 2330 return PTR_ERR(udc->usba_ep); 2331 2332 ret = devm_request_irq(&pdev->dev, irq, usba_udc_irq, 0, 2333 "atmel_usba_udc", udc); 2334 if (ret) { 2335 dev_err(&pdev->dev, "Cannot request irq %d (error %d)\n", 2336 irq, ret); 2337 return ret; 2338 } 2339 udc->irq = irq; 2340 2341 if (udc->vbus_pin) { 2342 irq_set_status_flags(gpiod_to_irq(udc->vbus_pin), IRQ_NOAUTOEN); 2343 ret = devm_request_threaded_irq(&pdev->dev, 2344 gpiod_to_irq(udc->vbus_pin), NULL, 2345 usba_vbus_irq_thread, USBA_VBUS_IRQFLAGS, 2346 "atmel_usba_udc", udc); 2347 if (ret) { 2348 udc->vbus_pin = NULL; 2349 dev_warn(&udc->pdev->dev, 2350 "failed to request vbus irq; " 2351 "assuming always on\n"); 2352 } 2353 } 2354 2355 ret = usb_add_gadget_udc(&pdev->dev, &udc->gadget); 2356 if (ret) 2357 return ret; 2358 device_init_wakeup(&pdev->dev, 1); 2359 2360 usba_init_debugfs(udc); 2361 for (i = 1; i < udc->num_ep; i++) 2362 usba_ep_init_debugfs(udc, &udc->usba_ep[i]); 2363 2364 return 0; 2365 } 2366 2367 static int usba_udc_remove(struct platform_device *pdev) 2368 { 2369 struct usba_udc *udc; 2370 int i; 2371 2372 udc = platform_get_drvdata(pdev); 2373 2374 device_init_wakeup(&pdev->dev, 0); 2375 usb_del_gadget_udc(&udc->gadget); 2376 2377 for (i = 1; i < udc->num_ep; i++) 2378 usba_ep_cleanup_debugfs(&udc->usba_ep[i]); 2379 usba_cleanup_debugfs(udc); 2380 2381 return 0; 2382 } 2383 2384 #ifdef CONFIG_PM_SLEEP 2385 static int usba_udc_suspend(struct device *dev) 2386 { 2387 struct usba_udc *udc = dev_get_drvdata(dev); 2388 2389 /* Not started */ 2390 if (!udc->driver) 2391 return 0; 2392 2393 mutex_lock(&udc->vbus_mutex); 2394 2395 if (!device_may_wakeup(dev)) { 2396 udc->suspended = false; 2397 usba_stop(udc); 2398 goto out; 2399 } 2400 2401 /* 2402 * Device may wake up. We stay clocked if we failed 2403 * to request vbus irq, assuming always on. 2404 */ 2405 if (udc->vbus_pin) { 2406 /* FIXME: right to stop here...??? */ 2407 usba_stop(udc); 2408 enable_irq_wake(gpiod_to_irq(udc->vbus_pin)); 2409 } 2410 2411 enable_irq_wake(udc->irq); 2412 2413 out: 2414 mutex_unlock(&udc->vbus_mutex); 2415 return 0; 2416 } 2417 2418 static int usba_udc_resume(struct device *dev) 2419 { 2420 struct usba_udc *udc = dev_get_drvdata(dev); 2421 2422 /* Not started */ 2423 if (!udc->driver) 2424 return 0; 2425 2426 if (device_may_wakeup(dev)) { 2427 if (udc->vbus_pin) 2428 disable_irq_wake(gpiod_to_irq(udc->vbus_pin)); 2429 2430 disable_irq_wake(udc->irq); 2431 } 2432 2433 /* If Vbus is present, enable the controller and wait for reset */ 2434 mutex_lock(&udc->vbus_mutex); 2435 udc->vbus_prev = vbus_is_present(udc); 2436 if (udc->vbus_prev) 2437 usba_start(udc); 2438 mutex_unlock(&udc->vbus_mutex); 2439 2440 return 0; 2441 } 2442 #endif 2443 2444 static SIMPLE_DEV_PM_OPS(usba_udc_pm_ops, usba_udc_suspend, usba_udc_resume); 2445 2446 static struct platform_driver udc_driver = { 2447 .remove = usba_udc_remove, 2448 .driver = { 2449 .name = "atmel_usba_udc", 2450 .pm = &usba_udc_pm_ops, 2451 .of_match_table = atmel_udc_dt_ids, 2452 }, 2453 }; 2454 2455 module_platform_driver_probe(udc_driver, usba_udc_probe); 2456 2457 MODULE_DESCRIPTION("Atmel USBA UDC driver"); 2458 MODULE_AUTHOR("Haavard Skinnemoen (Atmel)"); 2459 MODULE_LICENSE("GPL"); 2460 MODULE_ALIAS("platform:atmel_usba_udc"); 2461