1 // SPDX-License-Identifier: GPL-2.0
2 /*
3  * Driver for the Atmel USBA high speed USB device controller
4  *
5  * Copyright (C) 2005-2007 Atmel Corporation
6  */
7 #include <linux/clk.h>
8 #include <linux/clk/at91_pmc.h>
9 #include <linux/module.h>
10 #include <linux/init.h>
11 #include <linux/interrupt.h>
12 #include <linux/io.h>
13 #include <linux/slab.h>
14 #include <linux/device.h>
15 #include <linux/dma-mapping.h>
16 #include <linux/list.h>
17 #include <linux/mfd/syscon.h>
18 #include <linux/platform_device.h>
19 #include <linux/regmap.h>
20 #include <linux/ctype.h>
21 #include <linux/usb.h>
22 #include <linux/usb/ch9.h>
23 #include <linux/usb/gadget.h>
24 #include <linux/delay.h>
25 #include <linux/of.h>
26 #include <linux/irq.h>
27 #include <linux/gpio/consumer.h>
28 
29 #include "atmel_usba_udc.h"
30 #define USBA_VBUS_IRQFLAGS (IRQF_ONESHOT \
31 			   | IRQF_TRIGGER_FALLING | IRQF_TRIGGER_RISING)
32 
33 #ifdef CONFIG_USB_GADGET_DEBUG_FS
34 #include <linux/debugfs.h>
35 #include <linux/uaccess.h>
36 
37 static int queue_dbg_open(struct inode *inode, struct file *file)
38 {
39 	struct usba_ep *ep = inode->i_private;
40 	struct usba_request *req, *req_copy;
41 	struct list_head *queue_data;
42 
43 	queue_data = kmalloc(sizeof(*queue_data), GFP_KERNEL);
44 	if (!queue_data)
45 		return -ENOMEM;
46 	INIT_LIST_HEAD(queue_data);
47 
48 	spin_lock_irq(&ep->udc->lock);
49 	list_for_each_entry(req, &ep->queue, queue) {
50 		req_copy = kmemdup(req, sizeof(*req_copy), GFP_ATOMIC);
51 		if (!req_copy)
52 			goto fail;
53 		list_add_tail(&req_copy->queue, queue_data);
54 	}
55 	spin_unlock_irq(&ep->udc->lock);
56 
57 	file->private_data = queue_data;
58 	return 0;
59 
60 fail:
61 	spin_unlock_irq(&ep->udc->lock);
62 	list_for_each_entry_safe(req, req_copy, queue_data, queue) {
63 		list_del(&req->queue);
64 		kfree(req);
65 	}
66 	kfree(queue_data);
67 	return -ENOMEM;
68 }
69 
70 /*
71  * bbbbbbbb llllllll IZS sssss nnnn FDL\n\0
72  *
73  * b: buffer address
74  * l: buffer length
75  * I/i: interrupt/no interrupt
76  * Z/z: zero/no zero
77  * S/s: short ok/short not ok
78  * s: status
79  * n: nr_packets
80  * F/f: submitted/not submitted to FIFO
81  * D/d: using/not using DMA
82  * L/l: last transaction/not last transaction
83  */
84 static ssize_t queue_dbg_read(struct file *file, char __user *buf,
85 		size_t nbytes, loff_t *ppos)
86 {
87 	struct list_head *queue = file->private_data;
88 	struct usba_request *req, *tmp_req;
89 	size_t len, remaining, actual = 0;
90 	char tmpbuf[38];
91 
92 	if (!access_ok(buf, nbytes))
93 		return -EFAULT;
94 
95 	inode_lock(file_inode(file));
96 	list_for_each_entry_safe(req, tmp_req, queue, queue) {
97 		len = snprintf(tmpbuf, sizeof(tmpbuf),
98 				"%8p %08x %c%c%c %5d %c%c%c\n",
99 				req->req.buf, req->req.length,
100 				req->req.no_interrupt ? 'i' : 'I',
101 				req->req.zero ? 'Z' : 'z',
102 				req->req.short_not_ok ? 's' : 'S',
103 				req->req.status,
104 				req->submitted ? 'F' : 'f',
105 				req->using_dma ? 'D' : 'd',
106 				req->last_transaction ? 'L' : 'l');
107 		len = min(len, sizeof(tmpbuf));
108 		if (len > nbytes)
109 			break;
110 
111 		list_del(&req->queue);
112 		kfree(req);
113 
114 		remaining = __copy_to_user(buf, tmpbuf, len);
115 		actual += len - remaining;
116 		if (remaining)
117 			break;
118 
119 		nbytes -= len;
120 		buf += len;
121 	}
122 	inode_unlock(file_inode(file));
123 
124 	return actual;
125 }
126 
127 static int queue_dbg_release(struct inode *inode, struct file *file)
128 {
129 	struct list_head *queue_data = file->private_data;
130 	struct usba_request *req, *tmp_req;
131 
132 	list_for_each_entry_safe(req, tmp_req, queue_data, queue) {
133 		list_del(&req->queue);
134 		kfree(req);
135 	}
136 	kfree(queue_data);
137 	return 0;
138 }
139 
140 static int regs_dbg_open(struct inode *inode, struct file *file)
141 {
142 	struct usba_udc *udc;
143 	unsigned int i;
144 	u32 *data;
145 	int ret = -ENOMEM;
146 
147 	inode_lock(inode);
148 	udc = inode->i_private;
149 	data = kmalloc(inode->i_size, GFP_KERNEL);
150 	if (!data)
151 		goto out;
152 
153 	spin_lock_irq(&udc->lock);
154 	for (i = 0; i < inode->i_size / 4; i++)
155 		data[i] = readl_relaxed(udc->regs + i * 4);
156 	spin_unlock_irq(&udc->lock);
157 
158 	file->private_data = data;
159 	ret = 0;
160 
161 out:
162 	inode_unlock(inode);
163 
164 	return ret;
165 }
166 
167 static ssize_t regs_dbg_read(struct file *file, char __user *buf,
168 		size_t nbytes, loff_t *ppos)
169 {
170 	struct inode *inode = file_inode(file);
171 	int ret;
172 
173 	inode_lock(inode);
174 	ret = simple_read_from_buffer(buf, nbytes, ppos,
175 			file->private_data,
176 			file_inode(file)->i_size);
177 	inode_unlock(inode);
178 
179 	return ret;
180 }
181 
182 static int regs_dbg_release(struct inode *inode, struct file *file)
183 {
184 	kfree(file->private_data);
185 	return 0;
186 }
187 
188 static const struct file_operations queue_dbg_fops = {
189 	.owner		= THIS_MODULE,
190 	.open		= queue_dbg_open,
191 	.llseek		= no_llseek,
192 	.read		= queue_dbg_read,
193 	.release	= queue_dbg_release,
194 };
195 
196 static const struct file_operations regs_dbg_fops = {
197 	.owner		= THIS_MODULE,
198 	.open		= regs_dbg_open,
199 	.llseek		= generic_file_llseek,
200 	.read		= regs_dbg_read,
201 	.release	= regs_dbg_release,
202 };
203 
204 static void usba_ep_init_debugfs(struct usba_udc *udc,
205 		struct usba_ep *ep)
206 {
207 	struct dentry *ep_root;
208 
209 	ep_root = debugfs_create_dir(ep->ep.name, udc->debugfs_root);
210 	ep->debugfs_dir = ep_root;
211 
212 	debugfs_create_file("queue", 0400, ep_root, ep, &queue_dbg_fops);
213 	if (ep->can_dma)
214 		debugfs_create_u32("dma_status", 0400, ep_root,
215 				   &ep->last_dma_status);
216 	if (ep_is_control(ep))
217 		debugfs_create_u32("state", 0400, ep_root, &ep->state);
218 }
219 
220 static void usba_ep_cleanup_debugfs(struct usba_ep *ep)
221 {
222 	debugfs_remove_recursive(ep->debugfs_dir);
223 }
224 
225 static void usba_init_debugfs(struct usba_udc *udc)
226 {
227 	struct dentry *root;
228 	struct resource *regs_resource;
229 
230 	root = debugfs_create_dir(udc->gadget.name, usb_debug_root);
231 	udc->debugfs_root = root;
232 
233 	regs_resource = platform_get_resource(udc->pdev, IORESOURCE_MEM,
234 				CTRL_IOMEM_ID);
235 
236 	if (regs_resource) {
237 		debugfs_create_file_size("regs", 0400, root, udc,
238 					 &regs_dbg_fops,
239 					 resource_size(regs_resource));
240 	}
241 
242 	usba_ep_init_debugfs(udc, to_usba_ep(udc->gadget.ep0));
243 }
244 
245 static void usba_cleanup_debugfs(struct usba_udc *udc)
246 {
247 	usba_ep_cleanup_debugfs(to_usba_ep(udc->gadget.ep0));
248 	debugfs_remove_recursive(udc->debugfs_root);
249 }
250 #else
251 static inline void usba_ep_init_debugfs(struct usba_udc *udc,
252 					 struct usba_ep *ep)
253 {
254 
255 }
256 
257 static inline void usba_ep_cleanup_debugfs(struct usba_ep *ep)
258 {
259 
260 }
261 
262 static inline void usba_init_debugfs(struct usba_udc *udc)
263 {
264 
265 }
266 
267 static inline void usba_cleanup_debugfs(struct usba_udc *udc)
268 {
269 
270 }
271 #endif
272 
273 static ushort fifo_mode;
274 
275 module_param(fifo_mode, ushort, 0x0);
276 MODULE_PARM_DESC(fifo_mode, "Endpoint configuration mode");
277 
278 /* mode 0 - uses autoconfig */
279 
280 /* mode 1 - fits in 8KB, generic max fifo configuration */
281 static struct usba_fifo_cfg mode_1_cfg[] = {
282 { .hw_ep_num = 0, .fifo_size = 64,	.nr_banks = 1, },
283 { .hw_ep_num = 1, .fifo_size = 1024,	.nr_banks = 2, },
284 { .hw_ep_num = 2, .fifo_size = 1024,	.nr_banks = 1, },
285 { .hw_ep_num = 3, .fifo_size = 1024,	.nr_banks = 1, },
286 { .hw_ep_num = 4, .fifo_size = 1024,	.nr_banks = 1, },
287 { .hw_ep_num = 5, .fifo_size = 1024,	.nr_banks = 1, },
288 { .hw_ep_num = 6, .fifo_size = 1024,	.nr_banks = 1, },
289 };
290 
291 /* mode 2 - fits in 8KB, performance max fifo configuration */
292 static struct usba_fifo_cfg mode_2_cfg[] = {
293 { .hw_ep_num = 0, .fifo_size = 64,	.nr_banks = 1, },
294 { .hw_ep_num = 1, .fifo_size = 1024,	.nr_banks = 3, },
295 { .hw_ep_num = 2, .fifo_size = 1024,	.nr_banks = 2, },
296 { .hw_ep_num = 3, .fifo_size = 1024,	.nr_banks = 2, },
297 };
298 
299 /* mode 3 - fits in 8KB, mixed fifo configuration */
300 static struct usba_fifo_cfg mode_3_cfg[] = {
301 { .hw_ep_num = 0, .fifo_size = 64,	.nr_banks = 1, },
302 { .hw_ep_num = 1, .fifo_size = 1024,	.nr_banks = 2, },
303 { .hw_ep_num = 2, .fifo_size = 512,	.nr_banks = 2, },
304 { .hw_ep_num = 3, .fifo_size = 512,	.nr_banks = 2, },
305 { .hw_ep_num = 4, .fifo_size = 512,	.nr_banks = 2, },
306 { .hw_ep_num = 5, .fifo_size = 512,	.nr_banks = 2, },
307 { .hw_ep_num = 6, .fifo_size = 512,	.nr_banks = 2, },
308 };
309 
310 /* mode 4 - fits in 8KB, custom fifo configuration */
311 static struct usba_fifo_cfg mode_4_cfg[] = {
312 { .hw_ep_num = 0, .fifo_size = 64,	.nr_banks = 1, },
313 { .hw_ep_num = 1, .fifo_size = 512,	.nr_banks = 2, },
314 { .hw_ep_num = 2, .fifo_size = 512,	.nr_banks = 2, },
315 { .hw_ep_num = 3, .fifo_size = 8,	.nr_banks = 2, },
316 { .hw_ep_num = 4, .fifo_size = 512,	.nr_banks = 2, },
317 { .hw_ep_num = 5, .fifo_size = 512,	.nr_banks = 2, },
318 { .hw_ep_num = 6, .fifo_size = 16,	.nr_banks = 2, },
319 { .hw_ep_num = 7, .fifo_size = 8,	.nr_banks = 2, },
320 { .hw_ep_num = 8, .fifo_size = 8,	.nr_banks = 2, },
321 };
322 /* Add additional configurations here */
323 
324 static int usba_config_fifo_table(struct usba_udc *udc)
325 {
326 	int n;
327 
328 	switch (fifo_mode) {
329 	default:
330 		fifo_mode = 0;
331 		/* fall through */
332 	case 0:
333 		udc->fifo_cfg = NULL;
334 		n = 0;
335 		break;
336 	case 1:
337 		udc->fifo_cfg = mode_1_cfg;
338 		n = ARRAY_SIZE(mode_1_cfg);
339 		break;
340 	case 2:
341 		udc->fifo_cfg = mode_2_cfg;
342 		n = ARRAY_SIZE(mode_2_cfg);
343 		break;
344 	case 3:
345 		udc->fifo_cfg = mode_3_cfg;
346 		n = ARRAY_SIZE(mode_3_cfg);
347 		break;
348 	case 4:
349 		udc->fifo_cfg = mode_4_cfg;
350 		n = ARRAY_SIZE(mode_4_cfg);
351 		break;
352 	}
353 	DBG(DBG_HW, "Setup fifo_mode %d\n", fifo_mode);
354 
355 	return n;
356 }
357 
358 static inline u32 usba_int_enb_get(struct usba_udc *udc)
359 {
360 	return udc->int_enb_cache;
361 }
362 
363 static inline void usba_int_enb_set(struct usba_udc *udc, u32 mask)
364 {
365 	u32 val;
366 
367 	val = udc->int_enb_cache | mask;
368 	usba_writel(udc, INT_ENB, val);
369 	udc->int_enb_cache = val;
370 }
371 
372 static inline void usba_int_enb_clear(struct usba_udc *udc, u32 mask)
373 {
374 	u32 val;
375 
376 	val = udc->int_enb_cache & ~mask;
377 	usba_writel(udc, INT_ENB, val);
378 	udc->int_enb_cache = val;
379 }
380 
381 static int vbus_is_present(struct usba_udc *udc)
382 {
383 	if (udc->vbus_pin)
384 		return gpiod_get_value(udc->vbus_pin);
385 
386 	/* No Vbus detection: Assume always present */
387 	return 1;
388 }
389 
390 static void toggle_bias(struct usba_udc *udc, int is_on)
391 {
392 	if (udc->errata && udc->errata->toggle_bias)
393 		udc->errata->toggle_bias(udc, is_on);
394 }
395 
396 static void generate_bias_pulse(struct usba_udc *udc)
397 {
398 	if (!udc->bias_pulse_needed)
399 		return;
400 
401 	if (udc->errata && udc->errata->pulse_bias)
402 		udc->errata->pulse_bias(udc);
403 
404 	udc->bias_pulse_needed = false;
405 }
406 
407 static void next_fifo_transaction(struct usba_ep *ep, struct usba_request *req)
408 {
409 	unsigned int transaction_len;
410 
411 	transaction_len = req->req.length - req->req.actual;
412 	req->last_transaction = 1;
413 	if (transaction_len > ep->ep.maxpacket) {
414 		transaction_len = ep->ep.maxpacket;
415 		req->last_transaction = 0;
416 	} else if (transaction_len == ep->ep.maxpacket && req->req.zero)
417 		req->last_transaction = 0;
418 
419 	DBG(DBG_QUEUE, "%s: submit_transaction, req %p (length %d)%s\n",
420 		ep->ep.name, req, transaction_len,
421 		req->last_transaction ? ", done" : "");
422 
423 	memcpy_toio(ep->fifo, req->req.buf + req->req.actual, transaction_len);
424 	usba_ep_writel(ep, SET_STA, USBA_TX_PK_RDY);
425 	req->req.actual += transaction_len;
426 }
427 
428 static void submit_request(struct usba_ep *ep, struct usba_request *req)
429 {
430 	DBG(DBG_QUEUE, "%s: submit_request: req %p (length %d)\n",
431 		ep->ep.name, req, req->req.length);
432 
433 	req->req.actual = 0;
434 	req->submitted = 1;
435 
436 	if (req->using_dma) {
437 		if (req->req.length == 0) {
438 			usba_ep_writel(ep, CTL_ENB, USBA_TX_PK_RDY);
439 			return;
440 		}
441 
442 		if (req->req.zero)
443 			usba_ep_writel(ep, CTL_ENB, USBA_SHORT_PACKET);
444 		else
445 			usba_ep_writel(ep, CTL_DIS, USBA_SHORT_PACKET);
446 
447 		usba_dma_writel(ep, ADDRESS, req->req.dma);
448 		usba_dma_writel(ep, CONTROL, req->ctrl);
449 	} else {
450 		next_fifo_transaction(ep, req);
451 		if (req->last_transaction) {
452 			usba_ep_writel(ep, CTL_DIS, USBA_TX_PK_RDY);
453 			if (ep_is_control(ep))
454 				usba_ep_writel(ep, CTL_ENB, USBA_TX_COMPLETE);
455 		} else {
456 			if (ep_is_control(ep))
457 				usba_ep_writel(ep, CTL_DIS, USBA_TX_COMPLETE);
458 			usba_ep_writel(ep, CTL_ENB, USBA_TX_PK_RDY);
459 		}
460 	}
461 }
462 
463 static void submit_next_request(struct usba_ep *ep)
464 {
465 	struct usba_request *req;
466 
467 	if (list_empty(&ep->queue)) {
468 		usba_ep_writel(ep, CTL_DIS, USBA_TX_PK_RDY | USBA_RX_BK_RDY);
469 		return;
470 	}
471 
472 	req = list_entry(ep->queue.next, struct usba_request, queue);
473 	if (!req->submitted)
474 		submit_request(ep, req);
475 }
476 
477 static void send_status(struct usba_udc *udc, struct usba_ep *ep)
478 {
479 	ep->state = STATUS_STAGE_IN;
480 	usba_ep_writel(ep, SET_STA, USBA_TX_PK_RDY);
481 	usba_ep_writel(ep, CTL_ENB, USBA_TX_COMPLETE);
482 }
483 
484 static void receive_data(struct usba_ep *ep)
485 {
486 	struct usba_udc *udc = ep->udc;
487 	struct usba_request *req;
488 	unsigned long status;
489 	unsigned int bytecount, nr_busy;
490 	int is_complete = 0;
491 
492 	status = usba_ep_readl(ep, STA);
493 	nr_busy = USBA_BFEXT(BUSY_BANKS, status);
494 
495 	DBG(DBG_QUEUE, "receive data: nr_busy=%u\n", nr_busy);
496 
497 	while (nr_busy > 0) {
498 		if (list_empty(&ep->queue)) {
499 			usba_ep_writel(ep, CTL_DIS, USBA_RX_BK_RDY);
500 			break;
501 		}
502 		req = list_entry(ep->queue.next,
503 				 struct usba_request, queue);
504 
505 		bytecount = USBA_BFEXT(BYTE_COUNT, status);
506 
507 		if (status & (1 << 31))
508 			is_complete = 1;
509 		if (req->req.actual + bytecount >= req->req.length) {
510 			is_complete = 1;
511 			bytecount = req->req.length - req->req.actual;
512 		}
513 
514 		memcpy_fromio(req->req.buf + req->req.actual,
515 				ep->fifo, bytecount);
516 		req->req.actual += bytecount;
517 
518 		usba_ep_writel(ep, CLR_STA, USBA_RX_BK_RDY);
519 
520 		if (is_complete) {
521 			DBG(DBG_QUEUE, "%s: request done\n", ep->ep.name);
522 			req->req.status = 0;
523 			list_del_init(&req->queue);
524 			usba_ep_writel(ep, CTL_DIS, USBA_RX_BK_RDY);
525 			spin_unlock(&udc->lock);
526 			usb_gadget_giveback_request(&ep->ep, &req->req);
527 			spin_lock(&udc->lock);
528 		}
529 
530 		status = usba_ep_readl(ep, STA);
531 		nr_busy = USBA_BFEXT(BUSY_BANKS, status);
532 
533 		if (is_complete && ep_is_control(ep)) {
534 			send_status(udc, ep);
535 			break;
536 		}
537 	}
538 }
539 
540 static void
541 request_complete(struct usba_ep *ep, struct usba_request *req, int status)
542 {
543 	struct usba_udc *udc = ep->udc;
544 
545 	WARN_ON(!list_empty(&req->queue));
546 
547 	if (req->req.status == -EINPROGRESS)
548 		req->req.status = status;
549 
550 	if (req->using_dma)
551 		usb_gadget_unmap_request(&udc->gadget, &req->req, ep->is_in);
552 
553 	DBG(DBG_GADGET | DBG_REQ,
554 		"%s: req %p complete: status %d, actual %u\n",
555 		ep->ep.name, req, req->req.status, req->req.actual);
556 
557 	spin_unlock(&udc->lock);
558 	usb_gadget_giveback_request(&ep->ep, &req->req);
559 	spin_lock(&udc->lock);
560 }
561 
562 static void
563 request_complete_list(struct usba_ep *ep, struct list_head *list, int status)
564 {
565 	struct usba_request *req, *tmp_req;
566 
567 	list_for_each_entry_safe(req, tmp_req, list, queue) {
568 		list_del_init(&req->queue);
569 		request_complete(ep, req, status);
570 	}
571 }
572 
573 static int
574 usba_ep_enable(struct usb_ep *_ep, const struct usb_endpoint_descriptor *desc)
575 {
576 	struct usba_ep *ep = to_usba_ep(_ep);
577 	struct usba_udc *udc = ep->udc;
578 	unsigned long flags, maxpacket;
579 	unsigned int nr_trans;
580 
581 	DBG(DBG_GADGET, "%s: ep_enable: desc=%p\n", ep->ep.name, desc);
582 
583 	maxpacket = usb_endpoint_maxp(desc);
584 
585 	if (((desc->bEndpointAddress & USB_ENDPOINT_NUMBER_MASK) != ep->index)
586 			|| ep->index == 0
587 			|| desc->bDescriptorType != USB_DT_ENDPOINT
588 			|| maxpacket == 0
589 			|| maxpacket > ep->fifo_size) {
590 		DBG(DBG_ERR, "ep_enable: Invalid argument");
591 		return -EINVAL;
592 	}
593 
594 	ep->is_isoc = 0;
595 	ep->is_in = 0;
596 
597 	DBG(DBG_ERR, "%s: EPT_CFG = 0x%lx (maxpacket = %lu)\n",
598 			ep->ep.name, ep->ept_cfg, maxpacket);
599 
600 	if (usb_endpoint_dir_in(desc)) {
601 		ep->is_in = 1;
602 		ep->ept_cfg |= USBA_EPT_DIR_IN;
603 	}
604 
605 	switch (usb_endpoint_type(desc)) {
606 	case USB_ENDPOINT_XFER_CONTROL:
607 		ep->ept_cfg |= USBA_BF(EPT_TYPE, USBA_EPT_TYPE_CONTROL);
608 		break;
609 	case USB_ENDPOINT_XFER_ISOC:
610 		if (!ep->can_isoc) {
611 			DBG(DBG_ERR, "ep_enable: %s is not isoc capable\n",
612 					ep->ep.name);
613 			return -EINVAL;
614 		}
615 
616 		/*
617 		 * Bits 11:12 specify number of _additional_
618 		 * transactions per microframe.
619 		 */
620 		nr_trans = usb_endpoint_maxp_mult(desc);
621 		if (nr_trans > 3)
622 			return -EINVAL;
623 
624 		ep->is_isoc = 1;
625 		ep->ept_cfg |= USBA_BF(EPT_TYPE, USBA_EPT_TYPE_ISO);
626 		ep->ept_cfg |= USBA_BF(NB_TRANS, nr_trans);
627 
628 		break;
629 	case USB_ENDPOINT_XFER_BULK:
630 		ep->ept_cfg |= USBA_BF(EPT_TYPE, USBA_EPT_TYPE_BULK);
631 		break;
632 	case USB_ENDPOINT_XFER_INT:
633 		ep->ept_cfg |= USBA_BF(EPT_TYPE, USBA_EPT_TYPE_INT);
634 		break;
635 	}
636 
637 	spin_lock_irqsave(&ep->udc->lock, flags);
638 
639 	ep->ep.desc = desc;
640 	ep->ep.maxpacket = maxpacket;
641 
642 	usba_ep_writel(ep, CFG, ep->ept_cfg);
643 	usba_ep_writel(ep, CTL_ENB, USBA_EPT_ENABLE);
644 
645 	if (ep->can_dma) {
646 		u32 ctrl;
647 
648 		usba_int_enb_set(udc, USBA_BF(EPT_INT, 1 << ep->index) |
649 				      USBA_BF(DMA_INT, 1 << ep->index));
650 		ctrl = USBA_AUTO_VALID | USBA_INTDIS_DMA;
651 		usba_ep_writel(ep, CTL_ENB, ctrl);
652 	} else {
653 		usba_int_enb_set(udc, USBA_BF(EPT_INT, 1 << ep->index));
654 	}
655 
656 	spin_unlock_irqrestore(&udc->lock, flags);
657 
658 	DBG(DBG_HW, "EPT_CFG%d after init: %#08lx\n", ep->index,
659 			(unsigned long)usba_ep_readl(ep, CFG));
660 	DBG(DBG_HW, "INT_ENB after init: %#08lx\n",
661 			(unsigned long)usba_int_enb_get(udc));
662 
663 	return 0;
664 }
665 
666 static int usba_ep_disable(struct usb_ep *_ep)
667 {
668 	struct usba_ep *ep = to_usba_ep(_ep);
669 	struct usba_udc *udc = ep->udc;
670 	LIST_HEAD(req_list);
671 	unsigned long flags;
672 
673 	DBG(DBG_GADGET, "ep_disable: %s\n", ep->ep.name);
674 
675 	spin_lock_irqsave(&udc->lock, flags);
676 
677 	if (!ep->ep.desc) {
678 		spin_unlock_irqrestore(&udc->lock, flags);
679 		DBG(DBG_ERR, "ep_disable: %s not enabled\n", ep->ep.name);
680 		return -EINVAL;
681 	}
682 	ep->ep.desc = NULL;
683 
684 	list_splice_init(&ep->queue, &req_list);
685 	if (ep->can_dma) {
686 		usba_dma_writel(ep, CONTROL, 0);
687 		usba_dma_writel(ep, ADDRESS, 0);
688 		usba_dma_readl(ep, STATUS);
689 	}
690 	usba_ep_writel(ep, CTL_DIS, USBA_EPT_ENABLE);
691 	usba_int_enb_clear(udc, USBA_BF(EPT_INT, 1 << ep->index));
692 
693 	request_complete_list(ep, &req_list, -ESHUTDOWN);
694 
695 	spin_unlock_irqrestore(&udc->lock, flags);
696 
697 	return 0;
698 }
699 
700 static struct usb_request *
701 usba_ep_alloc_request(struct usb_ep *_ep, gfp_t gfp_flags)
702 {
703 	struct usba_request *req;
704 
705 	DBG(DBG_GADGET, "ep_alloc_request: %p, 0x%x\n", _ep, gfp_flags);
706 
707 	req = kzalloc(sizeof(*req), gfp_flags);
708 	if (!req)
709 		return NULL;
710 
711 	INIT_LIST_HEAD(&req->queue);
712 
713 	return &req->req;
714 }
715 
716 static void
717 usba_ep_free_request(struct usb_ep *_ep, struct usb_request *_req)
718 {
719 	struct usba_request *req = to_usba_req(_req);
720 
721 	DBG(DBG_GADGET, "ep_free_request: %p, %p\n", _ep, _req);
722 
723 	kfree(req);
724 }
725 
726 static int queue_dma(struct usba_udc *udc, struct usba_ep *ep,
727 		struct usba_request *req, gfp_t gfp_flags)
728 {
729 	unsigned long flags;
730 	int ret;
731 
732 	DBG(DBG_DMA, "%s: req l/%u d/%pad %c%c%c\n",
733 		ep->ep.name, req->req.length, &req->req.dma,
734 		req->req.zero ? 'Z' : 'z',
735 		req->req.short_not_ok ? 'S' : 's',
736 		req->req.no_interrupt ? 'I' : 'i');
737 
738 	if (req->req.length > 0x10000) {
739 		/* Lengths from 0 to 65536 (inclusive) are supported */
740 		DBG(DBG_ERR, "invalid request length %u\n", req->req.length);
741 		return -EINVAL;
742 	}
743 
744 	ret = usb_gadget_map_request(&udc->gadget, &req->req, ep->is_in);
745 	if (ret)
746 		return ret;
747 
748 	req->using_dma = 1;
749 	req->ctrl = USBA_BF(DMA_BUF_LEN, req->req.length)
750 			| USBA_DMA_CH_EN | USBA_DMA_END_BUF_IE
751 			| USBA_DMA_END_BUF_EN;
752 
753 	if (!ep->is_in)
754 		req->ctrl |= USBA_DMA_END_TR_EN | USBA_DMA_END_TR_IE;
755 
756 	/*
757 	 * Add this request to the queue and submit for DMA if
758 	 * possible. Check if we're still alive first -- we may have
759 	 * received a reset since last time we checked.
760 	 */
761 	ret = -ESHUTDOWN;
762 	spin_lock_irqsave(&udc->lock, flags);
763 	if (ep->ep.desc) {
764 		if (list_empty(&ep->queue))
765 			submit_request(ep, req);
766 
767 		list_add_tail(&req->queue, &ep->queue);
768 		ret = 0;
769 	}
770 	spin_unlock_irqrestore(&udc->lock, flags);
771 
772 	return ret;
773 }
774 
775 static int
776 usba_ep_queue(struct usb_ep *_ep, struct usb_request *_req, gfp_t gfp_flags)
777 {
778 	struct usba_request *req = to_usba_req(_req);
779 	struct usba_ep *ep = to_usba_ep(_ep);
780 	struct usba_udc *udc = ep->udc;
781 	unsigned long flags;
782 	int ret;
783 
784 	DBG(DBG_GADGET | DBG_QUEUE | DBG_REQ, "%s: queue req %p, len %u\n",
785 			ep->ep.name, req, _req->length);
786 
787 	if (!udc->driver || udc->gadget.speed == USB_SPEED_UNKNOWN ||
788 	    !ep->ep.desc)
789 		return -ESHUTDOWN;
790 
791 	req->submitted = 0;
792 	req->using_dma = 0;
793 	req->last_transaction = 0;
794 
795 	_req->status = -EINPROGRESS;
796 	_req->actual = 0;
797 
798 	if (ep->can_dma)
799 		return queue_dma(udc, ep, req, gfp_flags);
800 
801 	/* May have received a reset since last time we checked */
802 	ret = -ESHUTDOWN;
803 	spin_lock_irqsave(&udc->lock, flags);
804 	if (ep->ep.desc) {
805 		list_add_tail(&req->queue, &ep->queue);
806 
807 		if ((!ep_is_control(ep) && ep->is_in) ||
808 			(ep_is_control(ep)
809 				&& (ep->state == DATA_STAGE_IN
810 					|| ep->state == STATUS_STAGE_IN)))
811 			usba_ep_writel(ep, CTL_ENB, USBA_TX_PK_RDY);
812 		else
813 			usba_ep_writel(ep, CTL_ENB, USBA_RX_BK_RDY);
814 		ret = 0;
815 	}
816 	spin_unlock_irqrestore(&udc->lock, flags);
817 
818 	return ret;
819 }
820 
821 static void
822 usba_update_req(struct usba_ep *ep, struct usba_request *req, u32 status)
823 {
824 	req->req.actual = req->req.length - USBA_BFEXT(DMA_BUF_LEN, status);
825 }
826 
827 static int stop_dma(struct usba_ep *ep, u32 *pstatus)
828 {
829 	unsigned int timeout;
830 	u32 status;
831 
832 	/*
833 	 * Stop the DMA controller. When writing both CH_EN
834 	 * and LINK to 0, the other bits are not affected.
835 	 */
836 	usba_dma_writel(ep, CONTROL, 0);
837 
838 	/* Wait for the FIFO to empty */
839 	for (timeout = 40; timeout; --timeout) {
840 		status = usba_dma_readl(ep, STATUS);
841 		if (!(status & USBA_DMA_CH_EN))
842 			break;
843 		udelay(1);
844 	}
845 
846 	if (pstatus)
847 		*pstatus = status;
848 
849 	if (timeout == 0) {
850 		dev_err(&ep->udc->pdev->dev,
851 			"%s: timed out waiting for DMA FIFO to empty\n",
852 			ep->ep.name);
853 		return -ETIMEDOUT;
854 	}
855 
856 	return 0;
857 }
858 
859 static int usba_ep_dequeue(struct usb_ep *_ep, struct usb_request *_req)
860 {
861 	struct usba_ep *ep = to_usba_ep(_ep);
862 	struct usba_udc *udc = ep->udc;
863 	struct usba_request *req;
864 	unsigned long flags;
865 	u32 status;
866 
867 	DBG(DBG_GADGET | DBG_QUEUE, "ep_dequeue: %s, req %p\n",
868 			ep->ep.name, _req);
869 
870 	spin_lock_irqsave(&udc->lock, flags);
871 
872 	list_for_each_entry(req, &ep->queue, queue) {
873 		if (&req->req == _req)
874 			break;
875 	}
876 
877 	if (&req->req != _req) {
878 		spin_unlock_irqrestore(&udc->lock, flags);
879 		return -EINVAL;
880 	}
881 
882 	if (req->using_dma) {
883 		/*
884 		 * If this request is currently being transferred,
885 		 * stop the DMA controller and reset the FIFO.
886 		 */
887 		if (ep->queue.next == &req->queue) {
888 			status = usba_dma_readl(ep, STATUS);
889 			if (status & USBA_DMA_CH_EN)
890 				stop_dma(ep, &status);
891 
892 #ifdef CONFIG_USB_GADGET_DEBUG_FS
893 			ep->last_dma_status = status;
894 #endif
895 
896 			usba_writel(udc, EPT_RST, 1 << ep->index);
897 
898 			usba_update_req(ep, req, status);
899 		}
900 	}
901 
902 	/*
903 	 * Errors should stop the queue from advancing until the
904 	 * completion function returns.
905 	 */
906 	list_del_init(&req->queue);
907 
908 	request_complete(ep, req, -ECONNRESET);
909 
910 	/* Process the next request if any */
911 	submit_next_request(ep);
912 	spin_unlock_irqrestore(&udc->lock, flags);
913 
914 	return 0;
915 }
916 
917 static int usba_ep_set_halt(struct usb_ep *_ep, int value)
918 {
919 	struct usba_ep *ep = to_usba_ep(_ep);
920 	struct usba_udc *udc = ep->udc;
921 	unsigned long flags;
922 	int ret = 0;
923 
924 	DBG(DBG_GADGET, "endpoint %s: %s HALT\n", ep->ep.name,
925 			value ? "set" : "clear");
926 
927 	if (!ep->ep.desc) {
928 		DBG(DBG_ERR, "Attempted to halt uninitialized ep %s\n",
929 				ep->ep.name);
930 		return -ENODEV;
931 	}
932 	if (ep->is_isoc) {
933 		DBG(DBG_ERR, "Attempted to halt isochronous ep %s\n",
934 				ep->ep.name);
935 		return -ENOTTY;
936 	}
937 
938 	spin_lock_irqsave(&udc->lock, flags);
939 
940 	/*
941 	 * We can't halt IN endpoints while there are still data to be
942 	 * transferred
943 	 */
944 	if (!list_empty(&ep->queue)
945 			|| ((value && ep->is_in && (usba_ep_readl(ep, STA)
946 					& USBA_BF(BUSY_BANKS, -1L))))) {
947 		ret = -EAGAIN;
948 	} else {
949 		if (value)
950 			usba_ep_writel(ep, SET_STA, USBA_FORCE_STALL);
951 		else
952 			usba_ep_writel(ep, CLR_STA,
953 					USBA_FORCE_STALL | USBA_TOGGLE_CLR);
954 		usba_ep_readl(ep, STA);
955 	}
956 
957 	spin_unlock_irqrestore(&udc->lock, flags);
958 
959 	return ret;
960 }
961 
962 static int usba_ep_fifo_status(struct usb_ep *_ep)
963 {
964 	struct usba_ep *ep = to_usba_ep(_ep);
965 
966 	return USBA_BFEXT(BYTE_COUNT, usba_ep_readl(ep, STA));
967 }
968 
969 static void usba_ep_fifo_flush(struct usb_ep *_ep)
970 {
971 	struct usba_ep *ep = to_usba_ep(_ep);
972 	struct usba_udc *udc = ep->udc;
973 
974 	usba_writel(udc, EPT_RST, 1 << ep->index);
975 }
976 
977 static const struct usb_ep_ops usba_ep_ops = {
978 	.enable		= usba_ep_enable,
979 	.disable	= usba_ep_disable,
980 	.alloc_request	= usba_ep_alloc_request,
981 	.free_request	= usba_ep_free_request,
982 	.queue		= usba_ep_queue,
983 	.dequeue	= usba_ep_dequeue,
984 	.set_halt	= usba_ep_set_halt,
985 	.fifo_status	= usba_ep_fifo_status,
986 	.fifo_flush	= usba_ep_fifo_flush,
987 };
988 
989 static int usba_udc_get_frame(struct usb_gadget *gadget)
990 {
991 	struct usba_udc *udc = to_usba_udc(gadget);
992 
993 	return USBA_BFEXT(FRAME_NUMBER, usba_readl(udc, FNUM));
994 }
995 
996 static int usba_udc_wakeup(struct usb_gadget *gadget)
997 {
998 	struct usba_udc *udc = to_usba_udc(gadget);
999 	unsigned long flags;
1000 	u32 ctrl;
1001 	int ret = -EINVAL;
1002 
1003 	spin_lock_irqsave(&udc->lock, flags);
1004 	if (udc->devstatus & (1 << USB_DEVICE_REMOTE_WAKEUP)) {
1005 		ctrl = usba_readl(udc, CTRL);
1006 		usba_writel(udc, CTRL, ctrl | USBA_REMOTE_WAKE_UP);
1007 		ret = 0;
1008 	}
1009 	spin_unlock_irqrestore(&udc->lock, flags);
1010 
1011 	return ret;
1012 }
1013 
1014 static int
1015 usba_udc_set_selfpowered(struct usb_gadget *gadget, int is_selfpowered)
1016 {
1017 	struct usba_udc *udc = to_usba_udc(gadget);
1018 	unsigned long flags;
1019 
1020 	gadget->is_selfpowered = (is_selfpowered != 0);
1021 	spin_lock_irqsave(&udc->lock, flags);
1022 	if (is_selfpowered)
1023 		udc->devstatus |= 1 << USB_DEVICE_SELF_POWERED;
1024 	else
1025 		udc->devstatus &= ~(1 << USB_DEVICE_SELF_POWERED);
1026 	spin_unlock_irqrestore(&udc->lock, flags);
1027 
1028 	return 0;
1029 }
1030 
1031 static int atmel_usba_pullup(struct usb_gadget *gadget, int is_on);
1032 static int atmel_usba_start(struct usb_gadget *gadget,
1033 		struct usb_gadget_driver *driver);
1034 static int atmel_usba_stop(struct usb_gadget *gadget);
1035 
1036 static struct usb_ep *atmel_usba_match_ep(struct usb_gadget *gadget,
1037 				struct usb_endpoint_descriptor	*desc,
1038 				struct usb_ss_ep_comp_descriptor *ep_comp)
1039 {
1040 	struct usb_ep	*_ep;
1041 	struct usba_ep *ep;
1042 
1043 	/* Look at endpoints until an unclaimed one looks usable */
1044 	list_for_each_entry(_ep, &gadget->ep_list, ep_list) {
1045 		if (usb_gadget_ep_match_desc(gadget, _ep, desc, ep_comp))
1046 			goto found_ep;
1047 	}
1048 	/* Fail */
1049 	return NULL;
1050 
1051 found_ep:
1052 
1053 	if (fifo_mode == 0) {
1054 		/* Optimize hw fifo size based on ep type and other info */
1055 		ep = to_usba_ep(_ep);
1056 
1057 		switch (usb_endpoint_type(desc)) {
1058 		case USB_ENDPOINT_XFER_CONTROL:
1059 			break;
1060 
1061 		case USB_ENDPOINT_XFER_ISOC:
1062 			ep->fifo_size = 1024;
1063 			ep->nr_banks = 2;
1064 			break;
1065 
1066 		case USB_ENDPOINT_XFER_BULK:
1067 			ep->fifo_size = 512;
1068 			ep->nr_banks = 1;
1069 			break;
1070 
1071 		case USB_ENDPOINT_XFER_INT:
1072 			if (desc->wMaxPacketSize == 0)
1073 				ep->fifo_size =
1074 				    roundup_pow_of_two(_ep->maxpacket_limit);
1075 			else
1076 				ep->fifo_size =
1077 				    roundup_pow_of_two(le16_to_cpu(desc->wMaxPacketSize));
1078 			ep->nr_banks = 1;
1079 			break;
1080 		}
1081 
1082 		/* It might be a little bit late to set this */
1083 		usb_ep_set_maxpacket_limit(&ep->ep, ep->fifo_size);
1084 
1085 		/* Generate ept_cfg basd on FIFO size and number of banks */
1086 		if (ep->fifo_size  <= 8)
1087 			ep->ept_cfg = USBA_BF(EPT_SIZE, USBA_EPT_SIZE_8);
1088 		else
1089 			/* LSB is bit 1, not 0 */
1090 			ep->ept_cfg =
1091 				USBA_BF(EPT_SIZE, fls(ep->fifo_size - 1) - 3);
1092 
1093 		ep->ept_cfg |= USBA_BF(BK_NUMBER, ep->nr_banks);
1094 
1095 		ep->udc->configured_ep++;
1096 	}
1097 
1098 	return _ep;
1099 }
1100 
1101 static const struct usb_gadget_ops usba_udc_ops = {
1102 	.get_frame		= usba_udc_get_frame,
1103 	.wakeup			= usba_udc_wakeup,
1104 	.set_selfpowered	= usba_udc_set_selfpowered,
1105 	.pullup			= atmel_usba_pullup,
1106 	.udc_start		= atmel_usba_start,
1107 	.udc_stop		= atmel_usba_stop,
1108 	.match_ep		= atmel_usba_match_ep,
1109 };
1110 
1111 static struct usb_endpoint_descriptor usba_ep0_desc = {
1112 	.bLength = USB_DT_ENDPOINT_SIZE,
1113 	.bDescriptorType = USB_DT_ENDPOINT,
1114 	.bEndpointAddress = 0,
1115 	.bmAttributes = USB_ENDPOINT_XFER_CONTROL,
1116 	.wMaxPacketSize = cpu_to_le16(64),
1117 	/* FIXME: I have no idea what to put here */
1118 	.bInterval = 1,
1119 };
1120 
1121 static const struct usb_gadget usba_gadget_template = {
1122 	.ops		= &usba_udc_ops,
1123 	.max_speed	= USB_SPEED_HIGH,
1124 	.name		= "atmel_usba_udc",
1125 };
1126 
1127 /*
1128  * Called with interrupts disabled and udc->lock held.
1129  */
1130 static void reset_all_endpoints(struct usba_udc *udc)
1131 {
1132 	struct usba_ep *ep;
1133 	struct usba_request *req, *tmp_req;
1134 
1135 	usba_writel(udc, EPT_RST, ~0UL);
1136 
1137 	ep = to_usba_ep(udc->gadget.ep0);
1138 	list_for_each_entry_safe(req, tmp_req, &ep->queue, queue) {
1139 		list_del_init(&req->queue);
1140 		request_complete(ep, req, -ECONNRESET);
1141 	}
1142 }
1143 
1144 static struct usba_ep *get_ep_by_addr(struct usba_udc *udc, u16 wIndex)
1145 {
1146 	struct usba_ep *ep;
1147 
1148 	if ((wIndex & USB_ENDPOINT_NUMBER_MASK) == 0)
1149 		return to_usba_ep(udc->gadget.ep0);
1150 
1151 	list_for_each_entry (ep, &udc->gadget.ep_list, ep.ep_list) {
1152 		u8 bEndpointAddress;
1153 
1154 		if (!ep->ep.desc)
1155 			continue;
1156 		bEndpointAddress = ep->ep.desc->bEndpointAddress;
1157 		if ((wIndex ^ bEndpointAddress) & USB_DIR_IN)
1158 			continue;
1159 		if ((bEndpointAddress & USB_ENDPOINT_NUMBER_MASK)
1160 				== (wIndex & USB_ENDPOINT_NUMBER_MASK))
1161 			return ep;
1162 	}
1163 
1164 	return NULL;
1165 }
1166 
1167 /* Called with interrupts disabled and udc->lock held */
1168 static inline void set_protocol_stall(struct usba_udc *udc, struct usba_ep *ep)
1169 {
1170 	usba_ep_writel(ep, SET_STA, USBA_FORCE_STALL);
1171 	ep->state = WAIT_FOR_SETUP;
1172 }
1173 
1174 static inline int is_stalled(struct usba_udc *udc, struct usba_ep *ep)
1175 {
1176 	if (usba_ep_readl(ep, STA) & USBA_FORCE_STALL)
1177 		return 1;
1178 	return 0;
1179 }
1180 
1181 static inline void set_address(struct usba_udc *udc, unsigned int addr)
1182 {
1183 	u32 regval;
1184 
1185 	DBG(DBG_BUS, "setting address %u...\n", addr);
1186 	regval = usba_readl(udc, CTRL);
1187 	regval = USBA_BFINS(DEV_ADDR, addr, regval);
1188 	usba_writel(udc, CTRL, regval);
1189 }
1190 
1191 static int do_test_mode(struct usba_udc *udc)
1192 {
1193 	static const char test_packet_buffer[] = {
1194 		/* JKJKJKJK * 9 */
1195 		0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
1196 		/* JJKKJJKK * 8 */
1197 		0xAA, 0xAA, 0xAA, 0xAA, 0xAA, 0xAA, 0xAA, 0xAA,
1198 		/* JJKKJJKK * 8 */
1199 		0xEE, 0xEE, 0xEE, 0xEE, 0xEE, 0xEE, 0xEE, 0xEE,
1200 		/* JJJJJJJKKKKKKK * 8 */
1201 		0xFE, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF,
1202 		0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF,
1203 		/* JJJJJJJK * 8 */
1204 		0x7F, 0xBF, 0xDF, 0xEF, 0xF7, 0xFB, 0xFD,
1205 		/* {JKKKKKKK * 10}, JK */
1206 		0xFC, 0x7E, 0xBF, 0xDF, 0xEF, 0xF7, 0xFB, 0xFD, 0x7E
1207 	};
1208 	struct usba_ep *ep;
1209 	struct device *dev = &udc->pdev->dev;
1210 	int test_mode;
1211 
1212 	test_mode = udc->test_mode;
1213 
1214 	/* Start from a clean slate */
1215 	reset_all_endpoints(udc);
1216 
1217 	switch (test_mode) {
1218 	case 0x0100:
1219 		/* Test_J */
1220 		usba_writel(udc, TST, USBA_TST_J_MODE);
1221 		dev_info(dev, "Entering Test_J mode...\n");
1222 		break;
1223 	case 0x0200:
1224 		/* Test_K */
1225 		usba_writel(udc, TST, USBA_TST_K_MODE);
1226 		dev_info(dev, "Entering Test_K mode...\n");
1227 		break;
1228 	case 0x0300:
1229 		/*
1230 		 * Test_SE0_NAK: Force high-speed mode and set up ep0
1231 		 * for Bulk IN transfers
1232 		 */
1233 		ep = &udc->usba_ep[0];
1234 		usba_writel(udc, TST,
1235 				USBA_BF(SPEED_CFG, USBA_SPEED_CFG_FORCE_HIGH));
1236 		usba_ep_writel(ep, CFG,
1237 				USBA_BF(EPT_SIZE, USBA_EPT_SIZE_64)
1238 				| USBA_EPT_DIR_IN
1239 				| USBA_BF(EPT_TYPE, USBA_EPT_TYPE_BULK)
1240 				| USBA_BF(BK_NUMBER, 1));
1241 		if (!(usba_ep_readl(ep, CFG) & USBA_EPT_MAPPED)) {
1242 			set_protocol_stall(udc, ep);
1243 			dev_err(dev, "Test_SE0_NAK: ep0 not mapped\n");
1244 		} else {
1245 			usba_ep_writel(ep, CTL_ENB, USBA_EPT_ENABLE);
1246 			dev_info(dev, "Entering Test_SE0_NAK mode...\n");
1247 		}
1248 		break;
1249 	case 0x0400:
1250 		/* Test_Packet */
1251 		ep = &udc->usba_ep[0];
1252 		usba_ep_writel(ep, CFG,
1253 				USBA_BF(EPT_SIZE, USBA_EPT_SIZE_64)
1254 				| USBA_EPT_DIR_IN
1255 				| USBA_BF(EPT_TYPE, USBA_EPT_TYPE_BULK)
1256 				| USBA_BF(BK_NUMBER, 1));
1257 		if (!(usba_ep_readl(ep, CFG) & USBA_EPT_MAPPED)) {
1258 			set_protocol_stall(udc, ep);
1259 			dev_err(dev, "Test_Packet: ep0 not mapped\n");
1260 		} else {
1261 			usba_ep_writel(ep, CTL_ENB, USBA_EPT_ENABLE);
1262 			usba_writel(udc, TST, USBA_TST_PKT_MODE);
1263 			memcpy_toio(ep->fifo, test_packet_buffer,
1264 					sizeof(test_packet_buffer));
1265 			usba_ep_writel(ep, SET_STA, USBA_TX_PK_RDY);
1266 			dev_info(dev, "Entering Test_Packet mode...\n");
1267 		}
1268 		break;
1269 	default:
1270 		dev_err(dev, "Invalid test mode: 0x%04x\n", test_mode);
1271 		return -EINVAL;
1272 	}
1273 
1274 	return 0;
1275 }
1276 
1277 /* Avoid overly long expressions */
1278 static inline bool feature_is_dev_remote_wakeup(struct usb_ctrlrequest *crq)
1279 {
1280 	if (crq->wValue == cpu_to_le16(USB_DEVICE_REMOTE_WAKEUP))
1281 		return true;
1282 	return false;
1283 }
1284 
1285 static inline bool feature_is_dev_test_mode(struct usb_ctrlrequest *crq)
1286 {
1287 	if (crq->wValue == cpu_to_le16(USB_DEVICE_TEST_MODE))
1288 		return true;
1289 	return false;
1290 }
1291 
1292 static inline bool feature_is_ep_halt(struct usb_ctrlrequest *crq)
1293 {
1294 	if (crq->wValue == cpu_to_le16(USB_ENDPOINT_HALT))
1295 		return true;
1296 	return false;
1297 }
1298 
1299 static int handle_ep0_setup(struct usba_udc *udc, struct usba_ep *ep,
1300 		struct usb_ctrlrequest *crq)
1301 {
1302 	int retval = 0;
1303 
1304 	switch (crq->bRequest) {
1305 	case USB_REQ_GET_STATUS: {
1306 		u16 status;
1307 
1308 		if (crq->bRequestType == (USB_DIR_IN | USB_RECIP_DEVICE)) {
1309 			status = cpu_to_le16(udc->devstatus);
1310 		} else if (crq->bRequestType
1311 				== (USB_DIR_IN | USB_RECIP_INTERFACE)) {
1312 			status = cpu_to_le16(0);
1313 		} else if (crq->bRequestType
1314 				== (USB_DIR_IN | USB_RECIP_ENDPOINT)) {
1315 			struct usba_ep *target;
1316 
1317 			target = get_ep_by_addr(udc, le16_to_cpu(crq->wIndex));
1318 			if (!target)
1319 				goto stall;
1320 
1321 			status = 0;
1322 			if (is_stalled(udc, target))
1323 				status |= cpu_to_le16(1);
1324 		} else
1325 			goto delegate;
1326 
1327 		/* Write directly to the FIFO. No queueing is done. */
1328 		if (crq->wLength != cpu_to_le16(sizeof(status)))
1329 			goto stall;
1330 		ep->state = DATA_STAGE_IN;
1331 		writew_relaxed(status, ep->fifo);
1332 		usba_ep_writel(ep, SET_STA, USBA_TX_PK_RDY);
1333 		break;
1334 	}
1335 
1336 	case USB_REQ_CLEAR_FEATURE: {
1337 		if (crq->bRequestType == USB_RECIP_DEVICE) {
1338 			if (feature_is_dev_remote_wakeup(crq))
1339 				udc->devstatus
1340 					&= ~(1 << USB_DEVICE_REMOTE_WAKEUP);
1341 			else
1342 				/* Can't CLEAR_FEATURE TEST_MODE */
1343 				goto stall;
1344 		} else if (crq->bRequestType == USB_RECIP_ENDPOINT) {
1345 			struct usba_ep *target;
1346 
1347 			if (crq->wLength != cpu_to_le16(0)
1348 					|| !feature_is_ep_halt(crq))
1349 				goto stall;
1350 			target = get_ep_by_addr(udc, le16_to_cpu(crq->wIndex));
1351 			if (!target)
1352 				goto stall;
1353 
1354 			usba_ep_writel(target, CLR_STA, USBA_FORCE_STALL);
1355 			if (target->index != 0)
1356 				usba_ep_writel(target, CLR_STA,
1357 						USBA_TOGGLE_CLR);
1358 		} else {
1359 			goto delegate;
1360 		}
1361 
1362 		send_status(udc, ep);
1363 		break;
1364 	}
1365 
1366 	case USB_REQ_SET_FEATURE: {
1367 		if (crq->bRequestType == USB_RECIP_DEVICE) {
1368 			if (feature_is_dev_test_mode(crq)) {
1369 				send_status(udc, ep);
1370 				ep->state = STATUS_STAGE_TEST;
1371 				udc->test_mode = le16_to_cpu(crq->wIndex);
1372 				return 0;
1373 			} else if (feature_is_dev_remote_wakeup(crq)) {
1374 				udc->devstatus |= 1 << USB_DEVICE_REMOTE_WAKEUP;
1375 			} else {
1376 				goto stall;
1377 			}
1378 		} else if (crq->bRequestType == USB_RECIP_ENDPOINT) {
1379 			struct usba_ep *target;
1380 
1381 			if (crq->wLength != cpu_to_le16(0)
1382 					|| !feature_is_ep_halt(crq))
1383 				goto stall;
1384 
1385 			target = get_ep_by_addr(udc, le16_to_cpu(crq->wIndex));
1386 			if (!target)
1387 				goto stall;
1388 
1389 			usba_ep_writel(target, SET_STA, USBA_FORCE_STALL);
1390 		} else
1391 			goto delegate;
1392 
1393 		send_status(udc, ep);
1394 		break;
1395 	}
1396 
1397 	case USB_REQ_SET_ADDRESS:
1398 		if (crq->bRequestType != (USB_DIR_OUT | USB_RECIP_DEVICE))
1399 			goto delegate;
1400 
1401 		set_address(udc, le16_to_cpu(crq->wValue));
1402 		send_status(udc, ep);
1403 		ep->state = STATUS_STAGE_ADDR;
1404 		break;
1405 
1406 	default:
1407 delegate:
1408 		spin_unlock(&udc->lock);
1409 		retval = udc->driver->setup(&udc->gadget, crq);
1410 		spin_lock(&udc->lock);
1411 	}
1412 
1413 	return retval;
1414 
1415 stall:
1416 	pr_err("udc: %s: Invalid setup request: %02x.%02x v%04x i%04x l%d, "
1417 		"halting endpoint...\n",
1418 		ep->ep.name, crq->bRequestType, crq->bRequest,
1419 		le16_to_cpu(crq->wValue), le16_to_cpu(crq->wIndex),
1420 		le16_to_cpu(crq->wLength));
1421 	set_protocol_stall(udc, ep);
1422 	return -1;
1423 }
1424 
1425 static void usba_control_irq(struct usba_udc *udc, struct usba_ep *ep)
1426 {
1427 	struct usba_request *req;
1428 	u32 epstatus;
1429 	u32 epctrl;
1430 
1431 restart:
1432 	epstatus = usba_ep_readl(ep, STA);
1433 	epctrl = usba_ep_readl(ep, CTL);
1434 
1435 	DBG(DBG_INT, "%s [%d]: s/%08x c/%08x\n",
1436 			ep->ep.name, ep->state, epstatus, epctrl);
1437 
1438 	req = NULL;
1439 	if (!list_empty(&ep->queue))
1440 		req = list_entry(ep->queue.next,
1441 				 struct usba_request, queue);
1442 
1443 	if ((epctrl & USBA_TX_PK_RDY) && !(epstatus & USBA_TX_PK_RDY)) {
1444 		if (req->submitted)
1445 			next_fifo_transaction(ep, req);
1446 		else
1447 			submit_request(ep, req);
1448 
1449 		if (req->last_transaction) {
1450 			usba_ep_writel(ep, CTL_DIS, USBA_TX_PK_RDY);
1451 			usba_ep_writel(ep, CTL_ENB, USBA_TX_COMPLETE);
1452 		}
1453 		goto restart;
1454 	}
1455 	if ((epstatus & epctrl) & USBA_TX_COMPLETE) {
1456 		usba_ep_writel(ep, CLR_STA, USBA_TX_COMPLETE);
1457 
1458 		switch (ep->state) {
1459 		case DATA_STAGE_IN:
1460 			usba_ep_writel(ep, CTL_ENB, USBA_RX_BK_RDY);
1461 			usba_ep_writel(ep, CTL_DIS, USBA_TX_COMPLETE);
1462 			ep->state = STATUS_STAGE_OUT;
1463 			break;
1464 		case STATUS_STAGE_ADDR:
1465 			/* Activate our new address */
1466 			usba_writel(udc, CTRL, (usba_readl(udc, CTRL)
1467 						| USBA_FADDR_EN));
1468 			usba_ep_writel(ep, CTL_DIS, USBA_TX_COMPLETE);
1469 			ep->state = WAIT_FOR_SETUP;
1470 			break;
1471 		case STATUS_STAGE_IN:
1472 			if (req) {
1473 				list_del_init(&req->queue);
1474 				request_complete(ep, req, 0);
1475 				submit_next_request(ep);
1476 			}
1477 			usba_ep_writel(ep, CTL_DIS, USBA_TX_COMPLETE);
1478 			ep->state = WAIT_FOR_SETUP;
1479 			break;
1480 		case STATUS_STAGE_TEST:
1481 			usba_ep_writel(ep, CTL_DIS, USBA_TX_COMPLETE);
1482 			ep->state = WAIT_FOR_SETUP;
1483 			if (do_test_mode(udc))
1484 				set_protocol_stall(udc, ep);
1485 			break;
1486 		default:
1487 			pr_err("udc: %s: TXCOMP: Invalid endpoint state %d, "
1488 				"halting endpoint...\n",
1489 				ep->ep.name, ep->state);
1490 			set_protocol_stall(udc, ep);
1491 			break;
1492 		}
1493 
1494 		goto restart;
1495 	}
1496 	if ((epstatus & epctrl) & USBA_RX_BK_RDY) {
1497 		switch (ep->state) {
1498 		case STATUS_STAGE_OUT:
1499 			usba_ep_writel(ep, CLR_STA, USBA_RX_BK_RDY);
1500 			usba_ep_writel(ep, CTL_DIS, USBA_RX_BK_RDY);
1501 
1502 			if (req) {
1503 				list_del_init(&req->queue);
1504 				request_complete(ep, req, 0);
1505 			}
1506 			ep->state = WAIT_FOR_SETUP;
1507 			break;
1508 
1509 		case DATA_STAGE_OUT:
1510 			receive_data(ep);
1511 			break;
1512 
1513 		default:
1514 			usba_ep_writel(ep, CLR_STA, USBA_RX_BK_RDY);
1515 			usba_ep_writel(ep, CTL_DIS, USBA_RX_BK_RDY);
1516 			pr_err("udc: %s: RXRDY: Invalid endpoint state %d, "
1517 				"halting endpoint...\n",
1518 				ep->ep.name, ep->state);
1519 			set_protocol_stall(udc, ep);
1520 			break;
1521 		}
1522 
1523 		goto restart;
1524 	}
1525 	if (epstatus & USBA_RX_SETUP) {
1526 		union {
1527 			struct usb_ctrlrequest crq;
1528 			unsigned long data[2];
1529 		} crq;
1530 		unsigned int pkt_len;
1531 		int ret;
1532 
1533 		if (ep->state != WAIT_FOR_SETUP) {
1534 			/*
1535 			 * Didn't expect a SETUP packet at this
1536 			 * point. Clean up any pending requests (which
1537 			 * may be successful).
1538 			 */
1539 			int status = -EPROTO;
1540 
1541 			/*
1542 			 * RXRDY and TXCOMP are dropped when SETUP
1543 			 * packets arrive.  Just pretend we received
1544 			 * the status packet.
1545 			 */
1546 			if (ep->state == STATUS_STAGE_OUT
1547 					|| ep->state == STATUS_STAGE_IN) {
1548 				usba_ep_writel(ep, CTL_DIS, USBA_RX_BK_RDY);
1549 				status = 0;
1550 			}
1551 
1552 			if (req) {
1553 				list_del_init(&req->queue);
1554 				request_complete(ep, req, status);
1555 			}
1556 		}
1557 
1558 		pkt_len = USBA_BFEXT(BYTE_COUNT, usba_ep_readl(ep, STA));
1559 		DBG(DBG_HW, "Packet length: %u\n", pkt_len);
1560 		if (pkt_len != sizeof(crq)) {
1561 			pr_warn("udc: Invalid packet length %u (expected %zu)\n",
1562 				pkt_len, sizeof(crq));
1563 			set_protocol_stall(udc, ep);
1564 			return;
1565 		}
1566 
1567 		DBG(DBG_FIFO, "Copying ctrl request from 0x%p:\n", ep->fifo);
1568 		memcpy_fromio(crq.data, ep->fifo, sizeof(crq));
1569 
1570 		/* Free up one bank in the FIFO so that we can
1571 		 * generate or receive a reply right away. */
1572 		usba_ep_writel(ep, CLR_STA, USBA_RX_SETUP);
1573 
1574 		/* printk(KERN_DEBUG "setup: %d: %02x.%02x\n",
1575 			ep->state, crq.crq.bRequestType,
1576 			crq.crq.bRequest); */
1577 
1578 		if (crq.crq.bRequestType & USB_DIR_IN) {
1579 			/*
1580 			 * The USB 2.0 spec states that "if wLength is
1581 			 * zero, there is no data transfer phase."
1582 			 * However, testusb #14 seems to actually
1583 			 * expect a data phase even if wLength = 0...
1584 			 */
1585 			ep->state = DATA_STAGE_IN;
1586 		} else {
1587 			if (crq.crq.wLength != cpu_to_le16(0))
1588 				ep->state = DATA_STAGE_OUT;
1589 			else
1590 				ep->state = STATUS_STAGE_IN;
1591 		}
1592 
1593 		ret = -1;
1594 		if (ep->index == 0)
1595 			ret = handle_ep0_setup(udc, ep, &crq.crq);
1596 		else {
1597 			spin_unlock(&udc->lock);
1598 			ret = udc->driver->setup(&udc->gadget, &crq.crq);
1599 			spin_lock(&udc->lock);
1600 		}
1601 
1602 		DBG(DBG_BUS, "req %02x.%02x, length %d, state %d, ret %d\n",
1603 			crq.crq.bRequestType, crq.crq.bRequest,
1604 			le16_to_cpu(crq.crq.wLength), ep->state, ret);
1605 
1606 		if (ret < 0) {
1607 			/* Let the host know that we failed */
1608 			set_protocol_stall(udc, ep);
1609 		}
1610 	}
1611 }
1612 
1613 static void usba_ep_irq(struct usba_udc *udc, struct usba_ep *ep)
1614 {
1615 	struct usba_request *req;
1616 	u32 epstatus;
1617 	u32 epctrl;
1618 
1619 	epstatus = usba_ep_readl(ep, STA);
1620 	epctrl = usba_ep_readl(ep, CTL);
1621 
1622 	DBG(DBG_INT, "%s: interrupt, status: 0x%08x\n", ep->ep.name, epstatus);
1623 
1624 	while ((epctrl & USBA_TX_PK_RDY) && !(epstatus & USBA_TX_PK_RDY)) {
1625 		DBG(DBG_BUS, "%s: TX PK ready\n", ep->ep.name);
1626 
1627 		if (list_empty(&ep->queue)) {
1628 			dev_warn(&udc->pdev->dev, "ep_irq: queue empty\n");
1629 			usba_ep_writel(ep, CTL_DIS, USBA_TX_PK_RDY);
1630 			return;
1631 		}
1632 
1633 		req = list_entry(ep->queue.next, struct usba_request, queue);
1634 
1635 		if (req->using_dma) {
1636 			/* Send a zero-length packet */
1637 			usba_ep_writel(ep, SET_STA,
1638 					USBA_TX_PK_RDY);
1639 			usba_ep_writel(ep, CTL_DIS,
1640 					USBA_TX_PK_RDY);
1641 			list_del_init(&req->queue);
1642 			submit_next_request(ep);
1643 			request_complete(ep, req, 0);
1644 		} else {
1645 			if (req->submitted)
1646 				next_fifo_transaction(ep, req);
1647 			else
1648 				submit_request(ep, req);
1649 
1650 			if (req->last_transaction) {
1651 				list_del_init(&req->queue);
1652 				submit_next_request(ep);
1653 				request_complete(ep, req, 0);
1654 			}
1655 		}
1656 
1657 		epstatus = usba_ep_readl(ep, STA);
1658 		epctrl = usba_ep_readl(ep, CTL);
1659 	}
1660 	if ((epstatus & epctrl) & USBA_RX_BK_RDY) {
1661 		DBG(DBG_BUS, "%s: RX data ready\n", ep->ep.name);
1662 		receive_data(ep);
1663 	}
1664 }
1665 
1666 static void usba_dma_irq(struct usba_udc *udc, struct usba_ep *ep)
1667 {
1668 	struct usba_request *req;
1669 	u32 status, control, pending;
1670 
1671 	status = usba_dma_readl(ep, STATUS);
1672 	control = usba_dma_readl(ep, CONTROL);
1673 #ifdef CONFIG_USB_GADGET_DEBUG_FS
1674 	ep->last_dma_status = status;
1675 #endif
1676 	pending = status & control;
1677 	DBG(DBG_INT | DBG_DMA, "dma irq, s/%#08x, c/%#08x\n", status, control);
1678 
1679 	if (status & USBA_DMA_CH_EN) {
1680 		dev_err(&udc->pdev->dev,
1681 			"DMA_CH_EN is set after transfer is finished!\n");
1682 		dev_err(&udc->pdev->dev,
1683 			"status=%#08x, pending=%#08x, control=%#08x\n",
1684 			status, pending, control);
1685 
1686 		/*
1687 		 * try to pretend nothing happened. We might have to
1688 		 * do something here...
1689 		 */
1690 	}
1691 
1692 	if (list_empty(&ep->queue))
1693 		/* Might happen if a reset comes along at the right moment */
1694 		return;
1695 
1696 	if (pending & (USBA_DMA_END_TR_ST | USBA_DMA_END_BUF_ST)) {
1697 		req = list_entry(ep->queue.next, struct usba_request, queue);
1698 		usba_update_req(ep, req, status);
1699 
1700 		list_del_init(&req->queue);
1701 		submit_next_request(ep);
1702 		request_complete(ep, req, 0);
1703 	}
1704 }
1705 
1706 static int start_clock(struct usba_udc *udc);
1707 static void stop_clock(struct usba_udc *udc);
1708 
1709 static irqreturn_t usba_udc_irq(int irq, void *devid)
1710 {
1711 	struct usba_udc *udc = devid;
1712 	u32 status, int_enb;
1713 	u32 dma_status;
1714 	u32 ep_status;
1715 
1716 	spin_lock(&udc->lock);
1717 
1718 	int_enb = usba_int_enb_get(udc);
1719 	status = usba_readl(udc, INT_STA) & (int_enb | USBA_HIGH_SPEED);
1720 	DBG(DBG_INT, "irq, status=%#08x\n", status);
1721 
1722 	if (status & USBA_DET_SUSPEND) {
1723 		usba_writel(udc, INT_CLR, USBA_DET_SUSPEND|USBA_WAKE_UP);
1724 		usba_int_enb_set(udc, USBA_WAKE_UP);
1725 		usba_int_enb_clear(udc, USBA_DET_SUSPEND);
1726 		udc->suspended = true;
1727 		toggle_bias(udc, 0);
1728 		udc->bias_pulse_needed = true;
1729 		stop_clock(udc);
1730 		DBG(DBG_BUS, "Suspend detected\n");
1731 		if (udc->gadget.speed != USB_SPEED_UNKNOWN
1732 				&& udc->driver && udc->driver->suspend) {
1733 			spin_unlock(&udc->lock);
1734 			udc->driver->suspend(&udc->gadget);
1735 			spin_lock(&udc->lock);
1736 		}
1737 	}
1738 
1739 	if (status & USBA_WAKE_UP) {
1740 		start_clock(udc);
1741 		toggle_bias(udc, 1);
1742 		usba_writel(udc, INT_CLR, USBA_WAKE_UP);
1743 		DBG(DBG_BUS, "Wake Up CPU detected\n");
1744 	}
1745 
1746 	if (status & USBA_END_OF_RESUME) {
1747 		udc->suspended = false;
1748 		usba_writel(udc, INT_CLR, USBA_END_OF_RESUME);
1749 		usba_int_enb_clear(udc, USBA_WAKE_UP);
1750 		usba_int_enb_set(udc, USBA_DET_SUSPEND);
1751 		generate_bias_pulse(udc);
1752 		DBG(DBG_BUS, "Resume detected\n");
1753 		if (udc->gadget.speed != USB_SPEED_UNKNOWN
1754 				&& udc->driver && udc->driver->resume) {
1755 			spin_unlock(&udc->lock);
1756 			udc->driver->resume(&udc->gadget);
1757 			spin_lock(&udc->lock);
1758 		}
1759 	}
1760 
1761 	dma_status = USBA_BFEXT(DMA_INT, status);
1762 	if (dma_status) {
1763 		int i;
1764 
1765 		usba_int_enb_set(udc, USBA_DET_SUSPEND);
1766 
1767 		for (i = 1; i <= USBA_NR_DMAS; i++)
1768 			if (dma_status & (1 << i))
1769 				usba_dma_irq(udc, &udc->usba_ep[i]);
1770 	}
1771 
1772 	ep_status = USBA_BFEXT(EPT_INT, status);
1773 	if (ep_status) {
1774 		int i;
1775 
1776 		usba_int_enb_set(udc, USBA_DET_SUSPEND);
1777 
1778 		for (i = 0; i < udc->num_ep; i++)
1779 			if (ep_status & (1 << i)) {
1780 				if (ep_is_control(&udc->usba_ep[i]))
1781 					usba_control_irq(udc, &udc->usba_ep[i]);
1782 				else
1783 					usba_ep_irq(udc, &udc->usba_ep[i]);
1784 			}
1785 	}
1786 
1787 	if (status & USBA_END_OF_RESET) {
1788 		struct usba_ep *ep0, *ep;
1789 		int i, n;
1790 
1791 		usba_writel(udc, INT_CLR,
1792 			USBA_END_OF_RESET|USBA_END_OF_RESUME
1793 			|USBA_DET_SUSPEND|USBA_WAKE_UP);
1794 		generate_bias_pulse(udc);
1795 		reset_all_endpoints(udc);
1796 
1797 		if (udc->gadget.speed != USB_SPEED_UNKNOWN && udc->driver) {
1798 			udc->gadget.speed = USB_SPEED_UNKNOWN;
1799 			spin_unlock(&udc->lock);
1800 			usb_gadget_udc_reset(&udc->gadget, udc->driver);
1801 			spin_lock(&udc->lock);
1802 		}
1803 
1804 		if (status & USBA_HIGH_SPEED)
1805 			udc->gadget.speed = USB_SPEED_HIGH;
1806 		else
1807 			udc->gadget.speed = USB_SPEED_FULL;
1808 		DBG(DBG_BUS, "%s bus reset detected\n",
1809 		    usb_speed_string(udc->gadget.speed));
1810 
1811 		ep0 = &udc->usba_ep[0];
1812 		ep0->ep.desc = &usba_ep0_desc;
1813 		ep0->state = WAIT_FOR_SETUP;
1814 		usba_ep_writel(ep0, CFG,
1815 				(USBA_BF(EPT_SIZE, EP0_EPT_SIZE)
1816 				| USBA_BF(EPT_TYPE, USBA_EPT_TYPE_CONTROL)
1817 				| USBA_BF(BK_NUMBER, USBA_BK_NUMBER_ONE)));
1818 		usba_ep_writel(ep0, CTL_ENB,
1819 				USBA_EPT_ENABLE | USBA_RX_SETUP);
1820 
1821 		/* If we get reset while suspended... */
1822 		udc->suspended = false;
1823 		usba_int_enb_clear(udc, USBA_WAKE_UP);
1824 
1825 		usba_int_enb_set(udc, USBA_BF(EPT_INT, 1) |
1826 				      USBA_DET_SUSPEND | USBA_END_OF_RESUME);
1827 
1828 		/*
1829 		 * Unclear why we hit this irregularly, e.g. in usbtest,
1830 		 * but it's clearly harmless...
1831 		 */
1832 		if (!(usba_ep_readl(ep0, CFG) & USBA_EPT_MAPPED))
1833 			dev_err(&udc->pdev->dev,
1834 				"ODD: EP0 configuration is invalid!\n");
1835 
1836 		/* Preallocate other endpoints */
1837 		n = fifo_mode ? udc->num_ep : udc->configured_ep;
1838 		for (i = 1; i < n; i++) {
1839 			ep = &udc->usba_ep[i];
1840 			usba_ep_writel(ep, CFG, ep->ept_cfg);
1841 			if (!(usba_ep_readl(ep, CFG) & USBA_EPT_MAPPED))
1842 				dev_err(&udc->pdev->dev,
1843 					"ODD: EP%d configuration is invalid!\n", i);
1844 		}
1845 	}
1846 
1847 	spin_unlock(&udc->lock);
1848 
1849 	return IRQ_HANDLED;
1850 }
1851 
1852 static int start_clock(struct usba_udc *udc)
1853 {
1854 	int ret;
1855 
1856 	if (udc->clocked)
1857 		return 0;
1858 
1859 	pm_stay_awake(&udc->pdev->dev);
1860 
1861 	ret = clk_prepare_enable(udc->pclk);
1862 	if (ret)
1863 		return ret;
1864 	ret = clk_prepare_enable(udc->hclk);
1865 	if (ret) {
1866 		clk_disable_unprepare(udc->pclk);
1867 		return ret;
1868 	}
1869 
1870 	udc->clocked = true;
1871 	return 0;
1872 }
1873 
1874 static void stop_clock(struct usba_udc *udc)
1875 {
1876 	if (!udc->clocked)
1877 		return;
1878 
1879 	clk_disable_unprepare(udc->hclk);
1880 	clk_disable_unprepare(udc->pclk);
1881 
1882 	udc->clocked = false;
1883 
1884 	pm_relax(&udc->pdev->dev);
1885 }
1886 
1887 static int usba_start(struct usba_udc *udc)
1888 {
1889 	unsigned long flags;
1890 	int ret;
1891 
1892 	ret = start_clock(udc);
1893 	if (ret)
1894 		return ret;
1895 
1896 	if (udc->suspended)
1897 		return 0;
1898 
1899 	spin_lock_irqsave(&udc->lock, flags);
1900 	toggle_bias(udc, 1);
1901 	usba_writel(udc, CTRL, USBA_ENABLE_MASK);
1902 	/* Clear all requested and pending interrupts... */
1903 	usba_writel(udc, INT_ENB, 0);
1904 	udc->int_enb_cache = 0;
1905 	usba_writel(udc, INT_CLR,
1906 		USBA_END_OF_RESET|USBA_END_OF_RESUME
1907 		|USBA_DET_SUSPEND|USBA_WAKE_UP);
1908 	/* ...and enable just 'reset' IRQ to get us started */
1909 	usba_int_enb_set(udc, USBA_END_OF_RESET);
1910 	spin_unlock_irqrestore(&udc->lock, flags);
1911 
1912 	return 0;
1913 }
1914 
1915 static void usba_stop(struct usba_udc *udc)
1916 {
1917 	unsigned long flags;
1918 
1919 	if (udc->suspended)
1920 		return;
1921 
1922 	spin_lock_irqsave(&udc->lock, flags);
1923 	udc->gadget.speed = USB_SPEED_UNKNOWN;
1924 	reset_all_endpoints(udc);
1925 
1926 	/* This will also disable the DP pullup */
1927 	toggle_bias(udc, 0);
1928 	usba_writel(udc, CTRL, USBA_DISABLE_MASK);
1929 	spin_unlock_irqrestore(&udc->lock, flags);
1930 
1931 	stop_clock(udc);
1932 }
1933 
1934 static irqreturn_t usba_vbus_irq_thread(int irq, void *devid)
1935 {
1936 	struct usba_udc *udc = devid;
1937 	int vbus;
1938 
1939 	/* debounce */
1940 	udelay(10);
1941 
1942 	mutex_lock(&udc->vbus_mutex);
1943 
1944 	vbus = vbus_is_present(udc);
1945 	if (vbus != udc->vbus_prev) {
1946 		if (vbus) {
1947 			usba_start(udc);
1948 		} else {
1949 			udc->suspended = false;
1950 			if (udc->driver->disconnect)
1951 				udc->driver->disconnect(&udc->gadget);
1952 
1953 			usba_stop(udc);
1954 		}
1955 		udc->vbus_prev = vbus;
1956 	}
1957 
1958 	mutex_unlock(&udc->vbus_mutex);
1959 	return IRQ_HANDLED;
1960 }
1961 
1962 static int atmel_usba_pullup(struct usb_gadget *gadget, int is_on)
1963 {
1964 	struct usba_udc *udc = container_of(gadget, struct usba_udc, gadget);
1965 	unsigned long flags;
1966 	u32 ctrl;
1967 
1968 	spin_lock_irqsave(&udc->lock, flags);
1969 	ctrl = usba_readl(udc, CTRL);
1970 	if (is_on)
1971 		ctrl &= ~USBA_DETACH;
1972 	else
1973 		ctrl |= USBA_DETACH;
1974 	usba_writel(udc, CTRL, ctrl);
1975 	spin_unlock_irqrestore(&udc->lock, flags);
1976 
1977 	return 0;
1978 }
1979 
1980 static int atmel_usba_start(struct usb_gadget *gadget,
1981 		struct usb_gadget_driver *driver)
1982 {
1983 	int ret;
1984 	struct usba_udc *udc = container_of(gadget, struct usba_udc, gadget);
1985 	unsigned long flags;
1986 
1987 	spin_lock_irqsave(&udc->lock, flags);
1988 	udc->devstatus = 1 << USB_DEVICE_SELF_POWERED;
1989 	udc->driver = driver;
1990 	spin_unlock_irqrestore(&udc->lock, flags);
1991 
1992 	mutex_lock(&udc->vbus_mutex);
1993 
1994 	if (udc->vbus_pin)
1995 		enable_irq(gpiod_to_irq(udc->vbus_pin));
1996 
1997 	/* If Vbus is present, enable the controller and wait for reset */
1998 	udc->vbus_prev = vbus_is_present(udc);
1999 	if (udc->vbus_prev) {
2000 		ret = usba_start(udc);
2001 		if (ret)
2002 			goto err;
2003 	}
2004 
2005 	mutex_unlock(&udc->vbus_mutex);
2006 	return 0;
2007 
2008 err:
2009 	if (udc->vbus_pin)
2010 		disable_irq(gpiod_to_irq(udc->vbus_pin));
2011 
2012 	mutex_unlock(&udc->vbus_mutex);
2013 
2014 	spin_lock_irqsave(&udc->lock, flags);
2015 	udc->devstatus &= ~(1 << USB_DEVICE_SELF_POWERED);
2016 	udc->driver = NULL;
2017 	spin_unlock_irqrestore(&udc->lock, flags);
2018 	return ret;
2019 }
2020 
2021 static int atmel_usba_stop(struct usb_gadget *gadget)
2022 {
2023 	struct usba_udc *udc = container_of(gadget, struct usba_udc, gadget);
2024 
2025 	if (udc->vbus_pin)
2026 		disable_irq(gpiod_to_irq(udc->vbus_pin));
2027 
2028 	if (fifo_mode == 0)
2029 		udc->configured_ep = 1;
2030 
2031 	udc->suspended = false;
2032 	usba_stop(udc);
2033 
2034 	udc->driver = NULL;
2035 
2036 	return 0;
2037 }
2038 
2039 static void at91sam9rl_toggle_bias(struct usba_udc *udc, int is_on)
2040 {
2041 	regmap_update_bits(udc->pmc, AT91_CKGR_UCKR, AT91_PMC_BIASEN,
2042 			   is_on ? AT91_PMC_BIASEN : 0);
2043 }
2044 
2045 static void at91sam9g45_pulse_bias(struct usba_udc *udc)
2046 {
2047 	regmap_update_bits(udc->pmc, AT91_CKGR_UCKR, AT91_PMC_BIASEN, 0);
2048 	regmap_update_bits(udc->pmc, AT91_CKGR_UCKR, AT91_PMC_BIASEN,
2049 			   AT91_PMC_BIASEN);
2050 }
2051 
2052 static const struct usba_udc_errata at91sam9rl_errata = {
2053 	.toggle_bias = at91sam9rl_toggle_bias,
2054 };
2055 
2056 static const struct usba_udc_errata at91sam9g45_errata = {
2057 	.pulse_bias = at91sam9g45_pulse_bias,
2058 };
2059 
2060 static const struct usba_ep_config ep_config_sam9[] __initconst = {
2061 	{ .nr_banks = 1 },				/* ep 0 */
2062 	{ .nr_banks = 2, .can_dma = 1, .can_isoc = 1 },	/* ep 1 */
2063 	{ .nr_banks = 2, .can_dma = 1, .can_isoc = 1 },	/* ep 2 */
2064 	{ .nr_banks = 3, .can_dma = 1 },		/* ep 3 */
2065 	{ .nr_banks = 3, .can_dma = 1 },		/* ep 4 */
2066 	{ .nr_banks = 3, .can_dma = 1, .can_isoc = 1 },	/* ep 5 */
2067 	{ .nr_banks = 3, .can_dma = 1, .can_isoc = 1 },	/* ep 6 */
2068 };
2069 
2070 static const struct usba_ep_config ep_config_sama5[] __initconst = {
2071 	{ .nr_banks = 1 },				/* ep 0 */
2072 	{ .nr_banks = 3, .can_dma = 1, .can_isoc = 1 },	/* ep 1 */
2073 	{ .nr_banks = 3, .can_dma = 1, .can_isoc = 1 },	/* ep 2 */
2074 	{ .nr_banks = 2, .can_dma = 1, .can_isoc = 1 },	/* ep 3 */
2075 	{ .nr_banks = 2, .can_dma = 1, .can_isoc = 1 },	/* ep 4 */
2076 	{ .nr_banks = 2, .can_dma = 1, .can_isoc = 1 },	/* ep 5 */
2077 	{ .nr_banks = 2, .can_dma = 1, .can_isoc = 1 },	/* ep 6 */
2078 	{ .nr_banks = 2, .can_dma = 1, .can_isoc = 1 },	/* ep 7 */
2079 	{ .nr_banks = 2, .can_isoc = 1 },		/* ep 8 */
2080 	{ .nr_banks = 2, .can_isoc = 1 },		/* ep 9 */
2081 	{ .nr_banks = 2, .can_isoc = 1 },		/* ep 10 */
2082 	{ .nr_banks = 2, .can_isoc = 1 },		/* ep 11 */
2083 	{ .nr_banks = 2, .can_isoc = 1 },		/* ep 12 */
2084 	{ .nr_banks = 2, .can_isoc = 1 },		/* ep 13 */
2085 	{ .nr_banks = 2, .can_isoc = 1 },		/* ep 14 */
2086 	{ .nr_banks = 2, .can_isoc = 1 },		/* ep 15 */
2087 };
2088 
2089 static const struct usba_udc_config udc_at91sam9rl_cfg = {
2090 	.errata = &at91sam9rl_errata,
2091 	.config = ep_config_sam9,
2092 	.num_ep = ARRAY_SIZE(ep_config_sam9),
2093 };
2094 
2095 static const struct usba_udc_config udc_at91sam9g45_cfg = {
2096 	.errata = &at91sam9g45_errata,
2097 	.config = ep_config_sam9,
2098 	.num_ep = ARRAY_SIZE(ep_config_sam9),
2099 };
2100 
2101 static const struct usba_udc_config udc_sama5d3_cfg = {
2102 	.config = ep_config_sama5,
2103 	.num_ep = ARRAY_SIZE(ep_config_sama5),
2104 };
2105 
2106 static const struct of_device_id atmel_udc_dt_ids[] = {
2107 	{ .compatible = "atmel,at91sam9rl-udc", .data = &udc_at91sam9rl_cfg },
2108 	{ .compatible = "atmel,at91sam9g45-udc", .data = &udc_at91sam9g45_cfg },
2109 	{ .compatible = "atmel,sama5d3-udc", .data = &udc_sama5d3_cfg },
2110 	{ /* sentinel */ }
2111 };
2112 
2113 MODULE_DEVICE_TABLE(of, atmel_udc_dt_ids);
2114 
2115 static struct usba_ep * atmel_udc_of_init(struct platform_device *pdev,
2116 						    struct usba_udc *udc)
2117 {
2118 	struct device_node *np = pdev->dev.of_node;
2119 	const struct of_device_id *match;
2120 	int i, ret;
2121 	struct usba_ep *eps, *ep;
2122 	const struct usba_udc_config *udc_config;
2123 
2124 	match = of_match_node(atmel_udc_dt_ids, np);
2125 	if (!match)
2126 		return ERR_PTR(-EINVAL);
2127 
2128 	udc_config = match->data;
2129 	udc->errata = udc_config->errata;
2130 	udc->pmc = syscon_regmap_lookup_by_compatible("atmel,at91sam9g45-pmc");
2131 	if (IS_ERR(udc->pmc))
2132 		udc->pmc = syscon_regmap_lookup_by_compatible("atmel,at91sam9rl-pmc");
2133 	if (IS_ERR(udc->pmc))
2134 		udc->pmc = syscon_regmap_lookup_by_compatible("atmel,at91sam9x5-pmc");
2135 	if (udc->errata && IS_ERR(udc->pmc))
2136 		return ERR_CAST(udc->pmc);
2137 
2138 	udc->num_ep = 0;
2139 
2140 	udc->vbus_pin = devm_gpiod_get_optional(&pdev->dev, "atmel,vbus",
2141 						GPIOD_IN);
2142 
2143 	if (fifo_mode == 0) {
2144 		udc->num_ep = udc_config->num_ep;
2145 		udc->configured_ep = 1;
2146 	} else {
2147 		udc->num_ep = usba_config_fifo_table(udc);
2148 	}
2149 
2150 	eps = devm_kcalloc(&pdev->dev, udc->num_ep, sizeof(struct usba_ep),
2151 			   GFP_KERNEL);
2152 	if (!eps)
2153 		return ERR_PTR(-ENOMEM);
2154 
2155 	udc->gadget.ep0 = &eps[0].ep;
2156 
2157 	INIT_LIST_HEAD(&eps[0].ep.ep_list);
2158 
2159 	i = 0;
2160 	while (i < udc->num_ep) {
2161 		const struct usba_ep_config *ep_cfg = &udc_config->config[i];
2162 
2163 		ep = &eps[i];
2164 
2165 		ep->index = fifo_mode ? udc->fifo_cfg[i].hw_ep_num : i;
2166 
2167 		/* Only the first EP is 64 bytes */
2168 		if (ep->index == 0)
2169 			ep->fifo_size = 64;
2170 		else
2171 			ep->fifo_size = 1024;
2172 
2173 		if (fifo_mode) {
2174 			if (ep->fifo_size < udc->fifo_cfg[i].fifo_size)
2175 				dev_warn(&pdev->dev,
2176 					 "Using default max fifo-size value\n");
2177 			else
2178 				ep->fifo_size = udc->fifo_cfg[i].fifo_size;
2179 		}
2180 
2181 		ep->nr_banks = ep_cfg->nr_banks;
2182 		if (fifo_mode) {
2183 			if (ep->nr_banks < udc->fifo_cfg[i].nr_banks)
2184 				dev_warn(&pdev->dev,
2185 					 "Using default max nb-banks value\n");
2186 			else
2187 				ep->nr_banks = udc->fifo_cfg[i].nr_banks;
2188 		}
2189 
2190 		ep->can_dma = ep_cfg->can_dma;
2191 		ep->can_isoc = ep_cfg->can_isoc;
2192 
2193 		sprintf(ep->name, "ep%d", ep->index);
2194 		ep->ep.name = ep->name;
2195 
2196 		ep->ep_regs = udc->regs + USBA_EPT_BASE(i);
2197 		ep->dma_regs = udc->regs + USBA_DMA_BASE(i);
2198 		ep->fifo = udc->fifo + USBA_FIFO_BASE(i);
2199 		ep->ep.ops = &usba_ep_ops;
2200 		usb_ep_set_maxpacket_limit(&ep->ep, ep->fifo_size);
2201 		ep->udc = udc;
2202 		INIT_LIST_HEAD(&ep->queue);
2203 
2204 		if (ep->index == 0) {
2205 			ep->ep.caps.type_control = true;
2206 		} else {
2207 			ep->ep.caps.type_iso = ep->can_isoc;
2208 			ep->ep.caps.type_bulk = true;
2209 			ep->ep.caps.type_int = true;
2210 		}
2211 
2212 		ep->ep.caps.dir_in = true;
2213 		ep->ep.caps.dir_out = true;
2214 
2215 		if (fifo_mode != 0) {
2216 			/*
2217 			 * Generate ept_cfg based on FIFO size and
2218 			 * banks number
2219 			 */
2220 			if (ep->fifo_size  <= 8)
2221 				ep->ept_cfg = USBA_BF(EPT_SIZE, USBA_EPT_SIZE_8);
2222 			else
2223 				/* LSB is bit 1, not 0 */
2224 				ep->ept_cfg =
2225 				  USBA_BF(EPT_SIZE, fls(ep->fifo_size - 1) - 3);
2226 
2227 			ep->ept_cfg |= USBA_BF(BK_NUMBER, ep->nr_banks);
2228 		}
2229 
2230 		if (i)
2231 			list_add_tail(&ep->ep.ep_list, &udc->gadget.ep_list);
2232 
2233 		i++;
2234 	}
2235 
2236 	if (i == 0) {
2237 		dev_err(&pdev->dev, "of_probe: no endpoint specified\n");
2238 		ret = -EINVAL;
2239 		goto err;
2240 	}
2241 
2242 	return eps;
2243 err:
2244 	return ERR_PTR(ret);
2245 }
2246 
2247 static int usba_udc_probe(struct platform_device *pdev)
2248 {
2249 	struct resource *res;
2250 	struct clk *pclk, *hclk;
2251 	struct usba_udc *udc;
2252 	int irq, ret, i;
2253 
2254 	udc = devm_kzalloc(&pdev->dev, sizeof(*udc), GFP_KERNEL);
2255 	if (!udc)
2256 		return -ENOMEM;
2257 
2258 	udc->gadget = usba_gadget_template;
2259 	INIT_LIST_HEAD(&udc->gadget.ep_list);
2260 
2261 	res = platform_get_resource(pdev, IORESOURCE_MEM, CTRL_IOMEM_ID);
2262 	udc->regs = devm_ioremap_resource(&pdev->dev, res);
2263 	if (IS_ERR(udc->regs))
2264 		return PTR_ERR(udc->regs);
2265 	dev_info(&pdev->dev, "MMIO registers at %pR mapped at %p\n",
2266 		 res, udc->regs);
2267 
2268 	res = platform_get_resource(pdev, IORESOURCE_MEM, FIFO_IOMEM_ID);
2269 	udc->fifo = devm_ioremap_resource(&pdev->dev, res);
2270 	if (IS_ERR(udc->fifo))
2271 		return PTR_ERR(udc->fifo);
2272 	dev_info(&pdev->dev, "FIFO at %pR mapped at %p\n", res, udc->fifo);
2273 
2274 	irq = platform_get_irq(pdev, 0);
2275 	if (irq < 0)
2276 		return irq;
2277 
2278 	pclk = devm_clk_get(&pdev->dev, "pclk");
2279 	if (IS_ERR(pclk))
2280 		return PTR_ERR(pclk);
2281 	hclk = devm_clk_get(&pdev->dev, "hclk");
2282 	if (IS_ERR(hclk))
2283 		return PTR_ERR(hclk);
2284 
2285 	spin_lock_init(&udc->lock);
2286 	mutex_init(&udc->vbus_mutex);
2287 	udc->pdev = pdev;
2288 	udc->pclk = pclk;
2289 	udc->hclk = hclk;
2290 
2291 	platform_set_drvdata(pdev, udc);
2292 
2293 	/* Make sure we start from a clean slate */
2294 	ret = clk_prepare_enable(pclk);
2295 	if (ret) {
2296 		dev_err(&pdev->dev, "Unable to enable pclk, aborting.\n");
2297 		return ret;
2298 	}
2299 
2300 	usba_writel(udc, CTRL, USBA_DISABLE_MASK);
2301 	clk_disable_unprepare(pclk);
2302 
2303 	udc->usba_ep = atmel_udc_of_init(pdev, udc);
2304 
2305 	toggle_bias(udc, 0);
2306 
2307 	if (IS_ERR(udc->usba_ep))
2308 		return PTR_ERR(udc->usba_ep);
2309 
2310 	ret = devm_request_irq(&pdev->dev, irq, usba_udc_irq, 0,
2311 				"atmel_usba_udc", udc);
2312 	if (ret) {
2313 		dev_err(&pdev->dev, "Cannot request irq %d (error %d)\n",
2314 			irq, ret);
2315 		return ret;
2316 	}
2317 	udc->irq = irq;
2318 
2319 	if (udc->vbus_pin) {
2320 		irq_set_status_flags(gpiod_to_irq(udc->vbus_pin), IRQ_NOAUTOEN);
2321 		ret = devm_request_threaded_irq(&pdev->dev,
2322 				gpiod_to_irq(udc->vbus_pin), NULL,
2323 				usba_vbus_irq_thread, USBA_VBUS_IRQFLAGS,
2324 				"atmel_usba_udc", udc);
2325 		if (ret) {
2326 			udc->vbus_pin = NULL;
2327 			dev_warn(&udc->pdev->dev,
2328 				 "failed to request vbus irq; "
2329 				 "assuming always on\n");
2330 		}
2331 	}
2332 
2333 	ret = usb_add_gadget_udc(&pdev->dev, &udc->gadget);
2334 	if (ret)
2335 		return ret;
2336 	device_init_wakeup(&pdev->dev, 1);
2337 
2338 	usba_init_debugfs(udc);
2339 	for (i = 1; i < udc->num_ep; i++)
2340 		usba_ep_init_debugfs(udc, &udc->usba_ep[i]);
2341 
2342 	return 0;
2343 }
2344 
2345 static int usba_udc_remove(struct platform_device *pdev)
2346 {
2347 	struct usba_udc *udc;
2348 	int i;
2349 
2350 	udc = platform_get_drvdata(pdev);
2351 
2352 	device_init_wakeup(&pdev->dev, 0);
2353 	usb_del_gadget_udc(&udc->gadget);
2354 
2355 	for (i = 1; i < udc->num_ep; i++)
2356 		usba_ep_cleanup_debugfs(&udc->usba_ep[i]);
2357 	usba_cleanup_debugfs(udc);
2358 
2359 	return 0;
2360 }
2361 
2362 #ifdef CONFIG_PM_SLEEP
2363 static int usba_udc_suspend(struct device *dev)
2364 {
2365 	struct usba_udc *udc = dev_get_drvdata(dev);
2366 
2367 	/* Not started */
2368 	if (!udc->driver)
2369 		return 0;
2370 
2371 	mutex_lock(&udc->vbus_mutex);
2372 
2373 	if (!device_may_wakeup(dev)) {
2374 		udc->suspended = false;
2375 		usba_stop(udc);
2376 		goto out;
2377 	}
2378 
2379 	/*
2380 	 * Device may wake up. We stay clocked if we failed
2381 	 * to request vbus irq, assuming always on.
2382 	 */
2383 	if (udc->vbus_pin) {
2384 		/* FIXME: right to stop here...??? */
2385 		usba_stop(udc);
2386 		enable_irq_wake(gpiod_to_irq(udc->vbus_pin));
2387 	}
2388 
2389 	enable_irq_wake(udc->irq);
2390 
2391 out:
2392 	mutex_unlock(&udc->vbus_mutex);
2393 	return 0;
2394 }
2395 
2396 static int usba_udc_resume(struct device *dev)
2397 {
2398 	struct usba_udc *udc = dev_get_drvdata(dev);
2399 
2400 	/* Not started */
2401 	if (!udc->driver)
2402 		return 0;
2403 
2404 	if (device_may_wakeup(dev)) {
2405 		if (udc->vbus_pin)
2406 			disable_irq_wake(gpiod_to_irq(udc->vbus_pin));
2407 
2408 		disable_irq_wake(udc->irq);
2409 	}
2410 
2411 	/* If Vbus is present, enable the controller and wait for reset */
2412 	mutex_lock(&udc->vbus_mutex);
2413 	udc->vbus_prev = vbus_is_present(udc);
2414 	if (udc->vbus_prev)
2415 		usba_start(udc);
2416 	mutex_unlock(&udc->vbus_mutex);
2417 
2418 	return 0;
2419 }
2420 #endif
2421 
2422 static SIMPLE_DEV_PM_OPS(usba_udc_pm_ops, usba_udc_suspend, usba_udc_resume);
2423 
2424 static struct platform_driver udc_driver = {
2425 	.remove		= usba_udc_remove,
2426 	.driver		= {
2427 		.name		= "atmel_usba_udc",
2428 		.pm		= &usba_udc_pm_ops,
2429 		.of_match_table	= atmel_udc_dt_ids,
2430 	},
2431 };
2432 
2433 module_platform_driver_probe(udc_driver, usba_udc_probe);
2434 
2435 MODULE_DESCRIPTION("Atmel USBA UDC driver");
2436 MODULE_AUTHOR("Haavard Skinnemoen (Atmel)");
2437 MODULE_LICENSE("GPL");
2438 MODULE_ALIAS("platform:atmel_usba_udc");
2439