1 // SPDX-License-Identifier: GPL-2.0+
2 /*
3  * amd5536.h -- header for AMD 5536 UDC high/full speed USB device controller
4  *
5  * Copyright (C) 2007 AMD (http://www.amd.com)
6  * Author: Thomas Dahlmann
7  */
8 
9 #ifndef AMD5536UDC_H
10 #define AMD5536UDC_H
11 
12 /* debug control */
13 /* #define UDC_VERBOSE */
14 
15 #include <linux/extcon.h>
16 #include <linux/usb/ch9.h>
17 #include <linux/usb/gadget.h>
18 
19 /* various constants */
20 #define UDC_RDE_TIMER_SECONDS		1
21 #define UDC_RDE_TIMER_DIV		10
22 #define UDC_POLLSTALL_TIMER_USECONDS	500
23 
24 /* Hs AMD5536 chip rev. */
25 #define UDC_HSA0_REV 1
26 #define UDC_HSB1_REV 2
27 
28 /* Broadcom chip rev. */
29 #define UDC_BCM_REV 10
30 
31 /*
32  * SETUP usb commands
33  * needed, because some SETUP's are handled in hw, but must be passed to
34  * gadget driver above
35  * SET_CONFIG
36  */
37 #define UDC_SETCONFIG_DWORD0			0x00000900
38 #define UDC_SETCONFIG_DWORD0_VALUE_MASK		0xffff0000
39 #define UDC_SETCONFIG_DWORD0_VALUE_OFS		16
40 
41 #define UDC_SETCONFIG_DWORD1			0x00000000
42 
43 /* SET_INTERFACE */
44 #define UDC_SETINTF_DWORD0			0x00000b00
45 #define UDC_SETINTF_DWORD0_ALT_MASK		0xffff0000
46 #define UDC_SETINTF_DWORD0_ALT_OFS		16
47 
48 #define UDC_SETINTF_DWORD1			0x00000000
49 #define UDC_SETINTF_DWORD1_INTF_MASK		0x0000ffff
50 #define UDC_SETINTF_DWORD1_INTF_OFS		0
51 
52 /* Mass storage reset */
53 #define UDC_MSCRES_DWORD0			0x0000ff21
54 #define UDC_MSCRES_DWORD1			0x00000000
55 
56 /* Global CSR's -------------------------------------------------------------*/
57 #define UDC_CSR_ADDR				0x500
58 
59 /* EP NE bits */
60 /* EP number */
61 #define UDC_CSR_NE_NUM_MASK			0x0000000f
62 #define UDC_CSR_NE_NUM_OFS			0
63 /* EP direction */
64 #define UDC_CSR_NE_DIR_MASK			0x00000010
65 #define UDC_CSR_NE_DIR_OFS			4
66 /* EP type */
67 #define UDC_CSR_NE_TYPE_MASK			0x00000060
68 #define UDC_CSR_NE_TYPE_OFS			5
69 /* EP config number */
70 #define UDC_CSR_NE_CFG_MASK			0x00000780
71 #define UDC_CSR_NE_CFG_OFS			7
72 /* EP interface number */
73 #define UDC_CSR_NE_INTF_MASK			0x00007800
74 #define UDC_CSR_NE_INTF_OFS			11
75 /* EP alt setting */
76 #define UDC_CSR_NE_ALT_MASK			0x00078000
77 #define UDC_CSR_NE_ALT_OFS			15
78 
79 /* max pkt */
80 #define UDC_CSR_NE_MAX_PKT_MASK			0x3ff80000
81 #define UDC_CSR_NE_MAX_PKT_OFS			19
82 
83 /* Device Config Register ---------------------------------------------------*/
84 #define UDC_DEVCFG_ADDR				0x400
85 
86 #define UDC_DEVCFG_SOFTRESET			31
87 #define UDC_DEVCFG_HNPSFEN			30
88 #define UDC_DEVCFG_DMARST			29
89 #define UDC_DEVCFG_SET_DESC			18
90 #define UDC_DEVCFG_CSR_PRG			17
91 #define UDC_DEVCFG_STATUS			7
92 #define UDC_DEVCFG_DIR				6
93 #define UDC_DEVCFG_PI				5
94 #define UDC_DEVCFG_SS				4
95 #define UDC_DEVCFG_SP				3
96 #define UDC_DEVCFG_RWKP				2
97 
98 #define UDC_DEVCFG_SPD_MASK			0x3
99 #define UDC_DEVCFG_SPD_OFS			0
100 #define UDC_DEVCFG_SPD_HS			0x0
101 #define UDC_DEVCFG_SPD_FS			0x1
102 #define UDC_DEVCFG_SPD_LS			0x2
103 /*#define UDC_DEVCFG_SPD_FS			0x3*/
104 
105 
106 /* Device Control Register --------------------------------------------------*/
107 #define UDC_DEVCTL_ADDR				0x404
108 
109 #define UDC_DEVCTL_THLEN_MASK			0xff000000
110 #define UDC_DEVCTL_THLEN_OFS			24
111 
112 #define UDC_DEVCTL_BRLEN_MASK			0x00ff0000
113 #define UDC_DEVCTL_BRLEN_OFS			16
114 
115 #define UDC_DEVCTL_SRX_FLUSH			14
116 #define UDC_DEVCTL_CSR_DONE			13
117 #define UDC_DEVCTL_DEVNAK			12
118 #define UDC_DEVCTL_SD				10
119 #define UDC_DEVCTL_MODE				9
120 #define UDC_DEVCTL_BREN				8
121 #define UDC_DEVCTL_THE				7
122 #define UDC_DEVCTL_BF				6
123 #define UDC_DEVCTL_BE				5
124 #define UDC_DEVCTL_DU				4
125 #define UDC_DEVCTL_TDE				3
126 #define UDC_DEVCTL_RDE				2
127 #define UDC_DEVCTL_RES				0
128 
129 
130 /* Device Status Register ---------------------------------------------------*/
131 #define UDC_DEVSTS_ADDR				0x408
132 
133 #define UDC_DEVSTS_TS_MASK			0xfffc0000
134 #define UDC_DEVSTS_TS_OFS			18
135 
136 #define UDC_DEVSTS_SESSVLD			17
137 #define UDC_DEVSTS_PHY_ERROR			16
138 #define UDC_DEVSTS_RXFIFO_EMPTY			15
139 
140 #define UDC_DEVSTS_ENUM_SPEED_MASK		0x00006000
141 #define UDC_DEVSTS_ENUM_SPEED_OFS		13
142 #define UDC_DEVSTS_ENUM_SPEED_FULL		1
143 #define UDC_DEVSTS_ENUM_SPEED_HIGH		0
144 
145 #define UDC_DEVSTS_SUSP				12
146 
147 #define UDC_DEVSTS_ALT_MASK			0x00000f00
148 #define UDC_DEVSTS_ALT_OFS			8
149 
150 #define UDC_DEVSTS_INTF_MASK			0x000000f0
151 #define UDC_DEVSTS_INTF_OFS			4
152 
153 #define UDC_DEVSTS_CFG_MASK			0x0000000f
154 #define UDC_DEVSTS_CFG_OFS			0
155 
156 
157 /* Device Interrupt Register ------------------------------------------------*/
158 #define UDC_DEVINT_ADDR				0x40c
159 
160 #define UDC_DEVINT_SVC				7
161 #define UDC_DEVINT_ENUM				6
162 #define UDC_DEVINT_SOF				5
163 #define UDC_DEVINT_US				4
164 #define UDC_DEVINT_UR				3
165 #define UDC_DEVINT_ES				2
166 #define UDC_DEVINT_SI				1
167 #define UDC_DEVINT_SC				0
168 
169 /* Device Interrupt Mask Register -------------------------------------------*/
170 #define UDC_DEVINT_MSK_ADDR			0x410
171 
172 #define UDC_DEVINT_MSK				0x7f
173 
174 /* Endpoint Interrupt Register ----------------------------------------------*/
175 #define UDC_EPINT_ADDR				0x414
176 
177 #define UDC_EPINT_OUT_MASK			0xffff0000
178 #define UDC_EPINT_OUT_OFS			16
179 #define UDC_EPINT_IN_MASK			0x0000ffff
180 #define UDC_EPINT_IN_OFS			0
181 
182 #define UDC_EPINT_IN_EP0			0
183 #define UDC_EPINT_IN_EP1			1
184 #define UDC_EPINT_IN_EP2			2
185 #define UDC_EPINT_IN_EP3			3
186 #define UDC_EPINT_OUT_EP0			16
187 #define UDC_EPINT_OUT_EP1			17
188 #define UDC_EPINT_OUT_EP2			18
189 #define UDC_EPINT_OUT_EP3			19
190 
191 #define UDC_EPINT_EP0_ENABLE_MSK		0x001e001e
192 
193 /* Endpoint Interrupt Mask Register -----------------------------------------*/
194 #define UDC_EPINT_MSK_ADDR			0x418
195 
196 #define UDC_EPINT_OUT_MSK_MASK			0xffff0000
197 #define UDC_EPINT_OUT_MSK_OFS			16
198 #define UDC_EPINT_IN_MSK_MASK			0x0000ffff
199 #define UDC_EPINT_IN_MSK_OFS			0
200 
201 #define UDC_EPINT_MSK_DISABLE_ALL		0xffffffff
202 /* mask non-EP0 endpoints */
203 #define UDC_EPDATAINT_MSK_DISABLE		0xfffefffe
204 /* mask all dev interrupts */
205 #define UDC_DEV_MSK_DISABLE			0x7f
206 
207 /* Endpoint-specific CSR's --------------------------------------------------*/
208 #define UDC_EPREGS_ADDR				0x0
209 #define UDC_EPIN_REGS_ADDR			0x0
210 #define UDC_EPOUT_REGS_ADDR			0x200
211 
212 #define UDC_EPCTL_ADDR				0x0
213 
214 #define UDC_EPCTL_RRDY				9
215 #define UDC_EPCTL_CNAK				8
216 #define UDC_EPCTL_SNAK				7
217 #define UDC_EPCTL_NAK				6
218 
219 #define UDC_EPCTL_ET_MASK			0x00000030
220 #define UDC_EPCTL_ET_OFS			4
221 #define UDC_EPCTL_ET_CONTROL			0
222 #define UDC_EPCTL_ET_ISO			1
223 #define UDC_EPCTL_ET_BULK			2
224 #define UDC_EPCTL_ET_INTERRUPT			3
225 
226 #define UDC_EPCTL_P				3
227 #define UDC_EPCTL_SN				2
228 #define UDC_EPCTL_F				1
229 #define UDC_EPCTL_S				0
230 
231 /* Endpoint Status Registers ------------------------------------------------*/
232 #define UDC_EPSTS_ADDR				0x4
233 
234 #define UDC_EPSTS_RX_PKT_SIZE_MASK		0x007ff800
235 #define UDC_EPSTS_RX_PKT_SIZE_OFS		11
236 
237 #define UDC_EPSTS_TDC				10
238 #define UDC_EPSTS_HE				9
239 #define UDC_EPSTS_BNA				7
240 #define UDC_EPSTS_IN				6
241 
242 #define UDC_EPSTS_OUT_MASK			0x00000030
243 #define UDC_EPSTS_OUT_OFS			4
244 #define UDC_EPSTS_OUT_DATA			1
245 #define UDC_EPSTS_OUT_DATA_CLEAR		0x10
246 #define UDC_EPSTS_OUT_SETUP			2
247 #define UDC_EPSTS_OUT_SETUP_CLEAR		0x20
248 #define UDC_EPSTS_OUT_CLEAR			0x30
249 
250 /* Endpoint Buffer Size IN/ Receive Packet Frame Number OUT Registers ------*/
251 #define UDC_EPIN_BUFF_SIZE_ADDR			0x8
252 #define UDC_EPOUT_FRAME_NUMBER_ADDR		0x8
253 
254 #define UDC_EPIN_BUFF_SIZE_MASK			0x0000ffff
255 #define UDC_EPIN_BUFF_SIZE_OFS			0
256 /* EP0in txfifo = 128 bytes*/
257 #define UDC_EPIN0_BUFF_SIZE			32
258 /* EP0in fullspeed txfifo = 128 bytes*/
259 #define UDC_FS_EPIN0_BUFF_SIZE			32
260 
261 /* fifo size mult = fifo size / max packet */
262 #define UDC_EPIN_BUFF_SIZE_MULT			2
263 
264 /* EPin data fifo size = 1024 bytes DOUBLE BUFFERING */
265 #define UDC_EPIN_BUFF_SIZE			256
266 /* EPin small INT data fifo size = 128 bytes */
267 #define UDC_EPIN_SMALLINT_BUFF_SIZE		32
268 
269 /* EPin fullspeed data fifo size = 128 bytes DOUBLE BUFFERING */
270 #define UDC_FS_EPIN_BUFF_SIZE			32
271 
272 #define UDC_EPOUT_FRAME_NUMBER_MASK		0x0000ffff
273 #define UDC_EPOUT_FRAME_NUMBER_OFS		0
274 
275 /* Endpoint Buffer Size OUT/Max Packet Size Registers -----------------------*/
276 #define UDC_EPOUT_BUFF_SIZE_ADDR		0x0c
277 #define UDC_EP_MAX_PKT_SIZE_ADDR		0x0c
278 
279 #define UDC_EPOUT_BUFF_SIZE_MASK		0xffff0000
280 #define UDC_EPOUT_BUFF_SIZE_OFS			16
281 #define UDC_EP_MAX_PKT_SIZE_MASK		0x0000ffff
282 #define UDC_EP_MAX_PKT_SIZE_OFS			0
283 /* EP0in max packet size = 64 bytes */
284 #define UDC_EP0IN_MAX_PKT_SIZE			64
285 /* EP0out max packet size = 64 bytes */
286 #define UDC_EP0OUT_MAX_PKT_SIZE			64
287 /* EP0in fullspeed max packet size = 64 bytes */
288 #define UDC_FS_EP0IN_MAX_PKT_SIZE		64
289 /* EP0out fullspeed max packet size = 64 bytes */
290 #define UDC_FS_EP0OUT_MAX_PKT_SIZE		64
291 
292 /*
293  * Endpoint dma descriptors ------------------------------------------------
294  *
295  * Setup data, Status dword
296  */
297 #define UDC_DMA_STP_STS_CFG_MASK		0x0fff0000
298 #define UDC_DMA_STP_STS_CFG_OFS			16
299 #define UDC_DMA_STP_STS_CFG_ALT_MASK		0x000f0000
300 #define UDC_DMA_STP_STS_CFG_ALT_OFS		16
301 #define UDC_DMA_STP_STS_CFG_INTF_MASK		0x00f00000
302 #define UDC_DMA_STP_STS_CFG_INTF_OFS		20
303 #define UDC_DMA_STP_STS_CFG_NUM_MASK		0x0f000000
304 #define UDC_DMA_STP_STS_CFG_NUM_OFS		24
305 #define UDC_DMA_STP_STS_RX_MASK			0x30000000
306 #define UDC_DMA_STP_STS_RX_OFS			28
307 #define UDC_DMA_STP_STS_BS_MASK			0xc0000000
308 #define UDC_DMA_STP_STS_BS_OFS			30
309 #define UDC_DMA_STP_STS_BS_HOST_READY		0
310 #define UDC_DMA_STP_STS_BS_DMA_BUSY		1
311 #define UDC_DMA_STP_STS_BS_DMA_DONE		2
312 #define UDC_DMA_STP_STS_BS_HOST_BUSY		3
313 /* IN data, Status dword */
314 #define UDC_DMA_IN_STS_TXBYTES_MASK		0x0000ffff
315 #define UDC_DMA_IN_STS_TXBYTES_OFS		0
316 #define	UDC_DMA_IN_STS_FRAMENUM_MASK		0x07ff0000
317 #define UDC_DMA_IN_STS_FRAMENUM_OFS		0
318 #define UDC_DMA_IN_STS_L			27
319 #define UDC_DMA_IN_STS_TX_MASK			0x30000000
320 #define UDC_DMA_IN_STS_TX_OFS			28
321 #define UDC_DMA_IN_STS_BS_MASK			0xc0000000
322 #define UDC_DMA_IN_STS_BS_OFS			30
323 #define UDC_DMA_IN_STS_BS_HOST_READY		0
324 #define UDC_DMA_IN_STS_BS_DMA_BUSY		1
325 #define UDC_DMA_IN_STS_BS_DMA_DONE		2
326 #define UDC_DMA_IN_STS_BS_HOST_BUSY		3
327 /* OUT data, Status dword */
328 #define UDC_DMA_OUT_STS_RXBYTES_MASK		0x0000ffff
329 #define UDC_DMA_OUT_STS_RXBYTES_OFS		0
330 #define UDC_DMA_OUT_STS_FRAMENUM_MASK		0x07ff0000
331 #define UDC_DMA_OUT_STS_FRAMENUM_OFS		0
332 #define UDC_DMA_OUT_STS_L			27
333 #define UDC_DMA_OUT_STS_RX_MASK			0x30000000
334 #define UDC_DMA_OUT_STS_RX_OFS			28
335 #define UDC_DMA_OUT_STS_BS_MASK			0xc0000000
336 #define UDC_DMA_OUT_STS_BS_OFS			30
337 #define UDC_DMA_OUT_STS_BS_HOST_READY		0
338 #define UDC_DMA_OUT_STS_BS_DMA_BUSY		1
339 #define UDC_DMA_OUT_STS_BS_DMA_DONE		2
340 #define UDC_DMA_OUT_STS_BS_HOST_BUSY		3
341 /* max ep0in packet */
342 #define UDC_EP0IN_MAXPACKET			1000
343 /* max dma packet */
344 #define UDC_DMA_MAXPACKET			65536
345 
346 /* un-usable DMA address */
347 #define DMA_DONT_USE				(~(dma_addr_t) 0 )
348 
349 /* other Endpoint register addresses and values-----------------------------*/
350 #define UDC_EP_SUBPTR_ADDR			0x10
351 #define UDC_EP_DESPTR_ADDR			0x14
352 #define UDC_EP_WRITE_CONFIRM_ADDR		0x1c
353 
354 /* EP number as layouted in AHB space */
355 #define UDC_EP_NUM				32
356 #define UDC_EPIN_NUM				16
357 #define UDC_EPIN_NUM_USED			5
358 #define UDC_EPOUT_NUM				16
359 /* EP number of EP's really used = EP0 + 8 data EP's */
360 #define UDC_USED_EP_NUM				9
361 /* UDC CSR regs are aligned but AHB regs not - offset for OUT EP's */
362 #define UDC_CSR_EP_OUT_IX_OFS			12
363 
364 #define UDC_EP0OUT_IX				16
365 #define UDC_EP0IN_IX				0
366 
367 /* Rx fifo address and size = 1k -------------------------------------------*/
368 #define UDC_RXFIFO_ADDR				0x800
369 #define UDC_RXFIFO_SIZE				0x400
370 
371 /* Tx fifo address and size = 1.5k -----------------------------------------*/
372 #define UDC_TXFIFO_ADDR				0xc00
373 #define UDC_TXFIFO_SIZE				0x600
374 
375 /* default data endpoints --------------------------------------------------*/
376 #define UDC_EPIN_STATUS_IX			1
377 #define UDC_EPIN_IX				2
378 #define UDC_EPOUT_IX				18
379 
380 /* general constants -------------------------------------------------------*/
381 #define UDC_DWORD_BYTES				4
382 #define UDC_BITS_PER_BYTE_SHIFT			3
383 #define UDC_BYTE_MASK				0xff
384 #define UDC_BITS_PER_BYTE			8
385 
386 /*---------------------------------------------------------------------------*/
387 /* UDC CSR's */
388 struct udc_csrs {
389 
390 	/* sca - setup command address */
391 	u32 sca;
392 
393 	/* ep ne's */
394 	u32 ne[UDC_USED_EP_NUM];
395 } __attribute__ ((packed));
396 
397 /* AHB subsystem CSR registers */
398 struct udc_regs {
399 
400 	/* device configuration */
401 	u32 cfg;
402 
403 	/* device control */
404 	u32 ctl;
405 
406 	/* device status */
407 	u32 sts;
408 
409 	/* device interrupt */
410 	u32 irqsts;
411 
412 	/* device interrupt mask */
413 	u32 irqmsk;
414 
415 	/* endpoint interrupt */
416 	u32 ep_irqsts;
417 
418 	/* endpoint interrupt mask */
419 	u32 ep_irqmsk;
420 } __attribute__ ((packed));
421 
422 /* endpoint specific registers */
423 struct udc_ep_regs {
424 
425 	/* endpoint control */
426 	u32 ctl;
427 
428 	/* endpoint status */
429 	u32 sts;
430 
431 	/* endpoint buffer size in/ receive packet frame number out */
432 	u32 bufin_framenum;
433 
434 	/* endpoint buffer size out/max packet size */
435 	u32 bufout_maxpkt;
436 
437 	/* endpoint setup buffer pointer */
438 	u32 subptr;
439 
440 	/* endpoint data descriptor pointer */
441 	u32 desptr;
442 
443 	/* reserved */
444 	u32 reserved;
445 
446 	/* write/read confirmation */
447 	u32 confirm;
448 
449 } __attribute__ ((packed));
450 
451 /* control data DMA desc */
452 struct udc_stp_dma {
453 	/* status quadlet */
454 	u32	status;
455 	/* reserved */
456 	u32	_reserved;
457 	/* first setup word */
458 	u32	data12;
459 	/* second setup word */
460 	u32	data34;
461 } __attribute__ ((aligned (16)));
462 
463 /* normal data DMA desc */
464 struct udc_data_dma {
465 	/* status quadlet */
466 	u32	status;
467 	/* reserved */
468 	u32	_reserved;
469 	/* buffer pointer */
470 	u32	bufptr;
471 	/* next descriptor pointer */
472 	u32	next;
473 } __attribute__ ((aligned (16)));
474 
475 /* request packet */
476 struct udc_request {
477 	/* embedded gadget ep */
478 	struct usb_request		req;
479 
480 	/* flags */
481 	unsigned			dma_going : 1,
482 					dma_done : 1;
483 	/* phys. address */
484 	dma_addr_t			td_phys;
485 	/* first dma desc. of chain */
486 	struct udc_data_dma		*td_data;
487 	/* last dma desc. of chain */
488 	struct udc_data_dma		*td_data_last;
489 	struct list_head		queue;
490 
491 	/* chain length */
492 	unsigned			chain_len;
493 
494 };
495 
496 /* UDC specific endpoint parameters */
497 struct udc_ep {
498 	struct usb_ep			ep;
499 	struct udc_ep_regs __iomem	*regs;
500 	u32 __iomem			*txfifo;
501 	u32 __iomem			*dma;
502 	dma_addr_t			td_phys;
503 	dma_addr_t			td_stp_dma;
504 	struct udc_stp_dma		*td_stp;
505 	struct udc_data_dma		*td;
506 	/* temp request */
507 	struct udc_request		*req;
508 	unsigned			req_used;
509 	unsigned			req_completed;
510 	/* dummy DMA desc for BNA dummy */
511 	struct udc_request		*bna_dummy_req;
512 	unsigned			bna_occurred;
513 
514 	/* NAK state */
515 	unsigned			naking;
516 
517 	struct udc			*dev;
518 
519 	/* queue for requests */
520 	struct list_head		queue;
521 	unsigned			halted;
522 	unsigned			cancel_transfer;
523 	unsigned			num : 5,
524 					fifo_depth : 14,
525 					in : 1;
526 };
527 
528 /* device struct */
529 struct udc {
530 	struct usb_gadget		gadget;
531 	spinlock_t			lock;	/* protects all state */
532 	/* all endpoints */
533 	struct udc_ep			ep[UDC_EP_NUM];
534 	struct usb_gadget_driver	*driver;
535 	/* operational flags */
536 	unsigned			stall_ep0in : 1,
537 					waiting_zlp_ack_ep0in : 1,
538 					set_cfg_not_acked : 1,
539 					data_ep_enabled : 1,
540 					data_ep_queued : 1,
541 					sys_suspended : 1,
542 					connected;
543 
544 	u16				chiprev;
545 
546 	/* registers */
547 	struct pci_dev			*pdev;
548 	struct udc_csrs __iomem		*csr;
549 	struct udc_regs __iomem		*regs;
550 	struct udc_ep_regs __iomem	*ep_regs;
551 	u32 __iomem			*rxfifo;
552 	u32 __iomem			*txfifo;
553 
554 	/* DMA desc pools */
555 	struct dma_pool			*data_requests;
556 	struct dma_pool			*stp_requests;
557 
558 	/* device data */
559 	unsigned long			phys_addr;
560 	void __iomem			*virt_addr;
561 	unsigned			irq;
562 
563 	/* states */
564 	u16				cur_config;
565 	u16				cur_intf;
566 	u16				cur_alt;
567 
568 	/* for platform device and extcon support */
569 	struct device			*dev;
570 	struct phy			*udc_phy;
571 	struct extcon_dev		*edev;
572 	struct extcon_specific_cable_nb	extcon_nb;
573 	struct notifier_block		nb;
574 	struct delayed_work		drd_work;
575 	struct workqueue_struct		*drd_wq;
576 	u32				conn_type;
577 };
578 
579 #define to_amd5536_udc(g)	(container_of((g), struct udc, gadget))
580 
581 /* setup request data */
582 union udc_setup_data {
583 	u32			data[2];
584 	struct usb_ctrlrequest	request;
585 };
586 
587 /* Function declarations */
588 int udc_enable_dev_setup_interrupts(struct udc *dev);
589 int udc_mask_unused_interrupts(struct udc *dev);
590 irqreturn_t udc_irq(int irq, void *pdev);
591 void gadget_release(struct device *pdev);
592 void empty_req_queue(struct udc_ep *ep);
593 void udc_basic_init(struct udc *dev);
594 void free_dma_pools(struct udc *dev);
595 int init_dma_pools(struct udc *dev);
596 void udc_remove(struct udc *dev);
597 int udc_probe(struct udc *dev);
598 
599 /* DMA usage flag */
600 static bool use_dma = 1;
601 /* packet per buffer dma */
602 static bool use_dma_ppb = 1;
603 /* with per descr. update */
604 static bool use_dma_ppb_du;
605 /* full speed only mode */
606 static bool use_fullspeed;
607 
608 /* module parameters */
609 module_param(use_dma, bool, S_IRUGO);
610 MODULE_PARM_DESC(use_dma, "true for DMA");
611 module_param(use_dma_ppb, bool, S_IRUGO);
612 MODULE_PARM_DESC(use_dma_ppb, "true for DMA in packet per buffer mode");
613 module_param(use_dma_ppb_du, bool, S_IRUGO);
614 MODULE_PARM_DESC(use_dma_ppb_du,
615 	"true for DMA in packet per buffer mode with descriptor update");
616 module_param(use_fullspeed, bool, S_IRUGO);
617 MODULE_PARM_DESC(use_fullspeed, "true for fullspeed only");
618 /*
619  *---------------------------------------------------------------------------
620  * SET and GET bitfields in u32 values
621  * via constants for mask/offset:
622  * <bit_field_stub_name> is the text between
623  * UDC_ and _MASK|_OFS of appropriate
624  * constant
625  *
626  * set bitfield value in u32 u32Val
627  */
628 #define AMD_ADDBITS(u32Val, bitfield_val, bitfield_stub_name)		\
629 	(((u32Val) & (((u32) ~((u32) bitfield_stub_name##_MASK))))	\
630 	| (((bitfield_val) << ((u32) bitfield_stub_name##_OFS))		\
631 		& ((u32) bitfield_stub_name##_MASK)))
632 
633 /*
634  * set bitfield value in zero-initialized u32 u32Val
635  * => bitfield bits in u32Val are all zero
636  */
637 #define AMD_INIT_SETBITS(u32Val, bitfield_val, bitfield_stub_name)	\
638 	((u32Val)							\
639 	| (((bitfield_val) << ((u32) bitfield_stub_name##_OFS))		\
640 		& ((u32) bitfield_stub_name##_MASK)))
641 
642 /* get bitfield value from u32 u32Val */
643 #define AMD_GETBITS(u32Val, bitfield_stub_name)				\
644 	((u32Val & ((u32) bitfield_stub_name##_MASK))			\
645 		>> ((u32) bitfield_stub_name##_OFS))
646 
647 /* SET and GET bits in u32 values ------------------------------------------*/
648 #define AMD_BIT(bit_stub_name) (1 << bit_stub_name)
649 #define AMD_UNMASK_BIT(bit_stub_name) (~AMD_BIT(bit_stub_name))
650 #define AMD_CLEAR_BIT(bit_stub_name) (~AMD_BIT(bit_stub_name))
651 
652 /* debug macros ------------------------------------------------------------*/
653 
654 #define DBG(udc , args...)	dev_dbg(udc->dev, args)
655 
656 #ifdef UDC_VERBOSE
657 #define VDBG			DBG
658 #else
659 #define VDBG(udc , args...)	do {} while (0)
660 #endif
661 
662 #endif /* #ifdef AMD5536UDC_H */
663