1 /* 2 * amd5536.h -- header for AMD 5536 UDC high/full speed USB device controller 3 * 4 * Copyright (C) 2007 AMD (http://www.amd.com) 5 * Author: Thomas Dahlmann 6 * 7 * This program is free software; you can redistribute it and/or modify 8 * it under the terms of the GNU General Public License as published by 9 * the Free Software Foundation; either version 2 of the License, or 10 * (at your option) any later version. 11 */ 12 13 #ifndef AMD5536UDC_H 14 #define AMD5536UDC_H 15 16 /* debug control */ 17 /* #define UDC_VERBOSE */ 18 19 #include <linux/usb/ch9.h> 20 #include <linux/usb/gadget.h> 21 22 /* various constants */ 23 #define UDC_RDE_TIMER_SECONDS 1 24 #define UDC_RDE_TIMER_DIV 10 25 #define UDC_POLLSTALL_TIMER_USECONDS 500 26 27 /* Hs AMD5536 chip rev. */ 28 #define UDC_HSA0_REV 1 29 #define UDC_HSB1_REV 2 30 31 /* 32 * SETUP usb commands 33 * needed, because some SETUP's are handled in hw, but must be passed to 34 * gadget driver above 35 * SET_CONFIG 36 */ 37 #define UDC_SETCONFIG_DWORD0 0x00000900 38 #define UDC_SETCONFIG_DWORD0_VALUE_MASK 0xffff0000 39 #define UDC_SETCONFIG_DWORD0_VALUE_OFS 16 40 41 #define UDC_SETCONFIG_DWORD1 0x00000000 42 43 /* SET_INTERFACE */ 44 #define UDC_SETINTF_DWORD0 0x00000b00 45 #define UDC_SETINTF_DWORD0_ALT_MASK 0xffff0000 46 #define UDC_SETINTF_DWORD0_ALT_OFS 16 47 48 #define UDC_SETINTF_DWORD1 0x00000000 49 #define UDC_SETINTF_DWORD1_INTF_MASK 0x0000ffff 50 #define UDC_SETINTF_DWORD1_INTF_OFS 0 51 52 /* Mass storage reset */ 53 #define UDC_MSCRES_DWORD0 0x0000ff21 54 #define UDC_MSCRES_DWORD1 0x00000000 55 56 /* Global CSR's -------------------------------------------------------------*/ 57 #define UDC_CSR_ADDR 0x500 58 59 /* EP NE bits */ 60 /* EP number */ 61 #define UDC_CSR_NE_NUM_MASK 0x0000000f 62 #define UDC_CSR_NE_NUM_OFS 0 63 /* EP direction */ 64 #define UDC_CSR_NE_DIR_MASK 0x00000010 65 #define UDC_CSR_NE_DIR_OFS 4 66 /* EP type */ 67 #define UDC_CSR_NE_TYPE_MASK 0x00000060 68 #define UDC_CSR_NE_TYPE_OFS 5 69 /* EP config number */ 70 #define UDC_CSR_NE_CFG_MASK 0x00000780 71 #define UDC_CSR_NE_CFG_OFS 7 72 /* EP interface number */ 73 #define UDC_CSR_NE_INTF_MASK 0x00007800 74 #define UDC_CSR_NE_INTF_OFS 11 75 /* EP alt setting */ 76 #define UDC_CSR_NE_ALT_MASK 0x00078000 77 #define UDC_CSR_NE_ALT_OFS 15 78 79 /* max pkt */ 80 #define UDC_CSR_NE_MAX_PKT_MASK 0x3ff80000 81 #define UDC_CSR_NE_MAX_PKT_OFS 19 82 83 /* Device Config Register ---------------------------------------------------*/ 84 #define UDC_DEVCFG_ADDR 0x400 85 86 #define UDC_DEVCFG_SOFTRESET 31 87 #define UDC_DEVCFG_HNPSFEN 30 88 #define UDC_DEVCFG_DMARST 29 89 #define UDC_DEVCFG_SET_DESC 18 90 #define UDC_DEVCFG_CSR_PRG 17 91 #define UDC_DEVCFG_STATUS 7 92 #define UDC_DEVCFG_DIR 6 93 #define UDC_DEVCFG_PI 5 94 #define UDC_DEVCFG_SS 4 95 #define UDC_DEVCFG_SP 3 96 #define UDC_DEVCFG_RWKP 2 97 98 #define UDC_DEVCFG_SPD_MASK 0x3 99 #define UDC_DEVCFG_SPD_OFS 0 100 #define UDC_DEVCFG_SPD_HS 0x0 101 #define UDC_DEVCFG_SPD_FS 0x1 102 #define UDC_DEVCFG_SPD_LS 0x2 103 /*#define UDC_DEVCFG_SPD_FS 0x3*/ 104 105 106 /* Device Control Register --------------------------------------------------*/ 107 #define UDC_DEVCTL_ADDR 0x404 108 109 #define UDC_DEVCTL_THLEN_MASK 0xff000000 110 #define UDC_DEVCTL_THLEN_OFS 24 111 112 #define UDC_DEVCTL_BRLEN_MASK 0x00ff0000 113 #define UDC_DEVCTL_BRLEN_OFS 16 114 115 #define UDC_DEVCTL_CSR_DONE 13 116 #define UDC_DEVCTL_DEVNAK 12 117 #define UDC_DEVCTL_SD 10 118 #define UDC_DEVCTL_MODE 9 119 #define UDC_DEVCTL_BREN 8 120 #define UDC_DEVCTL_THE 7 121 #define UDC_DEVCTL_BF 6 122 #define UDC_DEVCTL_BE 5 123 #define UDC_DEVCTL_DU 4 124 #define UDC_DEVCTL_TDE 3 125 #define UDC_DEVCTL_RDE 2 126 #define UDC_DEVCTL_RES 0 127 128 129 /* Device Status Register ---------------------------------------------------*/ 130 #define UDC_DEVSTS_ADDR 0x408 131 132 #define UDC_DEVSTS_TS_MASK 0xfffc0000 133 #define UDC_DEVSTS_TS_OFS 18 134 135 #define UDC_DEVSTS_SESSVLD 17 136 #define UDC_DEVSTS_PHY_ERROR 16 137 #define UDC_DEVSTS_RXFIFO_EMPTY 15 138 139 #define UDC_DEVSTS_ENUM_SPEED_MASK 0x00006000 140 #define UDC_DEVSTS_ENUM_SPEED_OFS 13 141 #define UDC_DEVSTS_ENUM_SPEED_FULL 1 142 #define UDC_DEVSTS_ENUM_SPEED_HIGH 0 143 144 #define UDC_DEVSTS_SUSP 12 145 146 #define UDC_DEVSTS_ALT_MASK 0x00000f00 147 #define UDC_DEVSTS_ALT_OFS 8 148 149 #define UDC_DEVSTS_INTF_MASK 0x000000f0 150 #define UDC_DEVSTS_INTF_OFS 4 151 152 #define UDC_DEVSTS_CFG_MASK 0x0000000f 153 #define UDC_DEVSTS_CFG_OFS 0 154 155 156 /* Device Interrupt Register ------------------------------------------------*/ 157 #define UDC_DEVINT_ADDR 0x40c 158 159 #define UDC_DEVINT_SVC 7 160 #define UDC_DEVINT_ENUM 6 161 #define UDC_DEVINT_SOF 5 162 #define UDC_DEVINT_US 4 163 #define UDC_DEVINT_UR 3 164 #define UDC_DEVINT_ES 2 165 #define UDC_DEVINT_SI 1 166 #define UDC_DEVINT_SC 0 167 168 /* Device Interrupt Mask Register -------------------------------------------*/ 169 #define UDC_DEVINT_MSK_ADDR 0x410 170 171 #define UDC_DEVINT_MSK 0x7f 172 173 /* Endpoint Interrupt Register ----------------------------------------------*/ 174 #define UDC_EPINT_ADDR 0x414 175 176 #define UDC_EPINT_OUT_MASK 0xffff0000 177 #define UDC_EPINT_OUT_OFS 16 178 #define UDC_EPINT_IN_MASK 0x0000ffff 179 #define UDC_EPINT_IN_OFS 0 180 181 #define UDC_EPINT_IN_EP0 0 182 #define UDC_EPINT_IN_EP1 1 183 #define UDC_EPINT_IN_EP2 2 184 #define UDC_EPINT_IN_EP3 3 185 #define UDC_EPINT_OUT_EP0 16 186 #define UDC_EPINT_OUT_EP1 17 187 #define UDC_EPINT_OUT_EP2 18 188 #define UDC_EPINT_OUT_EP3 19 189 190 #define UDC_EPINT_EP0_ENABLE_MSK 0x001e001e 191 192 /* Endpoint Interrupt Mask Register -----------------------------------------*/ 193 #define UDC_EPINT_MSK_ADDR 0x418 194 195 #define UDC_EPINT_OUT_MSK_MASK 0xffff0000 196 #define UDC_EPINT_OUT_MSK_OFS 16 197 #define UDC_EPINT_IN_MSK_MASK 0x0000ffff 198 #define UDC_EPINT_IN_MSK_OFS 0 199 200 #define UDC_EPINT_MSK_DISABLE_ALL 0xffffffff 201 /* mask non-EP0 endpoints */ 202 #define UDC_EPDATAINT_MSK_DISABLE 0xfffefffe 203 /* mask all dev interrupts */ 204 #define UDC_DEV_MSK_DISABLE 0x7f 205 206 /* Endpoint-specific CSR's --------------------------------------------------*/ 207 #define UDC_EPREGS_ADDR 0x0 208 #define UDC_EPIN_REGS_ADDR 0x0 209 #define UDC_EPOUT_REGS_ADDR 0x200 210 211 #define UDC_EPCTL_ADDR 0x0 212 213 #define UDC_EPCTL_RRDY 9 214 #define UDC_EPCTL_CNAK 8 215 #define UDC_EPCTL_SNAK 7 216 #define UDC_EPCTL_NAK 6 217 218 #define UDC_EPCTL_ET_MASK 0x00000030 219 #define UDC_EPCTL_ET_OFS 4 220 #define UDC_EPCTL_ET_CONTROL 0 221 #define UDC_EPCTL_ET_ISO 1 222 #define UDC_EPCTL_ET_BULK 2 223 #define UDC_EPCTL_ET_INTERRUPT 3 224 225 #define UDC_EPCTL_P 3 226 #define UDC_EPCTL_SN 2 227 #define UDC_EPCTL_F 1 228 #define UDC_EPCTL_S 0 229 230 /* Endpoint Status Registers ------------------------------------------------*/ 231 #define UDC_EPSTS_ADDR 0x4 232 233 #define UDC_EPSTS_RX_PKT_SIZE_MASK 0x007ff800 234 #define UDC_EPSTS_RX_PKT_SIZE_OFS 11 235 236 #define UDC_EPSTS_TDC 10 237 #define UDC_EPSTS_HE 9 238 #define UDC_EPSTS_BNA 7 239 #define UDC_EPSTS_IN 6 240 241 #define UDC_EPSTS_OUT_MASK 0x00000030 242 #define UDC_EPSTS_OUT_OFS 4 243 #define UDC_EPSTS_OUT_DATA 1 244 #define UDC_EPSTS_OUT_DATA_CLEAR 0x10 245 #define UDC_EPSTS_OUT_SETUP 2 246 #define UDC_EPSTS_OUT_SETUP_CLEAR 0x20 247 #define UDC_EPSTS_OUT_CLEAR 0x30 248 249 /* Endpoint Buffer Size IN/ Receive Packet Frame Number OUT Registers ------*/ 250 #define UDC_EPIN_BUFF_SIZE_ADDR 0x8 251 #define UDC_EPOUT_FRAME_NUMBER_ADDR 0x8 252 253 #define UDC_EPIN_BUFF_SIZE_MASK 0x0000ffff 254 #define UDC_EPIN_BUFF_SIZE_OFS 0 255 /* EP0in txfifo = 128 bytes*/ 256 #define UDC_EPIN0_BUFF_SIZE 32 257 /* EP0in fullspeed txfifo = 128 bytes*/ 258 #define UDC_FS_EPIN0_BUFF_SIZE 32 259 260 /* fifo size mult = fifo size / max packet */ 261 #define UDC_EPIN_BUFF_SIZE_MULT 2 262 263 /* EPin data fifo size = 1024 bytes DOUBLE BUFFERING */ 264 #define UDC_EPIN_BUFF_SIZE 256 265 /* EPin small INT data fifo size = 128 bytes */ 266 #define UDC_EPIN_SMALLINT_BUFF_SIZE 32 267 268 /* EPin fullspeed data fifo size = 128 bytes DOUBLE BUFFERING */ 269 #define UDC_FS_EPIN_BUFF_SIZE 32 270 271 #define UDC_EPOUT_FRAME_NUMBER_MASK 0x0000ffff 272 #define UDC_EPOUT_FRAME_NUMBER_OFS 0 273 274 /* Endpoint Buffer Size OUT/Max Packet Size Registers -----------------------*/ 275 #define UDC_EPOUT_BUFF_SIZE_ADDR 0x0c 276 #define UDC_EP_MAX_PKT_SIZE_ADDR 0x0c 277 278 #define UDC_EPOUT_BUFF_SIZE_MASK 0xffff0000 279 #define UDC_EPOUT_BUFF_SIZE_OFS 16 280 #define UDC_EP_MAX_PKT_SIZE_MASK 0x0000ffff 281 #define UDC_EP_MAX_PKT_SIZE_OFS 0 282 /* EP0in max packet size = 64 bytes */ 283 #define UDC_EP0IN_MAX_PKT_SIZE 64 284 /* EP0out max packet size = 64 bytes */ 285 #define UDC_EP0OUT_MAX_PKT_SIZE 64 286 /* EP0in fullspeed max packet size = 64 bytes */ 287 #define UDC_FS_EP0IN_MAX_PKT_SIZE 64 288 /* EP0out fullspeed max packet size = 64 bytes */ 289 #define UDC_FS_EP0OUT_MAX_PKT_SIZE 64 290 291 /* 292 * Endpoint dma descriptors ------------------------------------------------ 293 * 294 * Setup data, Status dword 295 */ 296 #define UDC_DMA_STP_STS_CFG_MASK 0x0fff0000 297 #define UDC_DMA_STP_STS_CFG_OFS 16 298 #define UDC_DMA_STP_STS_CFG_ALT_MASK 0x000f0000 299 #define UDC_DMA_STP_STS_CFG_ALT_OFS 16 300 #define UDC_DMA_STP_STS_CFG_INTF_MASK 0x00f00000 301 #define UDC_DMA_STP_STS_CFG_INTF_OFS 20 302 #define UDC_DMA_STP_STS_CFG_NUM_MASK 0x0f000000 303 #define UDC_DMA_STP_STS_CFG_NUM_OFS 24 304 #define UDC_DMA_STP_STS_RX_MASK 0x30000000 305 #define UDC_DMA_STP_STS_RX_OFS 28 306 #define UDC_DMA_STP_STS_BS_MASK 0xc0000000 307 #define UDC_DMA_STP_STS_BS_OFS 30 308 #define UDC_DMA_STP_STS_BS_HOST_READY 0 309 #define UDC_DMA_STP_STS_BS_DMA_BUSY 1 310 #define UDC_DMA_STP_STS_BS_DMA_DONE 2 311 #define UDC_DMA_STP_STS_BS_HOST_BUSY 3 312 /* IN data, Status dword */ 313 #define UDC_DMA_IN_STS_TXBYTES_MASK 0x0000ffff 314 #define UDC_DMA_IN_STS_TXBYTES_OFS 0 315 #define UDC_DMA_IN_STS_FRAMENUM_MASK 0x07ff0000 316 #define UDC_DMA_IN_STS_FRAMENUM_OFS 0 317 #define UDC_DMA_IN_STS_L 27 318 #define UDC_DMA_IN_STS_TX_MASK 0x30000000 319 #define UDC_DMA_IN_STS_TX_OFS 28 320 #define UDC_DMA_IN_STS_BS_MASK 0xc0000000 321 #define UDC_DMA_IN_STS_BS_OFS 30 322 #define UDC_DMA_IN_STS_BS_HOST_READY 0 323 #define UDC_DMA_IN_STS_BS_DMA_BUSY 1 324 #define UDC_DMA_IN_STS_BS_DMA_DONE 2 325 #define UDC_DMA_IN_STS_BS_HOST_BUSY 3 326 /* OUT data, Status dword */ 327 #define UDC_DMA_OUT_STS_RXBYTES_MASK 0x0000ffff 328 #define UDC_DMA_OUT_STS_RXBYTES_OFS 0 329 #define UDC_DMA_OUT_STS_FRAMENUM_MASK 0x07ff0000 330 #define UDC_DMA_OUT_STS_FRAMENUM_OFS 0 331 #define UDC_DMA_OUT_STS_L 27 332 #define UDC_DMA_OUT_STS_RX_MASK 0x30000000 333 #define UDC_DMA_OUT_STS_RX_OFS 28 334 #define UDC_DMA_OUT_STS_BS_MASK 0xc0000000 335 #define UDC_DMA_OUT_STS_BS_OFS 30 336 #define UDC_DMA_OUT_STS_BS_HOST_READY 0 337 #define UDC_DMA_OUT_STS_BS_DMA_BUSY 1 338 #define UDC_DMA_OUT_STS_BS_DMA_DONE 2 339 #define UDC_DMA_OUT_STS_BS_HOST_BUSY 3 340 /* max ep0in packet */ 341 #define UDC_EP0IN_MAXPACKET 1000 342 /* max dma packet */ 343 #define UDC_DMA_MAXPACKET 65536 344 345 /* un-usable DMA address */ 346 #define DMA_DONT_USE (~(dma_addr_t) 0 ) 347 348 /* other Endpoint register addresses and values-----------------------------*/ 349 #define UDC_EP_SUBPTR_ADDR 0x10 350 #define UDC_EP_DESPTR_ADDR 0x14 351 #define UDC_EP_WRITE_CONFIRM_ADDR 0x1c 352 353 /* EP number as layouted in AHB space */ 354 #define UDC_EP_NUM 32 355 #define UDC_EPIN_NUM 16 356 #define UDC_EPIN_NUM_USED 5 357 #define UDC_EPOUT_NUM 16 358 /* EP number of EP's really used = EP0 + 8 data EP's */ 359 #define UDC_USED_EP_NUM 9 360 /* UDC CSR regs are aligned but AHB regs not - offset for OUT EP's */ 361 #define UDC_CSR_EP_OUT_IX_OFS 12 362 363 #define UDC_EP0OUT_IX 16 364 #define UDC_EP0IN_IX 0 365 366 /* Rx fifo address and size = 1k -------------------------------------------*/ 367 #define UDC_RXFIFO_ADDR 0x800 368 #define UDC_RXFIFO_SIZE 0x400 369 370 /* Tx fifo address and size = 1.5k -----------------------------------------*/ 371 #define UDC_TXFIFO_ADDR 0xc00 372 #define UDC_TXFIFO_SIZE 0x600 373 374 /* default data endpoints --------------------------------------------------*/ 375 #define UDC_EPIN_STATUS_IX 1 376 #define UDC_EPIN_IX 2 377 #define UDC_EPOUT_IX 18 378 379 /* general constants -------------------------------------------------------*/ 380 #define UDC_DWORD_BYTES 4 381 #define UDC_BITS_PER_BYTE_SHIFT 3 382 #define UDC_BYTE_MASK 0xff 383 #define UDC_BITS_PER_BYTE 8 384 385 /*---------------------------------------------------------------------------*/ 386 /* UDC CSR's */ 387 struct udc_csrs { 388 389 /* sca - setup command address */ 390 u32 sca; 391 392 /* ep ne's */ 393 u32 ne[UDC_USED_EP_NUM]; 394 } __attribute__ ((packed)); 395 396 /* AHB subsystem CSR registers */ 397 struct udc_regs { 398 399 /* device configuration */ 400 u32 cfg; 401 402 /* device control */ 403 u32 ctl; 404 405 /* device status */ 406 u32 sts; 407 408 /* device interrupt */ 409 u32 irqsts; 410 411 /* device interrupt mask */ 412 u32 irqmsk; 413 414 /* endpoint interrupt */ 415 u32 ep_irqsts; 416 417 /* endpoint interrupt mask */ 418 u32 ep_irqmsk; 419 } __attribute__ ((packed)); 420 421 /* endpoint specific registers */ 422 struct udc_ep_regs { 423 424 /* endpoint control */ 425 u32 ctl; 426 427 /* endpoint status */ 428 u32 sts; 429 430 /* endpoint buffer size in/ receive packet frame number out */ 431 u32 bufin_framenum; 432 433 /* endpoint buffer size out/max packet size */ 434 u32 bufout_maxpkt; 435 436 /* endpoint setup buffer pointer */ 437 u32 subptr; 438 439 /* endpoint data descriptor pointer */ 440 u32 desptr; 441 442 /* reserverd */ 443 u32 reserved; 444 445 /* write/read confirmation */ 446 u32 confirm; 447 448 } __attribute__ ((packed)); 449 450 /* control data DMA desc */ 451 struct udc_stp_dma { 452 /* status quadlet */ 453 u32 status; 454 /* reserved */ 455 u32 _reserved; 456 /* first setup word */ 457 u32 data12; 458 /* second setup word */ 459 u32 data34; 460 } __attribute__ ((aligned (16))); 461 462 /* normal data DMA desc */ 463 struct udc_data_dma { 464 /* status quadlet */ 465 u32 status; 466 /* reserved */ 467 u32 _reserved; 468 /* buffer pointer */ 469 u32 bufptr; 470 /* next descriptor pointer */ 471 u32 next; 472 } __attribute__ ((aligned (16))); 473 474 /* request packet */ 475 struct udc_request { 476 /* embedded gadget ep */ 477 struct usb_request req; 478 479 /* flags */ 480 unsigned dma_going : 1, 481 dma_done : 1; 482 /* phys. address */ 483 dma_addr_t td_phys; 484 /* first dma desc. of chain */ 485 struct udc_data_dma *td_data; 486 /* last dma desc. of chain */ 487 struct udc_data_dma *td_data_last; 488 struct list_head queue; 489 490 /* chain length */ 491 unsigned chain_len; 492 493 }; 494 495 /* UDC specific endpoint parameters */ 496 struct udc_ep { 497 struct usb_ep ep; 498 struct udc_ep_regs __iomem *regs; 499 u32 __iomem *txfifo; 500 u32 __iomem *dma; 501 dma_addr_t td_phys; 502 dma_addr_t td_stp_dma; 503 struct udc_stp_dma *td_stp; 504 struct udc_data_dma *td; 505 /* temp request */ 506 struct udc_request *req; 507 unsigned req_used; 508 unsigned req_completed; 509 /* dummy DMA desc for BNA dummy */ 510 struct udc_request *bna_dummy_req; 511 unsigned bna_occurred; 512 513 /* NAK state */ 514 unsigned naking; 515 516 struct udc *dev; 517 518 /* queue for requests */ 519 struct list_head queue; 520 unsigned halted; 521 unsigned cancel_transfer; 522 unsigned num : 5, 523 fifo_depth : 14, 524 in : 1; 525 }; 526 527 /* device struct */ 528 struct udc { 529 struct usb_gadget gadget; 530 spinlock_t lock; /* protects all state */ 531 /* all endpoints */ 532 struct udc_ep ep[UDC_EP_NUM]; 533 struct usb_gadget_driver *driver; 534 /* operational flags */ 535 unsigned stall_ep0in : 1, 536 waiting_zlp_ack_ep0in : 1, 537 set_cfg_not_acked : 1, 538 data_ep_enabled : 1, 539 data_ep_queued : 1, 540 sys_suspended : 1, 541 connected; 542 543 u16 chiprev; 544 545 /* registers */ 546 struct pci_dev *pdev; 547 struct udc_csrs __iomem *csr; 548 struct udc_regs __iomem *regs; 549 struct udc_ep_regs __iomem *ep_regs; 550 u32 __iomem *rxfifo; 551 u32 __iomem *txfifo; 552 553 /* DMA desc pools */ 554 struct dma_pool *data_requests; 555 struct dma_pool *stp_requests; 556 557 /* device data */ 558 unsigned long phys_addr; 559 void __iomem *virt_addr; 560 unsigned irq; 561 562 /* states */ 563 u16 cur_config; 564 u16 cur_intf; 565 u16 cur_alt; 566 }; 567 568 #define to_amd5536_udc(g) (container_of((g), struct udc, gadget)) 569 570 /* setup request data */ 571 union udc_setup_data { 572 u32 data[2]; 573 struct usb_ctrlrequest request; 574 }; 575 576 /* Function declarations */ 577 int udc_enable_dev_setup_interrupts(struct udc *dev); 578 int udc_mask_unused_interrupts(struct udc *dev); 579 irqreturn_t udc_irq(int irq, void *pdev); 580 void gadget_release(struct device *pdev); 581 void udc_basic_init(struct udc *dev); 582 void free_dma_pools(struct udc *dev); 583 int init_dma_pools(struct udc *dev); 584 void udc_remove(struct udc *dev); 585 int udc_probe(struct udc *dev); 586 587 /* DMA usage flag */ 588 static bool use_dma = 1; 589 /* packet per buffer dma */ 590 static bool use_dma_ppb = 1; 591 /* with per descr. update */ 592 static bool use_dma_ppb_du; 593 /* full speed only mode */ 594 static bool use_fullspeed; 595 596 /* module parameters */ 597 module_param(use_dma, bool, S_IRUGO); 598 MODULE_PARM_DESC(use_dma, "true for DMA"); 599 module_param(use_dma_ppb, bool, S_IRUGO); 600 MODULE_PARM_DESC(use_dma_ppb, "true for DMA in packet per buffer mode"); 601 module_param(use_dma_ppb_du, bool, S_IRUGO); 602 MODULE_PARM_DESC(use_dma_ppb_du, 603 "true for DMA in packet per buffer mode with descriptor update"); 604 module_param(use_fullspeed, bool, S_IRUGO); 605 MODULE_PARM_DESC(use_fullspeed, "true for fullspeed only"); 606 /* 607 *--------------------------------------------------------------------------- 608 * SET and GET bitfields in u32 values 609 * via constants for mask/offset: 610 * <bit_field_stub_name> is the text between 611 * UDC_ and _MASK|_OFS of appropriate 612 * constant 613 * 614 * set bitfield value in u32 u32Val 615 */ 616 #define AMD_ADDBITS(u32Val, bitfield_val, bitfield_stub_name) \ 617 (((u32Val) & (((u32) ~((u32) bitfield_stub_name##_MASK)))) \ 618 | (((bitfield_val) << ((u32) bitfield_stub_name##_OFS)) \ 619 & ((u32) bitfield_stub_name##_MASK))) 620 621 /* 622 * set bitfield value in zero-initialized u32 u32Val 623 * => bitfield bits in u32Val are all zero 624 */ 625 #define AMD_INIT_SETBITS(u32Val, bitfield_val, bitfield_stub_name) \ 626 ((u32Val) \ 627 | (((bitfield_val) << ((u32) bitfield_stub_name##_OFS)) \ 628 & ((u32) bitfield_stub_name##_MASK))) 629 630 /* get bitfield value from u32 u32Val */ 631 #define AMD_GETBITS(u32Val, bitfield_stub_name) \ 632 ((u32Val & ((u32) bitfield_stub_name##_MASK)) \ 633 >> ((u32) bitfield_stub_name##_OFS)) 634 635 /* SET and GET bits in u32 values ------------------------------------------*/ 636 #define AMD_BIT(bit_stub_name) (1 << bit_stub_name) 637 #define AMD_UNMASK_BIT(bit_stub_name) (~AMD_BIT(bit_stub_name)) 638 #define AMD_CLEAR_BIT(bit_stub_name) (~AMD_BIT(bit_stub_name)) 639 640 /* debug macros ------------------------------------------------------------*/ 641 642 #define DBG(udc , args...) dev_dbg(&(udc)->pdev->dev, args) 643 644 #ifdef UDC_VERBOSE 645 #define VDBG DBG 646 #else 647 #define VDBG(udc , args...) do {} while (0) 648 #endif 649 650 #endif /* #ifdef AMD5536UDC_H */ 651