1 /* 2 * amd5536.h -- header for AMD 5536 UDC high/full speed USB device controller 3 * 4 * Copyright (C) 2007 AMD (http://www.amd.com) 5 * Author: Thomas Dahlmann 6 * 7 * This program is free software; you can redistribute it and/or modify 8 * it under the terms of the GNU General Public License as published by 9 * the Free Software Foundation; either version 2 of the License, or 10 * (at your option) any later version. 11 */ 12 13 #ifndef AMD5536UDC_H 14 #define AMD5536UDC_H 15 16 /* debug control */ 17 /* #define UDC_VERBOSE */ 18 19 #include <linux/extcon.h> 20 #include <linux/usb/ch9.h> 21 #include <linux/usb/gadget.h> 22 23 /* various constants */ 24 #define UDC_RDE_TIMER_SECONDS 1 25 #define UDC_RDE_TIMER_DIV 10 26 #define UDC_POLLSTALL_TIMER_USECONDS 500 27 28 /* Hs AMD5536 chip rev. */ 29 #define UDC_HSA0_REV 1 30 #define UDC_HSB1_REV 2 31 32 /* Broadcom chip rev. */ 33 #define UDC_BCM_REV 10 34 35 /* 36 * SETUP usb commands 37 * needed, because some SETUP's are handled in hw, but must be passed to 38 * gadget driver above 39 * SET_CONFIG 40 */ 41 #define UDC_SETCONFIG_DWORD0 0x00000900 42 #define UDC_SETCONFIG_DWORD0_VALUE_MASK 0xffff0000 43 #define UDC_SETCONFIG_DWORD0_VALUE_OFS 16 44 45 #define UDC_SETCONFIG_DWORD1 0x00000000 46 47 /* SET_INTERFACE */ 48 #define UDC_SETINTF_DWORD0 0x00000b00 49 #define UDC_SETINTF_DWORD0_ALT_MASK 0xffff0000 50 #define UDC_SETINTF_DWORD0_ALT_OFS 16 51 52 #define UDC_SETINTF_DWORD1 0x00000000 53 #define UDC_SETINTF_DWORD1_INTF_MASK 0x0000ffff 54 #define UDC_SETINTF_DWORD1_INTF_OFS 0 55 56 /* Mass storage reset */ 57 #define UDC_MSCRES_DWORD0 0x0000ff21 58 #define UDC_MSCRES_DWORD1 0x00000000 59 60 /* Global CSR's -------------------------------------------------------------*/ 61 #define UDC_CSR_ADDR 0x500 62 63 /* EP NE bits */ 64 /* EP number */ 65 #define UDC_CSR_NE_NUM_MASK 0x0000000f 66 #define UDC_CSR_NE_NUM_OFS 0 67 /* EP direction */ 68 #define UDC_CSR_NE_DIR_MASK 0x00000010 69 #define UDC_CSR_NE_DIR_OFS 4 70 /* EP type */ 71 #define UDC_CSR_NE_TYPE_MASK 0x00000060 72 #define UDC_CSR_NE_TYPE_OFS 5 73 /* EP config number */ 74 #define UDC_CSR_NE_CFG_MASK 0x00000780 75 #define UDC_CSR_NE_CFG_OFS 7 76 /* EP interface number */ 77 #define UDC_CSR_NE_INTF_MASK 0x00007800 78 #define UDC_CSR_NE_INTF_OFS 11 79 /* EP alt setting */ 80 #define UDC_CSR_NE_ALT_MASK 0x00078000 81 #define UDC_CSR_NE_ALT_OFS 15 82 83 /* max pkt */ 84 #define UDC_CSR_NE_MAX_PKT_MASK 0x3ff80000 85 #define UDC_CSR_NE_MAX_PKT_OFS 19 86 87 /* Device Config Register ---------------------------------------------------*/ 88 #define UDC_DEVCFG_ADDR 0x400 89 90 #define UDC_DEVCFG_SOFTRESET 31 91 #define UDC_DEVCFG_HNPSFEN 30 92 #define UDC_DEVCFG_DMARST 29 93 #define UDC_DEVCFG_SET_DESC 18 94 #define UDC_DEVCFG_CSR_PRG 17 95 #define UDC_DEVCFG_STATUS 7 96 #define UDC_DEVCFG_DIR 6 97 #define UDC_DEVCFG_PI 5 98 #define UDC_DEVCFG_SS 4 99 #define UDC_DEVCFG_SP 3 100 #define UDC_DEVCFG_RWKP 2 101 102 #define UDC_DEVCFG_SPD_MASK 0x3 103 #define UDC_DEVCFG_SPD_OFS 0 104 #define UDC_DEVCFG_SPD_HS 0x0 105 #define UDC_DEVCFG_SPD_FS 0x1 106 #define UDC_DEVCFG_SPD_LS 0x2 107 /*#define UDC_DEVCFG_SPD_FS 0x3*/ 108 109 110 /* Device Control Register --------------------------------------------------*/ 111 #define UDC_DEVCTL_ADDR 0x404 112 113 #define UDC_DEVCTL_THLEN_MASK 0xff000000 114 #define UDC_DEVCTL_THLEN_OFS 24 115 116 #define UDC_DEVCTL_BRLEN_MASK 0x00ff0000 117 #define UDC_DEVCTL_BRLEN_OFS 16 118 119 #define UDC_DEVCTL_SRX_FLUSH 14 120 #define UDC_DEVCTL_CSR_DONE 13 121 #define UDC_DEVCTL_DEVNAK 12 122 #define UDC_DEVCTL_SD 10 123 #define UDC_DEVCTL_MODE 9 124 #define UDC_DEVCTL_BREN 8 125 #define UDC_DEVCTL_THE 7 126 #define UDC_DEVCTL_BF 6 127 #define UDC_DEVCTL_BE 5 128 #define UDC_DEVCTL_DU 4 129 #define UDC_DEVCTL_TDE 3 130 #define UDC_DEVCTL_RDE 2 131 #define UDC_DEVCTL_RES 0 132 133 134 /* Device Status Register ---------------------------------------------------*/ 135 #define UDC_DEVSTS_ADDR 0x408 136 137 #define UDC_DEVSTS_TS_MASK 0xfffc0000 138 #define UDC_DEVSTS_TS_OFS 18 139 140 #define UDC_DEVSTS_SESSVLD 17 141 #define UDC_DEVSTS_PHY_ERROR 16 142 #define UDC_DEVSTS_RXFIFO_EMPTY 15 143 144 #define UDC_DEVSTS_ENUM_SPEED_MASK 0x00006000 145 #define UDC_DEVSTS_ENUM_SPEED_OFS 13 146 #define UDC_DEVSTS_ENUM_SPEED_FULL 1 147 #define UDC_DEVSTS_ENUM_SPEED_HIGH 0 148 149 #define UDC_DEVSTS_SUSP 12 150 151 #define UDC_DEVSTS_ALT_MASK 0x00000f00 152 #define UDC_DEVSTS_ALT_OFS 8 153 154 #define UDC_DEVSTS_INTF_MASK 0x000000f0 155 #define UDC_DEVSTS_INTF_OFS 4 156 157 #define UDC_DEVSTS_CFG_MASK 0x0000000f 158 #define UDC_DEVSTS_CFG_OFS 0 159 160 161 /* Device Interrupt Register ------------------------------------------------*/ 162 #define UDC_DEVINT_ADDR 0x40c 163 164 #define UDC_DEVINT_SVC 7 165 #define UDC_DEVINT_ENUM 6 166 #define UDC_DEVINT_SOF 5 167 #define UDC_DEVINT_US 4 168 #define UDC_DEVINT_UR 3 169 #define UDC_DEVINT_ES 2 170 #define UDC_DEVINT_SI 1 171 #define UDC_DEVINT_SC 0 172 173 /* Device Interrupt Mask Register -------------------------------------------*/ 174 #define UDC_DEVINT_MSK_ADDR 0x410 175 176 #define UDC_DEVINT_MSK 0x7f 177 178 /* Endpoint Interrupt Register ----------------------------------------------*/ 179 #define UDC_EPINT_ADDR 0x414 180 181 #define UDC_EPINT_OUT_MASK 0xffff0000 182 #define UDC_EPINT_OUT_OFS 16 183 #define UDC_EPINT_IN_MASK 0x0000ffff 184 #define UDC_EPINT_IN_OFS 0 185 186 #define UDC_EPINT_IN_EP0 0 187 #define UDC_EPINT_IN_EP1 1 188 #define UDC_EPINT_IN_EP2 2 189 #define UDC_EPINT_IN_EP3 3 190 #define UDC_EPINT_OUT_EP0 16 191 #define UDC_EPINT_OUT_EP1 17 192 #define UDC_EPINT_OUT_EP2 18 193 #define UDC_EPINT_OUT_EP3 19 194 195 #define UDC_EPINT_EP0_ENABLE_MSK 0x001e001e 196 197 /* Endpoint Interrupt Mask Register -----------------------------------------*/ 198 #define UDC_EPINT_MSK_ADDR 0x418 199 200 #define UDC_EPINT_OUT_MSK_MASK 0xffff0000 201 #define UDC_EPINT_OUT_MSK_OFS 16 202 #define UDC_EPINT_IN_MSK_MASK 0x0000ffff 203 #define UDC_EPINT_IN_MSK_OFS 0 204 205 #define UDC_EPINT_MSK_DISABLE_ALL 0xffffffff 206 /* mask non-EP0 endpoints */ 207 #define UDC_EPDATAINT_MSK_DISABLE 0xfffefffe 208 /* mask all dev interrupts */ 209 #define UDC_DEV_MSK_DISABLE 0x7f 210 211 /* Endpoint-specific CSR's --------------------------------------------------*/ 212 #define UDC_EPREGS_ADDR 0x0 213 #define UDC_EPIN_REGS_ADDR 0x0 214 #define UDC_EPOUT_REGS_ADDR 0x200 215 216 #define UDC_EPCTL_ADDR 0x0 217 218 #define UDC_EPCTL_RRDY 9 219 #define UDC_EPCTL_CNAK 8 220 #define UDC_EPCTL_SNAK 7 221 #define UDC_EPCTL_NAK 6 222 223 #define UDC_EPCTL_ET_MASK 0x00000030 224 #define UDC_EPCTL_ET_OFS 4 225 #define UDC_EPCTL_ET_CONTROL 0 226 #define UDC_EPCTL_ET_ISO 1 227 #define UDC_EPCTL_ET_BULK 2 228 #define UDC_EPCTL_ET_INTERRUPT 3 229 230 #define UDC_EPCTL_P 3 231 #define UDC_EPCTL_SN 2 232 #define UDC_EPCTL_F 1 233 #define UDC_EPCTL_S 0 234 235 /* Endpoint Status Registers ------------------------------------------------*/ 236 #define UDC_EPSTS_ADDR 0x4 237 238 #define UDC_EPSTS_RX_PKT_SIZE_MASK 0x007ff800 239 #define UDC_EPSTS_RX_PKT_SIZE_OFS 11 240 241 #define UDC_EPSTS_TDC 10 242 #define UDC_EPSTS_HE 9 243 #define UDC_EPSTS_BNA 7 244 #define UDC_EPSTS_IN 6 245 246 #define UDC_EPSTS_OUT_MASK 0x00000030 247 #define UDC_EPSTS_OUT_OFS 4 248 #define UDC_EPSTS_OUT_DATA 1 249 #define UDC_EPSTS_OUT_DATA_CLEAR 0x10 250 #define UDC_EPSTS_OUT_SETUP 2 251 #define UDC_EPSTS_OUT_SETUP_CLEAR 0x20 252 #define UDC_EPSTS_OUT_CLEAR 0x30 253 254 /* Endpoint Buffer Size IN/ Receive Packet Frame Number OUT Registers ------*/ 255 #define UDC_EPIN_BUFF_SIZE_ADDR 0x8 256 #define UDC_EPOUT_FRAME_NUMBER_ADDR 0x8 257 258 #define UDC_EPIN_BUFF_SIZE_MASK 0x0000ffff 259 #define UDC_EPIN_BUFF_SIZE_OFS 0 260 /* EP0in txfifo = 128 bytes*/ 261 #define UDC_EPIN0_BUFF_SIZE 32 262 /* EP0in fullspeed txfifo = 128 bytes*/ 263 #define UDC_FS_EPIN0_BUFF_SIZE 32 264 265 /* fifo size mult = fifo size / max packet */ 266 #define UDC_EPIN_BUFF_SIZE_MULT 2 267 268 /* EPin data fifo size = 1024 bytes DOUBLE BUFFERING */ 269 #define UDC_EPIN_BUFF_SIZE 256 270 /* EPin small INT data fifo size = 128 bytes */ 271 #define UDC_EPIN_SMALLINT_BUFF_SIZE 32 272 273 /* EPin fullspeed data fifo size = 128 bytes DOUBLE BUFFERING */ 274 #define UDC_FS_EPIN_BUFF_SIZE 32 275 276 #define UDC_EPOUT_FRAME_NUMBER_MASK 0x0000ffff 277 #define UDC_EPOUT_FRAME_NUMBER_OFS 0 278 279 /* Endpoint Buffer Size OUT/Max Packet Size Registers -----------------------*/ 280 #define UDC_EPOUT_BUFF_SIZE_ADDR 0x0c 281 #define UDC_EP_MAX_PKT_SIZE_ADDR 0x0c 282 283 #define UDC_EPOUT_BUFF_SIZE_MASK 0xffff0000 284 #define UDC_EPOUT_BUFF_SIZE_OFS 16 285 #define UDC_EP_MAX_PKT_SIZE_MASK 0x0000ffff 286 #define UDC_EP_MAX_PKT_SIZE_OFS 0 287 /* EP0in max packet size = 64 bytes */ 288 #define UDC_EP0IN_MAX_PKT_SIZE 64 289 /* EP0out max packet size = 64 bytes */ 290 #define UDC_EP0OUT_MAX_PKT_SIZE 64 291 /* EP0in fullspeed max packet size = 64 bytes */ 292 #define UDC_FS_EP0IN_MAX_PKT_SIZE 64 293 /* EP0out fullspeed max packet size = 64 bytes */ 294 #define UDC_FS_EP0OUT_MAX_PKT_SIZE 64 295 296 /* 297 * Endpoint dma descriptors ------------------------------------------------ 298 * 299 * Setup data, Status dword 300 */ 301 #define UDC_DMA_STP_STS_CFG_MASK 0x0fff0000 302 #define UDC_DMA_STP_STS_CFG_OFS 16 303 #define UDC_DMA_STP_STS_CFG_ALT_MASK 0x000f0000 304 #define UDC_DMA_STP_STS_CFG_ALT_OFS 16 305 #define UDC_DMA_STP_STS_CFG_INTF_MASK 0x00f00000 306 #define UDC_DMA_STP_STS_CFG_INTF_OFS 20 307 #define UDC_DMA_STP_STS_CFG_NUM_MASK 0x0f000000 308 #define UDC_DMA_STP_STS_CFG_NUM_OFS 24 309 #define UDC_DMA_STP_STS_RX_MASK 0x30000000 310 #define UDC_DMA_STP_STS_RX_OFS 28 311 #define UDC_DMA_STP_STS_BS_MASK 0xc0000000 312 #define UDC_DMA_STP_STS_BS_OFS 30 313 #define UDC_DMA_STP_STS_BS_HOST_READY 0 314 #define UDC_DMA_STP_STS_BS_DMA_BUSY 1 315 #define UDC_DMA_STP_STS_BS_DMA_DONE 2 316 #define UDC_DMA_STP_STS_BS_HOST_BUSY 3 317 /* IN data, Status dword */ 318 #define UDC_DMA_IN_STS_TXBYTES_MASK 0x0000ffff 319 #define UDC_DMA_IN_STS_TXBYTES_OFS 0 320 #define UDC_DMA_IN_STS_FRAMENUM_MASK 0x07ff0000 321 #define UDC_DMA_IN_STS_FRAMENUM_OFS 0 322 #define UDC_DMA_IN_STS_L 27 323 #define UDC_DMA_IN_STS_TX_MASK 0x30000000 324 #define UDC_DMA_IN_STS_TX_OFS 28 325 #define UDC_DMA_IN_STS_BS_MASK 0xc0000000 326 #define UDC_DMA_IN_STS_BS_OFS 30 327 #define UDC_DMA_IN_STS_BS_HOST_READY 0 328 #define UDC_DMA_IN_STS_BS_DMA_BUSY 1 329 #define UDC_DMA_IN_STS_BS_DMA_DONE 2 330 #define UDC_DMA_IN_STS_BS_HOST_BUSY 3 331 /* OUT data, Status dword */ 332 #define UDC_DMA_OUT_STS_RXBYTES_MASK 0x0000ffff 333 #define UDC_DMA_OUT_STS_RXBYTES_OFS 0 334 #define UDC_DMA_OUT_STS_FRAMENUM_MASK 0x07ff0000 335 #define UDC_DMA_OUT_STS_FRAMENUM_OFS 0 336 #define UDC_DMA_OUT_STS_L 27 337 #define UDC_DMA_OUT_STS_RX_MASK 0x30000000 338 #define UDC_DMA_OUT_STS_RX_OFS 28 339 #define UDC_DMA_OUT_STS_BS_MASK 0xc0000000 340 #define UDC_DMA_OUT_STS_BS_OFS 30 341 #define UDC_DMA_OUT_STS_BS_HOST_READY 0 342 #define UDC_DMA_OUT_STS_BS_DMA_BUSY 1 343 #define UDC_DMA_OUT_STS_BS_DMA_DONE 2 344 #define UDC_DMA_OUT_STS_BS_HOST_BUSY 3 345 /* max ep0in packet */ 346 #define UDC_EP0IN_MAXPACKET 1000 347 /* max dma packet */ 348 #define UDC_DMA_MAXPACKET 65536 349 350 /* un-usable DMA address */ 351 #define DMA_DONT_USE (~(dma_addr_t) 0 ) 352 353 /* other Endpoint register addresses and values-----------------------------*/ 354 #define UDC_EP_SUBPTR_ADDR 0x10 355 #define UDC_EP_DESPTR_ADDR 0x14 356 #define UDC_EP_WRITE_CONFIRM_ADDR 0x1c 357 358 /* EP number as layouted in AHB space */ 359 #define UDC_EP_NUM 32 360 #define UDC_EPIN_NUM 16 361 #define UDC_EPIN_NUM_USED 5 362 #define UDC_EPOUT_NUM 16 363 /* EP number of EP's really used = EP0 + 8 data EP's */ 364 #define UDC_USED_EP_NUM 9 365 /* UDC CSR regs are aligned but AHB regs not - offset for OUT EP's */ 366 #define UDC_CSR_EP_OUT_IX_OFS 12 367 368 #define UDC_EP0OUT_IX 16 369 #define UDC_EP0IN_IX 0 370 371 /* Rx fifo address and size = 1k -------------------------------------------*/ 372 #define UDC_RXFIFO_ADDR 0x800 373 #define UDC_RXFIFO_SIZE 0x400 374 375 /* Tx fifo address and size = 1.5k -----------------------------------------*/ 376 #define UDC_TXFIFO_ADDR 0xc00 377 #define UDC_TXFIFO_SIZE 0x600 378 379 /* default data endpoints --------------------------------------------------*/ 380 #define UDC_EPIN_STATUS_IX 1 381 #define UDC_EPIN_IX 2 382 #define UDC_EPOUT_IX 18 383 384 /* general constants -------------------------------------------------------*/ 385 #define UDC_DWORD_BYTES 4 386 #define UDC_BITS_PER_BYTE_SHIFT 3 387 #define UDC_BYTE_MASK 0xff 388 #define UDC_BITS_PER_BYTE 8 389 390 /*---------------------------------------------------------------------------*/ 391 /* UDC CSR's */ 392 struct udc_csrs { 393 394 /* sca - setup command address */ 395 u32 sca; 396 397 /* ep ne's */ 398 u32 ne[UDC_USED_EP_NUM]; 399 } __attribute__ ((packed)); 400 401 /* AHB subsystem CSR registers */ 402 struct udc_regs { 403 404 /* device configuration */ 405 u32 cfg; 406 407 /* device control */ 408 u32 ctl; 409 410 /* device status */ 411 u32 sts; 412 413 /* device interrupt */ 414 u32 irqsts; 415 416 /* device interrupt mask */ 417 u32 irqmsk; 418 419 /* endpoint interrupt */ 420 u32 ep_irqsts; 421 422 /* endpoint interrupt mask */ 423 u32 ep_irqmsk; 424 } __attribute__ ((packed)); 425 426 /* endpoint specific registers */ 427 struct udc_ep_regs { 428 429 /* endpoint control */ 430 u32 ctl; 431 432 /* endpoint status */ 433 u32 sts; 434 435 /* endpoint buffer size in/ receive packet frame number out */ 436 u32 bufin_framenum; 437 438 /* endpoint buffer size out/max packet size */ 439 u32 bufout_maxpkt; 440 441 /* endpoint setup buffer pointer */ 442 u32 subptr; 443 444 /* endpoint data descriptor pointer */ 445 u32 desptr; 446 447 /* reserverd */ 448 u32 reserved; 449 450 /* write/read confirmation */ 451 u32 confirm; 452 453 } __attribute__ ((packed)); 454 455 /* control data DMA desc */ 456 struct udc_stp_dma { 457 /* status quadlet */ 458 u32 status; 459 /* reserved */ 460 u32 _reserved; 461 /* first setup word */ 462 u32 data12; 463 /* second setup word */ 464 u32 data34; 465 } __attribute__ ((aligned (16))); 466 467 /* normal data DMA desc */ 468 struct udc_data_dma { 469 /* status quadlet */ 470 u32 status; 471 /* reserved */ 472 u32 _reserved; 473 /* buffer pointer */ 474 u32 bufptr; 475 /* next descriptor pointer */ 476 u32 next; 477 } __attribute__ ((aligned (16))); 478 479 /* request packet */ 480 struct udc_request { 481 /* embedded gadget ep */ 482 struct usb_request req; 483 484 /* flags */ 485 unsigned dma_going : 1, 486 dma_done : 1; 487 /* phys. address */ 488 dma_addr_t td_phys; 489 /* first dma desc. of chain */ 490 struct udc_data_dma *td_data; 491 /* last dma desc. of chain */ 492 struct udc_data_dma *td_data_last; 493 struct list_head queue; 494 495 /* chain length */ 496 unsigned chain_len; 497 498 }; 499 500 /* UDC specific endpoint parameters */ 501 struct udc_ep { 502 struct usb_ep ep; 503 struct udc_ep_regs __iomem *regs; 504 u32 __iomem *txfifo; 505 u32 __iomem *dma; 506 dma_addr_t td_phys; 507 dma_addr_t td_stp_dma; 508 struct udc_stp_dma *td_stp; 509 struct udc_data_dma *td; 510 /* temp request */ 511 struct udc_request *req; 512 unsigned req_used; 513 unsigned req_completed; 514 /* dummy DMA desc for BNA dummy */ 515 struct udc_request *bna_dummy_req; 516 unsigned bna_occurred; 517 518 /* NAK state */ 519 unsigned naking; 520 521 struct udc *dev; 522 523 /* queue for requests */ 524 struct list_head queue; 525 unsigned halted; 526 unsigned cancel_transfer; 527 unsigned num : 5, 528 fifo_depth : 14, 529 in : 1; 530 }; 531 532 /* device struct */ 533 struct udc { 534 struct usb_gadget gadget; 535 spinlock_t lock; /* protects all state */ 536 /* all endpoints */ 537 struct udc_ep ep[UDC_EP_NUM]; 538 struct usb_gadget_driver *driver; 539 /* operational flags */ 540 unsigned stall_ep0in : 1, 541 waiting_zlp_ack_ep0in : 1, 542 set_cfg_not_acked : 1, 543 data_ep_enabled : 1, 544 data_ep_queued : 1, 545 sys_suspended : 1, 546 connected; 547 548 u16 chiprev; 549 550 /* registers */ 551 struct pci_dev *pdev; 552 struct udc_csrs __iomem *csr; 553 struct udc_regs __iomem *regs; 554 struct udc_ep_regs __iomem *ep_regs; 555 u32 __iomem *rxfifo; 556 u32 __iomem *txfifo; 557 558 /* DMA desc pools */ 559 struct dma_pool *data_requests; 560 struct dma_pool *stp_requests; 561 562 /* device data */ 563 unsigned long phys_addr; 564 void __iomem *virt_addr; 565 unsigned irq; 566 567 /* states */ 568 u16 cur_config; 569 u16 cur_intf; 570 u16 cur_alt; 571 572 /* for platform device and extcon support */ 573 struct device *dev; 574 struct phy *udc_phy; 575 struct extcon_dev *edev; 576 struct extcon_specific_cable_nb extcon_nb; 577 struct notifier_block nb; 578 struct delayed_work drd_work; 579 struct workqueue_struct *drd_wq; 580 u32 conn_type; 581 }; 582 583 #define to_amd5536_udc(g) (container_of((g), struct udc, gadget)) 584 585 /* setup request data */ 586 union udc_setup_data { 587 u32 data[2]; 588 struct usb_ctrlrequest request; 589 }; 590 591 /* Function declarations */ 592 int udc_enable_dev_setup_interrupts(struct udc *dev); 593 int udc_mask_unused_interrupts(struct udc *dev); 594 irqreturn_t udc_irq(int irq, void *pdev); 595 void gadget_release(struct device *pdev); 596 void empty_req_queue(struct udc_ep *ep); 597 void udc_basic_init(struct udc *dev); 598 void free_dma_pools(struct udc *dev); 599 int init_dma_pools(struct udc *dev); 600 void udc_remove(struct udc *dev); 601 int udc_probe(struct udc *dev); 602 603 /* DMA usage flag */ 604 static bool use_dma = 1; 605 /* packet per buffer dma */ 606 static bool use_dma_ppb = 1; 607 /* with per descr. update */ 608 static bool use_dma_ppb_du; 609 /* full speed only mode */ 610 static bool use_fullspeed; 611 612 /* module parameters */ 613 module_param(use_dma, bool, S_IRUGO); 614 MODULE_PARM_DESC(use_dma, "true for DMA"); 615 module_param(use_dma_ppb, bool, S_IRUGO); 616 MODULE_PARM_DESC(use_dma_ppb, "true for DMA in packet per buffer mode"); 617 module_param(use_dma_ppb_du, bool, S_IRUGO); 618 MODULE_PARM_DESC(use_dma_ppb_du, 619 "true for DMA in packet per buffer mode with descriptor update"); 620 module_param(use_fullspeed, bool, S_IRUGO); 621 MODULE_PARM_DESC(use_fullspeed, "true for fullspeed only"); 622 /* 623 *--------------------------------------------------------------------------- 624 * SET and GET bitfields in u32 values 625 * via constants for mask/offset: 626 * <bit_field_stub_name> is the text between 627 * UDC_ and _MASK|_OFS of appropriate 628 * constant 629 * 630 * set bitfield value in u32 u32Val 631 */ 632 #define AMD_ADDBITS(u32Val, bitfield_val, bitfield_stub_name) \ 633 (((u32Val) & (((u32) ~((u32) bitfield_stub_name##_MASK)))) \ 634 | (((bitfield_val) << ((u32) bitfield_stub_name##_OFS)) \ 635 & ((u32) bitfield_stub_name##_MASK))) 636 637 /* 638 * set bitfield value in zero-initialized u32 u32Val 639 * => bitfield bits in u32Val are all zero 640 */ 641 #define AMD_INIT_SETBITS(u32Val, bitfield_val, bitfield_stub_name) \ 642 ((u32Val) \ 643 | (((bitfield_val) << ((u32) bitfield_stub_name##_OFS)) \ 644 & ((u32) bitfield_stub_name##_MASK))) 645 646 /* get bitfield value from u32 u32Val */ 647 #define AMD_GETBITS(u32Val, bitfield_stub_name) \ 648 ((u32Val & ((u32) bitfield_stub_name##_MASK)) \ 649 >> ((u32) bitfield_stub_name##_OFS)) 650 651 /* SET and GET bits in u32 values ------------------------------------------*/ 652 #define AMD_BIT(bit_stub_name) (1 << bit_stub_name) 653 #define AMD_UNMASK_BIT(bit_stub_name) (~AMD_BIT(bit_stub_name)) 654 #define AMD_CLEAR_BIT(bit_stub_name) (~AMD_BIT(bit_stub_name)) 655 656 /* debug macros ------------------------------------------------------------*/ 657 658 #define DBG(udc , args...) dev_dbg(udc->dev, args) 659 660 #ifdef UDC_VERBOSE 661 #define VDBG DBG 662 #else 663 #define VDBG(udc , args...) do {} while (0) 664 #endif 665 666 #endif /* #ifdef AMD5536UDC_H */ 667