1 /** 2 * xhci-dbc.c - xHCI debug capability early driver 3 * 4 * Copyright (C) 2016 Intel Corporation 5 * 6 * Author: Lu Baolu <baolu.lu@linux.intel.com> 7 * 8 * This program is free software; you can redistribute it and/or modify 9 * it under the terms of the GNU General Public License version 2 as 10 * published by the Free Software Foundation. 11 */ 12 13 #define pr_fmt(fmt) KBUILD_MODNAME ":%s: " fmt, __func__ 14 15 #include <linux/console.h> 16 #include <linux/pci_regs.h> 17 #include <linux/pci_ids.h> 18 #include <linux/bootmem.h> 19 #include <linux/io.h> 20 #include <asm/pci-direct.h> 21 #include <asm/fixmap.h> 22 #include <linux/bcd.h> 23 #include <linux/export.h> 24 #include <linux/version.h> 25 #include <linux/module.h> 26 #include <linux/delay.h> 27 #include <linux/kthread.h> 28 29 #include "../host/xhci.h" 30 #include "xhci-dbc.h" 31 32 static struct xdbc_state xdbc; 33 static bool early_console_keep; 34 35 #define XDBC_TRACE 36 #ifdef XDBC_TRACE 37 #define xdbc_trace trace_printk 38 #else 39 static inline void xdbc_trace(const char *fmt, ...) { } 40 #endif /* XDBC_TRACE */ 41 42 static void __iomem * __init xdbc_map_pci_mmio(u32 bus, u32 dev, u32 func) 43 { 44 u64 val64, sz64, mask64; 45 void __iomem *base; 46 u32 val, sz; 47 u8 byte; 48 49 val = read_pci_config(bus, dev, func, PCI_BASE_ADDRESS_0); 50 write_pci_config(bus, dev, func, PCI_BASE_ADDRESS_0, ~0); 51 sz = read_pci_config(bus, dev, func, PCI_BASE_ADDRESS_0); 52 write_pci_config(bus, dev, func, PCI_BASE_ADDRESS_0, val); 53 54 if (val == 0xffffffff || sz == 0xffffffff) { 55 pr_notice("invalid mmio bar\n"); 56 return NULL; 57 } 58 59 val64 = val & PCI_BASE_ADDRESS_MEM_MASK; 60 sz64 = sz & PCI_BASE_ADDRESS_MEM_MASK; 61 mask64 = PCI_BASE_ADDRESS_MEM_MASK; 62 63 if ((val & PCI_BASE_ADDRESS_MEM_TYPE_MASK) == PCI_BASE_ADDRESS_MEM_TYPE_64) { 64 val = read_pci_config(bus, dev, func, PCI_BASE_ADDRESS_0 + 4); 65 write_pci_config(bus, dev, func, PCI_BASE_ADDRESS_0 + 4, ~0); 66 sz = read_pci_config(bus, dev, func, PCI_BASE_ADDRESS_0 + 4); 67 write_pci_config(bus, dev, func, PCI_BASE_ADDRESS_0 + 4, val); 68 69 val64 |= (u64)val << 32; 70 sz64 |= (u64)sz << 32; 71 mask64 |= ~0ULL << 32; 72 } 73 74 sz64 &= mask64; 75 76 if (!sz64) { 77 pr_notice("invalid mmio address\n"); 78 return NULL; 79 } 80 81 sz64 = 1ULL << __ffs64(sz64); 82 83 /* Check if the mem space is enabled: */ 84 byte = read_pci_config_byte(bus, dev, func, PCI_COMMAND); 85 if (!(byte & PCI_COMMAND_MEMORY)) { 86 byte |= PCI_COMMAND_MEMORY; 87 write_pci_config_byte(bus, dev, func, PCI_COMMAND, byte); 88 } 89 90 xdbc.xhci_start = val64; 91 xdbc.xhci_length = sz64; 92 base = early_ioremap(val64, sz64); 93 94 return base; 95 } 96 97 static void * __init xdbc_get_page(dma_addr_t *dma_addr) 98 { 99 void *virt; 100 101 virt = alloc_bootmem_pages_nopanic(PAGE_SIZE); 102 if (!virt) 103 return NULL; 104 105 if (dma_addr) 106 *dma_addr = (dma_addr_t)__pa(virt); 107 108 return virt; 109 } 110 111 static u32 __init xdbc_find_dbgp(int xdbc_num, u32 *b, u32 *d, u32 *f) 112 { 113 u32 bus, dev, func, class; 114 115 for (bus = 0; bus < XDBC_PCI_MAX_BUSES; bus++) { 116 for (dev = 0; dev < XDBC_PCI_MAX_DEVICES; dev++) { 117 for (func = 0; func < XDBC_PCI_MAX_FUNCTION; func++) { 118 119 class = read_pci_config(bus, dev, func, PCI_CLASS_REVISION); 120 if ((class >> 8) != PCI_CLASS_SERIAL_USB_XHCI) 121 continue; 122 123 if (xdbc_num-- != 0) 124 continue; 125 126 *b = bus; 127 *d = dev; 128 *f = func; 129 130 return 0; 131 } 132 } 133 } 134 135 return -1; 136 } 137 138 static int handshake(void __iomem *ptr, u32 mask, u32 done, int wait, int delay) 139 { 140 u32 result; 141 142 do { 143 result = readl(ptr); 144 result &= mask; 145 if (result == done) 146 return 0; 147 udelay(delay); 148 wait -= delay; 149 } while (wait > 0); 150 151 return -ETIMEDOUT; 152 } 153 154 static void __init xdbc_bios_handoff(void) 155 { 156 int offset, timeout; 157 u32 val; 158 159 offset = xhci_find_next_ext_cap(xdbc.xhci_base, 0, XHCI_EXT_CAPS_LEGACY); 160 val = readl(xdbc.xhci_base + offset); 161 162 if (val & XHCI_HC_BIOS_OWNED) { 163 writel(val | XHCI_HC_OS_OWNED, xdbc.xhci_base + offset); 164 timeout = handshake(xdbc.xhci_base + offset, XHCI_HC_BIOS_OWNED, 0, 5000, 10); 165 166 if (timeout) { 167 pr_notice("failed to hand over xHCI control from BIOS\n"); 168 writel(val & ~XHCI_HC_BIOS_OWNED, xdbc.xhci_base + offset); 169 } 170 } 171 172 /* Disable BIOS SMIs and clear all SMI events: */ 173 val = readl(xdbc.xhci_base + offset + XHCI_LEGACY_CONTROL_OFFSET); 174 val &= XHCI_LEGACY_DISABLE_SMI; 175 val |= XHCI_LEGACY_SMI_EVENTS; 176 writel(val, xdbc.xhci_base + offset + XHCI_LEGACY_CONTROL_OFFSET); 177 } 178 179 static int __init 180 xdbc_alloc_ring(struct xdbc_segment *seg, struct xdbc_ring *ring) 181 { 182 seg->trbs = xdbc_get_page(&seg->dma); 183 if (!seg->trbs) 184 return -ENOMEM; 185 186 ring->segment = seg; 187 188 return 0; 189 } 190 191 static void __init xdbc_free_ring(struct xdbc_ring *ring) 192 { 193 struct xdbc_segment *seg = ring->segment; 194 195 if (!seg) 196 return; 197 198 free_bootmem(seg->dma, PAGE_SIZE); 199 ring->segment = NULL; 200 } 201 202 static void xdbc_reset_ring(struct xdbc_ring *ring) 203 { 204 struct xdbc_segment *seg = ring->segment; 205 struct xdbc_trb *link_trb; 206 207 memset(seg->trbs, 0, PAGE_SIZE); 208 209 ring->enqueue = seg->trbs; 210 ring->dequeue = seg->trbs; 211 ring->cycle_state = 1; 212 213 if (ring != &xdbc.evt_ring) { 214 link_trb = &seg->trbs[XDBC_TRBS_PER_SEGMENT - 1]; 215 link_trb->field[0] = cpu_to_le32(lower_32_bits(seg->dma)); 216 link_trb->field[1] = cpu_to_le32(upper_32_bits(seg->dma)); 217 link_trb->field[3] = cpu_to_le32(TRB_TYPE(TRB_LINK)) | cpu_to_le32(LINK_TOGGLE); 218 } 219 } 220 221 static inline void xdbc_put_utf16(u16 *s, const char *c, size_t size) 222 { 223 int i; 224 225 for (i = 0; i < size; i++) 226 s[i] = cpu_to_le16(c[i]); 227 } 228 229 static void xdbc_mem_init(void) 230 { 231 struct xdbc_ep_context *ep_in, *ep_out; 232 struct usb_string_descriptor *s_desc; 233 struct xdbc_erst_entry *entry; 234 struct xdbc_strings *strings; 235 struct xdbc_context *ctx; 236 unsigned int max_burst; 237 u32 string_length; 238 int index = 0; 239 u32 dev_info; 240 241 xdbc_reset_ring(&xdbc.evt_ring); 242 xdbc_reset_ring(&xdbc.in_ring); 243 xdbc_reset_ring(&xdbc.out_ring); 244 memset(xdbc.table_base, 0, PAGE_SIZE); 245 memset(xdbc.out_buf, 0, PAGE_SIZE); 246 247 /* Initialize event ring segment table: */ 248 xdbc.erst_size = 16; 249 xdbc.erst_base = xdbc.table_base + index * XDBC_TABLE_ENTRY_SIZE; 250 xdbc.erst_dma = xdbc.table_dma + index * XDBC_TABLE_ENTRY_SIZE; 251 252 index += XDBC_ERST_ENTRY_NUM; 253 entry = (struct xdbc_erst_entry *)xdbc.erst_base; 254 255 entry->seg_addr = cpu_to_le64(xdbc.evt_seg.dma); 256 entry->seg_size = cpu_to_le32(XDBC_TRBS_PER_SEGMENT); 257 entry->__reserved_0 = 0; 258 259 /* Initialize ERST registers: */ 260 writel(1, &xdbc.xdbc_reg->ersts); 261 xdbc_write64(xdbc.erst_dma, &xdbc.xdbc_reg->erstba); 262 xdbc_write64(xdbc.evt_seg.dma, &xdbc.xdbc_reg->erdp); 263 264 /* Debug capability contexts: */ 265 xdbc.dbcc_size = 64 * 3; 266 xdbc.dbcc_base = xdbc.table_base + index * XDBC_TABLE_ENTRY_SIZE; 267 xdbc.dbcc_dma = xdbc.table_dma + index * XDBC_TABLE_ENTRY_SIZE; 268 269 index += XDBC_DBCC_ENTRY_NUM; 270 271 /* Popluate the strings: */ 272 xdbc.string_size = sizeof(struct xdbc_strings); 273 xdbc.string_base = xdbc.table_base + index * XDBC_TABLE_ENTRY_SIZE; 274 xdbc.string_dma = xdbc.table_dma + index * XDBC_TABLE_ENTRY_SIZE; 275 strings = (struct xdbc_strings *)xdbc.string_base; 276 277 index += XDBC_STRING_ENTRY_NUM; 278 279 /* Serial string: */ 280 s_desc = (struct usb_string_descriptor *)strings->serial; 281 s_desc->bLength = (strlen(XDBC_STRING_SERIAL) + 1) * 2; 282 s_desc->bDescriptorType = USB_DT_STRING; 283 284 xdbc_put_utf16(s_desc->wData, XDBC_STRING_SERIAL, strlen(XDBC_STRING_SERIAL)); 285 string_length = s_desc->bLength; 286 string_length <<= 8; 287 288 /* Product string: */ 289 s_desc = (struct usb_string_descriptor *)strings->product; 290 s_desc->bLength = (strlen(XDBC_STRING_PRODUCT) + 1) * 2; 291 s_desc->bDescriptorType = USB_DT_STRING; 292 293 xdbc_put_utf16(s_desc->wData, XDBC_STRING_PRODUCT, strlen(XDBC_STRING_PRODUCT)); 294 string_length += s_desc->bLength; 295 string_length <<= 8; 296 297 /* Manufacture string: */ 298 s_desc = (struct usb_string_descriptor *)strings->manufacturer; 299 s_desc->bLength = (strlen(XDBC_STRING_MANUFACTURER) + 1) * 2; 300 s_desc->bDescriptorType = USB_DT_STRING; 301 302 xdbc_put_utf16(s_desc->wData, XDBC_STRING_MANUFACTURER, strlen(XDBC_STRING_MANUFACTURER)); 303 string_length += s_desc->bLength; 304 string_length <<= 8; 305 306 /* String0: */ 307 strings->string0[0] = 4; 308 strings->string0[1] = USB_DT_STRING; 309 strings->string0[2] = 0x09; 310 strings->string0[3] = 0x04; 311 312 string_length += 4; 313 314 /* Populate info Context: */ 315 ctx = (struct xdbc_context *)xdbc.dbcc_base; 316 317 ctx->info.string0 = cpu_to_le64(xdbc.string_dma); 318 ctx->info.manufacturer = cpu_to_le64(xdbc.string_dma + XDBC_MAX_STRING_LENGTH); 319 ctx->info.product = cpu_to_le64(xdbc.string_dma + XDBC_MAX_STRING_LENGTH * 2); 320 ctx->info.serial = cpu_to_le64(xdbc.string_dma + XDBC_MAX_STRING_LENGTH * 3); 321 ctx->info.length = cpu_to_le32(string_length); 322 323 /* Populate bulk out endpoint context: */ 324 max_burst = DEBUG_MAX_BURST(readl(&xdbc.xdbc_reg->control)); 325 ep_out = (struct xdbc_ep_context *)&ctx->out; 326 327 ep_out->ep_info1 = 0; 328 ep_out->ep_info2 = cpu_to_le32(EP_TYPE(BULK_OUT_EP) | MAX_PACKET(1024) | MAX_BURST(max_burst)); 329 ep_out->deq = cpu_to_le64(xdbc.out_seg.dma | xdbc.out_ring.cycle_state); 330 331 /* Populate bulk in endpoint context: */ 332 ep_in = (struct xdbc_ep_context *)&ctx->in; 333 334 ep_in->ep_info1 = 0; 335 ep_in->ep_info2 = cpu_to_le32(EP_TYPE(BULK_OUT_EP) | MAX_PACKET(1024) | MAX_BURST(max_burst)); 336 ep_in->deq = cpu_to_le64(xdbc.in_seg.dma | xdbc.in_ring.cycle_state); 337 338 /* Set DbC context and info registers: */ 339 xdbc_write64(xdbc.dbcc_dma, &xdbc.xdbc_reg->dccp); 340 341 dev_info = cpu_to_le32((XDBC_VENDOR_ID << 16) | XDBC_PROTOCOL); 342 writel(dev_info, &xdbc.xdbc_reg->devinfo1); 343 344 dev_info = cpu_to_le32((XDBC_DEVICE_REV << 16) | XDBC_PRODUCT_ID); 345 writel(dev_info, &xdbc.xdbc_reg->devinfo2); 346 347 xdbc.in_buf = xdbc.out_buf + XDBC_MAX_PACKET; 348 xdbc.in_dma = xdbc.out_dma + XDBC_MAX_PACKET; 349 } 350 351 static void xdbc_do_reset_debug_port(u32 id, u32 count) 352 { 353 void __iomem *ops_reg; 354 void __iomem *portsc; 355 u32 val, cap_length; 356 int i; 357 358 cap_length = readl(xdbc.xhci_base) & 0xff; 359 ops_reg = xdbc.xhci_base + cap_length; 360 361 id--; 362 for (i = id; i < (id + count); i++) { 363 portsc = ops_reg + 0x400 + i * 0x10; 364 val = readl(portsc); 365 if (!(val & PORT_CONNECT)) 366 writel(val | PORT_RESET, portsc); 367 } 368 } 369 370 static void xdbc_reset_debug_port(void) 371 { 372 u32 val, port_offset, port_count; 373 int offset = 0; 374 375 do { 376 offset = xhci_find_next_ext_cap(xdbc.xhci_base, offset, XHCI_EXT_CAPS_PROTOCOL); 377 if (!offset) 378 break; 379 380 val = readl(xdbc.xhci_base + offset); 381 if (XHCI_EXT_PORT_MAJOR(val) != 0x3) 382 continue; 383 384 val = readl(xdbc.xhci_base + offset + 8); 385 port_offset = XHCI_EXT_PORT_OFF(val); 386 port_count = XHCI_EXT_PORT_COUNT(val); 387 388 xdbc_do_reset_debug_port(port_offset, port_count); 389 } while (1); 390 } 391 392 static void 393 xdbc_queue_trb(struct xdbc_ring *ring, u32 field1, u32 field2, u32 field3, u32 field4) 394 { 395 struct xdbc_trb *trb, *link_trb; 396 397 trb = ring->enqueue; 398 trb->field[0] = cpu_to_le32(field1); 399 trb->field[1] = cpu_to_le32(field2); 400 trb->field[2] = cpu_to_le32(field3); 401 trb->field[3] = cpu_to_le32(field4); 402 403 ++(ring->enqueue); 404 if (ring->enqueue >= &ring->segment->trbs[TRBS_PER_SEGMENT - 1]) { 405 link_trb = ring->enqueue; 406 if (ring->cycle_state) 407 link_trb->field[3] |= cpu_to_le32(TRB_CYCLE); 408 else 409 link_trb->field[3] &= cpu_to_le32(~TRB_CYCLE); 410 411 ring->enqueue = ring->segment->trbs; 412 ring->cycle_state ^= 1; 413 } 414 } 415 416 static void xdbc_ring_doorbell(int target) 417 { 418 writel(DOOR_BELL_TARGET(target), &xdbc.xdbc_reg->doorbell); 419 } 420 421 static int xdbc_start(void) 422 { 423 u32 ctrl, status; 424 int ret; 425 426 ctrl = readl(&xdbc.xdbc_reg->control); 427 writel(ctrl | CTRL_DBC_ENABLE | CTRL_PORT_ENABLE, &xdbc.xdbc_reg->control); 428 ret = handshake(&xdbc.xdbc_reg->control, CTRL_DBC_ENABLE, CTRL_DBC_ENABLE, 100000, 100); 429 if (ret) { 430 xdbc_trace("failed to initialize hardware\n"); 431 return ret; 432 } 433 434 /* Reset port to avoid bus hang: */ 435 if (xdbc.vendor == PCI_VENDOR_ID_INTEL) 436 xdbc_reset_debug_port(); 437 438 /* Wait for port connection: */ 439 ret = handshake(&xdbc.xdbc_reg->portsc, PORTSC_CONN_STATUS, PORTSC_CONN_STATUS, 5000000, 100); 440 if (ret) { 441 xdbc_trace("waiting for connection timed out\n"); 442 return ret; 443 } 444 445 /* Wait for debug device to be configured: */ 446 ret = handshake(&xdbc.xdbc_reg->control, CTRL_DBC_RUN, CTRL_DBC_RUN, 5000000, 100); 447 if (ret) { 448 xdbc_trace("waiting for device configuration timed out\n"); 449 return ret; 450 } 451 452 /* Check port number: */ 453 status = readl(&xdbc.xdbc_reg->status); 454 if (!DCST_DEBUG_PORT(status)) { 455 xdbc_trace("invalid root hub port number\n"); 456 return -ENODEV; 457 } 458 459 xdbc.port_number = DCST_DEBUG_PORT(status); 460 461 xdbc_trace("DbC is running now, control 0x%08x port ID %d\n", 462 readl(&xdbc.xdbc_reg->control), xdbc.port_number); 463 464 return 0; 465 } 466 467 static int xdbc_bulk_transfer(void *data, int size, bool read) 468 { 469 struct xdbc_ring *ring; 470 struct xdbc_trb *trb; 471 u32 length, control; 472 u32 cycle; 473 u64 addr; 474 475 if (size > XDBC_MAX_PACKET) { 476 xdbc_trace("bad parameter, size %d\n", size); 477 return -EINVAL; 478 } 479 480 if (!(xdbc.flags & XDBC_FLAGS_INITIALIZED) || 481 !(xdbc.flags & XDBC_FLAGS_CONFIGURED) || 482 (!read && (xdbc.flags & XDBC_FLAGS_OUT_STALL)) || 483 (read && (xdbc.flags & XDBC_FLAGS_IN_STALL))) { 484 485 xdbc_trace("connection not ready, flags %08x\n", xdbc.flags); 486 return -EIO; 487 } 488 489 ring = (read ? &xdbc.in_ring : &xdbc.out_ring); 490 trb = ring->enqueue; 491 cycle = ring->cycle_state; 492 length = TRB_LEN(size); 493 control = TRB_TYPE(TRB_NORMAL) | TRB_IOC; 494 495 if (cycle) 496 control &= cpu_to_le32(~TRB_CYCLE); 497 else 498 control |= cpu_to_le32(TRB_CYCLE); 499 500 if (read) { 501 memset(xdbc.in_buf, 0, XDBC_MAX_PACKET); 502 addr = xdbc.in_dma; 503 xdbc.flags |= XDBC_FLAGS_IN_PROCESS; 504 } else { 505 memset(xdbc.out_buf, 0, XDBC_MAX_PACKET); 506 memcpy(xdbc.out_buf, data, size); 507 addr = xdbc.out_dma; 508 xdbc.flags |= XDBC_FLAGS_OUT_PROCESS; 509 } 510 511 xdbc_queue_trb(ring, lower_32_bits(addr), upper_32_bits(addr), length, control); 512 513 /* 514 * Add a barrier between writes of trb fields and flipping 515 * the cycle bit: 516 */ 517 wmb(); 518 if (cycle) 519 trb->field[3] |= cpu_to_le32(cycle); 520 else 521 trb->field[3] &= cpu_to_le32(~TRB_CYCLE); 522 523 xdbc_ring_doorbell(read ? IN_EP_DOORBELL : OUT_EP_DOORBELL); 524 525 return size; 526 } 527 528 static int xdbc_handle_external_reset(void) 529 { 530 int ret = 0; 531 532 xdbc.flags = 0; 533 writel(0, &xdbc.xdbc_reg->control); 534 ret = handshake(&xdbc.xdbc_reg->control, CTRL_DBC_ENABLE, 0, 100000, 10); 535 if (ret) 536 goto reset_out; 537 538 xdbc_mem_init(); 539 540 mmiowb(); 541 542 ret = xdbc_start(); 543 if (ret < 0) 544 goto reset_out; 545 546 xdbc_trace("dbc recovered\n"); 547 548 xdbc.flags |= XDBC_FLAGS_INITIALIZED | XDBC_FLAGS_CONFIGURED; 549 550 xdbc_bulk_transfer(NULL, XDBC_MAX_PACKET, true); 551 552 return 0; 553 554 reset_out: 555 xdbc_trace("failed to recover from external reset\n"); 556 return ret; 557 } 558 559 static int __init xdbc_early_setup(void) 560 { 561 int ret; 562 563 writel(0, &xdbc.xdbc_reg->control); 564 ret = handshake(&xdbc.xdbc_reg->control, CTRL_DBC_ENABLE, 0, 100000, 100); 565 if (ret) 566 return ret; 567 568 /* Allocate the table page: */ 569 xdbc.table_base = xdbc_get_page(&xdbc.table_dma); 570 if (!xdbc.table_base) 571 return -ENOMEM; 572 573 /* Get and store the transfer buffer: */ 574 xdbc.out_buf = xdbc_get_page(&xdbc.out_dma); 575 if (!xdbc.out_buf) 576 return -ENOMEM; 577 578 /* Allocate the event ring: */ 579 ret = xdbc_alloc_ring(&xdbc.evt_seg, &xdbc.evt_ring); 580 if (ret < 0) 581 return ret; 582 583 /* Allocate IN/OUT endpoint transfer rings: */ 584 ret = xdbc_alloc_ring(&xdbc.in_seg, &xdbc.in_ring); 585 if (ret < 0) 586 return ret; 587 588 ret = xdbc_alloc_ring(&xdbc.out_seg, &xdbc.out_ring); 589 if (ret < 0) 590 return ret; 591 592 xdbc_mem_init(); 593 594 mmiowb(); 595 596 ret = xdbc_start(); 597 if (ret < 0) { 598 writel(0, &xdbc.xdbc_reg->control); 599 return ret; 600 } 601 602 xdbc.flags |= XDBC_FLAGS_INITIALIZED | XDBC_FLAGS_CONFIGURED; 603 604 xdbc_bulk_transfer(NULL, XDBC_MAX_PACKET, true); 605 606 return 0; 607 } 608 609 int __init early_xdbc_parse_parameter(char *s) 610 { 611 unsigned long dbgp_num = 0; 612 u32 bus, dev, func, offset; 613 int ret; 614 615 if (!early_pci_allowed()) 616 return -EPERM; 617 618 if (strstr(s, "keep")) 619 early_console_keep = true; 620 621 if (xdbc.xdbc_reg) 622 return 0; 623 624 if (*s && kstrtoul(s, 0, &dbgp_num)) 625 dbgp_num = 0; 626 627 pr_notice("dbgp_num: %lu\n", dbgp_num); 628 629 /* Locate the host controller: */ 630 ret = xdbc_find_dbgp(dbgp_num, &bus, &dev, &func); 631 if (ret) { 632 pr_notice("failed to locate xhci host\n"); 633 return -ENODEV; 634 } 635 636 xdbc.vendor = read_pci_config_16(bus, dev, func, PCI_VENDOR_ID); 637 xdbc.device = read_pci_config_16(bus, dev, func, PCI_DEVICE_ID); 638 xdbc.bus = bus; 639 xdbc.dev = dev; 640 xdbc.func = func; 641 642 /* Map the IO memory: */ 643 xdbc.xhci_base = xdbc_map_pci_mmio(bus, dev, func); 644 if (!xdbc.xhci_base) 645 return -EINVAL; 646 647 /* Locate DbC registers: */ 648 offset = xhci_find_next_ext_cap(xdbc.xhci_base, 0, XHCI_EXT_CAPS_DEBUG); 649 if (!offset) { 650 pr_notice("xhci host doesn't support debug capability\n"); 651 early_iounmap(xdbc.xhci_base, xdbc.xhci_length); 652 xdbc.xhci_base = NULL; 653 xdbc.xhci_length = 0; 654 655 return -ENODEV; 656 } 657 xdbc.xdbc_reg = (struct xdbc_regs __iomem *)(xdbc.xhci_base + offset); 658 659 return 0; 660 } 661 662 int __init early_xdbc_setup_hardware(void) 663 { 664 int ret; 665 666 if (!xdbc.xdbc_reg) 667 return -ENODEV; 668 669 xdbc_bios_handoff(); 670 671 raw_spin_lock_init(&xdbc.lock); 672 673 ret = xdbc_early_setup(); 674 if (ret) { 675 pr_notice("failed to setup the connection to host\n"); 676 677 xdbc_free_ring(&xdbc.evt_ring); 678 xdbc_free_ring(&xdbc.out_ring); 679 xdbc_free_ring(&xdbc.in_ring); 680 681 if (xdbc.table_dma) 682 free_bootmem(xdbc.table_dma, PAGE_SIZE); 683 684 if (xdbc.out_dma) 685 free_bootmem(xdbc.out_dma, PAGE_SIZE); 686 687 xdbc.table_base = NULL; 688 xdbc.out_buf = NULL; 689 } 690 691 return ret; 692 } 693 694 static void xdbc_handle_port_status(struct xdbc_trb *evt_trb) 695 { 696 u32 port_reg; 697 698 port_reg = readl(&xdbc.xdbc_reg->portsc); 699 if (port_reg & PORTSC_CONN_CHANGE) { 700 xdbc_trace("connect status change event\n"); 701 702 /* Check whether cable unplugged: */ 703 if (!(port_reg & PORTSC_CONN_STATUS)) { 704 xdbc.flags = 0; 705 xdbc_trace("cable unplugged\n"); 706 } 707 } 708 709 if (port_reg & PORTSC_RESET_CHANGE) 710 xdbc_trace("port reset change event\n"); 711 712 if (port_reg & PORTSC_LINK_CHANGE) 713 xdbc_trace("port link status change event\n"); 714 715 if (port_reg & PORTSC_CONFIG_CHANGE) 716 xdbc_trace("config error change\n"); 717 718 /* Write back the value to clear RW1C bits: */ 719 writel(port_reg, &xdbc.xdbc_reg->portsc); 720 } 721 722 static void xdbc_handle_tx_event(struct xdbc_trb *evt_trb) 723 { 724 size_t remain_length; 725 u32 comp_code; 726 int ep_id; 727 728 comp_code = GET_COMP_CODE(le32_to_cpu(evt_trb->field[2])); 729 remain_length = EVENT_TRB_LEN(le32_to_cpu(evt_trb->field[2])); 730 ep_id = TRB_TO_EP_ID(le32_to_cpu(evt_trb->field[3])); 731 732 switch (comp_code) { 733 case COMP_SUCCESS: 734 remain_length = 0; 735 case COMP_SHORT_PACKET: 736 break; 737 case COMP_TRB_ERROR: 738 case COMP_BABBLE_DETECTED_ERROR: 739 case COMP_USB_TRANSACTION_ERROR: 740 case COMP_STALL_ERROR: 741 default: 742 if (ep_id == XDBC_EPID_OUT) 743 xdbc.flags |= XDBC_FLAGS_OUT_STALL; 744 if (ep_id == XDBC_EPID_IN) 745 xdbc.flags |= XDBC_FLAGS_IN_STALL; 746 747 xdbc_trace("endpoint %d stalled\n", ep_id); 748 break; 749 } 750 751 if (ep_id == XDBC_EPID_IN) { 752 xdbc.flags &= ~XDBC_FLAGS_IN_PROCESS; 753 xdbc_bulk_transfer(NULL, XDBC_MAX_PACKET, true); 754 } else if (ep_id == XDBC_EPID_OUT) { 755 xdbc.flags &= ~XDBC_FLAGS_OUT_PROCESS; 756 } else { 757 xdbc_trace("invalid endpoint id %d\n", ep_id); 758 } 759 } 760 761 static void xdbc_handle_events(void) 762 { 763 struct xdbc_trb *evt_trb; 764 bool update_erdp = false; 765 u32 reg; 766 u8 cmd; 767 768 cmd = read_pci_config_byte(xdbc.bus, xdbc.dev, xdbc.func, PCI_COMMAND); 769 if (!(cmd & PCI_COMMAND_MASTER)) { 770 cmd |= PCI_COMMAND_MASTER | PCI_COMMAND_MEMORY; 771 write_pci_config_byte(xdbc.bus, xdbc.dev, xdbc.func, PCI_COMMAND, cmd); 772 } 773 774 if (!(xdbc.flags & XDBC_FLAGS_INITIALIZED)) 775 return; 776 777 /* Handle external reset events: */ 778 reg = readl(&xdbc.xdbc_reg->control); 779 if (!(reg & CTRL_DBC_ENABLE)) { 780 if (xdbc_handle_external_reset()) { 781 xdbc_trace("failed to recover connection\n"); 782 return; 783 } 784 } 785 786 /* Handle configure-exit event: */ 787 reg = readl(&xdbc.xdbc_reg->control); 788 if (reg & CTRL_DBC_RUN_CHANGE) { 789 writel(reg, &xdbc.xdbc_reg->control); 790 if (reg & CTRL_DBC_RUN) 791 xdbc.flags |= XDBC_FLAGS_CONFIGURED; 792 else 793 xdbc.flags &= ~XDBC_FLAGS_CONFIGURED; 794 } 795 796 /* Handle endpoint stall event: */ 797 reg = readl(&xdbc.xdbc_reg->control); 798 if (reg & CTRL_HALT_IN_TR) { 799 xdbc.flags |= XDBC_FLAGS_IN_STALL; 800 } else { 801 xdbc.flags &= ~XDBC_FLAGS_IN_STALL; 802 if (!(xdbc.flags & XDBC_FLAGS_IN_PROCESS)) 803 xdbc_bulk_transfer(NULL, XDBC_MAX_PACKET, true); 804 } 805 806 if (reg & CTRL_HALT_OUT_TR) 807 xdbc.flags |= XDBC_FLAGS_OUT_STALL; 808 else 809 xdbc.flags &= ~XDBC_FLAGS_OUT_STALL; 810 811 /* Handle the events in the event ring: */ 812 evt_trb = xdbc.evt_ring.dequeue; 813 while ((le32_to_cpu(evt_trb->field[3]) & TRB_CYCLE) == xdbc.evt_ring.cycle_state) { 814 /* 815 * Add a barrier between reading the cycle flag and any 816 * reads of the event's flags/data below: 817 */ 818 rmb(); 819 820 switch ((le32_to_cpu(evt_trb->field[3]) & TRB_TYPE_BITMASK)) { 821 case TRB_TYPE(TRB_PORT_STATUS): 822 xdbc_handle_port_status(evt_trb); 823 break; 824 case TRB_TYPE(TRB_TRANSFER): 825 xdbc_handle_tx_event(evt_trb); 826 break; 827 default: 828 break; 829 } 830 831 ++(xdbc.evt_ring.dequeue); 832 if (xdbc.evt_ring.dequeue == &xdbc.evt_seg.trbs[TRBS_PER_SEGMENT]) { 833 xdbc.evt_ring.dequeue = xdbc.evt_seg.trbs; 834 xdbc.evt_ring.cycle_state ^= 1; 835 } 836 837 evt_trb = xdbc.evt_ring.dequeue; 838 update_erdp = true; 839 } 840 841 /* Update event ring dequeue pointer: */ 842 if (update_erdp) 843 xdbc_write64(__pa(xdbc.evt_ring.dequeue), &xdbc.xdbc_reg->erdp); 844 } 845 846 static int xdbc_bulk_write(const char *bytes, int size) 847 { 848 int ret, timeout = 0; 849 unsigned long flags; 850 851 retry: 852 if (in_nmi()) { 853 if (!raw_spin_trylock_irqsave(&xdbc.lock, flags)) 854 return -EAGAIN; 855 } else { 856 raw_spin_lock_irqsave(&xdbc.lock, flags); 857 } 858 859 xdbc_handle_events(); 860 861 /* Check completion of the previous request: */ 862 if ((xdbc.flags & XDBC_FLAGS_OUT_PROCESS) && (timeout < 2000000)) { 863 raw_spin_unlock_irqrestore(&xdbc.lock, flags); 864 udelay(100); 865 timeout += 100; 866 goto retry; 867 } 868 869 if (xdbc.flags & XDBC_FLAGS_OUT_PROCESS) { 870 raw_spin_unlock_irqrestore(&xdbc.lock, flags); 871 xdbc_trace("previous transfer not completed yet\n"); 872 873 return -ETIMEDOUT; 874 } 875 876 ret = xdbc_bulk_transfer((void *)bytes, size, false); 877 raw_spin_unlock_irqrestore(&xdbc.lock, flags); 878 879 return ret; 880 } 881 882 static void early_xdbc_write(struct console *con, const char *str, u32 n) 883 { 884 static char buf[XDBC_MAX_PACKET]; 885 int chunk, ret; 886 int use_cr = 0; 887 888 if (!xdbc.xdbc_reg) 889 return; 890 memset(buf, 0, XDBC_MAX_PACKET); 891 while (n > 0) { 892 for (chunk = 0; chunk < XDBC_MAX_PACKET && n > 0; str++, chunk++, n--) { 893 894 if (!use_cr && *str == '\n') { 895 use_cr = 1; 896 buf[chunk] = '\r'; 897 str--; 898 n++; 899 continue; 900 } 901 902 if (use_cr) 903 use_cr = 0; 904 buf[chunk] = *str; 905 } 906 907 if (chunk > 0) { 908 ret = xdbc_bulk_write(buf, chunk); 909 if (ret < 0) 910 xdbc_trace("missed message {%s}\n", buf); 911 } 912 } 913 } 914 915 static struct console early_xdbc_console = { 916 .name = "earlyxdbc", 917 .write = early_xdbc_write, 918 .flags = CON_PRINTBUFFER, 919 .index = -1, 920 }; 921 922 void __init early_xdbc_register_console(void) 923 { 924 if (early_console) 925 return; 926 927 early_console = &early_xdbc_console; 928 if (early_console_keep) 929 early_console->flags &= ~CON_BOOT; 930 else 931 early_console->flags |= CON_BOOT; 932 register_console(early_console); 933 } 934 935 static void xdbc_unregister_console(void) 936 { 937 if (early_xdbc_console.flags & CON_ENABLED) 938 unregister_console(&early_xdbc_console); 939 } 940 941 static int xdbc_scrub_function(void *ptr) 942 { 943 unsigned long flags; 944 945 while (true) { 946 raw_spin_lock_irqsave(&xdbc.lock, flags); 947 xdbc_handle_events(); 948 949 if (!(xdbc.flags & XDBC_FLAGS_INITIALIZED)) { 950 raw_spin_unlock_irqrestore(&xdbc.lock, flags); 951 break; 952 } 953 954 raw_spin_unlock_irqrestore(&xdbc.lock, flags); 955 schedule_timeout_interruptible(1); 956 } 957 958 xdbc_unregister_console(); 959 writel(0, &xdbc.xdbc_reg->control); 960 xdbc_trace("dbc scrub function exits\n"); 961 962 return 0; 963 } 964 965 static int __init xdbc_init(void) 966 { 967 unsigned long flags; 968 void __iomem *base; 969 int ret = 0; 970 u32 offset; 971 972 if (!(xdbc.flags & XDBC_FLAGS_INITIALIZED)) 973 return 0; 974 975 /* 976 * It's time to shut down the DbC, so that the debug 977 * port can be reused by the host controller: 978 */ 979 if (early_xdbc_console.index == -1 || 980 (early_xdbc_console.flags & CON_BOOT)) { 981 xdbc_trace("hardware not used anymore\n"); 982 goto free_and_quit; 983 } 984 985 base = ioremap_nocache(xdbc.xhci_start, xdbc.xhci_length); 986 if (!base) { 987 xdbc_trace("failed to remap the io address\n"); 988 ret = -ENOMEM; 989 goto free_and_quit; 990 } 991 992 raw_spin_lock_irqsave(&xdbc.lock, flags); 993 early_iounmap(xdbc.xhci_base, xdbc.xhci_length); 994 xdbc.xhci_base = base; 995 offset = xhci_find_next_ext_cap(xdbc.xhci_base, 0, XHCI_EXT_CAPS_DEBUG); 996 xdbc.xdbc_reg = (struct xdbc_regs __iomem *)(xdbc.xhci_base + offset); 997 raw_spin_unlock_irqrestore(&xdbc.lock, flags); 998 999 kthread_run(xdbc_scrub_function, NULL, "%s", "xdbc"); 1000 1001 return 0; 1002 1003 free_and_quit: 1004 xdbc_free_ring(&xdbc.evt_ring); 1005 xdbc_free_ring(&xdbc.out_ring); 1006 xdbc_free_ring(&xdbc.in_ring); 1007 free_bootmem(xdbc.table_dma, PAGE_SIZE); 1008 free_bootmem(xdbc.out_dma, PAGE_SIZE); 1009 writel(0, &xdbc.xdbc_reg->control); 1010 early_iounmap(xdbc.xhci_base, xdbc.xhci_length); 1011 1012 return ret; 1013 } 1014 subsys_initcall(xdbc_init); 1015