1 /** 2 * gadget.c - DesignWare USB3 DRD Controller Gadget Framework Link 3 * 4 * Copyright (C) 2010-2011 Texas Instruments Incorporated - http://www.ti.com 5 * 6 * Authors: Felipe Balbi <balbi@ti.com>, 7 * Sebastian Andrzej Siewior <bigeasy@linutronix.de> 8 * 9 * This program is free software: you can redistribute it and/or modify 10 * it under the terms of the GNU General Public License version 2 of 11 * the License as published by the Free Software Foundation. 12 * 13 * This program is distributed in the hope that it will be useful, 14 * but WITHOUT ANY WARRANTY; without even the implied warranty of 15 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the 16 * GNU General Public License for more details. 17 */ 18 19 #include <linux/kernel.h> 20 #include <linux/delay.h> 21 #include <linux/slab.h> 22 #include <linux/spinlock.h> 23 #include <linux/platform_device.h> 24 #include <linux/pm_runtime.h> 25 #include <linux/interrupt.h> 26 #include <linux/io.h> 27 #include <linux/list.h> 28 #include <linux/dma-mapping.h> 29 30 #include <linux/usb/ch9.h> 31 #include <linux/usb/gadget.h> 32 33 #include "debug.h" 34 #include "core.h" 35 #include "gadget.h" 36 #include "io.h" 37 38 /** 39 * dwc3_gadget_set_test_mode - Enables USB2 Test Modes 40 * @dwc: pointer to our context structure 41 * @mode: the mode to set (J, K SE0 NAK, Force Enable) 42 * 43 * Caller should take care of locking. This function will 44 * return 0 on success or -EINVAL if wrong Test Selector 45 * is passed 46 */ 47 int dwc3_gadget_set_test_mode(struct dwc3 *dwc, int mode) 48 { 49 u32 reg; 50 51 reg = dwc3_readl(dwc->regs, DWC3_DCTL); 52 reg &= ~DWC3_DCTL_TSTCTRL_MASK; 53 54 switch (mode) { 55 case TEST_J: 56 case TEST_K: 57 case TEST_SE0_NAK: 58 case TEST_PACKET: 59 case TEST_FORCE_EN: 60 reg |= mode << 1; 61 break; 62 default: 63 return -EINVAL; 64 } 65 66 dwc3_writel(dwc->regs, DWC3_DCTL, reg); 67 68 return 0; 69 } 70 71 /** 72 * dwc3_gadget_get_link_state - Gets current state of USB Link 73 * @dwc: pointer to our context structure 74 * 75 * Caller should take care of locking. This function will 76 * return the link state on success (>= 0) or -ETIMEDOUT. 77 */ 78 int dwc3_gadget_get_link_state(struct dwc3 *dwc) 79 { 80 u32 reg; 81 82 reg = dwc3_readl(dwc->regs, DWC3_DSTS); 83 84 return DWC3_DSTS_USBLNKST(reg); 85 } 86 87 /** 88 * dwc3_gadget_set_link_state - Sets USB Link to a particular State 89 * @dwc: pointer to our context structure 90 * @state: the state to put link into 91 * 92 * Caller should take care of locking. This function will 93 * return 0 on success or -ETIMEDOUT. 94 */ 95 int dwc3_gadget_set_link_state(struct dwc3 *dwc, enum dwc3_link_state state) 96 { 97 int retries = 10000; 98 u32 reg; 99 100 /* 101 * Wait until device controller is ready. Only applies to 1.94a and 102 * later RTL. 103 */ 104 if (dwc->revision >= DWC3_REVISION_194A) { 105 while (--retries) { 106 reg = dwc3_readl(dwc->regs, DWC3_DSTS); 107 if (reg & DWC3_DSTS_DCNRD) 108 udelay(5); 109 else 110 break; 111 } 112 113 if (retries <= 0) 114 return -ETIMEDOUT; 115 } 116 117 reg = dwc3_readl(dwc->regs, DWC3_DCTL); 118 reg &= ~DWC3_DCTL_ULSTCHNGREQ_MASK; 119 120 /* set requested state */ 121 reg |= DWC3_DCTL_ULSTCHNGREQ(state); 122 dwc3_writel(dwc->regs, DWC3_DCTL, reg); 123 124 /* 125 * The following code is racy when called from dwc3_gadget_wakeup, 126 * and is not needed, at least on newer versions 127 */ 128 if (dwc->revision >= DWC3_REVISION_194A) 129 return 0; 130 131 /* wait for a change in DSTS */ 132 retries = 10000; 133 while (--retries) { 134 reg = dwc3_readl(dwc->regs, DWC3_DSTS); 135 136 if (DWC3_DSTS_USBLNKST(reg) == state) 137 return 0; 138 139 udelay(5); 140 } 141 142 dev_vdbg(dwc->dev, "link state change request timed out\n"); 143 144 return -ETIMEDOUT; 145 } 146 147 /** 148 * dwc3_gadget_resize_tx_fifos - reallocate fifo spaces for current use-case 149 * @dwc: pointer to our context structure 150 * 151 * This function will a best effort FIFO allocation in order 152 * to improve FIFO usage and throughput, while still allowing 153 * us to enable as many endpoints as possible. 154 * 155 * Keep in mind that this operation will be highly dependent 156 * on the configured size for RAM1 - which contains TxFifo -, 157 * the amount of endpoints enabled on coreConsultant tool, and 158 * the width of the Master Bus. 159 * 160 * In the ideal world, we would always be able to satisfy the 161 * following equation: 162 * 163 * ((512 + 2 * MDWIDTH-Bytes) + (Number of IN Endpoints - 1) * \ 164 * (3 * (1024 + MDWIDTH-Bytes) + MDWIDTH-Bytes)) / MDWIDTH-Bytes 165 * 166 * Unfortunately, due to many variables that's not always the case. 167 */ 168 int dwc3_gadget_resize_tx_fifos(struct dwc3 *dwc) 169 { 170 int last_fifo_depth = 0; 171 int ram1_depth; 172 int fifo_size; 173 int mdwidth; 174 int num; 175 176 if (!dwc->needs_fifo_resize) 177 return 0; 178 179 ram1_depth = DWC3_RAM1_DEPTH(dwc->hwparams.hwparams7); 180 mdwidth = DWC3_MDWIDTH(dwc->hwparams.hwparams0); 181 182 /* MDWIDTH is represented in bits, we need it in bytes */ 183 mdwidth >>= 3; 184 185 /* 186 * FIXME For now we will only allocate 1 wMaxPacketSize space 187 * for each enabled endpoint, later patches will come to 188 * improve this algorithm so that we better use the internal 189 * FIFO space 190 */ 191 for (num = 0; num < dwc->num_in_eps; num++) { 192 /* bit0 indicates direction; 1 means IN ep */ 193 struct dwc3_ep *dep = dwc->eps[(num << 1) | 1]; 194 int mult = 1; 195 int tmp; 196 197 if (!(dep->flags & DWC3_EP_ENABLED)) 198 continue; 199 200 if (usb_endpoint_xfer_bulk(dep->endpoint.desc) 201 || usb_endpoint_xfer_isoc(dep->endpoint.desc)) 202 mult = 3; 203 204 /* 205 * REVISIT: the following assumes we will always have enough 206 * space available on the FIFO RAM for all possible use cases. 207 * Make sure that's true somehow and change FIFO allocation 208 * accordingly. 209 * 210 * If we have Bulk or Isochronous endpoints, we want 211 * them to be able to be very, very fast. So we're giving 212 * those endpoints a fifo_size which is enough for 3 full 213 * packets 214 */ 215 tmp = mult * (dep->endpoint.maxpacket + mdwidth); 216 tmp += mdwidth; 217 218 fifo_size = DIV_ROUND_UP(tmp, mdwidth); 219 220 fifo_size |= (last_fifo_depth << 16); 221 222 dev_vdbg(dwc->dev, "%s: Fifo Addr %04x Size %d\n", 223 dep->name, last_fifo_depth, fifo_size & 0xffff); 224 225 dwc3_writel(dwc->regs, DWC3_GTXFIFOSIZ(num), fifo_size); 226 227 last_fifo_depth += (fifo_size & 0xffff); 228 } 229 230 return 0; 231 } 232 233 void dwc3_gadget_giveback(struct dwc3_ep *dep, struct dwc3_request *req, 234 int status) 235 { 236 struct dwc3 *dwc = dep->dwc; 237 int i; 238 239 if (req->queued) { 240 i = 0; 241 do { 242 dep->busy_slot++; 243 /* 244 * Skip LINK TRB. We can't use req->trb and check for 245 * DWC3_TRBCTL_LINK_TRB because it points the TRB we 246 * just completed (not the LINK TRB). 247 */ 248 if (((dep->busy_slot & DWC3_TRB_MASK) == 249 DWC3_TRB_NUM- 1) && 250 usb_endpoint_xfer_isoc(dep->endpoint.desc)) 251 dep->busy_slot++; 252 } while(++i < req->request.num_mapped_sgs); 253 req->queued = false; 254 } 255 list_del(&req->list); 256 req->trb = NULL; 257 258 if (req->request.status == -EINPROGRESS) 259 req->request.status = status; 260 261 if (dwc->ep0_bounced && dep->number == 0) 262 dwc->ep0_bounced = false; 263 else 264 usb_gadget_unmap_request(&dwc->gadget, &req->request, 265 req->direction); 266 267 dev_dbg(dwc->dev, "request %p from %s completed %d/%d ===> %d\n", 268 req, dep->name, req->request.actual, 269 req->request.length, status); 270 trace_dwc3_gadget_giveback(req); 271 272 spin_unlock(&dwc->lock); 273 usb_gadget_giveback_request(&dep->endpoint, &req->request); 274 spin_lock(&dwc->lock); 275 } 276 277 int dwc3_send_gadget_generic_command(struct dwc3 *dwc, unsigned cmd, u32 param) 278 { 279 u32 timeout = 500; 280 u32 reg; 281 282 trace_dwc3_gadget_generic_cmd(cmd, param); 283 284 dwc3_writel(dwc->regs, DWC3_DGCMDPAR, param); 285 dwc3_writel(dwc->regs, DWC3_DGCMD, cmd | DWC3_DGCMD_CMDACT); 286 287 do { 288 reg = dwc3_readl(dwc->regs, DWC3_DGCMD); 289 if (!(reg & DWC3_DGCMD_CMDACT)) { 290 dev_vdbg(dwc->dev, "Command Complete --> %d\n", 291 DWC3_DGCMD_STATUS(reg)); 292 return 0; 293 } 294 295 /* 296 * We can't sleep here, because it's also called from 297 * interrupt context. 298 */ 299 timeout--; 300 if (!timeout) 301 return -ETIMEDOUT; 302 udelay(1); 303 } while (1); 304 } 305 306 int dwc3_send_gadget_ep_cmd(struct dwc3 *dwc, unsigned ep, 307 unsigned cmd, struct dwc3_gadget_ep_cmd_params *params) 308 { 309 struct dwc3_ep *dep = dwc->eps[ep]; 310 u32 timeout = 500; 311 u32 reg; 312 313 trace_dwc3_gadget_ep_cmd(dep, cmd, params); 314 315 dwc3_writel(dwc->regs, DWC3_DEPCMDPAR0(ep), params->param0); 316 dwc3_writel(dwc->regs, DWC3_DEPCMDPAR1(ep), params->param1); 317 dwc3_writel(dwc->regs, DWC3_DEPCMDPAR2(ep), params->param2); 318 319 dwc3_writel(dwc->regs, DWC3_DEPCMD(ep), cmd | DWC3_DEPCMD_CMDACT); 320 do { 321 reg = dwc3_readl(dwc->regs, DWC3_DEPCMD(ep)); 322 if (!(reg & DWC3_DEPCMD_CMDACT)) { 323 dev_vdbg(dwc->dev, "Command Complete --> %d\n", 324 DWC3_DEPCMD_STATUS(reg)); 325 return 0; 326 } 327 328 /* 329 * We can't sleep here, because it is also called from 330 * interrupt context. 331 */ 332 timeout--; 333 if (!timeout) 334 return -ETIMEDOUT; 335 336 udelay(1); 337 } while (1); 338 } 339 340 static dma_addr_t dwc3_trb_dma_offset(struct dwc3_ep *dep, 341 struct dwc3_trb *trb) 342 { 343 u32 offset = (char *) trb - (char *) dep->trb_pool; 344 345 return dep->trb_pool_dma + offset; 346 } 347 348 static int dwc3_alloc_trb_pool(struct dwc3_ep *dep) 349 { 350 struct dwc3 *dwc = dep->dwc; 351 352 if (dep->trb_pool) 353 return 0; 354 355 if (dep->number == 0 || dep->number == 1) 356 return 0; 357 358 dep->trb_pool = dma_alloc_coherent(dwc->dev, 359 sizeof(struct dwc3_trb) * DWC3_TRB_NUM, 360 &dep->trb_pool_dma, GFP_KERNEL); 361 if (!dep->trb_pool) { 362 dev_err(dep->dwc->dev, "failed to allocate trb pool for %s\n", 363 dep->name); 364 return -ENOMEM; 365 } 366 367 return 0; 368 } 369 370 static void dwc3_free_trb_pool(struct dwc3_ep *dep) 371 { 372 struct dwc3 *dwc = dep->dwc; 373 374 dma_free_coherent(dwc->dev, sizeof(struct dwc3_trb) * DWC3_TRB_NUM, 375 dep->trb_pool, dep->trb_pool_dma); 376 377 dep->trb_pool = NULL; 378 dep->trb_pool_dma = 0; 379 } 380 381 static int dwc3_gadget_start_config(struct dwc3 *dwc, struct dwc3_ep *dep) 382 { 383 struct dwc3_gadget_ep_cmd_params params; 384 u32 cmd; 385 386 memset(¶ms, 0x00, sizeof(params)); 387 388 if (dep->number != 1) { 389 cmd = DWC3_DEPCMD_DEPSTARTCFG; 390 /* XferRscIdx == 0 for ep0 and 2 for the remaining */ 391 if (dep->number > 1) { 392 if (dwc->start_config_issued) 393 return 0; 394 dwc->start_config_issued = true; 395 cmd |= DWC3_DEPCMD_PARAM(2); 396 } 397 398 return dwc3_send_gadget_ep_cmd(dwc, 0, cmd, ¶ms); 399 } 400 401 return 0; 402 } 403 404 static int dwc3_gadget_set_ep_config(struct dwc3 *dwc, struct dwc3_ep *dep, 405 const struct usb_endpoint_descriptor *desc, 406 const struct usb_ss_ep_comp_descriptor *comp_desc, 407 bool ignore, bool restore) 408 { 409 struct dwc3_gadget_ep_cmd_params params; 410 411 memset(¶ms, 0x00, sizeof(params)); 412 413 params.param0 = DWC3_DEPCFG_EP_TYPE(usb_endpoint_type(desc)) 414 | DWC3_DEPCFG_MAX_PACKET_SIZE(usb_endpoint_maxp(desc)); 415 416 /* Burst size is only needed in SuperSpeed mode */ 417 if (dwc->gadget.speed == USB_SPEED_SUPER) { 418 u32 burst = dep->endpoint.maxburst - 1; 419 420 params.param0 |= DWC3_DEPCFG_BURST_SIZE(burst); 421 } 422 423 if (ignore) 424 params.param0 |= DWC3_DEPCFG_IGN_SEQ_NUM; 425 426 if (restore) { 427 params.param0 |= DWC3_DEPCFG_ACTION_RESTORE; 428 params.param2 |= dep->saved_state; 429 } 430 431 params.param1 = DWC3_DEPCFG_XFER_COMPLETE_EN 432 | DWC3_DEPCFG_XFER_NOT_READY_EN; 433 434 if (usb_ss_max_streams(comp_desc) && usb_endpoint_xfer_bulk(desc)) { 435 params.param1 |= DWC3_DEPCFG_STREAM_CAPABLE 436 | DWC3_DEPCFG_STREAM_EVENT_EN; 437 dep->stream_capable = true; 438 } 439 440 if (!usb_endpoint_xfer_control(desc)) 441 params.param1 |= DWC3_DEPCFG_XFER_IN_PROGRESS_EN; 442 443 /* 444 * We are doing 1:1 mapping for endpoints, meaning 445 * Physical Endpoints 2 maps to Logical Endpoint 2 and 446 * so on. We consider the direction bit as part of the physical 447 * endpoint number. So USB endpoint 0x81 is 0x03. 448 */ 449 params.param1 |= DWC3_DEPCFG_EP_NUMBER(dep->number); 450 451 /* 452 * We must use the lower 16 TX FIFOs even though 453 * HW might have more 454 */ 455 if (dep->direction) 456 params.param0 |= DWC3_DEPCFG_FIFO_NUMBER(dep->number >> 1); 457 458 if (desc->bInterval) { 459 params.param1 |= DWC3_DEPCFG_BINTERVAL_M1(desc->bInterval - 1); 460 dep->interval = 1 << (desc->bInterval - 1); 461 } 462 463 return dwc3_send_gadget_ep_cmd(dwc, dep->number, 464 DWC3_DEPCMD_SETEPCONFIG, ¶ms); 465 } 466 467 static int dwc3_gadget_set_xfer_resource(struct dwc3 *dwc, struct dwc3_ep *dep) 468 { 469 struct dwc3_gadget_ep_cmd_params params; 470 471 memset(¶ms, 0x00, sizeof(params)); 472 473 params.param0 = DWC3_DEPXFERCFG_NUM_XFER_RES(1); 474 475 return dwc3_send_gadget_ep_cmd(dwc, dep->number, 476 DWC3_DEPCMD_SETTRANSFRESOURCE, ¶ms); 477 } 478 479 /** 480 * __dwc3_gadget_ep_enable - Initializes a HW endpoint 481 * @dep: endpoint to be initialized 482 * @desc: USB Endpoint Descriptor 483 * 484 * Caller should take care of locking 485 */ 486 static int __dwc3_gadget_ep_enable(struct dwc3_ep *dep, 487 const struct usb_endpoint_descriptor *desc, 488 const struct usb_ss_ep_comp_descriptor *comp_desc, 489 bool ignore, bool restore) 490 { 491 struct dwc3 *dwc = dep->dwc; 492 u32 reg; 493 int ret; 494 495 dev_vdbg(dwc->dev, "Enabling %s\n", dep->name); 496 497 if (!(dep->flags & DWC3_EP_ENABLED)) { 498 ret = dwc3_gadget_start_config(dwc, dep); 499 if (ret) 500 return ret; 501 } 502 503 ret = dwc3_gadget_set_ep_config(dwc, dep, desc, comp_desc, ignore, 504 restore); 505 if (ret) 506 return ret; 507 508 if (!(dep->flags & DWC3_EP_ENABLED)) { 509 struct dwc3_trb *trb_st_hw; 510 struct dwc3_trb *trb_link; 511 512 ret = dwc3_gadget_set_xfer_resource(dwc, dep); 513 if (ret) 514 return ret; 515 516 dep->endpoint.desc = desc; 517 dep->comp_desc = comp_desc; 518 dep->type = usb_endpoint_type(desc); 519 dep->flags |= DWC3_EP_ENABLED; 520 521 reg = dwc3_readl(dwc->regs, DWC3_DALEPENA); 522 reg |= DWC3_DALEPENA_EP(dep->number); 523 dwc3_writel(dwc->regs, DWC3_DALEPENA, reg); 524 525 if (!usb_endpoint_xfer_isoc(desc)) 526 return 0; 527 528 memset(&trb_link, 0, sizeof(trb_link)); 529 530 /* Link TRB for ISOC. The HWO bit is never reset */ 531 trb_st_hw = &dep->trb_pool[0]; 532 533 trb_link = &dep->trb_pool[DWC3_TRB_NUM - 1]; 534 535 trb_link->bpl = lower_32_bits(dwc3_trb_dma_offset(dep, trb_st_hw)); 536 trb_link->bph = upper_32_bits(dwc3_trb_dma_offset(dep, trb_st_hw)); 537 trb_link->ctrl |= DWC3_TRBCTL_LINK_TRB; 538 trb_link->ctrl |= DWC3_TRB_CTRL_HWO; 539 } 540 541 return 0; 542 } 543 544 static void dwc3_stop_active_transfer(struct dwc3 *dwc, u32 epnum, bool force); 545 static void dwc3_remove_requests(struct dwc3 *dwc, struct dwc3_ep *dep) 546 { 547 struct dwc3_request *req; 548 549 if (!list_empty(&dep->req_queued)) { 550 dwc3_stop_active_transfer(dwc, dep->number, true); 551 552 /* - giveback all requests to gadget driver */ 553 while (!list_empty(&dep->req_queued)) { 554 req = next_request(&dep->req_queued); 555 556 dwc3_gadget_giveback(dep, req, -ESHUTDOWN); 557 } 558 } 559 560 while (!list_empty(&dep->request_list)) { 561 req = next_request(&dep->request_list); 562 563 dwc3_gadget_giveback(dep, req, -ESHUTDOWN); 564 } 565 } 566 567 /** 568 * __dwc3_gadget_ep_disable - Disables a HW endpoint 569 * @dep: the endpoint to disable 570 * 571 * This function also removes requests which are currently processed ny the 572 * hardware and those which are not yet scheduled. 573 * Caller should take care of locking. 574 */ 575 static int __dwc3_gadget_ep_disable(struct dwc3_ep *dep) 576 { 577 struct dwc3 *dwc = dep->dwc; 578 u32 reg; 579 580 dwc3_remove_requests(dwc, dep); 581 582 /* make sure HW endpoint isn't stalled */ 583 if (dep->flags & DWC3_EP_STALL) 584 __dwc3_gadget_ep_set_halt(dep, 0); 585 586 reg = dwc3_readl(dwc->regs, DWC3_DALEPENA); 587 reg &= ~DWC3_DALEPENA_EP(dep->number); 588 dwc3_writel(dwc->regs, DWC3_DALEPENA, reg); 589 590 dep->stream_capable = false; 591 dep->endpoint.desc = NULL; 592 dep->comp_desc = NULL; 593 dep->type = 0; 594 dep->flags = 0; 595 596 return 0; 597 } 598 599 /* -------------------------------------------------------------------------- */ 600 601 static int dwc3_gadget_ep0_enable(struct usb_ep *ep, 602 const struct usb_endpoint_descriptor *desc) 603 { 604 return -EINVAL; 605 } 606 607 static int dwc3_gadget_ep0_disable(struct usb_ep *ep) 608 { 609 return -EINVAL; 610 } 611 612 /* -------------------------------------------------------------------------- */ 613 614 static int dwc3_gadget_ep_enable(struct usb_ep *ep, 615 const struct usb_endpoint_descriptor *desc) 616 { 617 struct dwc3_ep *dep; 618 struct dwc3 *dwc; 619 unsigned long flags; 620 int ret; 621 622 if (!ep || !desc || desc->bDescriptorType != USB_DT_ENDPOINT) { 623 pr_debug("dwc3: invalid parameters\n"); 624 return -EINVAL; 625 } 626 627 if (!desc->wMaxPacketSize) { 628 pr_debug("dwc3: missing wMaxPacketSize\n"); 629 return -EINVAL; 630 } 631 632 dep = to_dwc3_ep(ep); 633 dwc = dep->dwc; 634 635 if (dep->flags & DWC3_EP_ENABLED) { 636 dev_WARN_ONCE(dwc->dev, true, "%s is already enabled\n", 637 dep->name); 638 return 0; 639 } 640 641 switch (usb_endpoint_type(desc)) { 642 case USB_ENDPOINT_XFER_CONTROL: 643 strlcat(dep->name, "-control", sizeof(dep->name)); 644 break; 645 case USB_ENDPOINT_XFER_ISOC: 646 strlcat(dep->name, "-isoc", sizeof(dep->name)); 647 break; 648 case USB_ENDPOINT_XFER_BULK: 649 strlcat(dep->name, "-bulk", sizeof(dep->name)); 650 break; 651 case USB_ENDPOINT_XFER_INT: 652 strlcat(dep->name, "-int", sizeof(dep->name)); 653 break; 654 default: 655 dev_err(dwc->dev, "invalid endpoint transfer type\n"); 656 } 657 658 spin_lock_irqsave(&dwc->lock, flags); 659 ret = __dwc3_gadget_ep_enable(dep, desc, ep->comp_desc, false, false); 660 spin_unlock_irqrestore(&dwc->lock, flags); 661 662 return ret; 663 } 664 665 static int dwc3_gadget_ep_disable(struct usb_ep *ep) 666 { 667 struct dwc3_ep *dep; 668 struct dwc3 *dwc; 669 unsigned long flags; 670 int ret; 671 672 if (!ep) { 673 pr_debug("dwc3: invalid parameters\n"); 674 return -EINVAL; 675 } 676 677 dep = to_dwc3_ep(ep); 678 dwc = dep->dwc; 679 680 if (!(dep->flags & DWC3_EP_ENABLED)) { 681 dev_WARN_ONCE(dwc->dev, true, "%s is already disabled\n", 682 dep->name); 683 return 0; 684 } 685 686 snprintf(dep->name, sizeof(dep->name), "ep%d%s", 687 dep->number >> 1, 688 (dep->number & 1) ? "in" : "out"); 689 690 spin_lock_irqsave(&dwc->lock, flags); 691 ret = __dwc3_gadget_ep_disable(dep); 692 spin_unlock_irqrestore(&dwc->lock, flags); 693 694 return ret; 695 } 696 697 static struct usb_request *dwc3_gadget_ep_alloc_request(struct usb_ep *ep, 698 gfp_t gfp_flags) 699 { 700 struct dwc3_request *req; 701 struct dwc3_ep *dep = to_dwc3_ep(ep); 702 703 req = kzalloc(sizeof(*req), gfp_flags); 704 if (!req) 705 return NULL; 706 707 req->epnum = dep->number; 708 req->dep = dep; 709 710 trace_dwc3_alloc_request(req); 711 712 return &req->request; 713 } 714 715 static void dwc3_gadget_ep_free_request(struct usb_ep *ep, 716 struct usb_request *request) 717 { 718 struct dwc3_request *req = to_dwc3_request(request); 719 720 trace_dwc3_free_request(req); 721 kfree(req); 722 } 723 724 /** 725 * dwc3_prepare_one_trb - setup one TRB from one request 726 * @dep: endpoint for which this request is prepared 727 * @req: dwc3_request pointer 728 */ 729 static void dwc3_prepare_one_trb(struct dwc3_ep *dep, 730 struct dwc3_request *req, dma_addr_t dma, 731 unsigned length, unsigned last, unsigned chain, unsigned node) 732 { 733 struct dwc3 *dwc = dep->dwc; 734 struct dwc3_trb *trb; 735 736 dev_vdbg(dwc->dev, "%s: req %p dma %08llx length %d%s%s\n", 737 dep->name, req, (unsigned long long) dma, 738 length, last ? " last" : "", 739 chain ? " chain" : ""); 740 741 742 trb = &dep->trb_pool[dep->free_slot & DWC3_TRB_MASK]; 743 744 if (!req->trb) { 745 dwc3_gadget_move_request_queued(req); 746 req->trb = trb; 747 req->trb_dma = dwc3_trb_dma_offset(dep, trb); 748 req->start_slot = dep->free_slot & DWC3_TRB_MASK; 749 } 750 751 dep->free_slot++; 752 /* Skip the LINK-TRB on ISOC */ 753 if (((dep->free_slot & DWC3_TRB_MASK) == DWC3_TRB_NUM - 1) && 754 usb_endpoint_xfer_isoc(dep->endpoint.desc)) 755 dep->free_slot++; 756 757 trb->size = DWC3_TRB_SIZE_LENGTH(length); 758 trb->bpl = lower_32_bits(dma); 759 trb->bph = upper_32_bits(dma); 760 761 switch (usb_endpoint_type(dep->endpoint.desc)) { 762 case USB_ENDPOINT_XFER_CONTROL: 763 trb->ctrl = DWC3_TRBCTL_CONTROL_SETUP; 764 break; 765 766 case USB_ENDPOINT_XFER_ISOC: 767 if (!node) 768 trb->ctrl = DWC3_TRBCTL_ISOCHRONOUS_FIRST; 769 else 770 trb->ctrl = DWC3_TRBCTL_ISOCHRONOUS; 771 break; 772 773 case USB_ENDPOINT_XFER_BULK: 774 case USB_ENDPOINT_XFER_INT: 775 trb->ctrl = DWC3_TRBCTL_NORMAL; 776 break; 777 default: 778 /* 779 * This is only possible with faulty memory because we 780 * checked it already :) 781 */ 782 BUG(); 783 } 784 785 if (!req->request.no_interrupt && !chain) 786 trb->ctrl |= DWC3_TRB_CTRL_IOC; 787 788 if (usb_endpoint_xfer_isoc(dep->endpoint.desc)) { 789 trb->ctrl |= DWC3_TRB_CTRL_ISP_IMI; 790 trb->ctrl |= DWC3_TRB_CTRL_CSP; 791 } else if (last) { 792 trb->ctrl |= DWC3_TRB_CTRL_LST; 793 } 794 795 if (chain) 796 trb->ctrl |= DWC3_TRB_CTRL_CHN; 797 798 if (usb_endpoint_xfer_bulk(dep->endpoint.desc) && dep->stream_capable) 799 trb->ctrl |= DWC3_TRB_CTRL_SID_SOFN(req->request.stream_id); 800 801 trb->ctrl |= DWC3_TRB_CTRL_HWO; 802 803 trace_dwc3_prepare_trb(dep, trb); 804 } 805 806 /* 807 * dwc3_prepare_trbs - setup TRBs from requests 808 * @dep: endpoint for which requests are being prepared 809 * @starting: true if the endpoint is idle and no requests are queued. 810 * 811 * The function goes through the requests list and sets up TRBs for the 812 * transfers. The function returns once there are no more TRBs available or 813 * it runs out of requests. 814 */ 815 static void dwc3_prepare_trbs(struct dwc3_ep *dep, bool starting) 816 { 817 struct dwc3_request *req, *n; 818 u32 trbs_left; 819 u32 max; 820 unsigned int last_one = 0; 821 822 BUILD_BUG_ON_NOT_POWER_OF_2(DWC3_TRB_NUM); 823 824 /* the first request must not be queued */ 825 trbs_left = (dep->busy_slot - dep->free_slot) & DWC3_TRB_MASK; 826 827 /* Can't wrap around on a non-isoc EP since there's no link TRB */ 828 if (!usb_endpoint_xfer_isoc(dep->endpoint.desc)) { 829 max = DWC3_TRB_NUM - (dep->free_slot & DWC3_TRB_MASK); 830 if (trbs_left > max) 831 trbs_left = max; 832 } 833 834 /* 835 * If busy & slot are equal than it is either full or empty. If we are 836 * starting to process requests then we are empty. Otherwise we are 837 * full and don't do anything 838 */ 839 if (!trbs_left) { 840 if (!starting) 841 return; 842 trbs_left = DWC3_TRB_NUM; 843 /* 844 * In case we start from scratch, we queue the ISOC requests 845 * starting from slot 1. This is done because we use ring 846 * buffer and have no LST bit to stop us. Instead, we place 847 * IOC bit every TRB_NUM/4. We try to avoid having an interrupt 848 * after the first request so we start at slot 1 and have 849 * 7 requests proceed before we hit the first IOC. 850 * Other transfer types don't use the ring buffer and are 851 * processed from the first TRB until the last one. Since we 852 * don't wrap around we have to start at the beginning. 853 */ 854 if (usb_endpoint_xfer_isoc(dep->endpoint.desc)) { 855 dep->busy_slot = 1; 856 dep->free_slot = 1; 857 } else { 858 dep->busy_slot = 0; 859 dep->free_slot = 0; 860 } 861 } 862 863 /* The last TRB is a link TRB, not used for xfer */ 864 if ((trbs_left <= 1) && usb_endpoint_xfer_isoc(dep->endpoint.desc)) 865 return; 866 867 list_for_each_entry_safe(req, n, &dep->request_list, list) { 868 unsigned length; 869 dma_addr_t dma; 870 last_one = false; 871 872 if (req->request.num_mapped_sgs > 0) { 873 struct usb_request *request = &req->request; 874 struct scatterlist *sg = request->sg; 875 struct scatterlist *s; 876 int i; 877 878 for_each_sg(sg, s, request->num_mapped_sgs, i) { 879 unsigned chain = true; 880 881 length = sg_dma_len(s); 882 dma = sg_dma_address(s); 883 884 if (i == (request->num_mapped_sgs - 1) || 885 sg_is_last(s)) { 886 if (list_is_last(&req->list, 887 &dep->request_list)) 888 last_one = true; 889 chain = false; 890 } 891 892 trbs_left--; 893 if (!trbs_left) 894 last_one = true; 895 896 if (last_one) 897 chain = false; 898 899 dwc3_prepare_one_trb(dep, req, dma, length, 900 last_one, chain, i); 901 902 if (last_one) 903 break; 904 } 905 } else { 906 dma = req->request.dma; 907 length = req->request.length; 908 trbs_left--; 909 910 if (!trbs_left) 911 last_one = 1; 912 913 /* Is this the last request? */ 914 if (list_is_last(&req->list, &dep->request_list)) 915 last_one = 1; 916 917 dwc3_prepare_one_trb(dep, req, dma, length, 918 last_one, false, 0); 919 920 if (last_one) 921 break; 922 } 923 } 924 } 925 926 static int __dwc3_gadget_kick_transfer(struct dwc3_ep *dep, u16 cmd_param, 927 int start_new) 928 { 929 struct dwc3_gadget_ep_cmd_params params; 930 struct dwc3_request *req; 931 struct dwc3 *dwc = dep->dwc; 932 int ret; 933 u32 cmd; 934 935 if (start_new && (dep->flags & DWC3_EP_BUSY)) { 936 dev_vdbg(dwc->dev, "%s: endpoint busy\n", dep->name); 937 return -EBUSY; 938 } 939 dep->flags &= ~DWC3_EP_PENDING_REQUEST; 940 941 /* 942 * If we are getting here after a short-out-packet we don't enqueue any 943 * new requests as we try to set the IOC bit only on the last request. 944 */ 945 if (start_new) { 946 if (list_empty(&dep->req_queued)) 947 dwc3_prepare_trbs(dep, start_new); 948 949 /* req points to the first request which will be sent */ 950 req = next_request(&dep->req_queued); 951 } else { 952 dwc3_prepare_trbs(dep, start_new); 953 954 /* 955 * req points to the first request where HWO changed from 0 to 1 956 */ 957 req = next_request(&dep->req_queued); 958 } 959 if (!req) { 960 dep->flags |= DWC3_EP_PENDING_REQUEST; 961 return 0; 962 } 963 964 memset(¶ms, 0, sizeof(params)); 965 966 if (start_new) { 967 params.param0 = upper_32_bits(req->trb_dma); 968 params.param1 = lower_32_bits(req->trb_dma); 969 cmd = DWC3_DEPCMD_STARTTRANSFER; 970 } else { 971 cmd = DWC3_DEPCMD_UPDATETRANSFER; 972 } 973 974 cmd |= DWC3_DEPCMD_PARAM(cmd_param); 975 ret = dwc3_send_gadget_ep_cmd(dwc, dep->number, cmd, ¶ms); 976 if (ret < 0) { 977 dev_dbg(dwc->dev, "failed to send STARTTRANSFER command\n"); 978 979 /* 980 * FIXME we need to iterate over the list of requests 981 * here and stop, unmap, free and del each of the linked 982 * requests instead of what we do now. 983 */ 984 usb_gadget_unmap_request(&dwc->gadget, &req->request, 985 req->direction); 986 list_del(&req->list); 987 return ret; 988 } 989 990 dep->flags |= DWC3_EP_BUSY; 991 992 if (start_new) { 993 dep->resource_index = dwc3_gadget_ep_get_transfer_index(dwc, 994 dep->number); 995 WARN_ON_ONCE(!dep->resource_index); 996 } 997 998 return 0; 999 } 1000 1001 static void __dwc3_gadget_start_isoc(struct dwc3 *dwc, 1002 struct dwc3_ep *dep, u32 cur_uf) 1003 { 1004 u32 uf; 1005 1006 if (list_empty(&dep->request_list)) { 1007 dev_vdbg(dwc->dev, "ISOC ep %s run out for requests.\n", 1008 dep->name); 1009 dep->flags |= DWC3_EP_PENDING_REQUEST; 1010 return; 1011 } 1012 1013 /* 4 micro frames in the future */ 1014 uf = cur_uf + dep->interval * 4; 1015 1016 __dwc3_gadget_kick_transfer(dep, uf, 1); 1017 } 1018 1019 static void dwc3_gadget_start_isoc(struct dwc3 *dwc, 1020 struct dwc3_ep *dep, const struct dwc3_event_depevt *event) 1021 { 1022 u32 cur_uf, mask; 1023 1024 mask = ~(dep->interval - 1); 1025 cur_uf = event->parameters & mask; 1026 1027 __dwc3_gadget_start_isoc(dwc, dep, cur_uf); 1028 } 1029 1030 static int __dwc3_gadget_ep_queue(struct dwc3_ep *dep, struct dwc3_request *req) 1031 { 1032 struct dwc3 *dwc = dep->dwc; 1033 int ret; 1034 1035 req->request.actual = 0; 1036 req->request.status = -EINPROGRESS; 1037 req->direction = dep->direction; 1038 req->epnum = dep->number; 1039 1040 /* 1041 * We only add to our list of requests now and 1042 * start consuming the list once we get XferNotReady 1043 * IRQ. 1044 * 1045 * That way, we avoid doing anything that we don't need 1046 * to do now and defer it until the point we receive a 1047 * particular token from the Host side. 1048 * 1049 * This will also avoid Host cancelling URBs due to too 1050 * many NAKs. 1051 */ 1052 ret = usb_gadget_map_request(&dwc->gadget, &req->request, 1053 dep->direction); 1054 if (ret) 1055 return ret; 1056 1057 list_add_tail(&req->list, &dep->request_list); 1058 1059 /* 1060 * There are a few special cases: 1061 * 1062 * 1. XferNotReady with empty list of requests. We need to kick the 1063 * transfer here in that situation, otherwise we will be NAKing 1064 * forever. If we get XferNotReady before gadget driver has a 1065 * chance to queue a request, we will ACK the IRQ but won't be 1066 * able to receive the data until the next request is queued. 1067 * The following code is handling exactly that. 1068 * 1069 */ 1070 if (dep->flags & DWC3_EP_PENDING_REQUEST) { 1071 /* 1072 * If xfernotready is already elapsed and it is a case 1073 * of isoc transfer, then issue END TRANSFER, so that 1074 * you can receive xfernotready again and can have 1075 * notion of current microframe. 1076 */ 1077 if (usb_endpoint_xfer_isoc(dep->endpoint.desc)) { 1078 if (list_empty(&dep->req_queued)) { 1079 dwc3_stop_active_transfer(dwc, dep->number, true); 1080 dep->flags = DWC3_EP_ENABLED; 1081 } 1082 return 0; 1083 } 1084 1085 ret = __dwc3_gadget_kick_transfer(dep, 0, true); 1086 if (ret && ret != -EBUSY) 1087 dev_dbg(dwc->dev, "%s: failed to kick transfers\n", 1088 dep->name); 1089 return ret; 1090 } 1091 1092 /* 1093 * 2. XferInProgress on Isoc EP with an active transfer. We need to 1094 * kick the transfer here after queuing a request, otherwise the 1095 * core may not see the modified TRB(s). 1096 */ 1097 if (usb_endpoint_xfer_isoc(dep->endpoint.desc) && 1098 (dep->flags & DWC3_EP_BUSY) && 1099 !(dep->flags & DWC3_EP_MISSED_ISOC)) { 1100 WARN_ON_ONCE(!dep->resource_index); 1101 ret = __dwc3_gadget_kick_transfer(dep, dep->resource_index, 1102 false); 1103 if (ret && ret != -EBUSY) 1104 dev_dbg(dwc->dev, "%s: failed to kick transfers\n", 1105 dep->name); 1106 return ret; 1107 } 1108 1109 /* 1110 * 4. Stream Capable Bulk Endpoints. We need to start the transfer 1111 * right away, otherwise host will not know we have streams to be 1112 * handled. 1113 */ 1114 if (dep->stream_capable) { 1115 int ret; 1116 1117 ret = __dwc3_gadget_kick_transfer(dep, 0, true); 1118 if (ret && ret != -EBUSY) { 1119 struct dwc3 *dwc = dep->dwc; 1120 1121 dev_dbg(dwc->dev, "%s: failed to kick transfers\n", 1122 dep->name); 1123 } 1124 } 1125 1126 return 0; 1127 } 1128 1129 static int dwc3_gadget_ep_queue(struct usb_ep *ep, struct usb_request *request, 1130 gfp_t gfp_flags) 1131 { 1132 struct dwc3_request *req = to_dwc3_request(request); 1133 struct dwc3_ep *dep = to_dwc3_ep(ep); 1134 struct dwc3 *dwc = dep->dwc; 1135 1136 unsigned long flags; 1137 1138 int ret; 1139 1140 spin_lock_irqsave(&dwc->lock, flags); 1141 if (!dep->endpoint.desc) { 1142 dev_dbg(dwc->dev, "trying to queue request %p to disabled %s\n", 1143 request, ep->name); 1144 spin_unlock_irqrestore(&dwc->lock, flags); 1145 return -ESHUTDOWN; 1146 } 1147 1148 dev_vdbg(dwc->dev, "queing request %p to %s length %d\n", 1149 request, ep->name, request->length); 1150 trace_dwc3_ep_queue(req); 1151 1152 ret = __dwc3_gadget_ep_queue(dep, req); 1153 spin_unlock_irqrestore(&dwc->lock, flags); 1154 1155 return ret; 1156 } 1157 1158 static int dwc3_gadget_ep_dequeue(struct usb_ep *ep, 1159 struct usb_request *request) 1160 { 1161 struct dwc3_request *req = to_dwc3_request(request); 1162 struct dwc3_request *r = NULL; 1163 1164 struct dwc3_ep *dep = to_dwc3_ep(ep); 1165 struct dwc3 *dwc = dep->dwc; 1166 1167 unsigned long flags; 1168 int ret = 0; 1169 1170 trace_dwc3_ep_dequeue(req); 1171 1172 spin_lock_irqsave(&dwc->lock, flags); 1173 1174 list_for_each_entry(r, &dep->request_list, list) { 1175 if (r == req) 1176 break; 1177 } 1178 1179 if (r != req) { 1180 list_for_each_entry(r, &dep->req_queued, list) { 1181 if (r == req) 1182 break; 1183 } 1184 if (r == req) { 1185 /* wait until it is processed */ 1186 dwc3_stop_active_transfer(dwc, dep->number, true); 1187 goto out1; 1188 } 1189 dev_err(dwc->dev, "request %p was not queued to %s\n", 1190 request, ep->name); 1191 ret = -EINVAL; 1192 goto out0; 1193 } 1194 1195 out1: 1196 /* giveback the request */ 1197 dwc3_gadget_giveback(dep, req, -ECONNRESET); 1198 1199 out0: 1200 spin_unlock_irqrestore(&dwc->lock, flags); 1201 1202 return ret; 1203 } 1204 1205 int __dwc3_gadget_ep_set_halt(struct dwc3_ep *dep, int value) 1206 { 1207 struct dwc3_gadget_ep_cmd_params params; 1208 struct dwc3 *dwc = dep->dwc; 1209 int ret; 1210 1211 memset(¶ms, 0x00, sizeof(params)); 1212 1213 if (value) { 1214 ret = dwc3_send_gadget_ep_cmd(dwc, dep->number, 1215 DWC3_DEPCMD_SETSTALL, ¶ms); 1216 if (ret) 1217 dev_err(dwc->dev, "failed to set STALL on %s\n", 1218 dep->name); 1219 else 1220 dep->flags |= DWC3_EP_STALL; 1221 } else { 1222 ret = dwc3_send_gadget_ep_cmd(dwc, dep->number, 1223 DWC3_DEPCMD_CLEARSTALL, ¶ms); 1224 if (ret) 1225 dev_err(dwc->dev, "failed to clear STALL on %s\n", 1226 dep->name); 1227 else 1228 dep->flags &= ~(DWC3_EP_STALL | DWC3_EP_WEDGE); 1229 } 1230 1231 return ret; 1232 } 1233 1234 static int dwc3_gadget_ep_set_halt(struct usb_ep *ep, int value) 1235 { 1236 struct dwc3_ep *dep = to_dwc3_ep(ep); 1237 struct dwc3 *dwc = dep->dwc; 1238 1239 unsigned long flags; 1240 1241 int ret; 1242 1243 spin_lock_irqsave(&dwc->lock, flags); 1244 1245 if (usb_endpoint_xfer_isoc(dep->endpoint.desc)) { 1246 dev_err(dwc->dev, "%s is of Isochronous type\n", dep->name); 1247 ret = -EINVAL; 1248 goto out; 1249 } 1250 1251 ret = __dwc3_gadget_ep_set_halt(dep, value); 1252 out: 1253 spin_unlock_irqrestore(&dwc->lock, flags); 1254 1255 return ret; 1256 } 1257 1258 static int dwc3_gadget_ep_set_wedge(struct usb_ep *ep) 1259 { 1260 struct dwc3_ep *dep = to_dwc3_ep(ep); 1261 struct dwc3 *dwc = dep->dwc; 1262 unsigned long flags; 1263 1264 spin_lock_irqsave(&dwc->lock, flags); 1265 dep->flags |= DWC3_EP_WEDGE; 1266 spin_unlock_irqrestore(&dwc->lock, flags); 1267 1268 if (dep->number == 0 || dep->number == 1) 1269 return dwc3_gadget_ep0_set_halt(ep, 1); 1270 else 1271 return dwc3_gadget_ep_set_halt(ep, 1); 1272 } 1273 1274 /* -------------------------------------------------------------------------- */ 1275 1276 static struct usb_endpoint_descriptor dwc3_gadget_ep0_desc = { 1277 .bLength = USB_DT_ENDPOINT_SIZE, 1278 .bDescriptorType = USB_DT_ENDPOINT, 1279 .bmAttributes = USB_ENDPOINT_XFER_CONTROL, 1280 }; 1281 1282 static const struct usb_ep_ops dwc3_gadget_ep0_ops = { 1283 .enable = dwc3_gadget_ep0_enable, 1284 .disable = dwc3_gadget_ep0_disable, 1285 .alloc_request = dwc3_gadget_ep_alloc_request, 1286 .free_request = dwc3_gadget_ep_free_request, 1287 .queue = dwc3_gadget_ep0_queue, 1288 .dequeue = dwc3_gadget_ep_dequeue, 1289 .set_halt = dwc3_gadget_ep0_set_halt, 1290 .set_wedge = dwc3_gadget_ep_set_wedge, 1291 }; 1292 1293 static const struct usb_ep_ops dwc3_gadget_ep_ops = { 1294 .enable = dwc3_gadget_ep_enable, 1295 .disable = dwc3_gadget_ep_disable, 1296 .alloc_request = dwc3_gadget_ep_alloc_request, 1297 .free_request = dwc3_gadget_ep_free_request, 1298 .queue = dwc3_gadget_ep_queue, 1299 .dequeue = dwc3_gadget_ep_dequeue, 1300 .set_halt = dwc3_gadget_ep_set_halt, 1301 .set_wedge = dwc3_gadget_ep_set_wedge, 1302 }; 1303 1304 /* -------------------------------------------------------------------------- */ 1305 1306 static int dwc3_gadget_get_frame(struct usb_gadget *g) 1307 { 1308 struct dwc3 *dwc = gadget_to_dwc(g); 1309 u32 reg; 1310 1311 reg = dwc3_readl(dwc->regs, DWC3_DSTS); 1312 return DWC3_DSTS_SOFFN(reg); 1313 } 1314 1315 static int dwc3_gadget_wakeup(struct usb_gadget *g) 1316 { 1317 struct dwc3 *dwc = gadget_to_dwc(g); 1318 1319 unsigned long timeout; 1320 unsigned long flags; 1321 1322 u32 reg; 1323 1324 int ret = 0; 1325 1326 u8 link_state; 1327 u8 speed; 1328 1329 spin_lock_irqsave(&dwc->lock, flags); 1330 1331 /* 1332 * According to the Databook Remote wakeup request should 1333 * be issued only when the device is in early suspend state. 1334 * 1335 * We can check that via USB Link State bits in DSTS register. 1336 */ 1337 reg = dwc3_readl(dwc->regs, DWC3_DSTS); 1338 1339 speed = reg & DWC3_DSTS_CONNECTSPD; 1340 if (speed == DWC3_DSTS_SUPERSPEED) { 1341 dev_dbg(dwc->dev, "no wakeup on SuperSpeed\n"); 1342 ret = -EINVAL; 1343 goto out; 1344 } 1345 1346 link_state = DWC3_DSTS_USBLNKST(reg); 1347 1348 switch (link_state) { 1349 case DWC3_LINK_STATE_RX_DET: /* in HS, means Early Suspend */ 1350 case DWC3_LINK_STATE_U3: /* in HS, means SUSPEND */ 1351 break; 1352 default: 1353 dev_dbg(dwc->dev, "can't wakeup from link state %d\n", 1354 link_state); 1355 ret = -EINVAL; 1356 goto out; 1357 } 1358 1359 ret = dwc3_gadget_set_link_state(dwc, DWC3_LINK_STATE_RECOV); 1360 if (ret < 0) { 1361 dev_err(dwc->dev, "failed to put link in Recovery\n"); 1362 goto out; 1363 } 1364 1365 /* Recent versions do this automatically */ 1366 if (dwc->revision < DWC3_REVISION_194A) { 1367 /* write zeroes to Link Change Request */ 1368 reg = dwc3_readl(dwc->regs, DWC3_DCTL); 1369 reg &= ~DWC3_DCTL_ULSTCHNGREQ_MASK; 1370 dwc3_writel(dwc->regs, DWC3_DCTL, reg); 1371 } 1372 1373 /* poll until Link State changes to ON */ 1374 timeout = jiffies + msecs_to_jiffies(100); 1375 1376 while (!time_after(jiffies, timeout)) { 1377 reg = dwc3_readl(dwc->regs, DWC3_DSTS); 1378 1379 /* in HS, means ON */ 1380 if (DWC3_DSTS_USBLNKST(reg) == DWC3_LINK_STATE_U0) 1381 break; 1382 } 1383 1384 if (DWC3_DSTS_USBLNKST(reg) != DWC3_LINK_STATE_U0) { 1385 dev_err(dwc->dev, "failed to send remote wakeup\n"); 1386 ret = -EINVAL; 1387 } 1388 1389 out: 1390 spin_unlock_irqrestore(&dwc->lock, flags); 1391 1392 return ret; 1393 } 1394 1395 static int dwc3_gadget_set_selfpowered(struct usb_gadget *g, 1396 int is_selfpowered) 1397 { 1398 struct dwc3 *dwc = gadget_to_dwc(g); 1399 unsigned long flags; 1400 1401 spin_lock_irqsave(&dwc->lock, flags); 1402 dwc->is_selfpowered = !!is_selfpowered; 1403 spin_unlock_irqrestore(&dwc->lock, flags); 1404 1405 return 0; 1406 } 1407 1408 static int dwc3_gadget_run_stop(struct dwc3 *dwc, int is_on, int suspend) 1409 { 1410 u32 reg; 1411 u32 timeout = 500; 1412 1413 reg = dwc3_readl(dwc->regs, DWC3_DCTL); 1414 if (is_on) { 1415 if (dwc->revision <= DWC3_REVISION_187A) { 1416 reg &= ~DWC3_DCTL_TRGTULST_MASK; 1417 reg |= DWC3_DCTL_TRGTULST_RX_DET; 1418 } 1419 1420 if (dwc->revision >= DWC3_REVISION_194A) 1421 reg &= ~DWC3_DCTL_KEEP_CONNECT; 1422 reg |= DWC3_DCTL_RUN_STOP; 1423 1424 if (dwc->has_hibernation) 1425 reg |= DWC3_DCTL_KEEP_CONNECT; 1426 1427 dwc->pullups_connected = true; 1428 } else { 1429 reg &= ~DWC3_DCTL_RUN_STOP; 1430 1431 if (dwc->has_hibernation && !suspend) 1432 reg &= ~DWC3_DCTL_KEEP_CONNECT; 1433 1434 dwc->pullups_connected = false; 1435 } 1436 1437 dwc3_writel(dwc->regs, DWC3_DCTL, reg); 1438 1439 do { 1440 reg = dwc3_readl(dwc->regs, DWC3_DSTS); 1441 if (is_on) { 1442 if (!(reg & DWC3_DSTS_DEVCTRLHLT)) 1443 break; 1444 } else { 1445 if (reg & DWC3_DSTS_DEVCTRLHLT) 1446 break; 1447 } 1448 timeout--; 1449 if (!timeout) 1450 return -ETIMEDOUT; 1451 udelay(1); 1452 } while (1); 1453 1454 dev_vdbg(dwc->dev, "gadget %s data soft-%s\n", 1455 dwc->gadget_driver 1456 ? dwc->gadget_driver->function : "no-function", 1457 is_on ? "connect" : "disconnect"); 1458 1459 return 0; 1460 } 1461 1462 static int dwc3_gadget_pullup(struct usb_gadget *g, int is_on) 1463 { 1464 struct dwc3 *dwc = gadget_to_dwc(g); 1465 unsigned long flags; 1466 int ret; 1467 1468 is_on = !!is_on; 1469 1470 spin_lock_irqsave(&dwc->lock, flags); 1471 ret = dwc3_gadget_run_stop(dwc, is_on, false); 1472 spin_unlock_irqrestore(&dwc->lock, flags); 1473 1474 return ret; 1475 } 1476 1477 static void dwc3_gadget_enable_irq(struct dwc3 *dwc) 1478 { 1479 u32 reg; 1480 1481 /* Enable all but Start and End of Frame IRQs */ 1482 reg = (DWC3_DEVTEN_VNDRDEVTSTRCVEDEN | 1483 DWC3_DEVTEN_EVNTOVERFLOWEN | 1484 DWC3_DEVTEN_CMDCMPLTEN | 1485 DWC3_DEVTEN_ERRTICERREN | 1486 DWC3_DEVTEN_WKUPEVTEN | 1487 DWC3_DEVTEN_ULSTCNGEN | 1488 DWC3_DEVTEN_CONNECTDONEEN | 1489 DWC3_DEVTEN_USBRSTEN | 1490 DWC3_DEVTEN_DISCONNEVTEN); 1491 1492 dwc3_writel(dwc->regs, DWC3_DEVTEN, reg); 1493 } 1494 1495 static void dwc3_gadget_disable_irq(struct dwc3 *dwc) 1496 { 1497 /* mask all interrupts */ 1498 dwc3_writel(dwc->regs, DWC3_DEVTEN, 0x00); 1499 } 1500 1501 static irqreturn_t dwc3_interrupt(int irq, void *_dwc); 1502 static irqreturn_t dwc3_thread_interrupt(int irq, void *_dwc); 1503 1504 static int dwc3_gadget_start(struct usb_gadget *g, 1505 struct usb_gadget_driver *driver) 1506 { 1507 struct dwc3 *dwc = gadget_to_dwc(g); 1508 struct dwc3_ep *dep; 1509 unsigned long flags; 1510 int ret = 0; 1511 int irq; 1512 u32 reg; 1513 1514 irq = platform_get_irq(to_platform_device(dwc->dev), 0); 1515 ret = request_threaded_irq(irq, dwc3_interrupt, dwc3_thread_interrupt, 1516 IRQF_SHARED, "dwc3", dwc); 1517 if (ret) { 1518 dev_err(dwc->dev, "failed to request irq #%d --> %d\n", 1519 irq, ret); 1520 goto err0; 1521 } 1522 1523 spin_lock_irqsave(&dwc->lock, flags); 1524 1525 if (dwc->gadget_driver) { 1526 dev_err(dwc->dev, "%s is already bound to %s\n", 1527 dwc->gadget.name, 1528 dwc->gadget_driver->driver.name); 1529 ret = -EBUSY; 1530 goto err1; 1531 } 1532 1533 dwc->gadget_driver = driver; 1534 1535 reg = dwc3_readl(dwc->regs, DWC3_DCFG); 1536 reg &= ~(DWC3_DCFG_SPEED_MASK); 1537 1538 /** 1539 * WORKAROUND: DWC3 revision < 2.20a have an issue 1540 * which would cause metastability state on Run/Stop 1541 * bit if we try to force the IP to USB2-only mode. 1542 * 1543 * Because of that, we cannot configure the IP to any 1544 * speed other than the SuperSpeed 1545 * 1546 * Refers to: 1547 * 1548 * STAR#9000525659: Clock Domain Crossing on DCTL in 1549 * USB 2.0 Mode 1550 */ 1551 if (dwc->revision < DWC3_REVISION_220A) { 1552 reg |= DWC3_DCFG_SUPERSPEED; 1553 } else { 1554 switch (dwc->maximum_speed) { 1555 case USB_SPEED_LOW: 1556 reg |= DWC3_DSTS_LOWSPEED; 1557 break; 1558 case USB_SPEED_FULL: 1559 reg |= DWC3_DSTS_FULLSPEED1; 1560 break; 1561 case USB_SPEED_HIGH: 1562 reg |= DWC3_DSTS_HIGHSPEED; 1563 break; 1564 case USB_SPEED_SUPER: /* FALLTHROUGH */ 1565 case USB_SPEED_UNKNOWN: /* FALTHROUGH */ 1566 default: 1567 reg |= DWC3_DSTS_SUPERSPEED; 1568 } 1569 } 1570 dwc3_writel(dwc->regs, DWC3_DCFG, reg); 1571 1572 dwc->start_config_issued = false; 1573 1574 /* Start with SuperSpeed Default */ 1575 dwc3_gadget_ep0_desc.wMaxPacketSize = cpu_to_le16(512); 1576 1577 dep = dwc->eps[0]; 1578 ret = __dwc3_gadget_ep_enable(dep, &dwc3_gadget_ep0_desc, NULL, false, 1579 false); 1580 if (ret) { 1581 dev_err(dwc->dev, "failed to enable %s\n", dep->name); 1582 goto err2; 1583 } 1584 1585 dep = dwc->eps[1]; 1586 ret = __dwc3_gadget_ep_enable(dep, &dwc3_gadget_ep0_desc, NULL, false, 1587 false); 1588 if (ret) { 1589 dev_err(dwc->dev, "failed to enable %s\n", dep->name); 1590 goto err3; 1591 } 1592 1593 /* begin to receive SETUP packets */ 1594 dwc->ep0state = EP0_SETUP_PHASE; 1595 dwc3_ep0_out_start(dwc); 1596 1597 dwc3_gadget_enable_irq(dwc); 1598 1599 spin_unlock_irqrestore(&dwc->lock, flags); 1600 1601 return 0; 1602 1603 err3: 1604 __dwc3_gadget_ep_disable(dwc->eps[0]); 1605 1606 err2: 1607 dwc->gadget_driver = NULL; 1608 1609 err1: 1610 spin_unlock_irqrestore(&dwc->lock, flags); 1611 1612 free_irq(irq, dwc); 1613 1614 err0: 1615 return ret; 1616 } 1617 1618 static int dwc3_gadget_stop(struct usb_gadget *g, 1619 struct usb_gadget_driver *driver) 1620 { 1621 struct dwc3 *dwc = gadget_to_dwc(g); 1622 unsigned long flags; 1623 int irq; 1624 1625 spin_lock_irqsave(&dwc->lock, flags); 1626 1627 dwc3_gadget_disable_irq(dwc); 1628 __dwc3_gadget_ep_disable(dwc->eps[0]); 1629 __dwc3_gadget_ep_disable(dwc->eps[1]); 1630 1631 dwc->gadget_driver = NULL; 1632 1633 spin_unlock_irqrestore(&dwc->lock, flags); 1634 1635 irq = platform_get_irq(to_platform_device(dwc->dev), 0); 1636 free_irq(irq, dwc); 1637 1638 return 0; 1639 } 1640 1641 static const struct usb_gadget_ops dwc3_gadget_ops = { 1642 .get_frame = dwc3_gadget_get_frame, 1643 .wakeup = dwc3_gadget_wakeup, 1644 .set_selfpowered = dwc3_gadget_set_selfpowered, 1645 .pullup = dwc3_gadget_pullup, 1646 .udc_start = dwc3_gadget_start, 1647 .udc_stop = dwc3_gadget_stop, 1648 }; 1649 1650 /* -------------------------------------------------------------------------- */ 1651 1652 static int dwc3_gadget_init_hw_endpoints(struct dwc3 *dwc, 1653 u8 num, u32 direction) 1654 { 1655 struct dwc3_ep *dep; 1656 u8 i; 1657 1658 for (i = 0; i < num; i++) { 1659 u8 epnum = (i << 1) | (!!direction); 1660 1661 dep = kzalloc(sizeof(*dep), GFP_KERNEL); 1662 if (!dep) 1663 return -ENOMEM; 1664 1665 dep->dwc = dwc; 1666 dep->number = epnum; 1667 dep->direction = !!direction; 1668 dwc->eps[epnum] = dep; 1669 1670 snprintf(dep->name, sizeof(dep->name), "ep%d%s", epnum >> 1, 1671 (epnum & 1) ? "in" : "out"); 1672 1673 dep->endpoint.name = dep->name; 1674 1675 dev_vdbg(dwc->dev, "initializing %s\n", dep->name); 1676 1677 if (epnum == 0 || epnum == 1) { 1678 usb_ep_set_maxpacket_limit(&dep->endpoint, 512); 1679 dep->endpoint.maxburst = 1; 1680 dep->endpoint.ops = &dwc3_gadget_ep0_ops; 1681 if (!epnum) 1682 dwc->gadget.ep0 = &dep->endpoint; 1683 } else { 1684 int ret; 1685 1686 usb_ep_set_maxpacket_limit(&dep->endpoint, 1024); 1687 dep->endpoint.max_streams = 15; 1688 dep->endpoint.ops = &dwc3_gadget_ep_ops; 1689 list_add_tail(&dep->endpoint.ep_list, 1690 &dwc->gadget.ep_list); 1691 1692 ret = dwc3_alloc_trb_pool(dep); 1693 if (ret) 1694 return ret; 1695 } 1696 1697 INIT_LIST_HEAD(&dep->request_list); 1698 INIT_LIST_HEAD(&dep->req_queued); 1699 } 1700 1701 return 0; 1702 } 1703 1704 static int dwc3_gadget_init_endpoints(struct dwc3 *dwc) 1705 { 1706 int ret; 1707 1708 INIT_LIST_HEAD(&dwc->gadget.ep_list); 1709 1710 ret = dwc3_gadget_init_hw_endpoints(dwc, dwc->num_out_eps, 0); 1711 if (ret < 0) { 1712 dev_vdbg(dwc->dev, "failed to allocate OUT endpoints\n"); 1713 return ret; 1714 } 1715 1716 ret = dwc3_gadget_init_hw_endpoints(dwc, dwc->num_in_eps, 1); 1717 if (ret < 0) { 1718 dev_vdbg(dwc->dev, "failed to allocate IN endpoints\n"); 1719 return ret; 1720 } 1721 1722 return 0; 1723 } 1724 1725 static void dwc3_gadget_free_endpoints(struct dwc3 *dwc) 1726 { 1727 struct dwc3_ep *dep; 1728 u8 epnum; 1729 1730 for (epnum = 0; epnum < DWC3_ENDPOINTS_NUM; epnum++) { 1731 dep = dwc->eps[epnum]; 1732 if (!dep) 1733 continue; 1734 /* 1735 * Physical endpoints 0 and 1 are special; they form the 1736 * bi-directional USB endpoint 0. 1737 * 1738 * For those two physical endpoints, we don't allocate a TRB 1739 * pool nor do we add them the endpoints list. Due to that, we 1740 * shouldn't do these two operations otherwise we would end up 1741 * with all sorts of bugs when removing dwc3.ko. 1742 */ 1743 if (epnum != 0 && epnum != 1) { 1744 dwc3_free_trb_pool(dep); 1745 list_del(&dep->endpoint.ep_list); 1746 } 1747 1748 kfree(dep); 1749 } 1750 } 1751 1752 /* -------------------------------------------------------------------------- */ 1753 1754 static int __dwc3_cleanup_done_trbs(struct dwc3 *dwc, struct dwc3_ep *dep, 1755 struct dwc3_request *req, struct dwc3_trb *trb, 1756 const struct dwc3_event_depevt *event, int status) 1757 { 1758 unsigned int count; 1759 unsigned int s_pkt = 0; 1760 unsigned int trb_status; 1761 1762 trace_dwc3_complete_trb(dep, trb); 1763 1764 if ((trb->ctrl & DWC3_TRB_CTRL_HWO) && status != -ESHUTDOWN) 1765 /* 1766 * We continue despite the error. There is not much we 1767 * can do. If we don't clean it up we loop forever. If 1768 * we skip the TRB then it gets overwritten after a 1769 * while since we use them in a ring buffer. A BUG() 1770 * would help. Lets hope that if this occurs, someone 1771 * fixes the root cause instead of looking away :) 1772 */ 1773 dev_err(dwc->dev, "%s's TRB (%p) still owned by HW\n", 1774 dep->name, trb); 1775 count = trb->size & DWC3_TRB_SIZE_MASK; 1776 1777 if (dep->direction) { 1778 if (count) { 1779 trb_status = DWC3_TRB_SIZE_TRBSTS(trb->size); 1780 if (trb_status == DWC3_TRBSTS_MISSED_ISOC) { 1781 dev_dbg(dwc->dev, "incomplete IN transfer %s\n", 1782 dep->name); 1783 /* 1784 * If missed isoc occurred and there is 1785 * no request queued then issue END 1786 * TRANSFER, so that core generates 1787 * next xfernotready and we will issue 1788 * a fresh START TRANSFER. 1789 * If there are still queued request 1790 * then wait, do not issue either END 1791 * or UPDATE TRANSFER, just attach next 1792 * request in request_list during 1793 * giveback.If any future queued request 1794 * is successfully transferred then we 1795 * will issue UPDATE TRANSFER for all 1796 * request in the request_list. 1797 */ 1798 dep->flags |= DWC3_EP_MISSED_ISOC; 1799 } else { 1800 dev_err(dwc->dev, "incomplete IN transfer %s\n", 1801 dep->name); 1802 status = -ECONNRESET; 1803 } 1804 } else { 1805 dep->flags &= ~DWC3_EP_MISSED_ISOC; 1806 } 1807 } else { 1808 if (count && (event->status & DEPEVT_STATUS_SHORT)) 1809 s_pkt = 1; 1810 } 1811 1812 /* 1813 * We assume here we will always receive the entire data block 1814 * which we should receive. Meaning, if we program RX to 1815 * receive 4K but we receive only 2K, we assume that's all we 1816 * should receive and we simply bounce the request back to the 1817 * gadget driver for further processing. 1818 */ 1819 req->request.actual += req->request.length - count; 1820 if (s_pkt) 1821 return 1; 1822 if ((event->status & DEPEVT_STATUS_LST) && 1823 (trb->ctrl & (DWC3_TRB_CTRL_LST | 1824 DWC3_TRB_CTRL_HWO))) 1825 return 1; 1826 if ((event->status & DEPEVT_STATUS_IOC) && 1827 (trb->ctrl & DWC3_TRB_CTRL_IOC)) 1828 return 1; 1829 return 0; 1830 } 1831 1832 static int dwc3_cleanup_done_reqs(struct dwc3 *dwc, struct dwc3_ep *dep, 1833 const struct dwc3_event_depevt *event, int status) 1834 { 1835 struct dwc3_request *req; 1836 struct dwc3_trb *trb; 1837 unsigned int slot; 1838 unsigned int i; 1839 int ret; 1840 1841 do { 1842 req = next_request(&dep->req_queued); 1843 if (!req) { 1844 WARN_ON_ONCE(1); 1845 return 1; 1846 } 1847 i = 0; 1848 do { 1849 slot = req->start_slot + i; 1850 if ((slot == DWC3_TRB_NUM - 1) && 1851 usb_endpoint_xfer_isoc(dep->endpoint.desc)) 1852 slot++; 1853 slot %= DWC3_TRB_NUM; 1854 trb = &dep->trb_pool[slot]; 1855 1856 ret = __dwc3_cleanup_done_trbs(dwc, dep, req, trb, 1857 event, status); 1858 if (ret) 1859 break; 1860 }while (++i < req->request.num_mapped_sgs); 1861 1862 dwc3_gadget_giveback(dep, req, status); 1863 1864 if (ret) 1865 break; 1866 } while (1); 1867 1868 if (usb_endpoint_xfer_isoc(dep->endpoint.desc) && 1869 list_empty(&dep->req_queued)) { 1870 if (list_empty(&dep->request_list)) { 1871 /* 1872 * If there is no entry in request list then do 1873 * not issue END TRANSFER now. Just set PENDING 1874 * flag, so that END TRANSFER is issued when an 1875 * entry is added into request list. 1876 */ 1877 dep->flags = DWC3_EP_PENDING_REQUEST; 1878 } else { 1879 dwc3_stop_active_transfer(dwc, dep->number, true); 1880 dep->flags = DWC3_EP_ENABLED; 1881 } 1882 return 1; 1883 } 1884 1885 return 1; 1886 } 1887 1888 static void dwc3_endpoint_transfer_complete(struct dwc3 *dwc, 1889 struct dwc3_ep *dep, const struct dwc3_event_depevt *event) 1890 { 1891 unsigned status = 0; 1892 int clean_busy; 1893 1894 if (event->status & DEPEVT_STATUS_BUSERR) 1895 status = -ECONNRESET; 1896 1897 clean_busy = dwc3_cleanup_done_reqs(dwc, dep, event, status); 1898 if (clean_busy) 1899 dep->flags &= ~DWC3_EP_BUSY; 1900 1901 /* 1902 * WORKAROUND: This is the 2nd half of U1/U2 -> U0 workaround. 1903 * See dwc3_gadget_linksts_change_interrupt() for 1st half. 1904 */ 1905 if (dwc->revision < DWC3_REVISION_183A) { 1906 u32 reg; 1907 int i; 1908 1909 for (i = 0; i < DWC3_ENDPOINTS_NUM; i++) { 1910 dep = dwc->eps[i]; 1911 1912 if (!(dep->flags & DWC3_EP_ENABLED)) 1913 continue; 1914 1915 if (!list_empty(&dep->req_queued)) 1916 return; 1917 } 1918 1919 reg = dwc3_readl(dwc->regs, DWC3_DCTL); 1920 reg |= dwc->u1u2; 1921 dwc3_writel(dwc->regs, DWC3_DCTL, reg); 1922 1923 dwc->u1u2 = 0; 1924 } 1925 } 1926 1927 static void dwc3_endpoint_interrupt(struct dwc3 *dwc, 1928 const struct dwc3_event_depevt *event) 1929 { 1930 struct dwc3_ep *dep; 1931 u8 epnum = event->endpoint_number; 1932 1933 dep = dwc->eps[epnum]; 1934 1935 if (!(dep->flags & DWC3_EP_ENABLED)) 1936 return; 1937 1938 if (epnum == 0 || epnum == 1) { 1939 dwc3_ep0_interrupt(dwc, event); 1940 return; 1941 } 1942 1943 switch (event->endpoint_event) { 1944 case DWC3_DEPEVT_XFERCOMPLETE: 1945 dep->resource_index = 0; 1946 1947 if (usb_endpoint_xfer_isoc(dep->endpoint.desc)) { 1948 dev_dbg(dwc->dev, "%s is an Isochronous endpoint\n", 1949 dep->name); 1950 return; 1951 } 1952 1953 dwc3_endpoint_transfer_complete(dwc, dep, event); 1954 break; 1955 case DWC3_DEPEVT_XFERINPROGRESS: 1956 dwc3_endpoint_transfer_complete(dwc, dep, event); 1957 break; 1958 case DWC3_DEPEVT_XFERNOTREADY: 1959 if (usb_endpoint_xfer_isoc(dep->endpoint.desc)) { 1960 dwc3_gadget_start_isoc(dwc, dep, event); 1961 } else { 1962 int ret; 1963 1964 dev_vdbg(dwc->dev, "%s: reason %s\n", 1965 dep->name, event->status & 1966 DEPEVT_STATUS_TRANSFER_ACTIVE 1967 ? "Transfer Active" 1968 : "Transfer Not Active"); 1969 1970 ret = __dwc3_gadget_kick_transfer(dep, 0, 1); 1971 if (!ret || ret == -EBUSY) 1972 return; 1973 1974 dev_dbg(dwc->dev, "%s: failed to kick transfers\n", 1975 dep->name); 1976 } 1977 1978 break; 1979 case DWC3_DEPEVT_STREAMEVT: 1980 if (!usb_endpoint_xfer_bulk(dep->endpoint.desc)) { 1981 dev_err(dwc->dev, "Stream event for non-Bulk %s\n", 1982 dep->name); 1983 return; 1984 } 1985 1986 switch (event->status) { 1987 case DEPEVT_STREAMEVT_FOUND: 1988 dev_vdbg(dwc->dev, "Stream %d found and started\n", 1989 event->parameters); 1990 1991 break; 1992 case DEPEVT_STREAMEVT_NOTFOUND: 1993 /* FALLTHROUGH */ 1994 default: 1995 dev_dbg(dwc->dev, "Couldn't find suitable stream\n"); 1996 } 1997 break; 1998 case DWC3_DEPEVT_RXTXFIFOEVT: 1999 dev_dbg(dwc->dev, "%s FIFO Overrun\n", dep->name); 2000 break; 2001 case DWC3_DEPEVT_EPCMDCMPLT: 2002 dev_vdbg(dwc->dev, "Endpoint Command Complete\n"); 2003 break; 2004 } 2005 } 2006 2007 static void dwc3_disconnect_gadget(struct dwc3 *dwc) 2008 { 2009 if (dwc->gadget_driver && dwc->gadget_driver->disconnect) { 2010 spin_unlock(&dwc->lock); 2011 dwc->gadget_driver->disconnect(&dwc->gadget); 2012 spin_lock(&dwc->lock); 2013 } 2014 } 2015 2016 static void dwc3_suspend_gadget(struct dwc3 *dwc) 2017 { 2018 if (dwc->gadget_driver && dwc->gadget_driver->suspend) { 2019 spin_unlock(&dwc->lock); 2020 dwc->gadget_driver->suspend(&dwc->gadget); 2021 spin_lock(&dwc->lock); 2022 } 2023 } 2024 2025 static void dwc3_resume_gadget(struct dwc3 *dwc) 2026 { 2027 if (dwc->gadget_driver && dwc->gadget_driver->resume) { 2028 spin_unlock(&dwc->lock); 2029 dwc->gadget_driver->resume(&dwc->gadget); 2030 spin_lock(&dwc->lock); 2031 } 2032 } 2033 2034 static void dwc3_stop_active_transfer(struct dwc3 *dwc, u32 epnum, bool force) 2035 { 2036 struct dwc3_ep *dep; 2037 struct dwc3_gadget_ep_cmd_params params; 2038 u32 cmd; 2039 int ret; 2040 2041 dep = dwc->eps[epnum]; 2042 2043 if (!dep->resource_index) 2044 return; 2045 2046 /* 2047 * NOTICE: We are violating what the Databook says about the 2048 * EndTransfer command. Ideally we would _always_ wait for the 2049 * EndTransfer Command Completion IRQ, but that's causing too 2050 * much trouble synchronizing between us and gadget driver. 2051 * 2052 * We have discussed this with the IP Provider and it was 2053 * suggested to giveback all requests here, but give HW some 2054 * extra time to synchronize with the interconnect. We're using 2055 * an arbitraty 100us delay for that. 2056 * 2057 * Note also that a similar handling was tested by Synopsys 2058 * (thanks a lot Paul) and nothing bad has come out of it. 2059 * In short, what we're doing is: 2060 * 2061 * - Issue EndTransfer WITH CMDIOC bit set 2062 * - Wait 100us 2063 */ 2064 2065 cmd = DWC3_DEPCMD_ENDTRANSFER; 2066 cmd |= force ? DWC3_DEPCMD_HIPRI_FORCERM : 0; 2067 cmd |= DWC3_DEPCMD_CMDIOC; 2068 cmd |= DWC3_DEPCMD_PARAM(dep->resource_index); 2069 memset(¶ms, 0, sizeof(params)); 2070 ret = dwc3_send_gadget_ep_cmd(dwc, dep->number, cmd, ¶ms); 2071 WARN_ON_ONCE(ret); 2072 dep->resource_index = 0; 2073 dep->flags &= ~DWC3_EP_BUSY; 2074 udelay(100); 2075 } 2076 2077 static void dwc3_stop_active_transfers(struct dwc3 *dwc) 2078 { 2079 u32 epnum; 2080 2081 for (epnum = 2; epnum < DWC3_ENDPOINTS_NUM; epnum++) { 2082 struct dwc3_ep *dep; 2083 2084 dep = dwc->eps[epnum]; 2085 if (!dep) 2086 continue; 2087 2088 if (!(dep->flags & DWC3_EP_ENABLED)) 2089 continue; 2090 2091 dwc3_remove_requests(dwc, dep); 2092 } 2093 } 2094 2095 static void dwc3_clear_stall_all_ep(struct dwc3 *dwc) 2096 { 2097 u32 epnum; 2098 2099 for (epnum = 1; epnum < DWC3_ENDPOINTS_NUM; epnum++) { 2100 struct dwc3_ep *dep; 2101 struct dwc3_gadget_ep_cmd_params params; 2102 int ret; 2103 2104 dep = dwc->eps[epnum]; 2105 if (!dep) 2106 continue; 2107 2108 if (!(dep->flags & DWC3_EP_STALL)) 2109 continue; 2110 2111 dep->flags &= ~DWC3_EP_STALL; 2112 2113 memset(¶ms, 0, sizeof(params)); 2114 ret = dwc3_send_gadget_ep_cmd(dwc, dep->number, 2115 DWC3_DEPCMD_CLEARSTALL, ¶ms); 2116 WARN_ON_ONCE(ret); 2117 } 2118 } 2119 2120 static void dwc3_gadget_disconnect_interrupt(struct dwc3 *dwc) 2121 { 2122 int reg; 2123 2124 reg = dwc3_readl(dwc->regs, DWC3_DCTL); 2125 reg &= ~DWC3_DCTL_INITU1ENA; 2126 dwc3_writel(dwc->regs, DWC3_DCTL, reg); 2127 2128 reg &= ~DWC3_DCTL_INITU2ENA; 2129 dwc3_writel(dwc->regs, DWC3_DCTL, reg); 2130 2131 dwc3_disconnect_gadget(dwc); 2132 dwc->start_config_issued = false; 2133 2134 dwc->gadget.speed = USB_SPEED_UNKNOWN; 2135 dwc->setup_packet_pending = false; 2136 } 2137 2138 static void dwc3_gadget_reset_interrupt(struct dwc3 *dwc) 2139 { 2140 u32 reg; 2141 2142 /* 2143 * WORKAROUND: DWC3 revisions <1.88a have an issue which 2144 * would cause a missing Disconnect Event if there's a 2145 * pending Setup Packet in the FIFO. 2146 * 2147 * There's no suggested workaround on the official Bug 2148 * report, which states that "unless the driver/application 2149 * is doing any special handling of a disconnect event, 2150 * there is no functional issue". 2151 * 2152 * Unfortunately, it turns out that we _do_ some special 2153 * handling of a disconnect event, namely complete all 2154 * pending transfers, notify gadget driver of the 2155 * disconnection, and so on. 2156 * 2157 * Our suggested workaround is to follow the Disconnect 2158 * Event steps here, instead, based on a setup_packet_pending 2159 * flag. Such flag gets set whenever we have a XferNotReady 2160 * event on EP0 and gets cleared on XferComplete for the 2161 * same endpoint. 2162 * 2163 * Refers to: 2164 * 2165 * STAR#9000466709: RTL: Device : Disconnect event not 2166 * generated if setup packet pending in FIFO 2167 */ 2168 if (dwc->revision < DWC3_REVISION_188A) { 2169 if (dwc->setup_packet_pending) 2170 dwc3_gadget_disconnect_interrupt(dwc); 2171 } 2172 2173 /* after reset -> Default State */ 2174 usb_gadget_set_state(&dwc->gadget, USB_STATE_DEFAULT); 2175 2176 if (dwc->gadget.speed != USB_SPEED_UNKNOWN) 2177 dwc3_disconnect_gadget(dwc); 2178 2179 reg = dwc3_readl(dwc->regs, DWC3_DCTL); 2180 reg &= ~DWC3_DCTL_TSTCTRL_MASK; 2181 dwc3_writel(dwc->regs, DWC3_DCTL, reg); 2182 dwc->test_mode = false; 2183 2184 dwc3_stop_active_transfers(dwc); 2185 dwc3_clear_stall_all_ep(dwc); 2186 dwc->start_config_issued = false; 2187 2188 /* Reset device address to zero */ 2189 reg = dwc3_readl(dwc->regs, DWC3_DCFG); 2190 reg &= ~(DWC3_DCFG_DEVADDR_MASK); 2191 dwc3_writel(dwc->regs, DWC3_DCFG, reg); 2192 } 2193 2194 static void dwc3_update_ram_clk_sel(struct dwc3 *dwc, u32 speed) 2195 { 2196 u32 reg; 2197 u32 usb30_clock = DWC3_GCTL_CLK_BUS; 2198 2199 /* 2200 * We change the clock only at SS but I dunno why I would want to do 2201 * this. Maybe it becomes part of the power saving plan. 2202 */ 2203 2204 if (speed != DWC3_DSTS_SUPERSPEED) 2205 return; 2206 2207 /* 2208 * RAMClkSel is reset to 0 after USB reset, so it must be reprogrammed 2209 * each time on Connect Done. 2210 */ 2211 if (!usb30_clock) 2212 return; 2213 2214 reg = dwc3_readl(dwc->regs, DWC3_GCTL); 2215 reg |= DWC3_GCTL_RAMCLKSEL(usb30_clock); 2216 dwc3_writel(dwc->regs, DWC3_GCTL, reg); 2217 } 2218 2219 static void dwc3_gadget_conndone_interrupt(struct dwc3 *dwc) 2220 { 2221 struct dwc3_ep *dep; 2222 int ret; 2223 u32 reg; 2224 u8 speed; 2225 2226 reg = dwc3_readl(dwc->regs, DWC3_DSTS); 2227 speed = reg & DWC3_DSTS_CONNECTSPD; 2228 dwc->speed = speed; 2229 2230 dwc3_update_ram_clk_sel(dwc, speed); 2231 2232 switch (speed) { 2233 case DWC3_DCFG_SUPERSPEED: 2234 /* 2235 * WORKAROUND: DWC3 revisions <1.90a have an issue which 2236 * would cause a missing USB3 Reset event. 2237 * 2238 * In such situations, we should force a USB3 Reset 2239 * event by calling our dwc3_gadget_reset_interrupt() 2240 * routine. 2241 * 2242 * Refers to: 2243 * 2244 * STAR#9000483510: RTL: SS : USB3 reset event may 2245 * not be generated always when the link enters poll 2246 */ 2247 if (dwc->revision < DWC3_REVISION_190A) 2248 dwc3_gadget_reset_interrupt(dwc); 2249 2250 dwc3_gadget_ep0_desc.wMaxPacketSize = cpu_to_le16(512); 2251 dwc->gadget.ep0->maxpacket = 512; 2252 dwc->gadget.speed = USB_SPEED_SUPER; 2253 break; 2254 case DWC3_DCFG_HIGHSPEED: 2255 dwc3_gadget_ep0_desc.wMaxPacketSize = cpu_to_le16(64); 2256 dwc->gadget.ep0->maxpacket = 64; 2257 dwc->gadget.speed = USB_SPEED_HIGH; 2258 break; 2259 case DWC3_DCFG_FULLSPEED2: 2260 case DWC3_DCFG_FULLSPEED1: 2261 dwc3_gadget_ep0_desc.wMaxPacketSize = cpu_to_le16(64); 2262 dwc->gadget.ep0->maxpacket = 64; 2263 dwc->gadget.speed = USB_SPEED_FULL; 2264 break; 2265 case DWC3_DCFG_LOWSPEED: 2266 dwc3_gadget_ep0_desc.wMaxPacketSize = cpu_to_le16(8); 2267 dwc->gadget.ep0->maxpacket = 8; 2268 dwc->gadget.speed = USB_SPEED_LOW; 2269 break; 2270 } 2271 2272 /* Enable USB2 LPM Capability */ 2273 2274 if ((dwc->revision > DWC3_REVISION_194A) 2275 && (speed != DWC3_DCFG_SUPERSPEED)) { 2276 reg = dwc3_readl(dwc->regs, DWC3_DCFG); 2277 reg |= DWC3_DCFG_LPM_CAP; 2278 dwc3_writel(dwc->regs, DWC3_DCFG, reg); 2279 2280 reg = dwc3_readl(dwc->regs, DWC3_DCTL); 2281 reg &= ~(DWC3_DCTL_HIRD_THRES_MASK | DWC3_DCTL_L1_HIBER_EN); 2282 2283 /* 2284 * TODO: This should be configurable. For now using 2285 * maximum allowed HIRD threshold value of 0b1100 2286 */ 2287 reg |= DWC3_DCTL_HIRD_THRES(12); 2288 2289 dwc3_writel(dwc->regs, DWC3_DCTL, reg); 2290 } else { 2291 reg = dwc3_readl(dwc->regs, DWC3_DCTL); 2292 reg &= ~DWC3_DCTL_HIRD_THRES_MASK; 2293 dwc3_writel(dwc->regs, DWC3_DCTL, reg); 2294 } 2295 2296 dep = dwc->eps[0]; 2297 ret = __dwc3_gadget_ep_enable(dep, &dwc3_gadget_ep0_desc, NULL, true, 2298 false); 2299 if (ret) { 2300 dev_err(dwc->dev, "failed to enable %s\n", dep->name); 2301 return; 2302 } 2303 2304 dep = dwc->eps[1]; 2305 ret = __dwc3_gadget_ep_enable(dep, &dwc3_gadget_ep0_desc, NULL, true, 2306 false); 2307 if (ret) { 2308 dev_err(dwc->dev, "failed to enable %s\n", dep->name); 2309 return; 2310 } 2311 2312 /* 2313 * Configure PHY via GUSB3PIPECTLn if required. 2314 * 2315 * Update GTXFIFOSIZn 2316 * 2317 * In both cases reset values should be sufficient. 2318 */ 2319 } 2320 2321 static void dwc3_gadget_wakeup_interrupt(struct dwc3 *dwc) 2322 { 2323 /* 2324 * TODO take core out of low power mode when that's 2325 * implemented. 2326 */ 2327 2328 dwc->gadget_driver->resume(&dwc->gadget); 2329 } 2330 2331 static void dwc3_gadget_linksts_change_interrupt(struct dwc3 *dwc, 2332 unsigned int evtinfo) 2333 { 2334 enum dwc3_link_state next = evtinfo & DWC3_LINK_STATE_MASK; 2335 unsigned int pwropt; 2336 2337 /* 2338 * WORKAROUND: DWC3 < 2.50a have an issue when configured without 2339 * Hibernation mode enabled which would show up when device detects 2340 * host-initiated U3 exit. 2341 * 2342 * In that case, device will generate a Link State Change Interrupt 2343 * from U3 to RESUME which is only necessary if Hibernation is 2344 * configured in. 2345 * 2346 * There are no functional changes due to such spurious event and we 2347 * just need to ignore it. 2348 * 2349 * Refers to: 2350 * 2351 * STAR#9000570034 RTL: SS Resume event generated in non-Hibernation 2352 * operational mode 2353 */ 2354 pwropt = DWC3_GHWPARAMS1_EN_PWROPT(dwc->hwparams.hwparams1); 2355 if ((dwc->revision < DWC3_REVISION_250A) && 2356 (pwropt != DWC3_GHWPARAMS1_EN_PWROPT_HIB)) { 2357 if ((dwc->link_state == DWC3_LINK_STATE_U3) && 2358 (next == DWC3_LINK_STATE_RESUME)) { 2359 dev_vdbg(dwc->dev, "ignoring transition U3 -> Resume\n"); 2360 return; 2361 } 2362 } 2363 2364 /* 2365 * WORKAROUND: DWC3 Revisions <1.83a have an issue which, depending 2366 * on the link partner, the USB session might do multiple entry/exit 2367 * of low power states before a transfer takes place. 2368 * 2369 * Due to this problem, we might experience lower throughput. The 2370 * suggested workaround is to disable DCTL[12:9] bits if we're 2371 * transitioning from U1/U2 to U0 and enable those bits again 2372 * after a transfer completes and there are no pending transfers 2373 * on any of the enabled endpoints. 2374 * 2375 * This is the first half of that workaround. 2376 * 2377 * Refers to: 2378 * 2379 * STAR#9000446952: RTL: Device SS : if U1/U2 ->U0 takes >128us 2380 * core send LGO_Ux entering U0 2381 */ 2382 if (dwc->revision < DWC3_REVISION_183A) { 2383 if (next == DWC3_LINK_STATE_U0) { 2384 u32 u1u2; 2385 u32 reg; 2386 2387 switch (dwc->link_state) { 2388 case DWC3_LINK_STATE_U1: 2389 case DWC3_LINK_STATE_U2: 2390 reg = dwc3_readl(dwc->regs, DWC3_DCTL); 2391 u1u2 = reg & (DWC3_DCTL_INITU2ENA 2392 | DWC3_DCTL_ACCEPTU2ENA 2393 | DWC3_DCTL_INITU1ENA 2394 | DWC3_DCTL_ACCEPTU1ENA); 2395 2396 if (!dwc->u1u2) 2397 dwc->u1u2 = reg & u1u2; 2398 2399 reg &= ~u1u2; 2400 2401 dwc3_writel(dwc->regs, DWC3_DCTL, reg); 2402 break; 2403 default: 2404 /* do nothing */ 2405 break; 2406 } 2407 } 2408 } 2409 2410 switch (next) { 2411 case DWC3_LINK_STATE_U1: 2412 if (dwc->speed == USB_SPEED_SUPER) 2413 dwc3_suspend_gadget(dwc); 2414 break; 2415 case DWC3_LINK_STATE_U2: 2416 case DWC3_LINK_STATE_U3: 2417 dwc3_suspend_gadget(dwc); 2418 break; 2419 case DWC3_LINK_STATE_RESUME: 2420 dwc3_resume_gadget(dwc); 2421 break; 2422 default: 2423 /* do nothing */ 2424 break; 2425 } 2426 2427 dwc->link_state = next; 2428 } 2429 2430 static void dwc3_gadget_hibernation_interrupt(struct dwc3 *dwc, 2431 unsigned int evtinfo) 2432 { 2433 unsigned int is_ss = evtinfo & BIT(4); 2434 2435 /** 2436 * WORKAROUND: DWC3 revison 2.20a with hibernation support 2437 * have a known issue which can cause USB CV TD.9.23 to fail 2438 * randomly. 2439 * 2440 * Because of this issue, core could generate bogus hibernation 2441 * events which SW needs to ignore. 2442 * 2443 * Refers to: 2444 * 2445 * STAR#9000546576: Device Mode Hibernation: Issue in USB 2.0 2446 * Device Fallback from SuperSpeed 2447 */ 2448 if (is_ss ^ (dwc->speed == USB_SPEED_SUPER)) 2449 return; 2450 2451 /* enter hibernation here */ 2452 } 2453 2454 static void dwc3_gadget_interrupt(struct dwc3 *dwc, 2455 const struct dwc3_event_devt *event) 2456 { 2457 switch (event->type) { 2458 case DWC3_DEVICE_EVENT_DISCONNECT: 2459 dwc3_gadget_disconnect_interrupt(dwc); 2460 break; 2461 case DWC3_DEVICE_EVENT_RESET: 2462 dwc3_gadget_reset_interrupt(dwc); 2463 break; 2464 case DWC3_DEVICE_EVENT_CONNECT_DONE: 2465 dwc3_gadget_conndone_interrupt(dwc); 2466 break; 2467 case DWC3_DEVICE_EVENT_WAKEUP: 2468 dwc3_gadget_wakeup_interrupt(dwc); 2469 break; 2470 case DWC3_DEVICE_EVENT_HIBER_REQ: 2471 if (dev_WARN_ONCE(dwc->dev, !dwc->has_hibernation, 2472 "unexpected hibernation event\n")) 2473 break; 2474 2475 dwc3_gadget_hibernation_interrupt(dwc, event->event_info); 2476 break; 2477 case DWC3_DEVICE_EVENT_LINK_STATUS_CHANGE: 2478 dwc3_gadget_linksts_change_interrupt(dwc, event->event_info); 2479 break; 2480 case DWC3_DEVICE_EVENT_EOPF: 2481 dev_vdbg(dwc->dev, "End of Periodic Frame\n"); 2482 break; 2483 case DWC3_DEVICE_EVENT_SOF: 2484 dev_vdbg(dwc->dev, "Start of Periodic Frame\n"); 2485 break; 2486 case DWC3_DEVICE_EVENT_ERRATIC_ERROR: 2487 dev_vdbg(dwc->dev, "Erratic Error\n"); 2488 break; 2489 case DWC3_DEVICE_EVENT_CMD_CMPL: 2490 dev_vdbg(dwc->dev, "Command Complete\n"); 2491 break; 2492 case DWC3_DEVICE_EVENT_OVERFLOW: 2493 dev_vdbg(dwc->dev, "Overflow\n"); 2494 break; 2495 default: 2496 dev_dbg(dwc->dev, "UNKNOWN IRQ %d\n", event->type); 2497 } 2498 } 2499 2500 static void dwc3_process_event_entry(struct dwc3 *dwc, 2501 const union dwc3_event *event) 2502 { 2503 trace_dwc3_event(event->raw); 2504 2505 /* Endpoint IRQ, handle it and return early */ 2506 if (event->type.is_devspec == 0) { 2507 /* depevt */ 2508 return dwc3_endpoint_interrupt(dwc, &event->depevt); 2509 } 2510 2511 switch (event->type.type) { 2512 case DWC3_EVENT_TYPE_DEV: 2513 dwc3_gadget_interrupt(dwc, &event->devt); 2514 break; 2515 /* REVISIT what to do with Carkit and I2C events ? */ 2516 default: 2517 dev_err(dwc->dev, "UNKNOWN IRQ type %d\n", event->raw); 2518 } 2519 } 2520 2521 static irqreturn_t dwc3_process_event_buf(struct dwc3 *dwc, u32 buf) 2522 { 2523 struct dwc3_event_buffer *evt; 2524 irqreturn_t ret = IRQ_NONE; 2525 int left; 2526 u32 reg; 2527 2528 evt = dwc->ev_buffs[buf]; 2529 left = evt->count; 2530 2531 if (!(evt->flags & DWC3_EVENT_PENDING)) 2532 return IRQ_NONE; 2533 2534 while (left > 0) { 2535 union dwc3_event event; 2536 2537 event.raw = *(u32 *) (evt->buf + evt->lpos); 2538 2539 dwc3_process_event_entry(dwc, &event); 2540 2541 /* 2542 * FIXME we wrap around correctly to the next entry as 2543 * almost all entries are 4 bytes in size. There is one 2544 * entry which has 12 bytes which is a regular entry 2545 * followed by 8 bytes data. ATM I don't know how 2546 * things are organized if we get next to the a 2547 * boundary so I worry about that once we try to handle 2548 * that. 2549 */ 2550 evt->lpos = (evt->lpos + 4) % DWC3_EVENT_BUFFERS_SIZE; 2551 left -= 4; 2552 2553 dwc3_writel(dwc->regs, DWC3_GEVNTCOUNT(buf), 4); 2554 } 2555 2556 evt->count = 0; 2557 evt->flags &= ~DWC3_EVENT_PENDING; 2558 ret = IRQ_HANDLED; 2559 2560 /* Unmask interrupt */ 2561 reg = dwc3_readl(dwc->regs, DWC3_GEVNTSIZ(buf)); 2562 reg &= ~DWC3_GEVNTSIZ_INTMASK; 2563 dwc3_writel(dwc->regs, DWC3_GEVNTSIZ(buf), reg); 2564 2565 return ret; 2566 } 2567 2568 static irqreturn_t dwc3_thread_interrupt(int irq, void *_dwc) 2569 { 2570 struct dwc3 *dwc = _dwc; 2571 unsigned long flags; 2572 irqreturn_t ret = IRQ_NONE; 2573 int i; 2574 2575 spin_lock_irqsave(&dwc->lock, flags); 2576 2577 for (i = 0; i < dwc->num_event_buffers; i++) 2578 ret |= dwc3_process_event_buf(dwc, i); 2579 2580 spin_unlock_irqrestore(&dwc->lock, flags); 2581 2582 return ret; 2583 } 2584 2585 static irqreturn_t dwc3_check_event_buf(struct dwc3 *dwc, u32 buf) 2586 { 2587 struct dwc3_event_buffer *evt; 2588 u32 count; 2589 u32 reg; 2590 2591 evt = dwc->ev_buffs[buf]; 2592 2593 count = dwc3_readl(dwc->regs, DWC3_GEVNTCOUNT(buf)); 2594 count &= DWC3_GEVNTCOUNT_MASK; 2595 if (!count) 2596 return IRQ_NONE; 2597 2598 evt->count = count; 2599 evt->flags |= DWC3_EVENT_PENDING; 2600 2601 /* Mask interrupt */ 2602 reg = dwc3_readl(dwc->regs, DWC3_GEVNTSIZ(buf)); 2603 reg |= DWC3_GEVNTSIZ_INTMASK; 2604 dwc3_writel(dwc->regs, DWC3_GEVNTSIZ(buf), reg); 2605 2606 return IRQ_WAKE_THREAD; 2607 } 2608 2609 static irqreturn_t dwc3_interrupt(int irq, void *_dwc) 2610 { 2611 struct dwc3 *dwc = _dwc; 2612 int i; 2613 irqreturn_t ret = IRQ_NONE; 2614 2615 spin_lock(&dwc->lock); 2616 2617 for (i = 0; i < dwc->num_event_buffers; i++) { 2618 irqreturn_t status; 2619 2620 status = dwc3_check_event_buf(dwc, i); 2621 if (status == IRQ_WAKE_THREAD) 2622 ret = status; 2623 } 2624 2625 spin_unlock(&dwc->lock); 2626 2627 return ret; 2628 } 2629 2630 /** 2631 * dwc3_gadget_init - Initializes gadget related registers 2632 * @dwc: pointer to our controller context structure 2633 * 2634 * Returns 0 on success otherwise negative errno. 2635 */ 2636 int dwc3_gadget_init(struct dwc3 *dwc) 2637 { 2638 int ret; 2639 2640 dwc->ctrl_req = dma_alloc_coherent(dwc->dev, sizeof(*dwc->ctrl_req), 2641 &dwc->ctrl_req_addr, GFP_KERNEL); 2642 if (!dwc->ctrl_req) { 2643 dev_err(dwc->dev, "failed to allocate ctrl request\n"); 2644 ret = -ENOMEM; 2645 goto err0; 2646 } 2647 2648 dwc->ep0_trb = dma_alloc_coherent(dwc->dev, sizeof(*dwc->ep0_trb), 2649 &dwc->ep0_trb_addr, GFP_KERNEL); 2650 if (!dwc->ep0_trb) { 2651 dev_err(dwc->dev, "failed to allocate ep0 trb\n"); 2652 ret = -ENOMEM; 2653 goto err1; 2654 } 2655 2656 dwc->setup_buf = kzalloc(DWC3_EP0_BOUNCE_SIZE, GFP_KERNEL); 2657 if (!dwc->setup_buf) { 2658 ret = -ENOMEM; 2659 goto err2; 2660 } 2661 2662 dwc->ep0_bounce = dma_alloc_coherent(dwc->dev, 2663 DWC3_EP0_BOUNCE_SIZE, &dwc->ep0_bounce_addr, 2664 GFP_KERNEL); 2665 if (!dwc->ep0_bounce) { 2666 dev_err(dwc->dev, "failed to allocate ep0 bounce buffer\n"); 2667 ret = -ENOMEM; 2668 goto err3; 2669 } 2670 2671 dwc->gadget.ops = &dwc3_gadget_ops; 2672 dwc->gadget.max_speed = USB_SPEED_SUPER; 2673 dwc->gadget.speed = USB_SPEED_UNKNOWN; 2674 dwc->gadget.sg_supported = true; 2675 dwc->gadget.name = "dwc3-gadget"; 2676 2677 /* 2678 * Per databook, DWC3 needs buffer size to be aligned to MaxPacketSize 2679 * on ep out. 2680 */ 2681 dwc->gadget.quirk_ep_out_aligned_size = true; 2682 2683 /* 2684 * REVISIT: Here we should clear all pending IRQs to be 2685 * sure we're starting from a well known location. 2686 */ 2687 2688 ret = dwc3_gadget_init_endpoints(dwc); 2689 if (ret) 2690 goto err4; 2691 2692 ret = usb_add_gadget_udc(dwc->dev, &dwc->gadget); 2693 if (ret) { 2694 dev_err(dwc->dev, "failed to register udc\n"); 2695 goto err4; 2696 } 2697 2698 return 0; 2699 2700 err4: 2701 dwc3_gadget_free_endpoints(dwc); 2702 dma_free_coherent(dwc->dev, DWC3_EP0_BOUNCE_SIZE, 2703 dwc->ep0_bounce, dwc->ep0_bounce_addr); 2704 2705 err3: 2706 kfree(dwc->setup_buf); 2707 2708 err2: 2709 dma_free_coherent(dwc->dev, sizeof(*dwc->ep0_trb), 2710 dwc->ep0_trb, dwc->ep0_trb_addr); 2711 2712 err1: 2713 dma_free_coherent(dwc->dev, sizeof(*dwc->ctrl_req), 2714 dwc->ctrl_req, dwc->ctrl_req_addr); 2715 2716 err0: 2717 return ret; 2718 } 2719 2720 /* -------------------------------------------------------------------------- */ 2721 2722 void dwc3_gadget_exit(struct dwc3 *dwc) 2723 { 2724 usb_del_gadget_udc(&dwc->gadget); 2725 2726 dwc3_gadget_free_endpoints(dwc); 2727 2728 dma_free_coherent(dwc->dev, DWC3_EP0_BOUNCE_SIZE, 2729 dwc->ep0_bounce, dwc->ep0_bounce_addr); 2730 2731 kfree(dwc->setup_buf); 2732 2733 dma_free_coherent(dwc->dev, sizeof(*dwc->ep0_trb), 2734 dwc->ep0_trb, dwc->ep0_trb_addr); 2735 2736 dma_free_coherent(dwc->dev, sizeof(*dwc->ctrl_req), 2737 dwc->ctrl_req, dwc->ctrl_req_addr); 2738 } 2739 2740 int dwc3_gadget_prepare(struct dwc3 *dwc) 2741 { 2742 if (dwc->pullups_connected) { 2743 dwc3_gadget_disable_irq(dwc); 2744 dwc3_gadget_run_stop(dwc, true, true); 2745 } 2746 2747 return 0; 2748 } 2749 2750 void dwc3_gadget_complete(struct dwc3 *dwc) 2751 { 2752 if (dwc->pullups_connected) { 2753 dwc3_gadget_enable_irq(dwc); 2754 dwc3_gadget_run_stop(dwc, true, false); 2755 } 2756 } 2757 2758 int dwc3_gadget_suspend(struct dwc3 *dwc) 2759 { 2760 __dwc3_gadget_ep_disable(dwc->eps[0]); 2761 __dwc3_gadget_ep_disable(dwc->eps[1]); 2762 2763 dwc->dcfg = dwc3_readl(dwc->regs, DWC3_DCFG); 2764 2765 return 0; 2766 } 2767 2768 int dwc3_gadget_resume(struct dwc3 *dwc) 2769 { 2770 struct dwc3_ep *dep; 2771 int ret; 2772 2773 /* Start with SuperSpeed Default */ 2774 dwc3_gadget_ep0_desc.wMaxPacketSize = cpu_to_le16(512); 2775 2776 dep = dwc->eps[0]; 2777 ret = __dwc3_gadget_ep_enable(dep, &dwc3_gadget_ep0_desc, NULL, false, 2778 false); 2779 if (ret) 2780 goto err0; 2781 2782 dep = dwc->eps[1]; 2783 ret = __dwc3_gadget_ep_enable(dep, &dwc3_gadget_ep0_desc, NULL, false, 2784 false); 2785 if (ret) 2786 goto err1; 2787 2788 /* begin to receive SETUP packets */ 2789 dwc->ep0state = EP0_SETUP_PHASE; 2790 dwc3_ep0_out_start(dwc); 2791 2792 dwc3_writel(dwc->regs, DWC3_DCFG, dwc->dcfg); 2793 2794 return 0; 2795 2796 err1: 2797 __dwc3_gadget_ep_disable(dwc->eps[0]); 2798 2799 err0: 2800 return ret; 2801 } 2802