1 // SPDX-License-Identifier: GPL-2.0 2 /* 3 * gadget.c - DesignWare USB3 DRD Controller Gadget Framework Link 4 * 5 * Copyright (C) 2010-2011 Texas Instruments Incorporated - http://www.ti.com 6 * 7 * Authors: Felipe Balbi <balbi@ti.com>, 8 * Sebastian Andrzej Siewior <bigeasy@linutronix.de> 9 */ 10 11 #include <linux/kernel.h> 12 #include <linux/delay.h> 13 #include <linux/slab.h> 14 #include <linux/spinlock.h> 15 #include <linux/platform_device.h> 16 #include <linux/pm_runtime.h> 17 #include <linux/interrupt.h> 18 #include <linux/io.h> 19 #include <linux/list.h> 20 #include <linux/dma-mapping.h> 21 22 #include <linux/usb/ch9.h> 23 #include <linux/usb/gadget.h> 24 25 #include "debug.h" 26 #include "core.h" 27 #include "gadget.h" 28 #include "io.h" 29 30 #define DWC3_ALIGN_FRAME(d, n) (((d)->frame_number + ((d)->interval * (n))) \ 31 & ~((d)->interval - 1)) 32 33 /** 34 * dwc3_gadget_set_test_mode - enables usb2 test modes 35 * @dwc: pointer to our context structure 36 * @mode: the mode to set (J, K SE0 NAK, Force Enable) 37 * 38 * Caller should take care of locking. This function will return 0 on 39 * success or -EINVAL if wrong Test Selector is passed. 40 */ 41 int dwc3_gadget_set_test_mode(struct dwc3 *dwc, int mode) 42 { 43 u32 reg; 44 45 reg = dwc3_readl(dwc->regs, DWC3_DCTL); 46 reg &= ~DWC3_DCTL_TSTCTRL_MASK; 47 48 switch (mode) { 49 case TEST_J: 50 case TEST_K: 51 case TEST_SE0_NAK: 52 case TEST_PACKET: 53 case TEST_FORCE_EN: 54 reg |= mode << 1; 55 break; 56 default: 57 return -EINVAL; 58 } 59 60 dwc3_writel(dwc->regs, DWC3_DCTL, reg); 61 62 return 0; 63 } 64 65 /** 66 * dwc3_gadget_get_link_state - gets current state of usb link 67 * @dwc: pointer to our context structure 68 * 69 * Caller should take care of locking. This function will 70 * return the link state on success (>= 0) or -ETIMEDOUT. 71 */ 72 int dwc3_gadget_get_link_state(struct dwc3 *dwc) 73 { 74 u32 reg; 75 76 reg = dwc3_readl(dwc->regs, DWC3_DSTS); 77 78 return DWC3_DSTS_USBLNKST(reg); 79 } 80 81 /** 82 * dwc3_gadget_set_link_state - sets usb link to a particular state 83 * @dwc: pointer to our context structure 84 * @state: the state to put link into 85 * 86 * Caller should take care of locking. This function will 87 * return 0 on success or -ETIMEDOUT. 88 */ 89 int dwc3_gadget_set_link_state(struct dwc3 *dwc, enum dwc3_link_state state) 90 { 91 int retries = 10000; 92 u32 reg; 93 94 /* 95 * Wait until device controller is ready. Only applies to 1.94a and 96 * later RTL. 97 */ 98 if (dwc->revision >= DWC3_REVISION_194A) { 99 while (--retries) { 100 reg = dwc3_readl(dwc->regs, DWC3_DSTS); 101 if (reg & DWC3_DSTS_DCNRD) 102 udelay(5); 103 else 104 break; 105 } 106 107 if (retries <= 0) 108 return -ETIMEDOUT; 109 } 110 111 reg = dwc3_readl(dwc->regs, DWC3_DCTL); 112 reg &= ~DWC3_DCTL_ULSTCHNGREQ_MASK; 113 114 /* set requested state */ 115 reg |= DWC3_DCTL_ULSTCHNGREQ(state); 116 dwc3_writel(dwc->regs, DWC3_DCTL, reg); 117 118 /* 119 * The following code is racy when called from dwc3_gadget_wakeup, 120 * and is not needed, at least on newer versions 121 */ 122 if (dwc->revision >= DWC3_REVISION_194A) 123 return 0; 124 125 /* wait for a change in DSTS */ 126 retries = 10000; 127 while (--retries) { 128 reg = dwc3_readl(dwc->regs, DWC3_DSTS); 129 130 if (DWC3_DSTS_USBLNKST(reg) == state) 131 return 0; 132 133 udelay(5); 134 } 135 136 return -ETIMEDOUT; 137 } 138 139 /** 140 * dwc3_ep_inc_trb - increment a trb index. 141 * @index: Pointer to the TRB index to increment. 142 * 143 * The index should never point to the link TRB. After incrementing, 144 * if it is point to the link TRB, wrap around to the beginning. The 145 * link TRB is always at the last TRB entry. 146 */ 147 static void dwc3_ep_inc_trb(u8 *index) 148 { 149 (*index)++; 150 if (*index == (DWC3_TRB_NUM - 1)) 151 *index = 0; 152 } 153 154 /** 155 * dwc3_ep_inc_enq - increment endpoint's enqueue pointer 156 * @dep: The endpoint whose enqueue pointer we're incrementing 157 */ 158 static void dwc3_ep_inc_enq(struct dwc3_ep *dep) 159 { 160 dwc3_ep_inc_trb(&dep->trb_enqueue); 161 } 162 163 /** 164 * dwc3_ep_inc_deq - increment endpoint's dequeue pointer 165 * @dep: The endpoint whose enqueue pointer we're incrementing 166 */ 167 static void dwc3_ep_inc_deq(struct dwc3_ep *dep) 168 { 169 dwc3_ep_inc_trb(&dep->trb_dequeue); 170 } 171 172 static void dwc3_gadget_del_and_unmap_request(struct dwc3_ep *dep, 173 struct dwc3_request *req, int status) 174 { 175 struct dwc3 *dwc = dep->dwc; 176 177 list_del(&req->list); 178 req->remaining = 0; 179 req->needs_extra_trb = false; 180 181 if (req->request.status == -EINPROGRESS) 182 req->request.status = status; 183 184 if (req->trb) 185 usb_gadget_unmap_request_by_dev(dwc->sysdev, 186 &req->request, req->direction); 187 188 req->trb = NULL; 189 trace_dwc3_gadget_giveback(req); 190 191 if (dep->number > 1) 192 pm_runtime_put(dwc->dev); 193 } 194 195 /** 196 * dwc3_gadget_giveback - call struct usb_request's ->complete callback 197 * @dep: The endpoint to whom the request belongs to 198 * @req: The request we're giving back 199 * @status: completion code for the request 200 * 201 * Must be called with controller's lock held and interrupts disabled. This 202 * function will unmap @req and call its ->complete() callback to notify upper 203 * layers that it has completed. 204 */ 205 void dwc3_gadget_giveback(struct dwc3_ep *dep, struct dwc3_request *req, 206 int status) 207 { 208 struct dwc3 *dwc = dep->dwc; 209 210 dwc3_gadget_del_and_unmap_request(dep, req, status); 211 req->status = DWC3_REQUEST_STATUS_COMPLETED; 212 213 spin_unlock(&dwc->lock); 214 usb_gadget_giveback_request(&dep->endpoint, &req->request); 215 spin_lock(&dwc->lock); 216 } 217 218 /** 219 * dwc3_send_gadget_generic_command - issue a generic command for the controller 220 * @dwc: pointer to the controller context 221 * @cmd: the command to be issued 222 * @param: command parameter 223 * 224 * Caller should take care of locking. Issue @cmd with a given @param to @dwc 225 * and wait for its completion. 226 */ 227 int dwc3_send_gadget_generic_command(struct dwc3 *dwc, unsigned cmd, u32 param) 228 { 229 u32 timeout = 500; 230 int status = 0; 231 int ret = 0; 232 u32 reg; 233 234 dwc3_writel(dwc->regs, DWC3_DGCMDPAR, param); 235 dwc3_writel(dwc->regs, DWC3_DGCMD, cmd | DWC3_DGCMD_CMDACT); 236 237 do { 238 reg = dwc3_readl(dwc->regs, DWC3_DGCMD); 239 if (!(reg & DWC3_DGCMD_CMDACT)) { 240 status = DWC3_DGCMD_STATUS(reg); 241 if (status) 242 ret = -EINVAL; 243 break; 244 } 245 } while (--timeout); 246 247 if (!timeout) { 248 ret = -ETIMEDOUT; 249 status = -ETIMEDOUT; 250 } 251 252 trace_dwc3_gadget_generic_cmd(cmd, param, status); 253 254 return ret; 255 } 256 257 static int __dwc3_gadget_wakeup(struct dwc3 *dwc); 258 259 /** 260 * dwc3_send_gadget_ep_cmd - issue an endpoint command 261 * @dep: the endpoint to which the command is going to be issued 262 * @cmd: the command to be issued 263 * @params: parameters to the command 264 * 265 * Caller should handle locking. This function will issue @cmd with given 266 * @params to @dep and wait for its completion. 267 */ 268 int dwc3_send_gadget_ep_cmd(struct dwc3_ep *dep, unsigned cmd, 269 struct dwc3_gadget_ep_cmd_params *params) 270 { 271 const struct usb_endpoint_descriptor *desc = dep->endpoint.desc; 272 struct dwc3 *dwc = dep->dwc; 273 u32 timeout = 1000; 274 u32 saved_config = 0; 275 u32 reg; 276 277 int cmd_status = 0; 278 int ret = -EINVAL; 279 280 /* 281 * When operating in USB 2.0 speeds (HS/FS), if GUSB2PHYCFG.ENBLSLPM or 282 * GUSB2PHYCFG.SUSPHY is set, it must be cleared before issuing an 283 * endpoint command. 284 * 285 * Save and clear both GUSB2PHYCFG.ENBLSLPM and GUSB2PHYCFG.SUSPHY 286 * settings. Restore them after the command is completed. 287 * 288 * DWC_usb3 3.30a and DWC_usb31 1.90a programming guide section 3.2.2 289 */ 290 if (dwc->gadget.speed <= USB_SPEED_HIGH) { 291 reg = dwc3_readl(dwc->regs, DWC3_GUSB2PHYCFG(0)); 292 if (unlikely(reg & DWC3_GUSB2PHYCFG_SUSPHY)) { 293 saved_config |= DWC3_GUSB2PHYCFG_SUSPHY; 294 reg &= ~DWC3_GUSB2PHYCFG_SUSPHY; 295 } 296 297 if (reg & DWC3_GUSB2PHYCFG_ENBLSLPM) { 298 saved_config |= DWC3_GUSB2PHYCFG_ENBLSLPM; 299 reg &= ~DWC3_GUSB2PHYCFG_ENBLSLPM; 300 } 301 302 if (saved_config) 303 dwc3_writel(dwc->regs, DWC3_GUSB2PHYCFG(0), reg); 304 } 305 306 if (DWC3_DEPCMD_CMD(cmd) == DWC3_DEPCMD_STARTTRANSFER) { 307 int needs_wakeup; 308 309 needs_wakeup = (dwc->link_state == DWC3_LINK_STATE_U1 || 310 dwc->link_state == DWC3_LINK_STATE_U2 || 311 dwc->link_state == DWC3_LINK_STATE_U3); 312 313 if (unlikely(needs_wakeup)) { 314 ret = __dwc3_gadget_wakeup(dwc); 315 dev_WARN_ONCE(dwc->dev, ret, "wakeup failed --> %d\n", 316 ret); 317 } 318 } 319 320 dwc3_writel(dep->regs, DWC3_DEPCMDPAR0, params->param0); 321 dwc3_writel(dep->regs, DWC3_DEPCMDPAR1, params->param1); 322 dwc3_writel(dep->regs, DWC3_DEPCMDPAR2, params->param2); 323 324 /* 325 * Synopsys Databook 2.60a states in section 6.3.2.5.6 of that if we're 326 * not relying on XferNotReady, we can make use of a special "No 327 * Response Update Transfer" command where we should clear both CmdAct 328 * and CmdIOC bits. 329 * 330 * With this, we don't need to wait for command completion and can 331 * straight away issue further commands to the endpoint. 332 * 333 * NOTICE: We're making an assumption that control endpoints will never 334 * make use of Update Transfer command. This is a safe assumption 335 * because we can never have more than one request at a time with 336 * Control Endpoints. If anybody changes that assumption, this chunk 337 * needs to be updated accordingly. 338 */ 339 if (DWC3_DEPCMD_CMD(cmd) == DWC3_DEPCMD_UPDATETRANSFER && 340 !usb_endpoint_xfer_isoc(desc)) 341 cmd &= ~(DWC3_DEPCMD_CMDIOC | DWC3_DEPCMD_CMDACT); 342 else 343 cmd |= DWC3_DEPCMD_CMDACT; 344 345 dwc3_writel(dep->regs, DWC3_DEPCMD, cmd); 346 do { 347 reg = dwc3_readl(dep->regs, DWC3_DEPCMD); 348 if (!(reg & DWC3_DEPCMD_CMDACT)) { 349 cmd_status = DWC3_DEPCMD_STATUS(reg); 350 351 switch (cmd_status) { 352 case 0: 353 ret = 0; 354 break; 355 case DEPEVT_TRANSFER_NO_RESOURCE: 356 ret = -EINVAL; 357 break; 358 case DEPEVT_TRANSFER_BUS_EXPIRY: 359 /* 360 * SW issues START TRANSFER command to 361 * isochronous ep with future frame interval. If 362 * future interval time has already passed when 363 * core receives the command, it will respond 364 * with an error status of 'Bus Expiry'. 365 * 366 * Instead of always returning -EINVAL, let's 367 * give a hint to the gadget driver that this is 368 * the case by returning -EAGAIN. 369 */ 370 ret = -EAGAIN; 371 break; 372 default: 373 dev_WARN(dwc->dev, "UNKNOWN cmd status\n"); 374 } 375 376 break; 377 } 378 } while (--timeout); 379 380 if (timeout == 0) { 381 ret = -ETIMEDOUT; 382 cmd_status = -ETIMEDOUT; 383 } 384 385 trace_dwc3_gadget_ep_cmd(dep, cmd, params, cmd_status); 386 387 if (ret == 0 && DWC3_DEPCMD_CMD(cmd) == DWC3_DEPCMD_STARTTRANSFER) { 388 dep->flags |= DWC3_EP_TRANSFER_STARTED; 389 dwc3_gadget_ep_get_transfer_index(dep); 390 } 391 392 if (saved_config) { 393 reg = dwc3_readl(dwc->regs, DWC3_GUSB2PHYCFG(0)); 394 reg |= saved_config; 395 dwc3_writel(dwc->regs, DWC3_GUSB2PHYCFG(0), reg); 396 } 397 398 return ret; 399 } 400 401 static int dwc3_send_clear_stall_ep_cmd(struct dwc3_ep *dep) 402 { 403 struct dwc3 *dwc = dep->dwc; 404 struct dwc3_gadget_ep_cmd_params params; 405 u32 cmd = DWC3_DEPCMD_CLEARSTALL; 406 407 /* 408 * As of core revision 2.60a the recommended programming model 409 * is to set the ClearPendIN bit when issuing a Clear Stall EP 410 * command for IN endpoints. This is to prevent an issue where 411 * some (non-compliant) hosts may not send ACK TPs for pending 412 * IN transfers due to a mishandled error condition. Synopsys 413 * STAR 9000614252. 414 */ 415 if (dep->direction && (dwc->revision >= DWC3_REVISION_260A) && 416 (dwc->gadget.speed >= USB_SPEED_SUPER)) 417 cmd |= DWC3_DEPCMD_CLEARPENDIN; 418 419 memset(¶ms, 0, sizeof(params)); 420 421 return dwc3_send_gadget_ep_cmd(dep, cmd, ¶ms); 422 } 423 424 static dma_addr_t dwc3_trb_dma_offset(struct dwc3_ep *dep, 425 struct dwc3_trb *trb) 426 { 427 u32 offset = (char *) trb - (char *) dep->trb_pool; 428 429 return dep->trb_pool_dma + offset; 430 } 431 432 static int dwc3_alloc_trb_pool(struct dwc3_ep *dep) 433 { 434 struct dwc3 *dwc = dep->dwc; 435 436 if (dep->trb_pool) 437 return 0; 438 439 dep->trb_pool = dma_alloc_coherent(dwc->sysdev, 440 sizeof(struct dwc3_trb) * DWC3_TRB_NUM, 441 &dep->trb_pool_dma, GFP_KERNEL); 442 if (!dep->trb_pool) { 443 dev_err(dep->dwc->dev, "failed to allocate trb pool for %s\n", 444 dep->name); 445 return -ENOMEM; 446 } 447 448 return 0; 449 } 450 451 static void dwc3_free_trb_pool(struct dwc3_ep *dep) 452 { 453 struct dwc3 *dwc = dep->dwc; 454 455 dma_free_coherent(dwc->sysdev, sizeof(struct dwc3_trb) * DWC3_TRB_NUM, 456 dep->trb_pool, dep->trb_pool_dma); 457 458 dep->trb_pool = NULL; 459 dep->trb_pool_dma = 0; 460 } 461 462 static int dwc3_gadget_set_xfer_resource(struct dwc3_ep *dep) 463 { 464 struct dwc3_gadget_ep_cmd_params params; 465 466 memset(¶ms, 0x00, sizeof(params)); 467 468 params.param0 = DWC3_DEPXFERCFG_NUM_XFER_RES(1); 469 470 return dwc3_send_gadget_ep_cmd(dep, DWC3_DEPCMD_SETTRANSFRESOURCE, 471 ¶ms); 472 } 473 474 /** 475 * dwc3_gadget_start_config - configure ep resources 476 * @dep: endpoint that is being enabled 477 * 478 * Issue a %DWC3_DEPCMD_DEPSTARTCFG command to @dep. After the command's 479 * completion, it will set Transfer Resource for all available endpoints. 480 * 481 * The assignment of transfer resources cannot perfectly follow the data book 482 * due to the fact that the controller driver does not have all knowledge of the 483 * configuration in advance. It is given this information piecemeal by the 484 * composite gadget framework after every SET_CONFIGURATION and 485 * SET_INTERFACE. Trying to follow the databook programming model in this 486 * scenario can cause errors. For two reasons: 487 * 488 * 1) The databook says to do %DWC3_DEPCMD_DEPSTARTCFG for every 489 * %USB_REQ_SET_CONFIGURATION and %USB_REQ_SET_INTERFACE (8.1.5). This is 490 * incorrect in the scenario of multiple interfaces. 491 * 492 * 2) The databook does not mention doing more %DWC3_DEPCMD_DEPXFERCFG for new 493 * endpoint on alt setting (8.1.6). 494 * 495 * The following simplified method is used instead: 496 * 497 * All hardware endpoints can be assigned a transfer resource and this setting 498 * will stay persistent until either a core reset or hibernation. So whenever we 499 * do a %DWC3_DEPCMD_DEPSTARTCFG(0) we can go ahead and do 500 * %DWC3_DEPCMD_DEPXFERCFG for every hardware endpoint as well. We are 501 * guaranteed that there are as many transfer resources as endpoints. 502 * 503 * This function is called for each endpoint when it is being enabled but is 504 * triggered only when called for EP0-out, which always happens first, and which 505 * should only happen in one of the above conditions. 506 */ 507 static int dwc3_gadget_start_config(struct dwc3_ep *dep) 508 { 509 struct dwc3_gadget_ep_cmd_params params; 510 struct dwc3 *dwc; 511 u32 cmd; 512 int i; 513 int ret; 514 515 if (dep->number) 516 return 0; 517 518 memset(¶ms, 0x00, sizeof(params)); 519 cmd = DWC3_DEPCMD_DEPSTARTCFG; 520 dwc = dep->dwc; 521 522 ret = dwc3_send_gadget_ep_cmd(dep, cmd, ¶ms); 523 if (ret) 524 return ret; 525 526 for (i = 0; i < DWC3_ENDPOINTS_NUM; i++) { 527 struct dwc3_ep *dep = dwc->eps[i]; 528 529 if (!dep) 530 continue; 531 532 ret = dwc3_gadget_set_xfer_resource(dep); 533 if (ret) 534 return ret; 535 } 536 537 return 0; 538 } 539 540 static int dwc3_gadget_set_ep_config(struct dwc3_ep *dep, unsigned int action) 541 { 542 const struct usb_ss_ep_comp_descriptor *comp_desc; 543 const struct usb_endpoint_descriptor *desc; 544 struct dwc3_gadget_ep_cmd_params params; 545 struct dwc3 *dwc = dep->dwc; 546 547 comp_desc = dep->endpoint.comp_desc; 548 desc = dep->endpoint.desc; 549 550 memset(¶ms, 0x00, sizeof(params)); 551 552 params.param0 = DWC3_DEPCFG_EP_TYPE(usb_endpoint_type(desc)) 553 | DWC3_DEPCFG_MAX_PACKET_SIZE(usb_endpoint_maxp(desc)); 554 555 /* Burst size is only needed in SuperSpeed mode */ 556 if (dwc->gadget.speed >= USB_SPEED_SUPER) { 557 u32 burst = dep->endpoint.maxburst; 558 params.param0 |= DWC3_DEPCFG_BURST_SIZE(burst - 1); 559 } 560 561 params.param0 |= action; 562 if (action == DWC3_DEPCFG_ACTION_RESTORE) 563 params.param2 |= dep->saved_state; 564 565 if (usb_endpoint_xfer_control(desc)) 566 params.param1 = DWC3_DEPCFG_XFER_COMPLETE_EN; 567 568 if (dep->number <= 1 || usb_endpoint_xfer_isoc(desc)) 569 params.param1 |= DWC3_DEPCFG_XFER_NOT_READY_EN; 570 571 if (usb_ss_max_streams(comp_desc) && usb_endpoint_xfer_bulk(desc)) { 572 params.param1 |= DWC3_DEPCFG_STREAM_CAPABLE 573 | DWC3_DEPCFG_STREAM_EVENT_EN; 574 dep->stream_capable = true; 575 } 576 577 if (!usb_endpoint_xfer_control(desc)) 578 params.param1 |= DWC3_DEPCFG_XFER_IN_PROGRESS_EN; 579 580 /* 581 * We are doing 1:1 mapping for endpoints, meaning 582 * Physical Endpoints 2 maps to Logical Endpoint 2 and 583 * so on. We consider the direction bit as part of the physical 584 * endpoint number. So USB endpoint 0x81 is 0x03. 585 */ 586 params.param1 |= DWC3_DEPCFG_EP_NUMBER(dep->number); 587 588 /* 589 * We must use the lower 16 TX FIFOs even though 590 * HW might have more 591 */ 592 if (dep->direction) 593 params.param0 |= DWC3_DEPCFG_FIFO_NUMBER(dep->number >> 1); 594 595 if (desc->bInterval) { 596 params.param1 |= DWC3_DEPCFG_BINTERVAL_M1(desc->bInterval - 1); 597 dep->interval = 1 << (desc->bInterval - 1); 598 } 599 600 return dwc3_send_gadget_ep_cmd(dep, DWC3_DEPCMD_SETEPCONFIG, ¶ms); 601 } 602 603 /** 604 * __dwc3_gadget_ep_enable - initializes a hw endpoint 605 * @dep: endpoint to be initialized 606 * @action: one of INIT, MODIFY or RESTORE 607 * 608 * Caller should take care of locking. Execute all necessary commands to 609 * initialize a HW endpoint so it can be used by a gadget driver. 610 */ 611 static int __dwc3_gadget_ep_enable(struct dwc3_ep *dep, unsigned int action) 612 { 613 const struct usb_endpoint_descriptor *desc = dep->endpoint.desc; 614 struct dwc3 *dwc = dep->dwc; 615 616 u32 reg; 617 int ret; 618 619 if (!(dep->flags & DWC3_EP_ENABLED)) { 620 ret = dwc3_gadget_start_config(dep); 621 if (ret) 622 return ret; 623 } 624 625 ret = dwc3_gadget_set_ep_config(dep, action); 626 if (ret) 627 return ret; 628 629 if (!(dep->flags & DWC3_EP_ENABLED)) { 630 struct dwc3_trb *trb_st_hw; 631 struct dwc3_trb *trb_link; 632 633 dep->type = usb_endpoint_type(desc); 634 dep->flags |= DWC3_EP_ENABLED; 635 636 reg = dwc3_readl(dwc->regs, DWC3_DALEPENA); 637 reg |= DWC3_DALEPENA_EP(dep->number); 638 dwc3_writel(dwc->regs, DWC3_DALEPENA, reg); 639 640 if (usb_endpoint_xfer_control(desc)) 641 goto out; 642 643 /* Initialize the TRB ring */ 644 dep->trb_dequeue = 0; 645 dep->trb_enqueue = 0; 646 memset(dep->trb_pool, 0, 647 sizeof(struct dwc3_trb) * DWC3_TRB_NUM); 648 649 /* Link TRB. The HWO bit is never reset */ 650 trb_st_hw = &dep->trb_pool[0]; 651 652 trb_link = &dep->trb_pool[DWC3_TRB_NUM - 1]; 653 trb_link->bpl = lower_32_bits(dwc3_trb_dma_offset(dep, trb_st_hw)); 654 trb_link->bph = upper_32_bits(dwc3_trb_dma_offset(dep, trb_st_hw)); 655 trb_link->ctrl |= DWC3_TRBCTL_LINK_TRB; 656 trb_link->ctrl |= DWC3_TRB_CTRL_HWO; 657 } 658 659 /* 660 * Issue StartTransfer here with no-op TRB so we can always rely on No 661 * Response Update Transfer command. 662 */ 663 if ((usb_endpoint_xfer_bulk(desc) && !dep->stream_capable) || 664 usb_endpoint_xfer_int(desc)) { 665 struct dwc3_gadget_ep_cmd_params params; 666 struct dwc3_trb *trb; 667 dma_addr_t trb_dma; 668 u32 cmd; 669 670 memset(¶ms, 0, sizeof(params)); 671 trb = &dep->trb_pool[0]; 672 trb_dma = dwc3_trb_dma_offset(dep, trb); 673 674 params.param0 = upper_32_bits(trb_dma); 675 params.param1 = lower_32_bits(trb_dma); 676 677 cmd = DWC3_DEPCMD_STARTTRANSFER; 678 679 ret = dwc3_send_gadget_ep_cmd(dep, cmd, ¶ms); 680 if (ret < 0) 681 return ret; 682 } 683 684 out: 685 trace_dwc3_gadget_ep_enable(dep); 686 687 return 0; 688 } 689 690 static void dwc3_stop_active_transfer(struct dwc3_ep *dep, bool force, 691 bool interrupt); 692 static void dwc3_remove_requests(struct dwc3 *dwc, struct dwc3_ep *dep) 693 { 694 struct dwc3_request *req; 695 696 dwc3_stop_active_transfer(dep, true, false); 697 698 /* - giveback all requests to gadget driver */ 699 while (!list_empty(&dep->started_list)) { 700 req = next_request(&dep->started_list); 701 702 dwc3_gadget_giveback(dep, req, -ESHUTDOWN); 703 } 704 705 while (!list_empty(&dep->pending_list)) { 706 req = next_request(&dep->pending_list); 707 708 dwc3_gadget_giveback(dep, req, -ESHUTDOWN); 709 } 710 } 711 712 /** 713 * __dwc3_gadget_ep_disable - disables a hw endpoint 714 * @dep: the endpoint to disable 715 * 716 * This function undoes what __dwc3_gadget_ep_enable did and also removes 717 * requests which are currently being processed by the hardware and those which 718 * are not yet scheduled. 719 * 720 * Caller should take care of locking. 721 */ 722 static int __dwc3_gadget_ep_disable(struct dwc3_ep *dep) 723 { 724 struct dwc3 *dwc = dep->dwc; 725 u32 reg; 726 727 trace_dwc3_gadget_ep_disable(dep); 728 729 dwc3_remove_requests(dwc, dep); 730 731 /* make sure HW endpoint isn't stalled */ 732 if (dep->flags & DWC3_EP_STALL) 733 __dwc3_gadget_ep_set_halt(dep, 0, false); 734 735 reg = dwc3_readl(dwc->regs, DWC3_DALEPENA); 736 reg &= ~DWC3_DALEPENA_EP(dep->number); 737 dwc3_writel(dwc->regs, DWC3_DALEPENA, reg); 738 739 dep->stream_capable = false; 740 dep->type = 0; 741 dep->flags = 0; 742 743 /* Clear out the ep descriptors for non-ep0 */ 744 if (dep->number > 1) { 745 dep->endpoint.comp_desc = NULL; 746 dep->endpoint.desc = NULL; 747 } 748 749 return 0; 750 } 751 752 /* -------------------------------------------------------------------------- */ 753 754 static int dwc3_gadget_ep0_enable(struct usb_ep *ep, 755 const struct usb_endpoint_descriptor *desc) 756 { 757 return -EINVAL; 758 } 759 760 static int dwc3_gadget_ep0_disable(struct usb_ep *ep) 761 { 762 return -EINVAL; 763 } 764 765 /* -------------------------------------------------------------------------- */ 766 767 static int dwc3_gadget_ep_enable(struct usb_ep *ep, 768 const struct usb_endpoint_descriptor *desc) 769 { 770 struct dwc3_ep *dep; 771 struct dwc3 *dwc; 772 unsigned long flags; 773 int ret; 774 775 if (!ep || !desc || desc->bDescriptorType != USB_DT_ENDPOINT) { 776 pr_debug("dwc3: invalid parameters\n"); 777 return -EINVAL; 778 } 779 780 if (!desc->wMaxPacketSize) { 781 pr_debug("dwc3: missing wMaxPacketSize\n"); 782 return -EINVAL; 783 } 784 785 dep = to_dwc3_ep(ep); 786 dwc = dep->dwc; 787 788 if (dev_WARN_ONCE(dwc->dev, dep->flags & DWC3_EP_ENABLED, 789 "%s is already enabled\n", 790 dep->name)) 791 return 0; 792 793 spin_lock_irqsave(&dwc->lock, flags); 794 ret = __dwc3_gadget_ep_enable(dep, DWC3_DEPCFG_ACTION_INIT); 795 spin_unlock_irqrestore(&dwc->lock, flags); 796 797 return ret; 798 } 799 800 static int dwc3_gadget_ep_disable(struct usb_ep *ep) 801 { 802 struct dwc3_ep *dep; 803 struct dwc3 *dwc; 804 unsigned long flags; 805 int ret; 806 807 if (!ep) { 808 pr_debug("dwc3: invalid parameters\n"); 809 return -EINVAL; 810 } 811 812 dep = to_dwc3_ep(ep); 813 dwc = dep->dwc; 814 815 if (dev_WARN_ONCE(dwc->dev, !(dep->flags & DWC3_EP_ENABLED), 816 "%s is already disabled\n", 817 dep->name)) 818 return 0; 819 820 spin_lock_irqsave(&dwc->lock, flags); 821 ret = __dwc3_gadget_ep_disable(dep); 822 spin_unlock_irqrestore(&dwc->lock, flags); 823 824 return ret; 825 } 826 827 static struct usb_request *dwc3_gadget_ep_alloc_request(struct usb_ep *ep, 828 gfp_t gfp_flags) 829 { 830 struct dwc3_request *req; 831 struct dwc3_ep *dep = to_dwc3_ep(ep); 832 833 req = kzalloc(sizeof(*req), gfp_flags); 834 if (!req) 835 return NULL; 836 837 req->direction = dep->direction; 838 req->epnum = dep->number; 839 req->dep = dep; 840 req->status = DWC3_REQUEST_STATUS_UNKNOWN; 841 842 trace_dwc3_alloc_request(req); 843 844 return &req->request; 845 } 846 847 static void dwc3_gadget_ep_free_request(struct usb_ep *ep, 848 struct usb_request *request) 849 { 850 struct dwc3_request *req = to_dwc3_request(request); 851 852 trace_dwc3_free_request(req); 853 kfree(req); 854 } 855 856 /** 857 * dwc3_ep_prev_trb - returns the previous TRB in the ring 858 * @dep: The endpoint with the TRB ring 859 * @index: The index of the current TRB in the ring 860 * 861 * Returns the TRB prior to the one pointed to by the index. If the 862 * index is 0, we will wrap backwards, skip the link TRB, and return 863 * the one just before that. 864 */ 865 static struct dwc3_trb *dwc3_ep_prev_trb(struct dwc3_ep *dep, u8 index) 866 { 867 u8 tmp = index; 868 869 if (!tmp) 870 tmp = DWC3_TRB_NUM - 1; 871 872 return &dep->trb_pool[tmp - 1]; 873 } 874 875 static u32 dwc3_calc_trbs_left(struct dwc3_ep *dep) 876 { 877 struct dwc3_trb *tmp; 878 u8 trbs_left; 879 880 /* 881 * If enqueue & dequeue are equal than it is either full or empty. 882 * 883 * One way to know for sure is if the TRB right before us has HWO bit 884 * set or not. If it has, then we're definitely full and can't fit any 885 * more transfers in our ring. 886 */ 887 if (dep->trb_enqueue == dep->trb_dequeue) { 888 tmp = dwc3_ep_prev_trb(dep, dep->trb_enqueue); 889 if (tmp->ctrl & DWC3_TRB_CTRL_HWO) 890 return 0; 891 892 return DWC3_TRB_NUM - 1; 893 } 894 895 trbs_left = dep->trb_dequeue - dep->trb_enqueue; 896 trbs_left &= (DWC3_TRB_NUM - 1); 897 898 if (dep->trb_dequeue < dep->trb_enqueue) 899 trbs_left--; 900 901 return trbs_left; 902 } 903 904 static void __dwc3_prepare_one_trb(struct dwc3_ep *dep, struct dwc3_trb *trb, 905 dma_addr_t dma, unsigned length, unsigned chain, unsigned node, 906 unsigned stream_id, unsigned short_not_ok, unsigned no_interrupt) 907 { 908 struct dwc3 *dwc = dep->dwc; 909 struct usb_gadget *gadget = &dwc->gadget; 910 enum usb_device_speed speed = gadget->speed; 911 912 trb->size = DWC3_TRB_SIZE_LENGTH(length); 913 trb->bpl = lower_32_bits(dma); 914 trb->bph = upper_32_bits(dma); 915 916 switch (usb_endpoint_type(dep->endpoint.desc)) { 917 case USB_ENDPOINT_XFER_CONTROL: 918 trb->ctrl = DWC3_TRBCTL_CONTROL_SETUP; 919 break; 920 921 case USB_ENDPOINT_XFER_ISOC: 922 if (!node) { 923 trb->ctrl = DWC3_TRBCTL_ISOCHRONOUS_FIRST; 924 925 /* 926 * USB Specification 2.0 Section 5.9.2 states that: "If 927 * there is only a single transaction in the microframe, 928 * only a DATA0 data packet PID is used. If there are 929 * two transactions per microframe, DATA1 is used for 930 * the first transaction data packet and DATA0 is used 931 * for the second transaction data packet. If there are 932 * three transactions per microframe, DATA2 is used for 933 * the first transaction data packet, DATA1 is used for 934 * the second, and DATA0 is used for the third." 935 * 936 * IOW, we should satisfy the following cases: 937 * 938 * 1) length <= maxpacket 939 * - DATA0 940 * 941 * 2) maxpacket < length <= (2 * maxpacket) 942 * - DATA1, DATA0 943 * 944 * 3) (2 * maxpacket) < length <= (3 * maxpacket) 945 * - DATA2, DATA1, DATA0 946 */ 947 if (speed == USB_SPEED_HIGH) { 948 struct usb_ep *ep = &dep->endpoint; 949 unsigned int mult = 2; 950 unsigned int maxp = usb_endpoint_maxp(ep->desc); 951 952 if (length <= (2 * maxp)) 953 mult--; 954 955 if (length <= maxp) 956 mult--; 957 958 trb->size |= DWC3_TRB_SIZE_PCM1(mult); 959 } 960 } else { 961 trb->ctrl = DWC3_TRBCTL_ISOCHRONOUS; 962 } 963 964 /* always enable Interrupt on Missed ISOC */ 965 trb->ctrl |= DWC3_TRB_CTRL_ISP_IMI; 966 break; 967 968 case USB_ENDPOINT_XFER_BULK: 969 case USB_ENDPOINT_XFER_INT: 970 trb->ctrl = DWC3_TRBCTL_NORMAL; 971 break; 972 default: 973 /* 974 * This is only possible with faulty memory because we 975 * checked it already :) 976 */ 977 dev_WARN(dwc->dev, "Unknown endpoint type %d\n", 978 usb_endpoint_type(dep->endpoint.desc)); 979 } 980 981 /* 982 * Enable Continue on Short Packet 983 * when endpoint is not a stream capable 984 */ 985 if (usb_endpoint_dir_out(dep->endpoint.desc)) { 986 if (!dep->stream_capable) 987 trb->ctrl |= DWC3_TRB_CTRL_CSP; 988 989 if (short_not_ok) 990 trb->ctrl |= DWC3_TRB_CTRL_ISP_IMI; 991 } 992 993 if ((!no_interrupt && !chain) || 994 (dwc3_calc_trbs_left(dep) == 1)) 995 trb->ctrl |= DWC3_TRB_CTRL_IOC; 996 997 if (chain) 998 trb->ctrl |= DWC3_TRB_CTRL_CHN; 999 1000 if (usb_endpoint_xfer_bulk(dep->endpoint.desc) && dep->stream_capable) 1001 trb->ctrl |= DWC3_TRB_CTRL_SID_SOFN(stream_id); 1002 1003 trb->ctrl |= DWC3_TRB_CTRL_HWO; 1004 1005 dwc3_ep_inc_enq(dep); 1006 1007 trace_dwc3_prepare_trb(dep, trb); 1008 } 1009 1010 /** 1011 * dwc3_prepare_one_trb - setup one TRB from one request 1012 * @dep: endpoint for which this request is prepared 1013 * @req: dwc3_request pointer 1014 * @chain: should this TRB be chained to the next? 1015 * @node: only for isochronous endpoints. First TRB needs different type. 1016 */ 1017 static void dwc3_prepare_one_trb(struct dwc3_ep *dep, 1018 struct dwc3_request *req, unsigned chain, unsigned node) 1019 { 1020 struct dwc3_trb *trb; 1021 unsigned int length; 1022 dma_addr_t dma; 1023 unsigned stream_id = req->request.stream_id; 1024 unsigned short_not_ok = req->request.short_not_ok; 1025 unsigned no_interrupt = req->request.no_interrupt; 1026 1027 if (req->request.num_sgs > 0) { 1028 length = sg_dma_len(req->start_sg); 1029 dma = sg_dma_address(req->start_sg); 1030 } else { 1031 length = req->request.length; 1032 dma = req->request.dma; 1033 } 1034 1035 trb = &dep->trb_pool[dep->trb_enqueue]; 1036 1037 if (!req->trb) { 1038 dwc3_gadget_move_started_request(req); 1039 req->trb = trb; 1040 req->trb_dma = dwc3_trb_dma_offset(dep, trb); 1041 } 1042 1043 req->num_trbs++; 1044 1045 __dwc3_prepare_one_trb(dep, trb, dma, length, chain, node, 1046 stream_id, short_not_ok, no_interrupt); 1047 } 1048 1049 static void dwc3_prepare_one_trb_sg(struct dwc3_ep *dep, 1050 struct dwc3_request *req) 1051 { 1052 struct scatterlist *sg = req->start_sg; 1053 struct scatterlist *s; 1054 int i; 1055 1056 unsigned int remaining = req->request.num_mapped_sgs 1057 - req->num_queued_sgs; 1058 1059 for_each_sg(sg, s, remaining, i) { 1060 unsigned int length = req->request.length; 1061 unsigned int maxp = usb_endpoint_maxp(dep->endpoint.desc); 1062 unsigned int rem = length % maxp; 1063 unsigned chain = true; 1064 1065 if (sg_is_last(s)) 1066 chain = false; 1067 1068 if (rem && usb_endpoint_dir_out(dep->endpoint.desc) && !chain) { 1069 struct dwc3 *dwc = dep->dwc; 1070 struct dwc3_trb *trb; 1071 1072 req->needs_extra_trb = true; 1073 1074 /* prepare normal TRB */ 1075 dwc3_prepare_one_trb(dep, req, true, i); 1076 1077 /* Now prepare one extra TRB to align transfer size */ 1078 trb = &dep->trb_pool[dep->trb_enqueue]; 1079 req->num_trbs++; 1080 __dwc3_prepare_one_trb(dep, trb, dwc->bounce_addr, 1081 maxp - rem, false, 1, 1082 req->request.stream_id, 1083 req->request.short_not_ok, 1084 req->request.no_interrupt); 1085 } else { 1086 dwc3_prepare_one_trb(dep, req, chain, i); 1087 } 1088 1089 /* 1090 * There can be a situation where all sgs in sglist are not 1091 * queued because of insufficient trb number. To handle this 1092 * case, update start_sg to next sg to be queued, so that 1093 * we have free trbs we can continue queuing from where we 1094 * previously stopped 1095 */ 1096 if (chain) 1097 req->start_sg = sg_next(s); 1098 1099 req->num_queued_sgs++; 1100 1101 if (!dwc3_calc_trbs_left(dep)) 1102 break; 1103 } 1104 } 1105 1106 static void dwc3_prepare_one_trb_linear(struct dwc3_ep *dep, 1107 struct dwc3_request *req) 1108 { 1109 unsigned int length = req->request.length; 1110 unsigned int maxp = usb_endpoint_maxp(dep->endpoint.desc); 1111 unsigned int rem = length % maxp; 1112 1113 if ((!length || rem) && usb_endpoint_dir_out(dep->endpoint.desc)) { 1114 struct dwc3 *dwc = dep->dwc; 1115 struct dwc3_trb *trb; 1116 1117 req->needs_extra_trb = true; 1118 1119 /* prepare normal TRB */ 1120 dwc3_prepare_one_trb(dep, req, true, 0); 1121 1122 /* Now prepare one extra TRB to align transfer size */ 1123 trb = &dep->trb_pool[dep->trb_enqueue]; 1124 req->num_trbs++; 1125 __dwc3_prepare_one_trb(dep, trb, dwc->bounce_addr, maxp - rem, 1126 false, 1, req->request.stream_id, 1127 req->request.short_not_ok, 1128 req->request.no_interrupt); 1129 } else if (req->request.zero && req->request.length && 1130 (IS_ALIGNED(req->request.length, maxp))) { 1131 struct dwc3 *dwc = dep->dwc; 1132 struct dwc3_trb *trb; 1133 1134 req->needs_extra_trb = true; 1135 1136 /* prepare normal TRB */ 1137 dwc3_prepare_one_trb(dep, req, true, 0); 1138 1139 /* Now prepare one extra TRB to handle ZLP */ 1140 trb = &dep->trb_pool[dep->trb_enqueue]; 1141 req->num_trbs++; 1142 __dwc3_prepare_one_trb(dep, trb, dwc->bounce_addr, 0, 1143 false, 1, req->request.stream_id, 1144 req->request.short_not_ok, 1145 req->request.no_interrupt); 1146 } else { 1147 dwc3_prepare_one_trb(dep, req, false, 0); 1148 } 1149 } 1150 1151 /* 1152 * dwc3_prepare_trbs - setup TRBs from requests 1153 * @dep: endpoint for which requests are being prepared 1154 * 1155 * The function goes through the requests list and sets up TRBs for the 1156 * transfers. The function returns once there are no more TRBs available or 1157 * it runs out of requests. 1158 */ 1159 static void dwc3_prepare_trbs(struct dwc3_ep *dep) 1160 { 1161 struct dwc3_request *req, *n; 1162 1163 BUILD_BUG_ON_NOT_POWER_OF_2(DWC3_TRB_NUM); 1164 1165 /* 1166 * We can get in a situation where there's a request in the started list 1167 * but there weren't enough TRBs to fully kick it in the first time 1168 * around, so it has been waiting for more TRBs to be freed up. 1169 * 1170 * In that case, we should check if we have a request with pending_sgs 1171 * in the started list and prepare TRBs for that request first, 1172 * otherwise we will prepare TRBs completely out of order and that will 1173 * break things. 1174 */ 1175 list_for_each_entry(req, &dep->started_list, list) { 1176 if (req->num_pending_sgs > 0) 1177 dwc3_prepare_one_trb_sg(dep, req); 1178 1179 if (!dwc3_calc_trbs_left(dep)) 1180 return; 1181 } 1182 1183 list_for_each_entry_safe(req, n, &dep->pending_list, list) { 1184 struct dwc3 *dwc = dep->dwc; 1185 int ret; 1186 1187 ret = usb_gadget_map_request_by_dev(dwc->sysdev, &req->request, 1188 dep->direction); 1189 if (ret) 1190 return; 1191 1192 req->sg = req->request.sg; 1193 req->start_sg = req->sg; 1194 req->num_queued_sgs = 0; 1195 req->num_pending_sgs = req->request.num_mapped_sgs; 1196 1197 if (req->num_pending_sgs > 0) 1198 dwc3_prepare_one_trb_sg(dep, req); 1199 else 1200 dwc3_prepare_one_trb_linear(dep, req); 1201 1202 if (!dwc3_calc_trbs_left(dep)) 1203 return; 1204 } 1205 } 1206 1207 static int __dwc3_gadget_kick_transfer(struct dwc3_ep *dep) 1208 { 1209 struct dwc3_gadget_ep_cmd_params params; 1210 struct dwc3_request *req; 1211 int starting; 1212 int ret; 1213 u32 cmd; 1214 1215 if (!dwc3_calc_trbs_left(dep)) 1216 return 0; 1217 1218 starting = !(dep->flags & DWC3_EP_TRANSFER_STARTED); 1219 1220 dwc3_prepare_trbs(dep); 1221 req = next_request(&dep->started_list); 1222 if (!req) { 1223 dep->flags |= DWC3_EP_PENDING_REQUEST; 1224 return 0; 1225 } 1226 1227 memset(¶ms, 0, sizeof(params)); 1228 1229 if (starting) { 1230 params.param0 = upper_32_bits(req->trb_dma); 1231 params.param1 = lower_32_bits(req->trb_dma); 1232 cmd = DWC3_DEPCMD_STARTTRANSFER; 1233 1234 if (dep->stream_capable) 1235 cmd |= DWC3_DEPCMD_PARAM(req->request.stream_id); 1236 1237 if (usb_endpoint_xfer_isoc(dep->endpoint.desc)) 1238 cmd |= DWC3_DEPCMD_PARAM(dep->frame_number); 1239 } else { 1240 cmd = DWC3_DEPCMD_UPDATETRANSFER | 1241 DWC3_DEPCMD_PARAM(dep->resource_index); 1242 } 1243 1244 ret = dwc3_send_gadget_ep_cmd(dep, cmd, ¶ms); 1245 if (ret < 0) { 1246 /* 1247 * FIXME we need to iterate over the list of requests 1248 * here and stop, unmap, free and del each of the linked 1249 * requests instead of what we do now. 1250 */ 1251 if (req->trb) 1252 memset(req->trb, 0, sizeof(struct dwc3_trb)); 1253 dwc3_gadget_del_and_unmap_request(dep, req, ret); 1254 return ret; 1255 } 1256 1257 return 0; 1258 } 1259 1260 static int __dwc3_gadget_get_frame(struct dwc3 *dwc) 1261 { 1262 u32 reg; 1263 1264 reg = dwc3_readl(dwc->regs, DWC3_DSTS); 1265 return DWC3_DSTS_SOFFN(reg); 1266 } 1267 1268 /** 1269 * dwc3_gadget_start_isoc_quirk - workaround invalid frame number 1270 * @dep: isoc endpoint 1271 * 1272 * This function tests for the correct combination of BIT[15:14] from the 16-bit 1273 * microframe number reported by the XferNotReady event for the future frame 1274 * number to start the isoc transfer. 1275 * 1276 * In DWC_usb31 version 1.70a-ea06 and prior, for highspeed and fullspeed 1277 * isochronous IN, BIT[15:14] of the 16-bit microframe number reported by the 1278 * XferNotReady event are invalid. The driver uses this number to schedule the 1279 * isochronous transfer and passes it to the START TRANSFER command. Because 1280 * this number is invalid, the command may fail. If BIT[15:14] matches the 1281 * internal 16-bit microframe, the START TRANSFER command will pass and the 1282 * transfer will start at the scheduled time, if it is off by 1, the command 1283 * will still pass, but the transfer will start 2 seconds in the future. For all 1284 * other conditions, the START TRANSFER command will fail with bus-expiry. 1285 * 1286 * In order to workaround this issue, we can test for the correct combination of 1287 * BIT[15:14] by sending START TRANSFER commands with different values of 1288 * BIT[15:14]: 'b00, 'b01, 'b10, and 'b11. Each combination is 2^14 uframe apart 1289 * (or 2 seconds). 4 seconds into the future will result in a bus-expiry status. 1290 * As the result, within the 4 possible combinations for BIT[15:14], there will 1291 * be 2 successful and 2 failure START COMMAND status. One of the 2 successful 1292 * command status will result in a 2-second delay start. The smaller BIT[15:14] 1293 * value is the correct combination. 1294 * 1295 * Since there are only 4 outcomes and the results are ordered, we can simply 1296 * test 2 START TRANSFER commands with BIT[15:14] combinations 'b00 and 'b01 to 1297 * deduce the smaller successful combination. 1298 * 1299 * Let test0 = test status for combination 'b00 and test1 = test status for 'b01 1300 * of BIT[15:14]. The correct combination is as follow: 1301 * 1302 * if test0 fails and test1 passes, BIT[15:14] is 'b01 1303 * if test0 fails and test1 fails, BIT[15:14] is 'b10 1304 * if test0 passes and test1 fails, BIT[15:14] is 'b11 1305 * if test0 passes and test1 passes, BIT[15:14] is 'b00 1306 * 1307 * Synopsys STAR 9001202023: Wrong microframe number for isochronous IN 1308 * endpoints. 1309 */ 1310 static int dwc3_gadget_start_isoc_quirk(struct dwc3_ep *dep) 1311 { 1312 int cmd_status = 0; 1313 bool test0; 1314 bool test1; 1315 1316 while (dep->combo_num < 2) { 1317 struct dwc3_gadget_ep_cmd_params params; 1318 u32 test_frame_number; 1319 u32 cmd; 1320 1321 /* 1322 * Check if we can start isoc transfer on the next interval or 1323 * 4 uframes in the future with BIT[15:14] as dep->combo_num 1324 */ 1325 test_frame_number = dep->frame_number & 0x3fff; 1326 test_frame_number |= dep->combo_num << 14; 1327 test_frame_number += max_t(u32, 4, dep->interval); 1328 1329 params.param0 = upper_32_bits(dep->dwc->bounce_addr); 1330 params.param1 = lower_32_bits(dep->dwc->bounce_addr); 1331 1332 cmd = DWC3_DEPCMD_STARTTRANSFER; 1333 cmd |= DWC3_DEPCMD_PARAM(test_frame_number); 1334 cmd_status = dwc3_send_gadget_ep_cmd(dep, cmd, ¶ms); 1335 1336 /* Redo if some other failure beside bus-expiry is received */ 1337 if (cmd_status && cmd_status != -EAGAIN) { 1338 dep->start_cmd_status = 0; 1339 dep->combo_num = 0; 1340 return 0; 1341 } 1342 1343 /* Store the first test status */ 1344 if (dep->combo_num == 0) 1345 dep->start_cmd_status = cmd_status; 1346 1347 dep->combo_num++; 1348 1349 /* 1350 * End the transfer if the START_TRANSFER command is successful 1351 * to wait for the next XferNotReady to test the command again 1352 */ 1353 if (cmd_status == 0) { 1354 dwc3_stop_active_transfer(dep, true, true); 1355 return 0; 1356 } 1357 } 1358 1359 /* test0 and test1 are both completed at this point */ 1360 test0 = (dep->start_cmd_status == 0); 1361 test1 = (cmd_status == 0); 1362 1363 if (!test0 && test1) 1364 dep->combo_num = 1; 1365 else if (!test0 && !test1) 1366 dep->combo_num = 2; 1367 else if (test0 && !test1) 1368 dep->combo_num = 3; 1369 else if (test0 && test1) 1370 dep->combo_num = 0; 1371 1372 dep->frame_number &= 0x3fff; 1373 dep->frame_number |= dep->combo_num << 14; 1374 dep->frame_number += max_t(u32, 4, dep->interval); 1375 1376 /* Reinitialize test variables */ 1377 dep->start_cmd_status = 0; 1378 dep->combo_num = 0; 1379 1380 return __dwc3_gadget_kick_transfer(dep); 1381 } 1382 1383 static int __dwc3_gadget_start_isoc(struct dwc3_ep *dep) 1384 { 1385 struct dwc3 *dwc = dep->dwc; 1386 int ret; 1387 int i; 1388 1389 if (list_empty(&dep->pending_list)) { 1390 dep->flags |= DWC3_EP_PENDING_REQUEST; 1391 return -EAGAIN; 1392 } 1393 1394 if (!dwc->dis_start_transfer_quirk && dwc3_is_usb31(dwc) && 1395 (dwc->revision <= DWC3_USB31_REVISION_160A || 1396 (dwc->revision == DWC3_USB31_REVISION_170A && 1397 dwc->version_type >= DWC31_VERSIONTYPE_EA01 && 1398 dwc->version_type <= DWC31_VERSIONTYPE_EA06))) { 1399 1400 if (dwc->gadget.speed <= USB_SPEED_HIGH && dep->direction) 1401 return dwc3_gadget_start_isoc_quirk(dep); 1402 } 1403 1404 for (i = 0; i < DWC3_ISOC_MAX_RETRIES; i++) { 1405 dep->frame_number = DWC3_ALIGN_FRAME(dep, i + 1); 1406 1407 ret = __dwc3_gadget_kick_transfer(dep); 1408 if (ret != -EAGAIN) 1409 break; 1410 } 1411 1412 return ret; 1413 } 1414 1415 static int __dwc3_gadget_ep_queue(struct dwc3_ep *dep, struct dwc3_request *req) 1416 { 1417 struct dwc3 *dwc = dep->dwc; 1418 1419 if (!dep->endpoint.desc) { 1420 dev_err(dwc->dev, "%s: can't queue to disabled endpoint\n", 1421 dep->name); 1422 return -ESHUTDOWN; 1423 } 1424 1425 if (WARN(req->dep != dep, "request %pK belongs to '%s'\n", 1426 &req->request, req->dep->name)) 1427 return -EINVAL; 1428 1429 if (WARN(req->status < DWC3_REQUEST_STATUS_COMPLETED, 1430 "%s: request %pK already in flight\n", 1431 dep->name, &req->request)) 1432 return -EINVAL; 1433 1434 pm_runtime_get(dwc->dev); 1435 1436 req->request.actual = 0; 1437 req->request.status = -EINPROGRESS; 1438 1439 trace_dwc3_ep_queue(req); 1440 1441 list_add_tail(&req->list, &dep->pending_list); 1442 req->status = DWC3_REQUEST_STATUS_QUEUED; 1443 1444 /* 1445 * NOTICE: Isochronous endpoints should NEVER be prestarted. We must 1446 * wait for a XferNotReady event so we will know what's the current 1447 * (micro-)frame number. 1448 * 1449 * Without this trick, we are very, very likely gonna get Bus Expiry 1450 * errors which will force us issue EndTransfer command. 1451 */ 1452 if (usb_endpoint_xfer_isoc(dep->endpoint.desc)) { 1453 if (!(dep->flags & DWC3_EP_PENDING_REQUEST) && 1454 !(dep->flags & DWC3_EP_TRANSFER_STARTED)) 1455 return 0; 1456 1457 if ((dep->flags & DWC3_EP_PENDING_REQUEST)) { 1458 if (!(dep->flags & DWC3_EP_TRANSFER_STARTED)) { 1459 return __dwc3_gadget_start_isoc(dep); 1460 } 1461 } 1462 } 1463 1464 return __dwc3_gadget_kick_transfer(dep); 1465 } 1466 1467 static int dwc3_gadget_ep_queue(struct usb_ep *ep, struct usb_request *request, 1468 gfp_t gfp_flags) 1469 { 1470 struct dwc3_request *req = to_dwc3_request(request); 1471 struct dwc3_ep *dep = to_dwc3_ep(ep); 1472 struct dwc3 *dwc = dep->dwc; 1473 1474 unsigned long flags; 1475 1476 int ret; 1477 1478 spin_lock_irqsave(&dwc->lock, flags); 1479 ret = __dwc3_gadget_ep_queue(dep, req); 1480 spin_unlock_irqrestore(&dwc->lock, flags); 1481 1482 return ret; 1483 } 1484 1485 static void dwc3_gadget_ep_skip_trbs(struct dwc3_ep *dep, struct dwc3_request *req) 1486 { 1487 int i; 1488 1489 /* 1490 * If request was already started, this means we had to 1491 * stop the transfer. With that we also need to ignore 1492 * all TRBs used by the request, however TRBs can only 1493 * be modified after completion of END_TRANSFER 1494 * command. So what we do here is that we wait for 1495 * END_TRANSFER completion and only after that, we jump 1496 * over TRBs by clearing HWO and incrementing dequeue 1497 * pointer. 1498 */ 1499 for (i = 0; i < req->num_trbs; i++) { 1500 struct dwc3_trb *trb; 1501 1502 trb = req->trb + i; 1503 trb->ctrl &= ~DWC3_TRB_CTRL_HWO; 1504 dwc3_ep_inc_deq(dep); 1505 } 1506 1507 req->num_trbs = 0; 1508 } 1509 1510 static void dwc3_gadget_ep_cleanup_cancelled_requests(struct dwc3_ep *dep) 1511 { 1512 struct dwc3_request *req; 1513 struct dwc3_request *tmp; 1514 1515 list_for_each_entry_safe(req, tmp, &dep->cancelled_list, list) { 1516 dwc3_gadget_ep_skip_trbs(dep, req); 1517 dwc3_gadget_giveback(dep, req, -ECONNRESET); 1518 } 1519 } 1520 1521 static int dwc3_gadget_ep_dequeue(struct usb_ep *ep, 1522 struct usb_request *request) 1523 { 1524 struct dwc3_request *req = to_dwc3_request(request); 1525 struct dwc3_request *r = NULL; 1526 1527 struct dwc3_ep *dep = to_dwc3_ep(ep); 1528 struct dwc3 *dwc = dep->dwc; 1529 1530 unsigned long flags; 1531 int ret = 0; 1532 1533 trace_dwc3_ep_dequeue(req); 1534 1535 spin_lock_irqsave(&dwc->lock, flags); 1536 1537 list_for_each_entry(r, &dep->pending_list, list) { 1538 if (r == req) 1539 break; 1540 } 1541 1542 if (r != req) { 1543 list_for_each_entry(r, &dep->started_list, list) { 1544 if (r == req) 1545 break; 1546 } 1547 if (r == req) { 1548 /* wait until it is processed */ 1549 dwc3_stop_active_transfer(dep, true, true); 1550 1551 if (!r->trb) 1552 goto out0; 1553 1554 dwc3_gadget_move_cancelled_request(req); 1555 if (dep->flags & DWC3_EP_TRANSFER_STARTED) 1556 goto out0; 1557 else 1558 goto out1; 1559 } 1560 dev_err(dwc->dev, "request %pK was not queued to %s\n", 1561 request, ep->name); 1562 ret = -EINVAL; 1563 goto out0; 1564 } 1565 1566 out1: 1567 dwc3_gadget_giveback(dep, req, -ECONNRESET); 1568 1569 out0: 1570 spin_unlock_irqrestore(&dwc->lock, flags); 1571 1572 return ret; 1573 } 1574 1575 int __dwc3_gadget_ep_set_halt(struct dwc3_ep *dep, int value, int protocol) 1576 { 1577 struct dwc3_gadget_ep_cmd_params params; 1578 struct dwc3 *dwc = dep->dwc; 1579 int ret; 1580 1581 if (usb_endpoint_xfer_isoc(dep->endpoint.desc)) { 1582 dev_err(dwc->dev, "%s is of Isochronous type\n", dep->name); 1583 return -EINVAL; 1584 } 1585 1586 memset(¶ms, 0x00, sizeof(params)); 1587 1588 if (value) { 1589 struct dwc3_trb *trb; 1590 1591 unsigned transfer_in_flight; 1592 unsigned started; 1593 1594 if (dep->number > 1) 1595 trb = dwc3_ep_prev_trb(dep, dep->trb_enqueue); 1596 else 1597 trb = &dwc->ep0_trb[dep->trb_enqueue]; 1598 1599 transfer_in_flight = trb->ctrl & DWC3_TRB_CTRL_HWO; 1600 started = !list_empty(&dep->started_list); 1601 1602 if (!protocol && ((dep->direction && transfer_in_flight) || 1603 (!dep->direction && started))) { 1604 return -EAGAIN; 1605 } 1606 1607 ret = dwc3_send_gadget_ep_cmd(dep, DWC3_DEPCMD_SETSTALL, 1608 ¶ms); 1609 if (ret) 1610 dev_err(dwc->dev, "failed to set STALL on %s\n", 1611 dep->name); 1612 else 1613 dep->flags |= DWC3_EP_STALL; 1614 } else { 1615 1616 ret = dwc3_send_clear_stall_ep_cmd(dep); 1617 if (ret) 1618 dev_err(dwc->dev, "failed to clear STALL on %s\n", 1619 dep->name); 1620 else 1621 dep->flags &= ~(DWC3_EP_STALL | DWC3_EP_WEDGE); 1622 } 1623 1624 return ret; 1625 } 1626 1627 static int dwc3_gadget_ep_set_halt(struct usb_ep *ep, int value) 1628 { 1629 struct dwc3_ep *dep = to_dwc3_ep(ep); 1630 struct dwc3 *dwc = dep->dwc; 1631 1632 unsigned long flags; 1633 1634 int ret; 1635 1636 spin_lock_irqsave(&dwc->lock, flags); 1637 ret = __dwc3_gadget_ep_set_halt(dep, value, false); 1638 spin_unlock_irqrestore(&dwc->lock, flags); 1639 1640 return ret; 1641 } 1642 1643 static int dwc3_gadget_ep_set_wedge(struct usb_ep *ep) 1644 { 1645 struct dwc3_ep *dep = to_dwc3_ep(ep); 1646 struct dwc3 *dwc = dep->dwc; 1647 unsigned long flags; 1648 int ret; 1649 1650 spin_lock_irqsave(&dwc->lock, flags); 1651 dep->flags |= DWC3_EP_WEDGE; 1652 1653 if (dep->number == 0 || dep->number == 1) 1654 ret = __dwc3_gadget_ep0_set_halt(ep, 1); 1655 else 1656 ret = __dwc3_gadget_ep_set_halt(dep, 1, false); 1657 spin_unlock_irqrestore(&dwc->lock, flags); 1658 1659 return ret; 1660 } 1661 1662 /* -------------------------------------------------------------------------- */ 1663 1664 static struct usb_endpoint_descriptor dwc3_gadget_ep0_desc = { 1665 .bLength = USB_DT_ENDPOINT_SIZE, 1666 .bDescriptorType = USB_DT_ENDPOINT, 1667 .bmAttributes = USB_ENDPOINT_XFER_CONTROL, 1668 }; 1669 1670 static const struct usb_ep_ops dwc3_gadget_ep0_ops = { 1671 .enable = dwc3_gadget_ep0_enable, 1672 .disable = dwc3_gadget_ep0_disable, 1673 .alloc_request = dwc3_gadget_ep_alloc_request, 1674 .free_request = dwc3_gadget_ep_free_request, 1675 .queue = dwc3_gadget_ep0_queue, 1676 .dequeue = dwc3_gadget_ep_dequeue, 1677 .set_halt = dwc3_gadget_ep0_set_halt, 1678 .set_wedge = dwc3_gadget_ep_set_wedge, 1679 }; 1680 1681 static const struct usb_ep_ops dwc3_gadget_ep_ops = { 1682 .enable = dwc3_gadget_ep_enable, 1683 .disable = dwc3_gadget_ep_disable, 1684 .alloc_request = dwc3_gadget_ep_alloc_request, 1685 .free_request = dwc3_gadget_ep_free_request, 1686 .queue = dwc3_gadget_ep_queue, 1687 .dequeue = dwc3_gadget_ep_dequeue, 1688 .set_halt = dwc3_gadget_ep_set_halt, 1689 .set_wedge = dwc3_gadget_ep_set_wedge, 1690 }; 1691 1692 /* -------------------------------------------------------------------------- */ 1693 1694 static int dwc3_gadget_get_frame(struct usb_gadget *g) 1695 { 1696 struct dwc3 *dwc = gadget_to_dwc(g); 1697 1698 return __dwc3_gadget_get_frame(dwc); 1699 } 1700 1701 static int __dwc3_gadget_wakeup(struct dwc3 *dwc) 1702 { 1703 int retries; 1704 1705 int ret; 1706 u32 reg; 1707 1708 u8 link_state; 1709 u8 speed; 1710 1711 /* 1712 * According to the Databook Remote wakeup request should 1713 * be issued only when the device is in early suspend state. 1714 * 1715 * We can check that via USB Link State bits in DSTS register. 1716 */ 1717 reg = dwc3_readl(dwc->regs, DWC3_DSTS); 1718 1719 speed = reg & DWC3_DSTS_CONNECTSPD; 1720 if ((speed == DWC3_DSTS_SUPERSPEED) || 1721 (speed == DWC3_DSTS_SUPERSPEED_PLUS)) 1722 return 0; 1723 1724 link_state = DWC3_DSTS_USBLNKST(reg); 1725 1726 switch (link_state) { 1727 case DWC3_LINK_STATE_RX_DET: /* in HS, means Early Suspend */ 1728 case DWC3_LINK_STATE_U3: /* in HS, means SUSPEND */ 1729 break; 1730 default: 1731 return -EINVAL; 1732 } 1733 1734 ret = dwc3_gadget_set_link_state(dwc, DWC3_LINK_STATE_RECOV); 1735 if (ret < 0) { 1736 dev_err(dwc->dev, "failed to put link in Recovery\n"); 1737 return ret; 1738 } 1739 1740 /* Recent versions do this automatically */ 1741 if (dwc->revision < DWC3_REVISION_194A) { 1742 /* write zeroes to Link Change Request */ 1743 reg = dwc3_readl(dwc->regs, DWC3_DCTL); 1744 reg &= ~DWC3_DCTL_ULSTCHNGREQ_MASK; 1745 dwc3_writel(dwc->regs, DWC3_DCTL, reg); 1746 } 1747 1748 /* poll until Link State changes to ON */ 1749 retries = 20000; 1750 1751 while (retries--) { 1752 reg = dwc3_readl(dwc->regs, DWC3_DSTS); 1753 1754 /* in HS, means ON */ 1755 if (DWC3_DSTS_USBLNKST(reg) == DWC3_LINK_STATE_U0) 1756 break; 1757 } 1758 1759 if (DWC3_DSTS_USBLNKST(reg) != DWC3_LINK_STATE_U0) { 1760 dev_err(dwc->dev, "failed to send remote wakeup\n"); 1761 return -EINVAL; 1762 } 1763 1764 return 0; 1765 } 1766 1767 static int dwc3_gadget_wakeup(struct usb_gadget *g) 1768 { 1769 struct dwc3 *dwc = gadget_to_dwc(g); 1770 unsigned long flags; 1771 int ret; 1772 1773 spin_lock_irqsave(&dwc->lock, flags); 1774 ret = __dwc3_gadget_wakeup(dwc); 1775 spin_unlock_irqrestore(&dwc->lock, flags); 1776 1777 return ret; 1778 } 1779 1780 static int dwc3_gadget_set_selfpowered(struct usb_gadget *g, 1781 int is_selfpowered) 1782 { 1783 struct dwc3 *dwc = gadget_to_dwc(g); 1784 unsigned long flags; 1785 1786 spin_lock_irqsave(&dwc->lock, flags); 1787 g->is_selfpowered = !!is_selfpowered; 1788 spin_unlock_irqrestore(&dwc->lock, flags); 1789 1790 return 0; 1791 } 1792 1793 static int dwc3_gadget_run_stop(struct dwc3 *dwc, int is_on, int suspend) 1794 { 1795 u32 reg; 1796 u32 timeout = 500; 1797 1798 if (pm_runtime_suspended(dwc->dev)) 1799 return 0; 1800 1801 reg = dwc3_readl(dwc->regs, DWC3_DCTL); 1802 if (is_on) { 1803 if (dwc->revision <= DWC3_REVISION_187A) { 1804 reg &= ~DWC3_DCTL_TRGTULST_MASK; 1805 reg |= DWC3_DCTL_TRGTULST_RX_DET; 1806 } 1807 1808 if (dwc->revision >= DWC3_REVISION_194A) 1809 reg &= ~DWC3_DCTL_KEEP_CONNECT; 1810 reg |= DWC3_DCTL_RUN_STOP; 1811 1812 if (dwc->has_hibernation) 1813 reg |= DWC3_DCTL_KEEP_CONNECT; 1814 1815 dwc->pullups_connected = true; 1816 } else { 1817 reg &= ~DWC3_DCTL_RUN_STOP; 1818 1819 if (dwc->has_hibernation && !suspend) 1820 reg &= ~DWC3_DCTL_KEEP_CONNECT; 1821 1822 dwc->pullups_connected = false; 1823 } 1824 1825 dwc3_writel(dwc->regs, DWC3_DCTL, reg); 1826 1827 do { 1828 reg = dwc3_readl(dwc->regs, DWC3_DSTS); 1829 reg &= DWC3_DSTS_DEVCTRLHLT; 1830 } while (--timeout && !(!is_on ^ !reg)); 1831 1832 if (!timeout) 1833 return -ETIMEDOUT; 1834 1835 return 0; 1836 } 1837 1838 static int dwc3_gadget_pullup(struct usb_gadget *g, int is_on) 1839 { 1840 struct dwc3 *dwc = gadget_to_dwc(g); 1841 unsigned long flags; 1842 int ret; 1843 1844 is_on = !!is_on; 1845 1846 /* 1847 * Per databook, when we want to stop the gadget, if a control transfer 1848 * is still in process, complete it and get the core into setup phase. 1849 */ 1850 if (!is_on && dwc->ep0state != EP0_SETUP_PHASE) { 1851 reinit_completion(&dwc->ep0_in_setup); 1852 1853 ret = wait_for_completion_timeout(&dwc->ep0_in_setup, 1854 msecs_to_jiffies(DWC3_PULL_UP_TIMEOUT)); 1855 if (ret == 0) { 1856 dev_err(dwc->dev, "timed out waiting for SETUP phase\n"); 1857 return -ETIMEDOUT; 1858 } 1859 } 1860 1861 spin_lock_irqsave(&dwc->lock, flags); 1862 ret = dwc3_gadget_run_stop(dwc, is_on, false); 1863 spin_unlock_irqrestore(&dwc->lock, flags); 1864 1865 return ret; 1866 } 1867 1868 static void dwc3_gadget_enable_irq(struct dwc3 *dwc) 1869 { 1870 u32 reg; 1871 1872 /* Enable all but Start and End of Frame IRQs */ 1873 reg = (DWC3_DEVTEN_VNDRDEVTSTRCVEDEN | 1874 DWC3_DEVTEN_EVNTOVERFLOWEN | 1875 DWC3_DEVTEN_CMDCMPLTEN | 1876 DWC3_DEVTEN_ERRTICERREN | 1877 DWC3_DEVTEN_WKUPEVTEN | 1878 DWC3_DEVTEN_CONNECTDONEEN | 1879 DWC3_DEVTEN_USBRSTEN | 1880 DWC3_DEVTEN_DISCONNEVTEN); 1881 1882 if (dwc->revision < DWC3_REVISION_250A) 1883 reg |= DWC3_DEVTEN_ULSTCNGEN; 1884 1885 dwc3_writel(dwc->regs, DWC3_DEVTEN, reg); 1886 } 1887 1888 static void dwc3_gadget_disable_irq(struct dwc3 *dwc) 1889 { 1890 /* mask all interrupts */ 1891 dwc3_writel(dwc->regs, DWC3_DEVTEN, 0x00); 1892 } 1893 1894 static irqreturn_t dwc3_interrupt(int irq, void *_dwc); 1895 static irqreturn_t dwc3_thread_interrupt(int irq, void *_dwc); 1896 1897 /** 1898 * dwc3_gadget_setup_nump - calculate and initialize NUMP field of %DWC3_DCFG 1899 * @dwc: pointer to our context structure 1900 * 1901 * The following looks like complex but it's actually very simple. In order to 1902 * calculate the number of packets we can burst at once on OUT transfers, we're 1903 * gonna use RxFIFO size. 1904 * 1905 * To calculate RxFIFO size we need two numbers: 1906 * MDWIDTH = size, in bits, of the internal memory bus 1907 * RAM2_DEPTH = depth, in MDWIDTH, of internal RAM2 (where RxFIFO sits) 1908 * 1909 * Given these two numbers, the formula is simple: 1910 * 1911 * RxFIFO Size = (RAM2_DEPTH * MDWIDTH / 8) - 24 - 16; 1912 * 1913 * 24 bytes is for 3x SETUP packets 1914 * 16 bytes is a clock domain crossing tolerance 1915 * 1916 * Given RxFIFO Size, NUMP = RxFIFOSize / 1024; 1917 */ 1918 static void dwc3_gadget_setup_nump(struct dwc3 *dwc) 1919 { 1920 u32 ram2_depth; 1921 u32 mdwidth; 1922 u32 nump; 1923 u32 reg; 1924 1925 ram2_depth = DWC3_GHWPARAMS7_RAM2_DEPTH(dwc->hwparams.hwparams7); 1926 mdwidth = DWC3_GHWPARAMS0_MDWIDTH(dwc->hwparams.hwparams0); 1927 1928 nump = ((ram2_depth * mdwidth / 8) - 24 - 16) / 1024; 1929 nump = min_t(u32, nump, 16); 1930 1931 /* update NumP */ 1932 reg = dwc3_readl(dwc->regs, DWC3_DCFG); 1933 reg &= ~DWC3_DCFG_NUMP_MASK; 1934 reg |= nump << DWC3_DCFG_NUMP_SHIFT; 1935 dwc3_writel(dwc->regs, DWC3_DCFG, reg); 1936 } 1937 1938 static int __dwc3_gadget_start(struct dwc3 *dwc) 1939 { 1940 struct dwc3_ep *dep; 1941 int ret = 0; 1942 u32 reg; 1943 1944 /* 1945 * Use IMOD if enabled via dwc->imod_interval. Otherwise, if 1946 * the core supports IMOD, disable it. 1947 */ 1948 if (dwc->imod_interval) { 1949 dwc3_writel(dwc->regs, DWC3_DEV_IMOD(0), dwc->imod_interval); 1950 dwc3_writel(dwc->regs, DWC3_GEVNTCOUNT(0), DWC3_GEVNTCOUNT_EHB); 1951 } else if (dwc3_has_imod(dwc)) { 1952 dwc3_writel(dwc->regs, DWC3_DEV_IMOD(0), 0); 1953 } 1954 1955 /* 1956 * We are telling dwc3 that we want to use DCFG.NUMP as ACK TP's NUMP 1957 * field instead of letting dwc3 itself calculate that automatically. 1958 * 1959 * This way, we maximize the chances that we'll be able to get several 1960 * bursts of data without going through any sort of endpoint throttling. 1961 */ 1962 reg = dwc3_readl(dwc->regs, DWC3_GRXTHRCFG); 1963 if (dwc3_is_usb31(dwc)) 1964 reg &= ~DWC31_GRXTHRCFG_PKTCNTSEL; 1965 else 1966 reg &= ~DWC3_GRXTHRCFG_PKTCNTSEL; 1967 1968 dwc3_writel(dwc->regs, DWC3_GRXTHRCFG, reg); 1969 1970 dwc3_gadget_setup_nump(dwc); 1971 1972 /* Start with SuperSpeed Default */ 1973 dwc3_gadget_ep0_desc.wMaxPacketSize = cpu_to_le16(512); 1974 1975 dep = dwc->eps[0]; 1976 ret = __dwc3_gadget_ep_enable(dep, DWC3_DEPCFG_ACTION_INIT); 1977 if (ret) { 1978 dev_err(dwc->dev, "failed to enable %s\n", dep->name); 1979 goto err0; 1980 } 1981 1982 dep = dwc->eps[1]; 1983 ret = __dwc3_gadget_ep_enable(dep, DWC3_DEPCFG_ACTION_INIT); 1984 if (ret) { 1985 dev_err(dwc->dev, "failed to enable %s\n", dep->name); 1986 goto err1; 1987 } 1988 1989 /* begin to receive SETUP packets */ 1990 dwc->ep0state = EP0_SETUP_PHASE; 1991 dwc->link_state = DWC3_LINK_STATE_SS_DIS; 1992 dwc3_ep0_out_start(dwc); 1993 1994 dwc3_gadget_enable_irq(dwc); 1995 1996 return 0; 1997 1998 err1: 1999 __dwc3_gadget_ep_disable(dwc->eps[0]); 2000 2001 err0: 2002 return ret; 2003 } 2004 2005 static int dwc3_gadget_start(struct usb_gadget *g, 2006 struct usb_gadget_driver *driver) 2007 { 2008 struct dwc3 *dwc = gadget_to_dwc(g); 2009 unsigned long flags; 2010 int ret = 0; 2011 int irq; 2012 2013 irq = dwc->irq_gadget; 2014 ret = request_threaded_irq(irq, dwc3_interrupt, dwc3_thread_interrupt, 2015 IRQF_SHARED, "dwc3", dwc->ev_buf); 2016 if (ret) { 2017 dev_err(dwc->dev, "failed to request irq #%d --> %d\n", 2018 irq, ret); 2019 goto err0; 2020 } 2021 2022 spin_lock_irqsave(&dwc->lock, flags); 2023 if (dwc->gadget_driver) { 2024 dev_err(dwc->dev, "%s is already bound to %s\n", 2025 dwc->gadget.name, 2026 dwc->gadget_driver->driver.name); 2027 ret = -EBUSY; 2028 goto err1; 2029 } 2030 2031 dwc->gadget_driver = driver; 2032 2033 if (pm_runtime_active(dwc->dev)) 2034 __dwc3_gadget_start(dwc); 2035 2036 spin_unlock_irqrestore(&dwc->lock, flags); 2037 2038 return 0; 2039 2040 err1: 2041 spin_unlock_irqrestore(&dwc->lock, flags); 2042 free_irq(irq, dwc); 2043 2044 err0: 2045 return ret; 2046 } 2047 2048 static void __dwc3_gadget_stop(struct dwc3 *dwc) 2049 { 2050 dwc3_gadget_disable_irq(dwc); 2051 __dwc3_gadget_ep_disable(dwc->eps[0]); 2052 __dwc3_gadget_ep_disable(dwc->eps[1]); 2053 } 2054 2055 static int dwc3_gadget_stop(struct usb_gadget *g) 2056 { 2057 struct dwc3 *dwc = gadget_to_dwc(g); 2058 unsigned long flags; 2059 2060 spin_lock_irqsave(&dwc->lock, flags); 2061 2062 if (pm_runtime_suspended(dwc->dev)) 2063 goto out; 2064 2065 __dwc3_gadget_stop(dwc); 2066 2067 out: 2068 dwc->gadget_driver = NULL; 2069 spin_unlock_irqrestore(&dwc->lock, flags); 2070 2071 free_irq(dwc->irq_gadget, dwc->ev_buf); 2072 2073 return 0; 2074 } 2075 2076 static void dwc3_gadget_config_params(struct usb_gadget *g, 2077 struct usb_dcd_config_params *params) 2078 { 2079 struct dwc3 *dwc = gadget_to_dwc(g); 2080 2081 params->besl_baseline = USB_DEFAULT_BESL_UNSPECIFIED; 2082 params->besl_deep = USB_DEFAULT_BESL_UNSPECIFIED; 2083 2084 /* Recommended BESL */ 2085 if (!dwc->dis_enblslpm_quirk) { 2086 /* 2087 * If the recommended BESL baseline is 0 or if the BESL deep is 2088 * less than 2, Microsoft's Windows 10 host usb stack will issue 2089 * a usb reset immediately after it receives the extended BOS 2090 * descriptor and the enumeration will fail. To maintain 2091 * compatibility with the Windows' usb stack, let's set the 2092 * recommended BESL baseline to 1 and clamp the BESL deep to be 2093 * within 2 to 15. 2094 */ 2095 params->besl_baseline = 1; 2096 if (dwc->is_utmi_l1_suspend) 2097 params->besl_deep = 2098 clamp_t(u8, dwc->hird_threshold, 2, 15); 2099 } 2100 2101 /* U1 Device exit Latency */ 2102 if (dwc->dis_u1_entry_quirk) 2103 params->bU1devExitLat = 0; 2104 else 2105 params->bU1devExitLat = DWC3_DEFAULT_U1_DEV_EXIT_LAT; 2106 2107 /* U2 Device exit Latency */ 2108 if (dwc->dis_u2_entry_quirk) 2109 params->bU2DevExitLat = 0; 2110 else 2111 params->bU2DevExitLat = 2112 cpu_to_le16(DWC3_DEFAULT_U2_DEV_EXIT_LAT); 2113 } 2114 2115 static void dwc3_gadget_set_speed(struct usb_gadget *g, 2116 enum usb_device_speed speed) 2117 { 2118 struct dwc3 *dwc = gadget_to_dwc(g); 2119 unsigned long flags; 2120 u32 reg; 2121 2122 spin_lock_irqsave(&dwc->lock, flags); 2123 reg = dwc3_readl(dwc->regs, DWC3_DCFG); 2124 reg &= ~(DWC3_DCFG_SPEED_MASK); 2125 2126 /* 2127 * WORKAROUND: DWC3 revision < 2.20a have an issue 2128 * which would cause metastability state on Run/Stop 2129 * bit if we try to force the IP to USB2-only mode. 2130 * 2131 * Because of that, we cannot configure the IP to any 2132 * speed other than the SuperSpeed 2133 * 2134 * Refers to: 2135 * 2136 * STAR#9000525659: Clock Domain Crossing on DCTL in 2137 * USB 2.0 Mode 2138 */ 2139 if (dwc->revision < DWC3_REVISION_220A && 2140 !dwc->dis_metastability_quirk) { 2141 reg |= DWC3_DCFG_SUPERSPEED; 2142 } else { 2143 switch (speed) { 2144 case USB_SPEED_LOW: 2145 reg |= DWC3_DCFG_LOWSPEED; 2146 break; 2147 case USB_SPEED_FULL: 2148 reg |= DWC3_DCFG_FULLSPEED; 2149 break; 2150 case USB_SPEED_HIGH: 2151 reg |= DWC3_DCFG_HIGHSPEED; 2152 break; 2153 case USB_SPEED_SUPER: 2154 reg |= DWC3_DCFG_SUPERSPEED; 2155 break; 2156 case USB_SPEED_SUPER_PLUS: 2157 if (dwc3_is_usb31(dwc)) 2158 reg |= DWC3_DCFG_SUPERSPEED_PLUS; 2159 else 2160 reg |= DWC3_DCFG_SUPERSPEED; 2161 break; 2162 default: 2163 dev_err(dwc->dev, "invalid speed (%d)\n", speed); 2164 2165 if (dwc->revision & DWC3_REVISION_IS_DWC31) 2166 reg |= DWC3_DCFG_SUPERSPEED_PLUS; 2167 else 2168 reg |= DWC3_DCFG_SUPERSPEED; 2169 } 2170 } 2171 dwc3_writel(dwc->regs, DWC3_DCFG, reg); 2172 2173 spin_unlock_irqrestore(&dwc->lock, flags); 2174 } 2175 2176 static const struct usb_gadget_ops dwc3_gadget_ops = { 2177 .get_frame = dwc3_gadget_get_frame, 2178 .wakeup = dwc3_gadget_wakeup, 2179 .set_selfpowered = dwc3_gadget_set_selfpowered, 2180 .pullup = dwc3_gadget_pullup, 2181 .udc_start = dwc3_gadget_start, 2182 .udc_stop = dwc3_gadget_stop, 2183 .udc_set_speed = dwc3_gadget_set_speed, 2184 .get_config_params = dwc3_gadget_config_params, 2185 }; 2186 2187 /* -------------------------------------------------------------------------- */ 2188 2189 static int dwc3_gadget_init_control_endpoint(struct dwc3_ep *dep) 2190 { 2191 struct dwc3 *dwc = dep->dwc; 2192 2193 usb_ep_set_maxpacket_limit(&dep->endpoint, 512); 2194 dep->endpoint.maxburst = 1; 2195 dep->endpoint.ops = &dwc3_gadget_ep0_ops; 2196 if (!dep->direction) 2197 dwc->gadget.ep0 = &dep->endpoint; 2198 2199 dep->endpoint.caps.type_control = true; 2200 2201 return 0; 2202 } 2203 2204 static int dwc3_gadget_init_in_endpoint(struct dwc3_ep *dep) 2205 { 2206 struct dwc3 *dwc = dep->dwc; 2207 int mdwidth; 2208 int kbytes; 2209 int size; 2210 2211 mdwidth = DWC3_MDWIDTH(dwc->hwparams.hwparams0); 2212 /* MDWIDTH is represented in bits, we need it in bytes */ 2213 mdwidth /= 8; 2214 2215 size = dwc3_readl(dwc->regs, DWC3_GTXFIFOSIZ(dep->number >> 1)); 2216 if (dwc3_is_usb31(dwc)) 2217 size = DWC31_GTXFIFOSIZ_TXFDEF(size); 2218 else 2219 size = DWC3_GTXFIFOSIZ_TXFDEF(size); 2220 2221 /* FIFO Depth is in MDWDITH bytes. Multiply */ 2222 size *= mdwidth; 2223 2224 kbytes = size / 1024; 2225 if (kbytes == 0) 2226 kbytes = 1; 2227 2228 /* 2229 * FIFO sizes account an extra MDWIDTH * (kbytes + 1) bytes for 2230 * internal overhead. We don't really know how these are used, 2231 * but documentation say it exists. 2232 */ 2233 size -= mdwidth * (kbytes + 1); 2234 size /= kbytes; 2235 2236 usb_ep_set_maxpacket_limit(&dep->endpoint, size); 2237 2238 dep->endpoint.max_streams = 15; 2239 dep->endpoint.ops = &dwc3_gadget_ep_ops; 2240 list_add_tail(&dep->endpoint.ep_list, 2241 &dwc->gadget.ep_list); 2242 dep->endpoint.caps.type_iso = true; 2243 dep->endpoint.caps.type_bulk = true; 2244 dep->endpoint.caps.type_int = true; 2245 2246 return dwc3_alloc_trb_pool(dep); 2247 } 2248 2249 static int dwc3_gadget_init_out_endpoint(struct dwc3_ep *dep) 2250 { 2251 struct dwc3 *dwc = dep->dwc; 2252 2253 usb_ep_set_maxpacket_limit(&dep->endpoint, 1024); 2254 dep->endpoint.max_streams = 15; 2255 dep->endpoint.ops = &dwc3_gadget_ep_ops; 2256 list_add_tail(&dep->endpoint.ep_list, 2257 &dwc->gadget.ep_list); 2258 dep->endpoint.caps.type_iso = true; 2259 dep->endpoint.caps.type_bulk = true; 2260 dep->endpoint.caps.type_int = true; 2261 2262 return dwc3_alloc_trb_pool(dep); 2263 } 2264 2265 static int dwc3_gadget_init_endpoint(struct dwc3 *dwc, u8 epnum) 2266 { 2267 struct dwc3_ep *dep; 2268 bool direction = epnum & 1; 2269 int ret; 2270 u8 num = epnum >> 1; 2271 2272 dep = kzalloc(sizeof(*dep), GFP_KERNEL); 2273 if (!dep) 2274 return -ENOMEM; 2275 2276 dep->dwc = dwc; 2277 dep->number = epnum; 2278 dep->direction = direction; 2279 dep->regs = dwc->regs + DWC3_DEP_BASE(epnum); 2280 dwc->eps[epnum] = dep; 2281 dep->combo_num = 0; 2282 dep->start_cmd_status = 0; 2283 2284 snprintf(dep->name, sizeof(dep->name), "ep%u%s", num, 2285 direction ? "in" : "out"); 2286 2287 dep->endpoint.name = dep->name; 2288 2289 if (!(dep->number > 1)) { 2290 dep->endpoint.desc = &dwc3_gadget_ep0_desc; 2291 dep->endpoint.comp_desc = NULL; 2292 } 2293 2294 if (num == 0) 2295 ret = dwc3_gadget_init_control_endpoint(dep); 2296 else if (direction) 2297 ret = dwc3_gadget_init_in_endpoint(dep); 2298 else 2299 ret = dwc3_gadget_init_out_endpoint(dep); 2300 2301 if (ret) 2302 return ret; 2303 2304 dep->endpoint.caps.dir_in = direction; 2305 dep->endpoint.caps.dir_out = !direction; 2306 2307 INIT_LIST_HEAD(&dep->pending_list); 2308 INIT_LIST_HEAD(&dep->started_list); 2309 INIT_LIST_HEAD(&dep->cancelled_list); 2310 2311 return 0; 2312 } 2313 2314 static int dwc3_gadget_init_endpoints(struct dwc3 *dwc, u8 total) 2315 { 2316 u8 epnum; 2317 2318 INIT_LIST_HEAD(&dwc->gadget.ep_list); 2319 2320 for (epnum = 0; epnum < total; epnum++) { 2321 int ret; 2322 2323 ret = dwc3_gadget_init_endpoint(dwc, epnum); 2324 if (ret) 2325 return ret; 2326 } 2327 2328 return 0; 2329 } 2330 2331 static void dwc3_gadget_free_endpoints(struct dwc3 *dwc) 2332 { 2333 struct dwc3_ep *dep; 2334 u8 epnum; 2335 2336 for (epnum = 0; epnum < DWC3_ENDPOINTS_NUM; epnum++) { 2337 dep = dwc->eps[epnum]; 2338 if (!dep) 2339 continue; 2340 /* 2341 * Physical endpoints 0 and 1 are special; they form the 2342 * bi-directional USB endpoint 0. 2343 * 2344 * For those two physical endpoints, we don't allocate a TRB 2345 * pool nor do we add them the endpoints list. Due to that, we 2346 * shouldn't do these two operations otherwise we would end up 2347 * with all sorts of bugs when removing dwc3.ko. 2348 */ 2349 if (epnum != 0 && epnum != 1) { 2350 dwc3_free_trb_pool(dep); 2351 list_del(&dep->endpoint.ep_list); 2352 } 2353 2354 kfree(dep); 2355 } 2356 } 2357 2358 /* -------------------------------------------------------------------------- */ 2359 2360 static int dwc3_gadget_ep_reclaim_completed_trb(struct dwc3_ep *dep, 2361 struct dwc3_request *req, struct dwc3_trb *trb, 2362 const struct dwc3_event_depevt *event, int status, int chain) 2363 { 2364 unsigned int count; 2365 2366 dwc3_ep_inc_deq(dep); 2367 2368 trace_dwc3_complete_trb(dep, trb); 2369 req->num_trbs--; 2370 2371 /* 2372 * If we're in the middle of series of chained TRBs and we 2373 * receive a short transfer along the way, DWC3 will skip 2374 * through all TRBs including the last TRB in the chain (the 2375 * where CHN bit is zero. DWC3 will also avoid clearing HWO 2376 * bit and SW has to do it manually. 2377 * 2378 * We're going to do that here to avoid problems of HW trying 2379 * to use bogus TRBs for transfers. 2380 */ 2381 if (chain && (trb->ctrl & DWC3_TRB_CTRL_HWO)) 2382 trb->ctrl &= ~DWC3_TRB_CTRL_HWO; 2383 2384 /* 2385 * For isochronous transfers, the first TRB in a service interval must 2386 * have the Isoc-First type. Track and report its interval frame number. 2387 */ 2388 if (usb_endpoint_xfer_isoc(dep->endpoint.desc) && 2389 (trb->ctrl & DWC3_TRBCTL_ISOCHRONOUS_FIRST)) { 2390 unsigned int frame_number; 2391 2392 frame_number = DWC3_TRB_CTRL_GET_SID_SOFN(trb->ctrl); 2393 frame_number &= ~(dep->interval - 1); 2394 req->request.frame_number = frame_number; 2395 } 2396 2397 /* 2398 * If we're dealing with unaligned size OUT transfer, we will be left 2399 * with one TRB pending in the ring. We need to manually clear HWO bit 2400 * from that TRB. 2401 */ 2402 2403 if (req->needs_extra_trb && !(trb->ctrl & DWC3_TRB_CTRL_CHN)) { 2404 trb->ctrl &= ~DWC3_TRB_CTRL_HWO; 2405 return 1; 2406 } 2407 2408 count = trb->size & DWC3_TRB_SIZE_MASK; 2409 req->remaining += count; 2410 2411 if ((trb->ctrl & DWC3_TRB_CTRL_HWO) && status != -ESHUTDOWN) 2412 return 1; 2413 2414 if (event->status & DEPEVT_STATUS_SHORT && !chain) 2415 return 1; 2416 2417 if (event->status & DEPEVT_STATUS_IOC) 2418 return 1; 2419 2420 return 0; 2421 } 2422 2423 static int dwc3_gadget_ep_reclaim_trb_sg(struct dwc3_ep *dep, 2424 struct dwc3_request *req, const struct dwc3_event_depevt *event, 2425 int status) 2426 { 2427 struct dwc3_trb *trb = &dep->trb_pool[dep->trb_dequeue]; 2428 struct scatterlist *sg = req->sg; 2429 struct scatterlist *s; 2430 unsigned int pending = req->num_pending_sgs; 2431 unsigned int i; 2432 int ret = 0; 2433 2434 for_each_sg(sg, s, pending, i) { 2435 trb = &dep->trb_pool[dep->trb_dequeue]; 2436 2437 if (trb->ctrl & DWC3_TRB_CTRL_HWO) 2438 break; 2439 2440 req->sg = sg_next(s); 2441 req->num_pending_sgs--; 2442 2443 ret = dwc3_gadget_ep_reclaim_completed_trb(dep, req, 2444 trb, event, status, true); 2445 if (ret) 2446 break; 2447 } 2448 2449 return ret; 2450 } 2451 2452 static int dwc3_gadget_ep_reclaim_trb_linear(struct dwc3_ep *dep, 2453 struct dwc3_request *req, const struct dwc3_event_depevt *event, 2454 int status) 2455 { 2456 struct dwc3_trb *trb = &dep->trb_pool[dep->trb_dequeue]; 2457 2458 return dwc3_gadget_ep_reclaim_completed_trb(dep, req, trb, 2459 event, status, false); 2460 } 2461 2462 static bool dwc3_gadget_ep_request_completed(struct dwc3_request *req) 2463 { 2464 return req->request.actual == req->request.length; 2465 } 2466 2467 static int dwc3_gadget_ep_cleanup_completed_request(struct dwc3_ep *dep, 2468 const struct dwc3_event_depevt *event, 2469 struct dwc3_request *req, int status) 2470 { 2471 int ret; 2472 2473 if (req->num_pending_sgs) 2474 ret = dwc3_gadget_ep_reclaim_trb_sg(dep, req, event, 2475 status); 2476 else 2477 ret = dwc3_gadget_ep_reclaim_trb_linear(dep, req, event, 2478 status); 2479 2480 if (req->needs_extra_trb) { 2481 ret = dwc3_gadget_ep_reclaim_trb_linear(dep, req, event, 2482 status); 2483 req->needs_extra_trb = false; 2484 } 2485 2486 req->request.actual = req->request.length - req->remaining; 2487 2488 if (!dwc3_gadget_ep_request_completed(req) && 2489 req->num_pending_sgs) { 2490 __dwc3_gadget_kick_transfer(dep); 2491 goto out; 2492 } 2493 2494 dwc3_gadget_giveback(dep, req, status); 2495 2496 out: 2497 return ret; 2498 } 2499 2500 static void dwc3_gadget_ep_cleanup_completed_requests(struct dwc3_ep *dep, 2501 const struct dwc3_event_depevt *event, int status) 2502 { 2503 struct dwc3_request *req; 2504 struct dwc3_request *tmp; 2505 2506 list_for_each_entry_safe(req, tmp, &dep->started_list, list) { 2507 int ret; 2508 2509 ret = dwc3_gadget_ep_cleanup_completed_request(dep, event, 2510 req, status); 2511 if (ret) 2512 break; 2513 } 2514 } 2515 2516 static void dwc3_gadget_endpoint_frame_from_event(struct dwc3_ep *dep, 2517 const struct dwc3_event_depevt *event) 2518 { 2519 dep->frame_number = event->parameters; 2520 } 2521 2522 static void dwc3_gadget_endpoint_transfer_in_progress(struct dwc3_ep *dep, 2523 const struct dwc3_event_depevt *event) 2524 { 2525 struct dwc3 *dwc = dep->dwc; 2526 unsigned status = 0; 2527 bool stop = false; 2528 2529 dwc3_gadget_endpoint_frame_from_event(dep, event); 2530 2531 if (event->status & DEPEVT_STATUS_BUSERR) 2532 status = -ECONNRESET; 2533 2534 if (event->status & DEPEVT_STATUS_MISSED_ISOC) { 2535 status = -EXDEV; 2536 2537 if (list_empty(&dep->started_list)) 2538 stop = true; 2539 } 2540 2541 dwc3_gadget_ep_cleanup_completed_requests(dep, event, status); 2542 2543 if (stop) { 2544 dwc3_stop_active_transfer(dep, true, true); 2545 dep->flags = DWC3_EP_ENABLED; 2546 } 2547 2548 /* 2549 * WORKAROUND: This is the 2nd half of U1/U2 -> U0 workaround. 2550 * See dwc3_gadget_linksts_change_interrupt() for 1st half. 2551 */ 2552 if (dwc->revision < DWC3_REVISION_183A) { 2553 u32 reg; 2554 int i; 2555 2556 for (i = 0; i < DWC3_ENDPOINTS_NUM; i++) { 2557 dep = dwc->eps[i]; 2558 2559 if (!(dep->flags & DWC3_EP_ENABLED)) 2560 continue; 2561 2562 if (!list_empty(&dep->started_list)) 2563 return; 2564 } 2565 2566 reg = dwc3_readl(dwc->regs, DWC3_DCTL); 2567 reg |= dwc->u1u2; 2568 dwc3_writel(dwc->regs, DWC3_DCTL, reg); 2569 2570 dwc->u1u2 = 0; 2571 } 2572 } 2573 2574 static void dwc3_gadget_endpoint_transfer_not_ready(struct dwc3_ep *dep, 2575 const struct dwc3_event_depevt *event) 2576 { 2577 dwc3_gadget_endpoint_frame_from_event(dep, event); 2578 (void) __dwc3_gadget_start_isoc(dep); 2579 } 2580 2581 static void dwc3_endpoint_interrupt(struct dwc3 *dwc, 2582 const struct dwc3_event_depevt *event) 2583 { 2584 struct dwc3_ep *dep; 2585 u8 epnum = event->endpoint_number; 2586 u8 cmd; 2587 2588 dep = dwc->eps[epnum]; 2589 2590 if (!(dep->flags & DWC3_EP_ENABLED)) { 2591 if (!(dep->flags & DWC3_EP_TRANSFER_STARTED)) 2592 return; 2593 2594 /* Handle only EPCMDCMPLT when EP disabled */ 2595 if (event->endpoint_event != DWC3_DEPEVT_EPCMDCMPLT) 2596 return; 2597 } 2598 2599 if (epnum == 0 || epnum == 1) { 2600 dwc3_ep0_interrupt(dwc, event); 2601 return; 2602 } 2603 2604 switch (event->endpoint_event) { 2605 case DWC3_DEPEVT_XFERINPROGRESS: 2606 dwc3_gadget_endpoint_transfer_in_progress(dep, event); 2607 break; 2608 case DWC3_DEPEVT_XFERNOTREADY: 2609 dwc3_gadget_endpoint_transfer_not_ready(dep, event); 2610 break; 2611 case DWC3_DEPEVT_EPCMDCMPLT: 2612 cmd = DEPEVT_PARAMETER_CMD(event->parameters); 2613 2614 if (cmd == DWC3_DEPCMD_ENDTRANSFER) { 2615 dep->flags &= ~DWC3_EP_TRANSFER_STARTED; 2616 dwc3_gadget_ep_cleanup_cancelled_requests(dep); 2617 } 2618 break; 2619 case DWC3_DEPEVT_STREAMEVT: 2620 case DWC3_DEPEVT_XFERCOMPLETE: 2621 case DWC3_DEPEVT_RXTXFIFOEVT: 2622 break; 2623 } 2624 } 2625 2626 static void dwc3_disconnect_gadget(struct dwc3 *dwc) 2627 { 2628 if (dwc->gadget_driver && dwc->gadget_driver->disconnect) { 2629 spin_unlock(&dwc->lock); 2630 dwc->gadget_driver->disconnect(&dwc->gadget); 2631 spin_lock(&dwc->lock); 2632 } 2633 } 2634 2635 static void dwc3_suspend_gadget(struct dwc3 *dwc) 2636 { 2637 if (dwc->gadget_driver && dwc->gadget_driver->suspend) { 2638 spin_unlock(&dwc->lock); 2639 dwc->gadget_driver->suspend(&dwc->gadget); 2640 spin_lock(&dwc->lock); 2641 } 2642 } 2643 2644 static void dwc3_resume_gadget(struct dwc3 *dwc) 2645 { 2646 if (dwc->gadget_driver && dwc->gadget_driver->resume) { 2647 spin_unlock(&dwc->lock); 2648 dwc->gadget_driver->resume(&dwc->gadget); 2649 spin_lock(&dwc->lock); 2650 } 2651 } 2652 2653 static void dwc3_reset_gadget(struct dwc3 *dwc) 2654 { 2655 if (!dwc->gadget_driver) 2656 return; 2657 2658 if (dwc->gadget.speed != USB_SPEED_UNKNOWN) { 2659 spin_unlock(&dwc->lock); 2660 usb_gadget_udc_reset(&dwc->gadget, dwc->gadget_driver); 2661 spin_lock(&dwc->lock); 2662 } 2663 } 2664 2665 static void dwc3_stop_active_transfer(struct dwc3_ep *dep, bool force, 2666 bool interrupt) 2667 { 2668 struct dwc3 *dwc = dep->dwc; 2669 struct dwc3_gadget_ep_cmd_params params; 2670 u32 cmd; 2671 int ret; 2672 2673 if (!(dep->flags & DWC3_EP_TRANSFER_STARTED)) 2674 return; 2675 2676 /* 2677 * NOTICE: We are violating what the Databook says about the 2678 * EndTransfer command. Ideally we would _always_ wait for the 2679 * EndTransfer Command Completion IRQ, but that's causing too 2680 * much trouble synchronizing between us and gadget driver. 2681 * 2682 * We have discussed this with the IP Provider and it was 2683 * suggested to giveback all requests here, but give HW some 2684 * extra time to synchronize with the interconnect. We're using 2685 * an arbitrary 100us delay for that. 2686 * 2687 * Note also that a similar handling was tested by Synopsys 2688 * (thanks a lot Paul) and nothing bad has come out of it. 2689 * In short, what we're doing is: 2690 * 2691 * - Issue EndTransfer WITH CMDIOC bit set 2692 * - Wait 100us 2693 * 2694 * As of IP version 3.10a of the DWC_usb3 IP, the controller 2695 * supports a mode to work around the above limitation. The 2696 * software can poll the CMDACT bit in the DEPCMD register 2697 * after issuing a EndTransfer command. This mode is enabled 2698 * by writing GUCTL2[14]. This polling is already done in the 2699 * dwc3_send_gadget_ep_cmd() function so if the mode is 2700 * enabled, the EndTransfer command will have completed upon 2701 * returning from this function and we don't need to delay for 2702 * 100us. 2703 * 2704 * This mode is NOT available on the DWC_usb31 IP. 2705 */ 2706 2707 cmd = DWC3_DEPCMD_ENDTRANSFER; 2708 cmd |= force ? DWC3_DEPCMD_HIPRI_FORCERM : 0; 2709 cmd |= interrupt ? DWC3_DEPCMD_CMDIOC : 0; 2710 cmd |= DWC3_DEPCMD_PARAM(dep->resource_index); 2711 memset(¶ms, 0, sizeof(params)); 2712 ret = dwc3_send_gadget_ep_cmd(dep, cmd, ¶ms); 2713 WARN_ON_ONCE(ret); 2714 dep->resource_index = 0; 2715 2716 if (dwc3_is_usb31(dwc) || dwc->revision < DWC3_REVISION_310A) 2717 udelay(100); 2718 } 2719 2720 static void dwc3_clear_stall_all_ep(struct dwc3 *dwc) 2721 { 2722 u32 epnum; 2723 2724 for (epnum = 1; epnum < DWC3_ENDPOINTS_NUM; epnum++) { 2725 struct dwc3_ep *dep; 2726 int ret; 2727 2728 dep = dwc->eps[epnum]; 2729 if (!dep) 2730 continue; 2731 2732 if (!(dep->flags & DWC3_EP_STALL)) 2733 continue; 2734 2735 dep->flags &= ~DWC3_EP_STALL; 2736 2737 ret = dwc3_send_clear_stall_ep_cmd(dep); 2738 WARN_ON_ONCE(ret); 2739 } 2740 } 2741 2742 static void dwc3_gadget_disconnect_interrupt(struct dwc3 *dwc) 2743 { 2744 int reg; 2745 2746 reg = dwc3_readl(dwc->regs, DWC3_DCTL); 2747 reg &= ~DWC3_DCTL_INITU1ENA; 2748 dwc3_writel(dwc->regs, DWC3_DCTL, reg); 2749 2750 reg &= ~DWC3_DCTL_INITU2ENA; 2751 dwc3_writel(dwc->regs, DWC3_DCTL, reg); 2752 2753 dwc3_disconnect_gadget(dwc); 2754 2755 dwc->gadget.speed = USB_SPEED_UNKNOWN; 2756 dwc->setup_packet_pending = false; 2757 usb_gadget_set_state(&dwc->gadget, USB_STATE_NOTATTACHED); 2758 2759 dwc->connected = false; 2760 } 2761 2762 static void dwc3_gadget_reset_interrupt(struct dwc3 *dwc) 2763 { 2764 u32 reg; 2765 2766 dwc->connected = true; 2767 2768 /* 2769 * WORKAROUND: DWC3 revisions <1.88a have an issue which 2770 * would cause a missing Disconnect Event if there's a 2771 * pending Setup Packet in the FIFO. 2772 * 2773 * There's no suggested workaround on the official Bug 2774 * report, which states that "unless the driver/application 2775 * is doing any special handling of a disconnect event, 2776 * there is no functional issue". 2777 * 2778 * Unfortunately, it turns out that we _do_ some special 2779 * handling of a disconnect event, namely complete all 2780 * pending transfers, notify gadget driver of the 2781 * disconnection, and so on. 2782 * 2783 * Our suggested workaround is to follow the Disconnect 2784 * Event steps here, instead, based on a setup_packet_pending 2785 * flag. Such flag gets set whenever we have a SETUP_PENDING 2786 * status for EP0 TRBs and gets cleared on XferComplete for the 2787 * same endpoint. 2788 * 2789 * Refers to: 2790 * 2791 * STAR#9000466709: RTL: Device : Disconnect event not 2792 * generated if setup packet pending in FIFO 2793 */ 2794 if (dwc->revision < DWC3_REVISION_188A) { 2795 if (dwc->setup_packet_pending) 2796 dwc3_gadget_disconnect_interrupt(dwc); 2797 } 2798 2799 dwc3_reset_gadget(dwc); 2800 2801 reg = dwc3_readl(dwc->regs, DWC3_DCTL); 2802 reg &= ~DWC3_DCTL_TSTCTRL_MASK; 2803 dwc3_writel(dwc->regs, DWC3_DCTL, reg); 2804 dwc->test_mode = false; 2805 dwc3_clear_stall_all_ep(dwc); 2806 2807 /* Reset device address to zero */ 2808 reg = dwc3_readl(dwc->regs, DWC3_DCFG); 2809 reg &= ~(DWC3_DCFG_DEVADDR_MASK); 2810 dwc3_writel(dwc->regs, DWC3_DCFG, reg); 2811 } 2812 2813 static void dwc3_gadget_conndone_interrupt(struct dwc3 *dwc) 2814 { 2815 struct dwc3_ep *dep; 2816 int ret; 2817 u32 reg; 2818 u8 speed; 2819 2820 reg = dwc3_readl(dwc->regs, DWC3_DSTS); 2821 speed = reg & DWC3_DSTS_CONNECTSPD; 2822 dwc->speed = speed; 2823 2824 /* 2825 * RAMClkSel is reset to 0 after USB reset, so it must be reprogrammed 2826 * each time on Connect Done. 2827 * 2828 * Currently we always use the reset value. If any platform 2829 * wants to set this to a different value, we need to add a 2830 * setting and update GCTL.RAMCLKSEL here. 2831 */ 2832 2833 switch (speed) { 2834 case DWC3_DSTS_SUPERSPEED_PLUS: 2835 dwc3_gadget_ep0_desc.wMaxPacketSize = cpu_to_le16(512); 2836 dwc->gadget.ep0->maxpacket = 512; 2837 dwc->gadget.speed = USB_SPEED_SUPER_PLUS; 2838 break; 2839 case DWC3_DSTS_SUPERSPEED: 2840 /* 2841 * WORKAROUND: DWC3 revisions <1.90a have an issue which 2842 * would cause a missing USB3 Reset event. 2843 * 2844 * In such situations, we should force a USB3 Reset 2845 * event by calling our dwc3_gadget_reset_interrupt() 2846 * routine. 2847 * 2848 * Refers to: 2849 * 2850 * STAR#9000483510: RTL: SS : USB3 reset event may 2851 * not be generated always when the link enters poll 2852 */ 2853 if (dwc->revision < DWC3_REVISION_190A) 2854 dwc3_gadget_reset_interrupt(dwc); 2855 2856 dwc3_gadget_ep0_desc.wMaxPacketSize = cpu_to_le16(512); 2857 dwc->gadget.ep0->maxpacket = 512; 2858 dwc->gadget.speed = USB_SPEED_SUPER; 2859 break; 2860 case DWC3_DSTS_HIGHSPEED: 2861 dwc3_gadget_ep0_desc.wMaxPacketSize = cpu_to_le16(64); 2862 dwc->gadget.ep0->maxpacket = 64; 2863 dwc->gadget.speed = USB_SPEED_HIGH; 2864 break; 2865 case DWC3_DSTS_FULLSPEED: 2866 dwc3_gadget_ep0_desc.wMaxPacketSize = cpu_to_le16(64); 2867 dwc->gadget.ep0->maxpacket = 64; 2868 dwc->gadget.speed = USB_SPEED_FULL; 2869 break; 2870 case DWC3_DSTS_LOWSPEED: 2871 dwc3_gadget_ep0_desc.wMaxPacketSize = cpu_to_le16(8); 2872 dwc->gadget.ep0->maxpacket = 8; 2873 dwc->gadget.speed = USB_SPEED_LOW; 2874 break; 2875 } 2876 2877 dwc->eps[1]->endpoint.maxpacket = dwc->gadget.ep0->maxpacket; 2878 2879 /* Enable USB2 LPM Capability */ 2880 2881 if ((dwc->revision > DWC3_REVISION_194A) && 2882 (speed != DWC3_DSTS_SUPERSPEED) && 2883 (speed != DWC3_DSTS_SUPERSPEED_PLUS)) { 2884 reg = dwc3_readl(dwc->regs, DWC3_DCFG); 2885 reg |= DWC3_DCFG_LPM_CAP; 2886 dwc3_writel(dwc->regs, DWC3_DCFG, reg); 2887 2888 reg = dwc3_readl(dwc->regs, DWC3_DCTL); 2889 reg &= ~(DWC3_DCTL_HIRD_THRES_MASK | DWC3_DCTL_L1_HIBER_EN); 2890 2891 reg |= DWC3_DCTL_HIRD_THRES(dwc->hird_threshold | 2892 (dwc->is_utmi_l1_suspend << 4)); 2893 2894 /* 2895 * When dwc3 revisions >= 2.40a, LPM Erratum is enabled and 2896 * DCFG.LPMCap is set, core responses with an ACK and the 2897 * BESL value in the LPM token is less than or equal to LPM 2898 * NYET threshold. 2899 */ 2900 WARN_ONCE(dwc->revision < DWC3_REVISION_240A 2901 && dwc->has_lpm_erratum, 2902 "LPM Erratum not available on dwc3 revisions < 2.40a\n"); 2903 2904 if (dwc->has_lpm_erratum && dwc->revision >= DWC3_REVISION_240A) 2905 reg |= DWC3_DCTL_NYET_THRES(dwc->lpm_nyet_threshold); 2906 2907 dwc3_writel(dwc->regs, DWC3_DCTL, reg); 2908 } else { 2909 reg = dwc3_readl(dwc->regs, DWC3_DCTL); 2910 reg &= ~DWC3_DCTL_HIRD_THRES_MASK; 2911 dwc3_writel(dwc->regs, DWC3_DCTL, reg); 2912 } 2913 2914 dep = dwc->eps[0]; 2915 ret = __dwc3_gadget_ep_enable(dep, DWC3_DEPCFG_ACTION_MODIFY); 2916 if (ret) { 2917 dev_err(dwc->dev, "failed to enable %s\n", dep->name); 2918 return; 2919 } 2920 2921 dep = dwc->eps[1]; 2922 ret = __dwc3_gadget_ep_enable(dep, DWC3_DEPCFG_ACTION_MODIFY); 2923 if (ret) { 2924 dev_err(dwc->dev, "failed to enable %s\n", dep->name); 2925 return; 2926 } 2927 2928 /* 2929 * Configure PHY via GUSB3PIPECTLn if required. 2930 * 2931 * Update GTXFIFOSIZn 2932 * 2933 * In both cases reset values should be sufficient. 2934 */ 2935 } 2936 2937 static void dwc3_gadget_wakeup_interrupt(struct dwc3 *dwc) 2938 { 2939 /* 2940 * TODO take core out of low power mode when that's 2941 * implemented. 2942 */ 2943 2944 if (dwc->gadget_driver && dwc->gadget_driver->resume) { 2945 spin_unlock(&dwc->lock); 2946 dwc->gadget_driver->resume(&dwc->gadget); 2947 spin_lock(&dwc->lock); 2948 } 2949 } 2950 2951 static void dwc3_gadget_linksts_change_interrupt(struct dwc3 *dwc, 2952 unsigned int evtinfo) 2953 { 2954 enum dwc3_link_state next = evtinfo & DWC3_LINK_STATE_MASK; 2955 unsigned int pwropt; 2956 2957 /* 2958 * WORKAROUND: DWC3 < 2.50a have an issue when configured without 2959 * Hibernation mode enabled which would show up when device detects 2960 * host-initiated U3 exit. 2961 * 2962 * In that case, device will generate a Link State Change Interrupt 2963 * from U3 to RESUME which is only necessary if Hibernation is 2964 * configured in. 2965 * 2966 * There are no functional changes due to such spurious event and we 2967 * just need to ignore it. 2968 * 2969 * Refers to: 2970 * 2971 * STAR#9000570034 RTL: SS Resume event generated in non-Hibernation 2972 * operational mode 2973 */ 2974 pwropt = DWC3_GHWPARAMS1_EN_PWROPT(dwc->hwparams.hwparams1); 2975 if ((dwc->revision < DWC3_REVISION_250A) && 2976 (pwropt != DWC3_GHWPARAMS1_EN_PWROPT_HIB)) { 2977 if ((dwc->link_state == DWC3_LINK_STATE_U3) && 2978 (next == DWC3_LINK_STATE_RESUME)) { 2979 return; 2980 } 2981 } 2982 2983 /* 2984 * WORKAROUND: DWC3 Revisions <1.83a have an issue which, depending 2985 * on the link partner, the USB session might do multiple entry/exit 2986 * of low power states before a transfer takes place. 2987 * 2988 * Due to this problem, we might experience lower throughput. The 2989 * suggested workaround is to disable DCTL[12:9] bits if we're 2990 * transitioning from U1/U2 to U0 and enable those bits again 2991 * after a transfer completes and there are no pending transfers 2992 * on any of the enabled endpoints. 2993 * 2994 * This is the first half of that workaround. 2995 * 2996 * Refers to: 2997 * 2998 * STAR#9000446952: RTL: Device SS : if U1/U2 ->U0 takes >128us 2999 * core send LGO_Ux entering U0 3000 */ 3001 if (dwc->revision < DWC3_REVISION_183A) { 3002 if (next == DWC3_LINK_STATE_U0) { 3003 u32 u1u2; 3004 u32 reg; 3005 3006 switch (dwc->link_state) { 3007 case DWC3_LINK_STATE_U1: 3008 case DWC3_LINK_STATE_U2: 3009 reg = dwc3_readl(dwc->regs, DWC3_DCTL); 3010 u1u2 = reg & (DWC3_DCTL_INITU2ENA 3011 | DWC3_DCTL_ACCEPTU2ENA 3012 | DWC3_DCTL_INITU1ENA 3013 | DWC3_DCTL_ACCEPTU1ENA); 3014 3015 if (!dwc->u1u2) 3016 dwc->u1u2 = reg & u1u2; 3017 3018 reg &= ~u1u2; 3019 3020 dwc3_writel(dwc->regs, DWC3_DCTL, reg); 3021 break; 3022 default: 3023 /* do nothing */ 3024 break; 3025 } 3026 } 3027 } 3028 3029 switch (next) { 3030 case DWC3_LINK_STATE_U1: 3031 if (dwc->speed == USB_SPEED_SUPER) 3032 dwc3_suspend_gadget(dwc); 3033 break; 3034 case DWC3_LINK_STATE_U2: 3035 case DWC3_LINK_STATE_U3: 3036 dwc3_suspend_gadget(dwc); 3037 break; 3038 case DWC3_LINK_STATE_RESUME: 3039 dwc3_resume_gadget(dwc); 3040 break; 3041 default: 3042 /* do nothing */ 3043 break; 3044 } 3045 3046 dwc->link_state = next; 3047 } 3048 3049 static void dwc3_gadget_suspend_interrupt(struct dwc3 *dwc, 3050 unsigned int evtinfo) 3051 { 3052 enum dwc3_link_state next = evtinfo & DWC3_LINK_STATE_MASK; 3053 3054 if (dwc->link_state != next && next == DWC3_LINK_STATE_U3) 3055 dwc3_suspend_gadget(dwc); 3056 3057 dwc->link_state = next; 3058 } 3059 3060 static void dwc3_gadget_hibernation_interrupt(struct dwc3 *dwc, 3061 unsigned int evtinfo) 3062 { 3063 unsigned int is_ss = evtinfo & BIT(4); 3064 3065 /* 3066 * WORKAROUND: DWC3 revison 2.20a with hibernation support 3067 * have a known issue which can cause USB CV TD.9.23 to fail 3068 * randomly. 3069 * 3070 * Because of this issue, core could generate bogus hibernation 3071 * events which SW needs to ignore. 3072 * 3073 * Refers to: 3074 * 3075 * STAR#9000546576: Device Mode Hibernation: Issue in USB 2.0 3076 * Device Fallback from SuperSpeed 3077 */ 3078 if (is_ss ^ (dwc->speed == USB_SPEED_SUPER)) 3079 return; 3080 3081 /* enter hibernation here */ 3082 } 3083 3084 static void dwc3_gadget_interrupt(struct dwc3 *dwc, 3085 const struct dwc3_event_devt *event) 3086 { 3087 switch (event->type) { 3088 case DWC3_DEVICE_EVENT_DISCONNECT: 3089 dwc3_gadget_disconnect_interrupt(dwc); 3090 break; 3091 case DWC3_DEVICE_EVENT_RESET: 3092 dwc3_gadget_reset_interrupt(dwc); 3093 break; 3094 case DWC3_DEVICE_EVENT_CONNECT_DONE: 3095 dwc3_gadget_conndone_interrupt(dwc); 3096 break; 3097 case DWC3_DEVICE_EVENT_WAKEUP: 3098 dwc3_gadget_wakeup_interrupt(dwc); 3099 break; 3100 case DWC3_DEVICE_EVENT_HIBER_REQ: 3101 if (dev_WARN_ONCE(dwc->dev, !dwc->has_hibernation, 3102 "unexpected hibernation event\n")) 3103 break; 3104 3105 dwc3_gadget_hibernation_interrupt(dwc, event->event_info); 3106 break; 3107 case DWC3_DEVICE_EVENT_LINK_STATUS_CHANGE: 3108 dwc3_gadget_linksts_change_interrupt(dwc, event->event_info); 3109 break; 3110 case DWC3_DEVICE_EVENT_EOPF: 3111 /* It changed to be suspend event for version 2.30a and above */ 3112 if (dwc->revision >= DWC3_REVISION_230A) { 3113 /* 3114 * Ignore suspend event until the gadget enters into 3115 * USB_STATE_CONFIGURED state. 3116 */ 3117 if (dwc->gadget.state >= USB_STATE_CONFIGURED) 3118 dwc3_gadget_suspend_interrupt(dwc, 3119 event->event_info); 3120 } 3121 break; 3122 case DWC3_DEVICE_EVENT_SOF: 3123 case DWC3_DEVICE_EVENT_ERRATIC_ERROR: 3124 case DWC3_DEVICE_EVENT_CMD_CMPL: 3125 case DWC3_DEVICE_EVENT_OVERFLOW: 3126 break; 3127 default: 3128 dev_WARN(dwc->dev, "UNKNOWN IRQ %d\n", event->type); 3129 } 3130 } 3131 3132 static void dwc3_process_event_entry(struct dwc3 *dwc, 3133 const union dwc3_event *event) 3134 { 3135 trace_dwc3_event(event->raw, dwc); 3136 3137 if (!event->type.is_devspec) 3138 dwc3_endpoint_interrupt(dwc, &event->depevt); 3139 else if (event->type.type == DWC3_EVENT_TYPE_DEV) 3140 dwc3_gadget_interrupt(dwc, &event->devt); 3141 else 3142 dev_err(dwc->dev, "UNKNOWN IRQ type %d\n", event->raw); 3143 } 3144 3145 static irqreturn_t dwc3_process_event_buf(struct dwc3_event_buffer *evt) 3146 { 3147 struct dwc3 *dwc = evt->dwc; 3148 irqreturn_t ret = IRQ_NONE; 3149 int left; 3150 u32 reg; 3151 3152 left = evt->count; 3153 3154 if (!(evt->flags & DWC3_EVENT_PENDING)) 3155 return IRQ_NONE; 3156 3157 while (left > 0) { 3158 union dwc3_event event; 3159 3160 event.raw = *(u32 *) (evt->cache + evt->lpos); 3161 3162 dwc3_process_event_entry(dwc, &event); 3163 3164 /* 3165 * FIXME we wrap around correctly to the next entry as 3166 * almost all entries are 4 bytes in size. There is one 3167 * entry which has 12 bytes which is a regular entry 3168 * followed by 8 bytes data. ATM I don't know how 3169 * things are organized if we get next to the a 3170 * boundary so I worry about that once we try to handle 3171 * that. 3172 */ 3173 evt->lpos = (evt->lpos + 4) % evt->length; 3174 left -= 4; 3175 } 3176 3177 evt->count = 0; 3178 evt->flags &= ~DWC3_EVENT_PENDING; 3179 ret = IRQ_HANDLED; 3180 3181 /* Unmask interrupt */ 3182 reg = dwc3_readl(dwc->regs, DWC3_GEVNTSIZ(0)); 3183 reg &= ~DWC3_GEVNTSIZ_INTMASK; 3184 dwc3_writel(dwc->regs, DWC3_GEVNTSIZ(0), reg); 3185 3186 if (dwc->imod_interval) { 3187 dwc3_writel(dwc->regs, DWC3_GEVNTCOUNT(0), DWC3_GEVNTCOUNT_EHB); 3188 dwc3_writel(dwc->regs, DWC3_DEV_IMOD(0), dwc->imod_interval); 3189 } 3190 3191 return ret; 3192 } 3193 3194 static irqreturn_t dwc3_thread_interrupt(int irq, void *_evt) 3195 { 3196 struct dwc3_event_buffer *evt = _evt; 3197 struct dwc3 *dwc = evt->dwc; 3198 unsigned long flags; 3199 irqreturn_t ret = IRQ_NONE; 3200 3201 spin_lock_irqsave(&dwc->lock, flags); 3202 ret = dwc3_process_event_buf(evt); 3203 spin_unlock_irqrestore(&dwc->lock, flags); 3204 3205 return ret; 3206 } 3207 3208 static irqreturn_t dwc3_check_event_buf(struct dwc3_event_buffer *evt) 3209 { 3210 struct dwc3 *dwc = evt->dwc; 3211 u32 amount; 3212 u32 count; 3213 u32 reg; 3214 3215 if (pm_runtime_suspended(dwc->dev)) { 3216 pm_runtime_get(dwc->dev); 3217 disable_irq_nosync(dwc->irq_gadget); 3218 dwc->pending_events = true; 3219 return IRQ_HANDLED; 3220 } 3221 3222 /* 3223 * With PCIe legacy interrupt, test shows that top-half irq handler can 3224 * be called again after HW interrupt deassertion. Check if bottom-half 3225 * irq event handler completes before caching new event to prevent 3226 * losing events. 3227 */ 3228 if (evt->flags & DWC3_EVENT_PENDING) 3229 return IRQ_HANDLED; 3230 3231 count = dwc3_readl(dwc->regs, DWC3_GEVNTCOUNT(0)); 3232 count &= DWC3_GEVNTCOUNT_MASK; 3233 if (!count) 3234 return IRQ_NONE; 3235 3236 evt->count = count; 3237 evt->flags |= DWC3_EVENT_PENDING; 3238 3239 /* Mask interrupt */ 3240 reg = dwc3_readl(dwc->regs, DWC3_GEVNTSIZ(0)); 3241 reg |= DWC3_GEVNTSIZ_INTMASK; 3242 dwc3_writel(dwc->regs, DWC3_GEVNTSIZ(0), reg); 3243 3244 amount = min(count, evt->length - evt->lpos); 3245 memcpy(evt->cache + evt->lpos, evt->buf + evt->lpos, amount); 3246 3247 if (amount < count) 3248 memcpy(evt->cache, evt->buf, count - amount); 3249 3250 dwc3_writel(dwc->regs, DWC3_GEVNTCOUNT(0), count); 3251 3252 return IRQ_WAKE_THREAD; 3253 } 3254 3255 static irqreturn_t dwc3_interrupt(int irq, void *_evt) 3256 { 3257 struct dwc3_event_buffer *evt = _evt; 3258 3259 return dwc3_check_event_buf(evt); 3260 } 3261 3262 static int dwc3_gadget_get_irq(struct dwc3 *dwc) 3263 { 3264 struct platform_device *dwc3_pdev = to_platform_device(dwc->dev); 3265 int irq; 3266 3267 irq = platform_get_irq_byname(dwc3_pdev, "peripheral"); 3268 if (irq > 0) 3269 goto out; 3270 3271 if (irq == -EPROBE_DEFER) 3272 goto out; 3273 3274 irq = platform_get_irq_byname(dwc3_pdev, "dwc_usb3"); 3275 if (irq > 0) 3276 goto out; 3277 3278 if (irq == -EPROBE_DEFER) 3279 goto out; 3280 3281 irq = platform_get_irq(dwc3_pdev, 0); 3282 if (irq > 0) 3283 goto out; 3284 3285 if (irq != -EPROBE_DEFER) 3286 dev_err(dwc->dev, "missing peripheral IRQ\n"); 3287 3288 if (!irq) 3289 irq = -EINVAL; 3290 3291 out: 3292 return irq; 3293 } 3294 3295 /** 3296 * dwc3_gadget_init - initializes gadget related registers 3297 * @dwc: pointer to our controller context structure 3298 * 3299 * Returns 0 on success otherwise negative errno. 3300 */ 3301 int dwc3_gadget_init(struct dwc3 *dwc) 3302 { 3303 int ret; 3304 int irq; 3305 3306 irq = dwc3_gadget_get_irq(dwc); 3307 if (irq < 0) { 3308 ret = irq; 3309 goto err0; 3310 } 3311 3312 dwc->irq_gadget = irq; 3313 3314 dwc->ep0_trb = dma_alloc_coherent(dwc->sysdev, 3315 sizeof(*dwc->ep0_trb) * 2, 3316 &dwc->ep0_trb_addr, GFP_KERNEL); 3317 if (!dwc->ep0_trb) { 3318 dev_err(dwc->dev, "failed to allocate ep0 trb\n"); 3319 ret = -ENOMEM; 3320 goto err0; 3321 } 3322 3323 dwc->setup_buf = kzalloc(DWC3_EP0_SETUP_SIZE, GFP_KERNEL); 3324 if (!dwc->setup_buf) { 3325 ret = -ENOMEM; 3326 goto err1; 3327 } 3328 3329 dwc->bounce = dma_alloc_coherent(dwc->sysdev, DWC3_BOUNCE_SIZE, 3330 &dwc->bounce_addr, GFP_KERNEL); 3331 if (!dwc->bounce) { 3332 ret = -ENOMEM; 3333 goto err2; 3334 } 3335 3336 init_completion(&dwc->ep0_in_setup); 3337 3338 dwc->gadget.ops = &dwc3_gadget_ops; 3339 dwc->gadget.speed = USB_SPEED_UNKNOWN; 3340 dwc->gadget.sg_supported = true; 3341 dwc->gadget.name = "dwc3-gadget"; 3342 dwc->gadget.lpm_capable = true; 3343 3344 /* 3345 * FIXME We might be setting max_speed to <SUPER, however versions 3346 * <2.20a of dwc3 have an issue with metastability (documented 3347 * elsewhere in this driver) which tells us we can't set max speed to 3348 * anything lower than SUPER. 3349 * 3350 * Because gadget.max_speed is only used by composite.c and function 3351 * drivers (i.e. it won't go into dwc3's registers) we are allowing this 3352 * to happen so we avoid sending SuperSpeed Capability descriptor 3353 * together with our BOS descriptor as that could confuse host into 3354 * thinking we can handle super speed. 3355 * 3356 * Note that, in fact, we won't even support GetBOS requests when speed 3357 * is less than super speed because we don't have means, yet, to tell 3358 * composite.c that we are USB 2.0 + LPM ECN. 3359 */ 3360 if (dwc->revision < DWC3_REVISION_220A && 3361 !dwc->dis_metastability_quirk) 3362 dev_info(dwc->dev, "changing max_speed on rev %08x\n", 3363 dwc->revision); 3364 3365 dwc->gadget.max_speed = dwc->maximum_speed; 3366 3367 /* 3368 * REVISIT: Here we should clear all pending IRQs to be 3369 * sure we're starting from a well known location. 3370 */ 3371 3372 ret = dwc3_gadget_init_endpoints(dwc, dwc->num_eps); 3373 if (ret) 3374 goto err3; 3375 3376 ret = usb_add_gadget_udc(dwc->dev, &dwc->gadget); 3377 if (ret) { 3378 dev_err(dwc->dev, "failed to register udc\n"); 3379 goto err4; 3380 } 3381 3382 dwc3_gadget_set_speed(&dwc->gadget, dwc->maximum_speed); 3383 3384 return 0; 3385 3386 err4: 3387 dwc3_gadget_free_endpoints(dwc); 3388 3389 err3: 3390 dma_free_coherent(dwc->sysdev, DWC3_BOUNCE_SIZE, dwc->bounce, 3391 dwc->bounce_addr); 3392 3393 err2: 3394 kfree(dwc->setup_buf); 3395 3396 err1: 3397 dma_free_coherent(dwc->sysdev, sizeof(*dwc->ep0_trb) * 2, 3398 dwc->ep0_trb, dwc->ep0_trb_addr); 3399 3400 err0: 3401 return ret; 3402 } 3403 3404 /* -------------------------------------------------------------------------- */ 3405 3406 void dwc3_gadget_exit(struct dwc3 *dwc) 3407 { 3408 usb_del_gadget_udc(&dwc->gadget); 3409 dwc3_gadget_free_endpoints(dwc); 3410 dma_free_coherent(dwc->sysdev, DWC3_BOUNCE_SIZE, dwc->bounce, 3411 dwc->bounce_addr); 3412 kfree(dwc->setup_buf); 3413 dma_free_coherent(dwc->sysdev, sizeof(*dwc->ep0_trb) * 2, 3414 dwc->ep0_trb, dwc->ep0_trb_addr); 3415 } 3416 3417 int dwc3_gadget_suspend(struct dwc3 *dwc) 3418 { 3419 if (!dwc->gadget_driver) 3420 return 0; 3421 3422 dwc3_gadget_run_stop(dwc, false, false); 3423 dwc3_disconnect_gadget(dwc); 3424 __dwc3_gadget_stop(dwc); 3425 3426 return 0; 3427 } 3428 3429 int dwc3_gadget_resume(struct dwc3 *dwc) 3430 { 3431 int ret; 3432 3433 if (!dwc->gadget_driver) 3434 return 0; 3435 3436 ret = __dwc3_gadget_start(dwc); 3437 if (ret < 0) 3438 goto err0; 3439 3440 ret = dwc3_gadget_run_stop(dwc, true, false); 3441 if (ret < 0) 3442 goto err1; 3443 3444 return 0; 3445 3446 err1: 3447 __dwc3_gadget_stop(dwc); 3448 3449 err0: 3450 return ret; 3451 } 3452 3453 void dwc3_gadget_process_pending_events(struct dwc3 *dwc) 3454 { 3455 if (dwc->pending_events) { 3456 dwc3_interrupt(dwc->irq_gadget, dwc->ev_buf); 3457 dwc->pending_events = false; 3458 enable_irq(dwc->irq_gadget); 3459 } 3460 } 3461