xref: /openbmc/linux/drivers/usb/dwc3/gadget.c (revision 7b73a9c8)
1 // SPDX-License-Identifier: GPL-2.0
2 /*
3  * gadget.c - DesignWare USB3 DRD Controller Gadget Framework Link
4  *
5  * Copyright (C) 2010-2011 Texas Instruments Incorporated - http://www.ti.com
6  *
7  * Authors: Felipe Balbi <balbi@ti.com>,
8  *	    Sebastian Andrzej Siewior <bigeasy@linutronix.de>
9  */
10 
11 #include <linux/kernel.h>
12 #include <linux/delay.h>
13 #include <linux/slab.h>
14 #include <linux/spinlock.h>
15 #include <linux/platform_device.h>
16 #include <linux/pm_runtime.h>
17 #include <linux/interrupt.h>
18 #include <linux/io.h>
19 #include <linux/list.h>
20 #include <linux/dma-mapping.h>
21 
22 #include <linux/usb/ch9.h>
23 #include <linux/usb/gadget.h>
24 
25 #include "debug.h"
26 #include "core.h"
27 #include "gadget.h"
28 #include "io.h"
29 
30 #define DWC3_ALIGN_FRAME(d, n)	(((d)->frame_number + ((d)->interval * (n))) \
31 					& ~((d)->interval - 1))
32 
33 /**
34  * dwc3_gadget_set_test_mode - enables usb2 test modes
35  * @dwc: pointer to our context structure
36  * @mode: the mode to set (J, K SE0 NAK, Force Enable)
37  *
38  * Caller should take care of locking. This function will return 0 on
39  * success or -EINVAL if wrong Test Selector is passed.
40  */
41 int dwc3_gadget_set_test_mode(struct dwc3 *dwc, int mode)
42 {
43 	u32		reg;
44 
45 	reg = dwc3_readl(dwc->regs, DWC3_DCTL);
46 	reg &= ~DWC3_DCTL_TSTCTRL_MASK;
47 
48 	switch (mode) {
49 	case TEST_J:
50 	case TEST_K:
51 	case TEST_SE0_NAK:
52 	case TEST_PACKET:
53 	case TEST_FORCE_EN:
54 		reg |= mode << 1;
55 		break;
56 	default:
57 		return -EINVAL;
58 	}
59 
60 	dwc3_writel(dwc->regs, DWC3_DCTL, reg);
61 
62 	return 0;
63 }
64 
65 /**
66  * dwc3_gadget_get_link_state - gets current state of usb link
67  * @dwc: pointer to our context structure
68  *
69  * Caller should take care of locking. This function will
70  * return the link state on success (>= 0) or -ETIMEDOUT.
71  */
72 int dwc3_gadget_get_link_state(struct dwc3 *dwc)
73 {
74 	u32		reg;
75 
76 	reg = dwc3_readl(dwc->regs, DWC3_DSTS);
77 
78 	return DWC3_DSTS_USBLNKST(reg);
79 }
80 
81 /**
82  * dwc3_gadget_set_link_state - sets usb link to a particular state
83  * @dwc: pointer to our context structure
84  * @state: the state to put link into
85  *
86  * Caller should take care of locking. This function will
87  * return 0 on success or -ETIMEDOUT.
88  */
89 int dwc3_gadget_set_link_state(struct dwc3 *dwc, enum dwc3_link_state state)
90 {
91 	int		retries = 10000;
92 	u32		reg;
93 
94 	/*
95 	 * Wait until device controller is ready. Only applies to 1.94a and
96 	 * later RTL.
97 	 */
98 	if (dwc->revision >= DWC3_REVISION_194A) {
99 		while (--retries) {
100 			reg = dwc3_readl(dwc->regs, DWC3_DSTS);
101 			if (reg & DWC3_DSTS_DCNRD)
102 				udelay(5);
103 			else
104 				break;
105 		}
106 
107 		if (retries <= 0)
108 			return -ETIMEDOUT;
109 	}
110 
111 	reg = dwc3_readl(dwc->regs, DWC3_DCTL);
112 	reg &= ~DWC3_DCTL_ULSTCHNGREQ_MASK;
113 
114 	/* set requested state */
115 	reg |= DWC3_DCTL_ULSTCHNGREQ(state);
116 	dwc3_writel(dwc->regs, DWC3_DCTL, reg);
117 
118 	/*
119 	 * The following code is racy when called from dwc3_gadget_wakeup,
120 	 * and is not needed, at least on newer versions
121 	 */
122 	if (dwc->revision >= DWC3_REVISION_194A)
123 		return 0;
124 
125 	/* wait for a change in DSTS */
126 	retries = 10000;
127 	while (--retries) {
128 		reg = dwc3_readl(dwc->regs, DWC3_DSTS);
129 
130 		if (DWC3_DSTS_USBLNKST(reg) == state)
131 			return 0;
132 
133 		udelay(5);
134 	}
135 
136 	return -ETIMEDOUT;
137 }
138 
139 /**
140  * dwc3_ep_inc_trb - increment a trb index.
141  * @index: Pointer to the TRB index to increment.
142  *
143  * The index should never point to the link TRB. After incrementing,
144  * if it is point to the link TRB, wrap around to the beginning. The
145  * link TRB is always at the last TRB entry.
146  */
147 static void dwc3_ep_inc_trb(u8 *index)
148 {
149 	(*index)++;
150 	if (*index == (DWC3_TRB_NUM - 1))
151 		*index = 0;
152 }
153 
154 /**
155  * dwc3_ep_inc_enq - increment endpoint's enqueue pointer
156  * @dep: The endpoint whose enqueue pointer we're incrementing
157  */
158 static void dwc3_ep_inc_enq(struct dwc3_ep *dep)
159 {
160 	dwc3_ep_inc_trb(&dep->trb_enqueue);
161 }
162 
163 /**
164  * dwc3_ep_inc_deq - increment endpoint's dequeue pointer
165  * @dep: The endpoint whose enqueue pointer we're incrementing
166  */
167 static void dwc3_ep_inc_deq(struct dwc3_ep *dep)
168 {
169 	dwc3_ep_inc_trb(&dep->trb_dequeue);
170 }
171 
172 static void dwc3_gadget_del_and_unmap_request(struct dwc3_ep *dep,
173 		struct dwc3_request *req, int status)
174 {
175 	struct dwc3			*dwc = dep->dwc;
176 
177 	list_del(&req->list);
178 	req->remaining = 0;
179 	req->needs_extra_trb = false;
180 
181 	if (req->request.status == -EINPROGRESS)
182 		req->request.status = status;
183 
184 	if (req->trb)
185 		usb_gadget_unmap_request_by_dev(dwc->sysdev,
186 				&req->request, req->direction);
187 
188 	req->trb = NULL;
189 	trace_dwc3_gadget_giveback(req);
190 
191 	if (dep->number > 1)
192 		pm_runtime_put(dwc->dev);
193 }
194 
195 /**
196  * dwc3_gadget_giveback - call struct usb_request's ->complete callback
197  * @dep: The endpoint to whom the request belongs to
198  * @req: The request we're giving back
199  * @status: completion code for the request
200  *
201  * Must be called with controller's lock held and interrupts disabled. This
202  * function will unmap @req and call its ->complete() callback to notify upper
203  * layers that it has completed.
204  */
205 void dwc3_gadget_giveback(struct dwc3_ep *dep, struct dwc3_request *req,
206 		int status)
207 {
208 	struct dwc3			*dwc = dep->dwc;
209 
210 	dwc3_gadget_del_and_unmap_request(dep, req, status);
211 	req->status = DWC3_REQUEST_STATUS_COMPLETED;
212 
213 	spin_unlock(&dwc->lock);
214 	usb_gadget_giveback_request(&dep->endpoint, &req->request);
215 	spin_lock(&dwc->lock);
216 }
217 
218 /**
219  * dwc3_send_gadget_generic_command - issue a generic command for the controller
220  * @dwc: pointer to the controller context
221  * @cmd: the command to be issued
222  * @param: command parameter
223  *
224  * Caller should take care of locking. Issue @cmd with a given @param to @dwc
225  * and wait for its completion.
226  */
227 int dwc3_send_gadget_generic_command(struct dwc3 *dwc, unsigned cmd, u32 param)
228 {
229 	u32		timeout = 500;
230 	int		status = 0;
231 	int		ret = 0;
232 	u32		reg;
233 
234 	dwc3_writel(dwc->regs, DWC3_DGCMDPAR, param);
235 	dwc3_writel(dwc->regs, DWC3_DGCMD, cmd | DWC3_DGCMD_CMDACT);
236 
237 	do {
238 		reg = dwc3_readl(dwc->regs, DWC3_DGCMD);
239 		if (!(reg & DWC3_DGCMD_CMDACT)) {
240 			status = DWC3_DGCMD_STATUS(reg);
241 			if (status)
242 				ret = -EINVAL;
243 			break;
244 		}
245 	} while (--timeout);
246 
247 	if (!timeout) {
248 		ret = -ETIMEDOUT;
249 		status = -ETIMEDOUT;
250 	}
251 
252 	trace_dwc3_gadget_generic_cmd(cmd, param, status);
253 
254 	return ret;
255 }
256 
257 static int __dwc3_gadget_wakeup(struct dwc3 *dwc);
258 
259 /**
260  * dwc3_send_gadget_ep_cmd - issue an endpoint command
261  * @dep: the endpoint to which the command is going to be issued
262  * @cmd: the command to be issued
263  * @params: parameters to the command
264  *
265  * Caller should handle locking. This function will issue @cmd with given
266  * @params to @dep and wait for its completion.
267  */
268 int dwc3_send_gadget_ep_cmd(struct dwc3_ep *dep, unsigned cmd,
269 		struct dwc3_gadget_ep_cmd_params *params)
270 {
271 	const struct usb_endpoint_descriptor *desc = dep->endpoint.desc;
272 	struct dwc3		*dwc = dep->dwc;
273 	u32			timeout = 1000;
274 	u32			saved_config = 0;
275 	u32			reg;
276 
277 	int			cmd_status = 0;
278 	int			ret = -EINVAL;
279 
280 	/*
281 	 * When operating in USB 2.0 speeds (HS/FS), if GUSB2PHYCFG.ENBLSLPM or
282 	 * GUSB2PHYCFG.SUSPHY is set, it must be cleared before issuing an
283 	 * endpoint command.
284 	 *
285 	 * Save and clear both GUSB2PHYCFG.ENBLSLPM and GUSB2PHYCFG.SUSPHY
286 	 * settings. Restore them after the command is completed.
287 	 *
288 	 * DWC_usb3 3.30a and DWC_usb31 1.90a programming guide section 3.2.2
289 	 */
290 	if (dwc->gadget.speed <= USB_SPEED_HIGH) {
291 		reg = dwc3_readl(dwc->regs, DWC3_GUSB2PHYCFG(0));
292 		if (unlikely(reg & DWC3_GUSB2PHYCFG_SUSPHY)) {
293 			saved_config |= DWC3_GUSB2PHYCFG_SUSPHY;
294 			reg &= ~DWC3_GUSB2PHYCFG_SUSPHY;
295 		}
296 
297 		if (reg & DWC3_GUSB2PHYCFG_ENBLSLPM) {
298 			saved_config |= DWC3_GUSB2PHYCFG_ENBLSLPM;
299 			reg &= ~DWC3_GUSB2PHYCFG_ENBLSLPM;
300 		}
301 
302 		if (saved_config)
303 			dwc3_writel(dwc->regs, DWC3_GUSB2PHYCFG(0), reg);
304 	}
305 
306 	if (DWC3_DEPCMD_CMD(cmd) == DWC3_DEPCMD_STARTTRANSFER) {
307 		int		needs_wakeup;
308 
309 		needs_wakeup = (dwc->link_state == DWC3_LINK_STATE_U1 ||
310 				dwc->link_state == DWC3_LINK_STATE_U2 ||
311 				dwc->link_state == DWC3_LINK_STATE_U3);
312 
313 		if (unlikely(needs_wakeup)) {
314 			ret = __dwc3_gadget_wakeup(dwc);
315 			dev_WARN_ONCE(dwc->dev, ret, "wakeup failed --> %d\n",
316 					ret);
317 		}
318 	}
319 
320 	dwc3_writel(dep->regs, DWC3_DEPCMDPAR0, params->param0);
321 	dwc3_writel(dep->regs, DWC3_DEPCMDPAR1, params->param1);
322 	dwc3_writel(dep->regs, DWC3_DEPCMDPAR2, params->param2);
323 
324 	/*
325 	 * Synopsys Databook 2.60a states in section 6.3.2.5.6 of that if we're
326 	 * not relying on XferNotReady, we can make use of a special "No
327 	 * Response Update Transfer" command where we should clear both CmdAct
328 	 * and CmdIOC bits.
329 	 *
330 	 * With this, we don't need to wait for command completion and can
331 	 * straight away issue further commands to the endpoint.
332 	 *
333 	 * NOTICE: We're making an assumption that control endpoints will never
334 	 * make use of Update Transfer command. This is a safe assumption
335 	 * because we can never have more than one request at a time with
336 	 * Control Endpoints. If anybody changes that assumption, this chunk
337 	 * needs to be updated accordingly.
338 	 */
339 	if (DWC3_DEPCMD_CMD(cmd) == DWC3_DEPCMD_UPDATETRANSFER &&
340 			!usb_endpoint_xfer_isoc(desc))
341 		cmd &= ~(DWC3_DEPCMD_CMDIOC | DWC3_DEPCMD_CMDACT);
342 	else
343 		cmd |= DWC3_DEPCMD_CMDACT;
344 
345 	dwc3_writel(dep->regs, DWC3_DEPCMD, cmd);
346 	do {
347 		reg = dwc3_readl(dep->regs, DWC3_DEPCMD);
348 		if (!(reg & DWC3_DEPCMD_CMDACT)) {
349 			cmd_status = DWC3_DEPCMD_STATUS(reg);
350 
351 			switch (cmd_status) {
352 			case 0:
353 				ret = 0;
354 				break;
355 			case DEPEVT_TRANSFER_NO_RESOURCE:
356 				ret = -EINVAL;
357 				break;
358 			case DEPEVT_TRANSFER_BUS_EXPIRY:
359 				/*
360 				 * SW issues START TRANSFER command to
361 				 * isochronous ep with future frame interval. If
362 				 * future interval time has already passed when
363 				 * core receives the command, it will respond
364 				 * with an error status of 'Bus Expiry'.
365 				 *
366 				 * Instead of always returning -EINVAL, let's
367 				 * give a hint to the gadget driver that this is
368 				 * the case by returning -EAGAIN.
369 				 */
370 				ret = -EAGAIN;
371 				break;
372 			default:
373 				dev_WARN(dwc->dev, "UNKNOWN cmd status\n");
374 			}
375 
376 			break;
377 		}
378 	} while (--timeout);
379 
380 	if (timeout == 0) {
381 		ret = -ETIMEDOUT;
382 		cmd_status = -ETIMEDOUT;
383 	}
384 
385 	trace_dwc3_gadget_ep_cmd(dep, cmd, params, cmd_status);
386 
387 	if (ret == 0 && DWC3_DEPCMD_CMD(cmd) == DWC3_DEPCMD_STARTTRANSFER) {
388 		dep->flags |= DWC3_EP_TRANSFER_STARTED;
389 		dwc3_gadget_ep_get_transfer_index(dep);
390 	}
391 
392 	if (saved_config) {
393 		reg = dwc3_readl(dwc->regs, DWC3_GUSB2PHYCFG(0));
394 		reg |= saved_config;
395 		dwc3_writel(dwc->regs, DWC3_GUSB2PHYCFG(0), reg);
396 	}
397 
398 	return ret;
399 }
400 
401 static int dwc3_send_clear_stall_ep_cmd(struct dwc3_ep *dep)
402 {
403 	struct dwc3 *dwc = dep->dwc;
404 	struct dwc3_gadget_ep_cmd_params params;
405 	u32 cmd = DWC3_DEPCMD_CLEARSTALL;
406 
407 	/*
408 	 * As of core revision 2.60a the recommended programming model
409 	 * is to set the ClearPendIN bit when issuing a Clear Stall EP
410 	 * command for IN endpoints. This is to prevent an issue where
411 	 * some (non-compliant) hosts may not send ACK TPs for pending
412 	 * IN transfers due to a mishandled error condition. Synopsys
413 	 * STAR 9000614252.
414 	 */
415 	if (dep->direction && (dwc->revision >= DWC3_REVISION_260A) &&
416 	    (dwc->gadget.speed >= USB_SPEED_SUPER))
417 		cmd |= DWC3_DEPCMD_CLEARPENDIN;
418 
419 	memset(&params, 0, sizeof(params));
420 
421 	return dwc3_send_gadget_ep_cmd(dep, cmd, &params);
422 }
423 
424 static dma_addr_t dwc3_trb_dma_offset(struct dwc3_ep *dep,
425 		struct dwc3_trb *trb)
426 {
427 	u32		offset = (char *) trb - (char *) dep->trb_pool;
428 
429 	return dep->trb_pool_dma + offset;
430 }
431 
432 static int dwc3_alloc_trb_pool(struct dwc3_ep *dep)
433 {
434 	struct dwc3		*dwc = dep->dwc;
435 
436 	if (dep->trb_pool)
437 		return 0;
438 
439 	dep->trb_pool = dma_alloc_coherent(dwc->sysdev,
440 			sizeof(struct dwc3_trb) * DWC3_TRB_NUM,
441 			&dep->trb_pool_dma, GFP_KERNEL);
442 	if (!dep->trb_pool) {
443 		dev_err(dep->dwc->dev, "failed to allocate trb pool for %s\n",
444 				dep->name);
445 		return -ENOMEM;
446 	}
447 
448 	return 0;
449 }
450 
451 static void dwc3_free_trb_pool(struct dwc3_ep *dep)
452 {
453 	struct dwc3		*dwc = dep->dwc;
454 
455 	dma_free_coherent(dwc->sysdev, sizeof(struct dwc3_trb) * DWC3_TRB_NUM,
456 			dep->trb_pool, dep->trb_pool_dma);
457 
458 	dep->trb_pool = NULL;
459 	dep->trb_pool_dma = 0;
460 }
461 
462 static int dwc3_gadget_set_xfer_resource(struct dwc3_ep *dep)
463 {
464 	struct dwc3_gadget_ep_cmd_params params;
465 
466 	memset(&params, 0x00, sizeof(params));
467 
468 	params.param0 = DWC3_DEPXFERCFG_NUM_XFER_RES(1);
469 
470 	return dwc3_send_gadget_ep_cmd(dep, DWC3_DEPCMD_SETTRANSFRESOURCE,
471 			&params);
472 }
473 
474 /**
475  * dwc3_gadget_start_config - configure ep resources
476  * @dep: endpoint that is being enabled
477  *
478  * Issue a %DWC3_DEPCMD_DEPSTARTCFG command to @dep. After the command's
479  * completion, it will set Transfer Resource for all available endpoints.
480  *
481  * The assignment of transfer resources cannot perfectly follow the data book
482  * due to the fact that the controller driver does not have all knowledge of the
483  * configuration in advance. It is given this information piecemeal by the
484  * composite gadget framework after every SET_CONFIGURATION and
485  * SET_INTERFACE. Trying to follow the databook programming model in this
486  * scenario can cause errors. For two reasons:
487  *
488  * 1) The databook says to do %DWC3_DEPCMD_DEPSTARTCFG for every
489  * %USB_REQ_SET_CONFIGURATION and %USB_REQ_SET_INTERFACE (8.1.5). This is
490  * incorrect in the scenario of multiple interfaces.
491  *
492  * 2) The databook does not mention doing more %DWC3_DEPCMD_DEPXFERCFG for new
493  * endpoint on alt setting (8.1.6).
494  *
495  * The following simplified method is used instead:
496  *
497  * All hardware endpoints can be assigned a transfer resource and this setting
498  * will stay persistent until either a core reset or hibernation. So whenever we
499  * do a %DWC3_DEPCMD_DEPSTARTCFG(0) we can go ahead and do
500  * %DWC3_DEPCMD_DEPXFERCFG for every hardware endpoint as well. We are
501  * guaranteed that there are as many transfer resources as endpoints.
502  *
503  * This function is called for each endpoint when it is being enabled but is
504  * triggered only when called for EP0-out, which always happens first, and which
505  * should only happen in one of the above conditions.
506  */
507 static int dwc3_gadget_start_config(struct dwc3_ep *dep)
508 {
509 	struct dwc3_gadget_ep_cmd_params params;
510 	struct dwc3		*dwc;
511 	u32			cmd;
512 	int			i;
513 	int			ret;
514 
515 	if (dep->number)
516 		return 0;
517 
518 	memset(&params, 0x00, sizeof(params));
519 	cmd = DWC3_DEPCMD_DEPSTARTCFG;
520 	dwc = dep->dwc;
521 
522 	ret = dwc3_send_gadget_ep_cmd(dep, cmd, &params);
523 	if (ret)
524 		return ret;
525 
526 	for (i = 0; i < DWC3_ENDPOINTS_NUM; i++) {
527 		struct dwc3_ep *dep = dwc->eps[i];
528 
529 		if (!dep)
530 			continue;
531 
532 		ret = dwc3_gadget_set_xfer_resource(dep);
533 		if (ret)
534 			return ret;
535 	}
536 
537 	return 0;
538 }
539 
540 static int dwc3_gadget_set_ep_config(struct dwc3_ep *dep, unsigned int action)
541 {
542 	const struct usb_ss_ep_comp_descriptor *comp_desc;
543 	const struct usb_endpoint_descriptor *desc;
544 	struct dwc3_gadget_ep_cmd_params params;
545 	struct dwc3 *dwc = dep->dwc;
546 
547 	comp_desc = dep->endpoint.comp_desc;
548 	desc = dep->endpoint.desc;
549 
550 	memset(&params, 0x00, sizeof(params));
551 
552 	params.param0 = DWC3_DEPCFG_EP_TYPE(usb_endpoint_type(desc))
553 		| DWC3_DEPCFG_MAX_PACKET_SIZE(usb_endpoint_maxp(desc));
554 
555 	/* Burst size is only needed in SuperSpeed mode */
556 	if (dwc->gadget.speed >= USB_SPEED_SUPER) {
557 		u32 burst = dep->endpoint.maxburst;
558 		params.param0 |= DWC3_DEPCFG_BURST_SIZE(burst - 1);
559 	}
560 
561 	params.param0 |= action;
562 	if (action == DWC3_DEPCFG_ACTION_RESTORE)
563 		params.param2 |= dep->saved_state;
564 
565 	if (usb_endpoint_xfer_control(desc))
566 		params.param1 = DWC3_DEPCFG_XFER_COMPLETE_EN;
567 
568 	if (dep->number <= 1 || usb_endpoint_xfer_isoc(desc))
569 		params.param1 |= DWC3_DEPCFG_XFER_NOT_READY_EN;
570 
571 	if (usb_ss_max_streams(comp_desc) && usb_endpoint_xfer_bulk(desc)) {
572 		params.param1 |= DWC3_DEPCFG_STREAM_CAPABLE
573 			| DWC3_DEPCFG_STREAM_EVENT_EN;
574 		dep->stream_capable = true;
575 	}
576 
577 	if (!usb_endpoint_xfer_control(desc))
578 		params.param1 |= DWC3_DEPCFG_XFER_IN_PROGRESS_EN;
579 
580 	/*
581 	 * We are doing 1:1 mapping for endpoints, meaning
582 	 * Physical Endpoints 2 maps to Logical Endpoint 2 and
583 	 * so on. We consider the direction bit as part of the physical
584 	 * endpoint number. So USB endpoint 0x81 is 0x03.
585 	 */
586 	params.param1 |= DWC3_DEPCFG_EP_NUMBER(dep->number);
587 
588 	/*
589 	 * We must use the lower 16 TX FIFOs even though
590 	 * HW might have more
591 	 */
592 	if (dep->direction)
593 		params.param0 |= DWC3_DEPCFG_FIFO_NUMBER(dep->number >> 1);
594 
595 	if (desc->bInterval) {
596 		params.param1 |= DWC3_DEPCFG_BINTERVAL_M1(desc->bInterval - 1);
597 		dep->interval = 1 << (desc->bInterval - 1);
598 	}
599 
600 	return dwc3_send_gadget_ep_cmd(dep, DWC3_DEPCMD_SETEPCONFIG, &params);
601 }
602 
603 /**
604  * __dwc3_gadget_ep_enable - initializes a hw endpoint
605  * @dep: endpoint to be initialized
606  * @action: one of INIT, MODIFY or RESTORE
607  *
608  * Caller should take care of locking. Execute all necessary commands to
609  * initialize a HW endpoint so it can be used by a gadget driver.
610  */
611 static int __dwc3_gadget_ep_enable(struct dwc3_ep *dep, unsigned int action)
612 {
613 	const struct usb_endpoint_descriptor *desc = dep->endpoint.desc;
614 	struct dwc3		*dwc = dep->dwc;
615 
616 	u32			reg;
617 	int			ret;
618 
619 	if (!(dep->flags & DWC3_EP_ENABLED)) {
620 		ret = dwc3_gadget_start_config(dep);
621 		if (ret)
622 			return ret;
623 	}
624 
625 	ret = dwc3_gadget_set_ep_config(dep, action);
626 	if (ret)
627 		return ret;
628 
629 	if (!(dep->flags & DWC3_EP_ENABLED)) {
630 		struct dwc3_trb	*trb_st_hw;
631 		struct dwc3_trb	*trb_link;
632 
633 		dep->type = usb_endpoint_type(desc);
634 		dep->flags |= DWC3_EP_ENABLED;
635 
636 		reg = dwc3_readl(dwc->regs, DWC3_DALEPENA);
637 		reg |= DWC3_DALEPENA_EP(dep->number);
638 		dwc3_writel(dwc->regs, DWC3_DALEPENA, reg);
639 
640 		if (usb_endpoint_xfer_control(desc))
641 			goto out;
642 
643 		/* Initialize the TRB ring */
644 		dep->trb_dequeue = 0;
645 		dep->trb_enqueue = 0;
646 		memset(dep->trb_pool, 0,
647 		       sizeof(struct dwc3_trb) * DWC3_TRB_NUM);
648 
649 		/* Link TRB. The HWO bit is never reset */
650 		trb_st_hw = &dep->trb_pool[0];
651 
652 		trb_link = &dep->trb_pool[DWC3_TRB_NUM - 1];
653 		trb_link->bpl = lower_32_bits(dwc3_trb_dma_offset(dep, trb_st_hw));
654 		trb_link->bph = upper_32_bits(dwc3_trb_dma_offset(dep, trb_st_hw));
655 		trb_link->ctrl |= DWC3_TRBCTL_LINK_TRB;
656 		trb_link->ctrl |= DWC3_TRB_CTRL_HWO;
657 	}
658 
659 	/*
660 	 * Issue StartTransfer here with no-op TRB so we can always rely on No
661 	 * Response Update Transfer command.
662 	 */
663 	if ((usb_endpoint_xfer_bulk(desc) && !dep->stream_capable) ||
664 			usb_endpoint_xfer_int(desc)) {
665 		struct dwc3_gadget_ep_cmd_params params;
666 		struct dwc3_trb	*trb;
667 		dma_addr_t trb_dma;
668 		u32 cmd;
669 
670 		memset(&params, 0, sizeof(params));
671 		trb = &dep->trb_pool[0];
672 		trb_dma = dwc3_trb_dma_offset(dep, trb);
673 
674 		params.param0 = upper_32_bits(trb_dma);
675 		params.param1 = lower_32_bits(trb_dma);
676 
677 		cmd = DWC3_DEPCMD_STARTTRANSFER;
678 
679 		ret = dwc3_send_gadget_ep_cmd(dep, cmd, &params);
680 		if (ret < 0)
681 			return ret;
682 	}
683 
684 out:
685 	trace_dwc3_gadget_ep_enable(dep);
686 
687 	return 0;
688 }
689 
690 static void dwc3_stop_active_transfer(struct dwc3_ep *dep, bool force,
691 		bool interrupt);
692 static void dwc3_remove_requests(struct dwc3 *dwc, struct dwc3_ep *dep)
693 {
694 	struct dwc3_request		*req;
695 
696 	dwc3_stop_active_transfer(dep, true, false);
697 
698 	/* - giveback all requests to gadget driver */
699 	while (!list_empty(&dep->started_list)) {
700 		req = next_request(&dep->started_list);
701 
702 		dwc3_gadget_giveback(dep, req, -ESHUTDOWN);
703 	}
704 
705 	while (!list_empty(&dep->pending_list)) {
706 		req = next_request(&dep->pending_list);
707 
708 		dwc3_gadget_giveback(dep, req, -ESHUTDOWN);
709 	}
710 
711 	while (!list_empty(&dep->cancelled_list)) {
712 		req = next_request(&dep->cancelled_list);
713 
714 		dwc3_gadget_giveback(dep, req, -ESHUTDOWN);
715 	}
716 }
717 
718 /**
719  * __dwc3_gadget_ep_disable - disables a hw endpoint
720  * @dep: the endpoint to disable
721  *
722  * This function undoes what __dwc3_gadget_ep_enable did and also removes
723  * requests which are currently being processed by the hardware and those which
724  * are not yet scheduled.
725  *
726  * Caller should take care of locking.
727  */
728 static int __dwc3_gadget_ep_disable(struct dwc3_ep *dep)
729 {
730 	struct dwc3		*dwc = dep->dwc;
731 	u32			reg;
732 
733 	trace_dwc3_gadget_ep_disable(dep);
734 
735 	dwc3_remove_requests(dwc, dep);
736 
737 	/* make sure HW endpoint isn't stalled */
738 	if (dep->flags & DWC3_EP_STALL)
739 		__dwc3_gadget_ep_set_halt(dep, 0, false);
740 
741 	reg = dwc3_readl(dwc->regs, DWC3_DALEPENA);
742 	reg &= ~DWC3_DALEPENA_EP(dep->number);
743 	dwc3_writel(dwc->regs, DWC3_DALEPENA, reg);
744 
745 	dep->stream_capable = false;
746 	dep->type = 0;
747 	dep->flags = 0;
748 
749 	/* Clear out the ep descriptors for non-ep0 */
750 	if (dep->number > 1) {
751 		dep->endpoint.comp_desc = NULL;
752 		dep->endpoint.desc = NULL;
753 	}
754 
755 	return 0;
756 }
757 
758 /* -------------------------------------------------------------------------- */
759 
760 static int dwc3_gadget_ep0_enable(struct usb_ep *ep,
761 		const struct usb_endpoint_descriptor *desc)
762 {
763 	return -EINVAL;
764 }
765 
766 static int dwc3_gadget_ep0_disable(struct usb_ep *ep)
767 {
768 	return -EINVAL;
769 }
770 
771 /* -------------------------------------------------------------------------- */
772 
773 static int dwc3_gadget_ep_enable(struct usb_ep *ep,
774 		const struct usb_endpoint_descriptor *desc)
775 {
776 	struct dwc3_ep			*dep;
777 	struct dwc3			*dwc;
778 	unsigned long			flags;
779 	int				ret;
780 
781 	if (!ep || !desc || desc->bDescriptorType != USB_DT_ENDPOINT) {
782 		pr_debug("dwc3: invalid parameters\n");
783 		return -EINVAL;
784 	}
785 
786 	if (!desc->wMaxPacketSize) {
787 		pr_debug("dwc3: missing wMaxPacketSize\n");
788 		return -EINVAL;
789 	}
790 
791 	dep = to_dwc3_ep(ep);
792 	dwc = dep->dwc;
793 
794 	if (dev_WARN_ONCE(dwc->dev, dep->flags & DWC3_EP_ENABLED,
795 					"%s is already enabled\n",
796 					dep->name))
797 		return 0;
798 
799 	spin_lock_irqsave(&dwc->lock, flags);
800 	ret = __dwc3_gadget_ep_enable(dep, DWC3_DEPCFG_ACTION_INIT);
801 	spin_unlock_irqrestore(&dwc->lock, flags);
802 
803 	return ret;
804 }
805 
806 static int dwc3_gadget_ep_disable(struct usb_ep *ep)
807 {
808 	struct dwc3_ep			*dep;
809 	struct dwc3			*dwc;
810 	unsigned long			flags;
811 	int				ret;
812 
813 	if (!ep) {
814 		pr_debug("dwc3: invalid parameters\n");
815 		return -EINVAL;
816 	}
817 
818 	dep = to_dwc3_ep(ep);
819 	dwc = dep->dwc;
820 
821 	if (dev_WARN_ONCE(dwc->dev, !(dep->flags & DWC3_EP_ENABLED),
822 					"%s is already disabled\n",
823 					dep->name))
824 		return 0;
825 
826 	spin_lock_irqsave(&dwc->lock, flags);
827 	ret = __dwc3_gadget_ep_disable(dep);
828 	spin_unlock_irqrestore(&dwc->lock, flags);
829 
830 	return ret;
831 }
832 
833 static struct usb_request *dwc3_gadget_ep_alloc_request(struct usb_ep *ep,
834 		gfp_t gfp_flags)
835 {
836 	struct dwc3_request		*req;
837 	struct dwc3_ep			*dep = to_dwc3_ep(ep);
838 
839 	req = kzalloc(sizeof(*req), gfp_flags);
840 	if (!req)
841 		return NULL;
842 
843 	req->direction	= dep->direction;
844 	req->epnum	= dep->number;
845 	req->dep	= dep;
846 	req->status	= DWC3_REQUEST_STATUS_UNKNOWN;
847 
848 	trace_dwc3_alloc_request(req);
849 
850 	return &req->request;
851 }
852 
853 static void dwc3_gadget_ep_free_request(struct usb_ep *ep,
854 		struct usb_request *request)
855 {
856 	struct dwc3_request		*req = to_dwc3_request(request);
857 
858 	trace_dwc3_free_request(req);
859 	kfree(req);
860 }
861 
862 /**
863  * dwc3_ep_prev_trb - returns the previous TRB in the ring
864  * @dep: The endpoint with the TRB ring
865  * @index: The index of the current TRB in the ring
866  *
867  * Returns the TRB prior to the one pointed to by the index. If the
868  * index is 0, we will wrap backwards, skip the link TRB, and return
869  * the one just before that.
870  */
871 static struct dwc3_trb *dwc3_ep_prev_trb(struct dwc3_ep *dep, u8 index)
872 {
873 	u8 tmp = index;
874 
875 	if (!tmp)
876 		tmp = DWC3_TRB_NUM - 1;
877 
878 	return &dep->trb_pool[tmp - 1];
879 }
880 
881 static u32 dwc3_calc_trbs_left(struct dwc3_ep *dep)
882 {
883 	struct dwc3_trb		*tmp;
884 	u8			trbs_left;
885 
886 	/*
887 	 * If enqueue & dequeue are equal than it is either full or empty.
888 	 *
889 	 * One way to know for sure is if the TRB right before us has HWO bit
890 	 * set or not. If it has, then we're definitely full and can't fit any
891 	 * more transfers in our ring.
892 	 */
893 	if (dep->trb_enqueue == dep->trb_dequeue) {
894 		tmp = dwc3_ep_prev_trb(dep, dep->trb_enqueue);
895 		if (tmp->ctrl & DWC3_TRB_CTRL_HWO)
896 			return 0;
897 
898 		return DWC3_TRB_NUM - 1;
899 	}
900 
901 	trbs_left = dep->trb_dequeue - dep->trb_enqueue;
902 	trbs_left &= (DWC3_TRB_NUM - 1);
903 
904 	if (dep->trb_dequeue < dep->trb_enqueue)
905 		trbs_left--;
906 
907 	return trbs_left;
908 }
909 
910 static void __dwc3_prepare_one_trb(struct dwc3_ep *dep, struct dwc3_trb *trb,
911 		dma_addr_t dma, unsigned length, unsigned chain, unsigned node,
912 		unsigned stream_id, unsigned short_not_ok, unsigned no_interrupt)
913 {
914 	struct dwc3		*dwc = dep->dwc;
915 	struct usb_gadget	*gadget = &dwc->gadget;
916 	enum usb_device_speed	speed = gadget->speed;
917 
918 	trb->size = DWC3_TRB_SIZE_LENGTH(length);
919 	trb->bpl = lower_32_bits(dma);
920 	trb->bph = upper_32_bits(dma);
921 
922 	switch (usb_endpoint_type(dep->endpoint.desc)) {
923 	case USB_ENDPOINT_XFER_CONTROL:
924 		trb->ctrl = DWC3_TRBCTL_CONTROL_SETUP;
925 		break;
926 
927 	case USB_ENDPOINT_XFER_ISOC:
928 		if (!node) {
929 			trb->ctrl = DWC3_TRBCTL_ISOCHRONOUS_FIRST;
930 
931 			/*
932 			 * USB Specification 2.0 Section 5.9.2 states that: "If
933 			 * there is only a single transaction in the microframe,
934 			 * only a DATA0 data packet PID is used.  If there are
935 			 * two transactions per microframe, DATA1 is used for
936 			 * the first transaction data packet and DATA0 is used
937 			 * for the second transaction data packet.  If there are
938 			 * three transactions per microframe, DATA2 is used for
939 			 * the first transaction data packet, DATA1 is used for
940 			 * the second, and DATA0 is used for the third."
941 			 *
942 			 * IOW, we should satisfy the following cases:
943 			 *
944 			 * 1) length <= maxpacket
945 			 *	- DATA0
946 			 *
947 			 * 2) maxpacket < length <= (2 * maxpacket)
948 			 *	- DATA1, DATA0
949 			 *
950 			 * 3) (2 * maxpacket) < length <= (3 * maxpacket)
951 			 *	- DATA2, DATA1, DATA0
952 			 */
953 			if (speed == USB_SPEED_HIGH) {
954 				struct usb_ep *ep = &dep->endpoint;
955 				unsigned int mult = 2;
956 				unsigned int maxp = usb_endpoint_maxp(ep->desc);
957 
958 				if (length <= (2 * maxp))
959 					mult--;
960 
961 				if (length <= maxp)
962 					mult--;
963 
964 				trb->size |= DWC3_TRB_SIZE_PCM1(mult);
965 			}
966 		} else {
967 			trb->ctrl = DWC3_TRBCTL_ISOCHRONOUS;
968 		}
969 
970 		/* always enable Interrupt on Missed ISOC */
971 		trb->ctrl |= DWC3_TRB_CTRL_ISP_IMI;
972 		break;
973 
974 	case USB_ENDPOINT_XFER_BULK:
975 	case USB_ENDPOINT_XFER_INT:
976 		trb->ctrl = DWC3_TRBCTL_NORMAL;
977 		break;
978 	default:
979 		/*
980 		 * This is only possible with faulty memory because we
981 		 * checked it already :)
982 		 */
983 		dev_WARN(dwc->dev, "Unknown endpoint type %d\n",
984 				usb_endpoint_type(dep->endpoint.desc));
985 	}
986 
987 	/*
988 	 * Enable Continue on Short Packet
989 	 * when endpoint is not a stream capable
990 	 */
991 	if (usb_endpoint_dir_out(dep->endpoint.desc)) {
992 		if (!dep->stream_capable)
993 			trb->ctrl |= DWC3_TRB_CTRL_CSP;
994 
995 		if (short_not_ok)
996 			trb->ctrl |= DWC3_TRB_CTRL_ISP_IMI;
997 	}
998 
999 	if ((!no_interrupt && !chain) ||
1000 			(dwc3_calc_trbs_left(dep) == 1))
1001 		trb->ctrl |= DWC3_TRB_CTRL_IOC;
1002 
1003 	if (chain)
1004 		trb->ctrl |= DWC3_TRB_CTRL_CHN;
1005 
1006 	if (usb_endpoint_xfer_bulk(dep->endpoint.desc) && dep->stream_capable)
1007 		trb->ctrl |= DWC3_TRB_CTRL_SID_SOFN(stream_id);
1008 
1009 	trb->ctrl |= DWC3_TRB_CTRL_HWO;
1010 
1011 	dwc3_ep_inc_enq(dep);
1012 
1013 	trace_dwc3_prepare_trb(dep, trb);
1014 }
1015 
1016 /**
1017  * dwc3_prepare_one_trb - setup one TRB from one request
1018  * @dep: endpoint for which this request is prepared
1019  * @req: dwc3_request pointer
1020  * @chain: should this TRB be chained to the next?
1021  * @node: only for isochronous endpoints. First TRB needs different type.
1022  */
1023 static void dwc3_prepare_one_trb(struct dwc3_ep *dep,
1024 		struct dwc3_request *req, unsigned chain, unsigned node)
1025 {
1026 	struct dwc3_trb		*trb;
1027 	unsigned int		length;
1028 	dma_addr_t		dma;
1029 	unsigned		stream_id = req->request.stream_id;
1030 	unsigned		short_not_ok = req->request.short_not_ok;
1031 	unsigned		no_interrupt = req->request.no_interrupt;
1032 
1033 	if (req->request.num_sgs > 0) {
1034 		length = sg_dma_len(req->start_sg);
1035 		dma = sg_dma_address(req->start_sg);
1036 	} else {
1037 		length = req->request.length;
1038 		dma = req->request.dma;
1039 	}
1040 
1041 	trb = &dep->trb_pool[dep->trb_enqueue];
1042 
1043 	if (!req->trb) {
1044 		dwc3_gadget_move_started_request(req);
1045 		req->trb = trb;
1046 		req->trb_dma = dwc3_trb_dma_offset(dep, trb);
1047 	}
1048 
1049 	req->num_trbs++;
1050 
1051 	__dwc3_prepare_one_trb(dep, trb, dma, length, chain, node,
1052 			stream_id, short_not_ok, no_interrupt);
1053 }
1054 
1055 static void dwc3_prepare_one_trb_sg(struct dwc3_ep *dep,
1056 		struct dwc3_request *req)
1057 {
1058 	struct scatterlist *sg = req->start_sg;
1059 	struct scatterlist *s;
1060 	int		i;
1061 
1062 	unsigned int remaining = req->request.num_mapped_sgs
1063 		- req->num_queued_sgs;
1064 
1065 	for_each_sg(sg, s, remaining, i) {
1066 		unsigned int length = req->request.length;
1067 		unsigned int maxp = usb_endpoint_maxp(dep->endpoint.desc);
1068 		unsigned int rem = length % maxp;
1069 		unsigned chain = true;
1070 
1071 		if (sg_is_last(s))
1072 			chain = false;
1073 
1074 		if (rem && usb_endpoint_dir_out(dep->endpoint.desc) && !chain) {
1075 			struct dwc3	*dwc = dep->dwc;
1076 			struct dwc3_trb	*trb;
1077 
1078 			req->needs_extra_trb = true;
1079 
1080 			/* prepare normal TRB */
1081 			dwc3_prepare_one_trb(dep, req, true, i);
1082 
1083 			/* Now prepare one extra TRB to align transfer size */
1084 			trb = &dep->trb_pool[dep->trb_enqueue];
1085 			req->num_trbs++;
1086 			__dwc3_prepare_one_trb(dep, trb, dwc->bounce_addr,
1087 					maxp - rem, false, 1,
1088 					req->request.stream_id,
1089 					req->request.short_not_ok,
1090 					req->request.no_interrupt);
1091 		} else {
1092 			dwc3_prepare_one_trb(dep, req, chain, i);
1093 		}
1094 
1095 		/*
1096 		 * There can be a situation where all sgs in sglist are not
1097 		 * queued because of insufficient trb number. To handle this
1098 		 * case, update start_sg to next sg to be queued, so that
1099 		 * we have free trbs we can continue queuing from where we
1100 		 * previously stopped
1101 		 */
1102 		if (chain)
1103 			req->start_sg = sg_next(s);
1104 
1105 		req->num_queued_sgs++;
1106 
1107 		if (!dwc3_calc_trbs_left(dep))
1108 			break;
1109 	}
1110 }
1111 
1112 static void dwc3_prepare_one_trb_linear(struct dwc3_ep *dep,
1113 		struct dwc3_request *req)
1114 {
1115 	unsigned int length = req->request.length;
1116 	unsigned int maxp = usb_endpoint_maxp(dep->endpoint.desc);
1117 	unsigned int rem = length % maxp;
1118 
1119 	if ((!length || rem) && usb_endpoint_dir_out(dep->endpoint.desc)) {
1120 		struct dwc3	*dwc = dep->dwc;
1121 		struct dwc3_trb	*trb;
1122 
1123 		req->needs_extra_trb = true;
1124 
1125 		/* prepare normal TRB */
1126 		dwc3_prepare_one_trb(dep, req, true, 0);
1127 
1128 		/* Now prepare one extra TRB to align transfer size */
1129 		trb = &dep->trb_pool[dep->trb_enqueue];
1130 		req->num_trbs++;
1131 		__dwc3_prepare_one_trb(dep, trb, dwc->bounce_addr, maxp - rem,
1132 				false, 1, req->request.stream_id,
1133 				req->request.short_not_ok,
1134 				req->request.no_interrupt);
1135 	} else if (req->request.zero && req->request.length &&
1136 		   (IS_ALIGNED(req->request.length, maxp))) {
1137 		struct dwc3	*dwc = dep->dwc;
1138 		struct dwc3_trb	*trb;
1139 
1140 		req->needs_extra_trb = true;
1141 
1142 		/* prepare normal TRB */
1143 		dwc3_prepare_one_trb(dep, req, true, 0);
1144 
1145 		/* Now prepare one extra TRB to handle ZLP */
1146 		trb = &dep->trb_pool[dep->trb_enqueue];
1147 		req->num_trbs++;
1148 		__dwc3_prepare_one_trb(dep, trb, dwc->bounce_addr, 0,
1149 				false, 1, req->request.stream_id,
1150 				req->request.short_not_ok,
1151 				req->request.no_interrupt);
1152 	} else {
1153 		dwc3_prepare_one_trb(dep, req, false, 0);
1154 	}
1155 }
1156 
1157 /*
1158  * dwc3_prepare_trbs - setup TRBs from requests
1159  * @dep: endpoint for which requests are being prepared
1160  *
1161  * The function goes through the requests list and sets up TRBs for the
1162  * transfers. The function returns once there are no more TRBs available or
1163  * it runs out of requests.
1164  */
1165 static void dwc3_prepare_trbs(struct dwc3_ep *dep)
1166 {
1167 	struct dwc3_request	*req, *n;
1168 
1169 	BUILD_BUG_ON_NOT_POWER_OF_2(DWC3_TRB_NUM);
1170 
1171 	/*
1172 	 * We can get in a situation where there's a request in the started list
1173 	 * but there weren't enough TRBs to fully kick it in the first time
1174 	 * around, so it has been waiting for more TRBs to be freed up.
1175 	 *
1176 	 * In that case, we should check if we have a request with pending_sgs
1177 	 * in the started list and prepare TRBs for that request first,
1178 	 * otherwise we will prepare TRBs completely out of order and that will
1179 	 * break things.
1180 	 */
1181 	list_for_each_entry(req, &dep->started_list, list) {
1182 		if (req->num_pending_sgs > 0)
1183 			dwc3_prepare_one_trb_sg(dep, req);
1184 
1185 		if (!dwc3_calc_trbs_left(dep))
1186 			return;
1187 	}
1188 
1189 	list_for_each_entry_safe(req, n, &dep->pending_list, list) {
1190 		struct dwc3	*dwc = dep->dwc;
1191 		int		ret;
1192 
1193 		ret = usb_gadget_map_request_by_dev(dwc->sysdev, &req->request,
1194 						    dep->direction);
1195 		if (ret)
1196 			return;
1197 
1198 		req->sg			= req->request.sg;
1199 		req->start_sg		= req->sg;
1200 		req->num_queued_sgs	= 0;
1201 		req->num_pending_sgs	= req->request.num_mapped_sgs;
1202 
1203 		if (req->num_pending_sgs > 0)
1204 			dwc3_prepare_one_trb_sg(dep, req);
1205 		else
1206 			dwc3_prepare_one_trb_linear(dep, req);
1207 
1208 		if (!dwc3_calc_trbs_left(dep))
1209 			return;
1210 	}
1211 }
1212 
1213 static int __dwc3_gadget_kick_transfer(struct dwc3_ep *dep)
1214 {
1215 	struct dwc3_gadget_ep_cmd_params params;
1216 	struct dwc3_request		*req;
1217 	int				starting;
1218 	int				ret;
1219 	u32				cmd;
1220 
1221 	if (!dwc3_calc_trbs_left(dep))
1222 		return 0;
1223 
1224 	starting = !(dep->flags & DWC3_EP_TRANSFER_STARTED);
1225 
1226 	dwc3_prepare_trbs(dep);
1227 	req = next_request(&dep->started_list);
1228 	if (!req) {
1229 		dep->flags |= DWC3_EP_PENDING_REQUEST;
1230 		return 0;
1231 	}
1232 
1233 	memset(&params, 0, sizeof(params));
1234 
1235 	if (starting) {
1236 		params.param0 = upper_32_bits(req->trb_dma);
1237 		params.param1 = lower_32_bits(req->trb_dma);
1238 		cmd = DWC3_DEPCMD_STARTTRANSFER;
1239 
1240 		if (dep->stream_capable)
1241 			cmd |= DWC3_DEPCMD_PARAM(req->request.stream_id);
1242 
1243 		if (usb_endpoint_xfer_isoc(dep->endpoint.desc))
1244 			cmd |= DWC3_DEPCMD_PARAM(dep->frame_number);
1245 	} else {
1246 		cmd = DWC3_DEPCMD_UPDATETRANSFER |
1247 			DWC3_DEPCMD_PARAM(dep->resource_index);
1248 	}
1249 
1250 	ret = dwc3_send_gadget_ep_cmd(dep, cmd, &params);
1251 	if (ret < 0) {
1252 		/*
1253 		 * FIXME we need to iterate over the list of requests
1254 		 * here and stop, unmap, free and del each of the linked
1255 		 * requests instead of what we do now.
1256 		 */
1257 		if (req->trb)
1258 			memset(req->trb, 0, sizeof(struct dwc3_trb));
1259 		dwc3_gadget_del_and_unmap_request(dep, req, ret);
1260 		return ret;
1261 	}
1262 
1263 	return 0;
1264 }
1265 
1266 static int __dwc3_gadget_get_frame(struct dwc3 *dwc)
1267 {
1268 	u32			reg;
1269 
1270 	reg = dwc3_readl(dwc->regs, DWC3_DSTS);
1271 	return DWC3_DSTS_SOFFN(reg);
1272 }
1273 
1274 /**
1275  * dwc3_gadget_start_isoc_quirk - workaround invalid frame number
1276  * @dep: isoc endpoint
1277  *
1278  * This function tests for the correct combination of BIT[15:14] from the 16-bit
1279  * microframe number reported by the XferNotReady event for the future frame
1280  * number to start the isoc transfer.
1281  *
1282  * In DWC_usb31 version 1.70a-ea06 and prior, for highspeed and fullspeed
1283  * isochronous IN, BIT[15:14] of the 16-bit microframe number reported by the
1284  * XferNotReady event are invalid. The driver uses this number to schedule the
1285  * isochronous transfer and passes it to the START TRANSFER command. Because
1286  * this number is invalid, the command may fail. If BIT[15:14] matches the
1287  * internal 16-bit microframe, the START TRANSFER command will pass and the
1288  * transfer will start at the scheduled time, if it is off by 1, the command
1289  * will still pass, but the transfer will start 2 seconds in the future. For all
1290  * other conditions, the START TRANSFER command will fail with bus-expiry.
1291  *
1292  * In order to workaround this issue, we can test for the correct combination of
1293  * BIT[15:14] by sending START TRANSFER commands with different values of
1294  * BIT[15:14]: 'b00, 'b01, 'b10, and 'b11. Each combination is 2^14 uframe apart
1295  * (or 2 seconds). 4 seconds into the future will result in a bus-expiry status.
1296  * As the result, within the 4 possible combinations for BIT[15:14], there will
1297  * be 2 successful and 2 failure START COMMAND status. One of the 2 successful
1298  * command status will result in a 2-second delay start. The smaller BIT[15:14]
1299  * value is the correct combination.
1300  *
1301  * Since there are only 4 outcomes and the results are ordered, we can simply
1302  * test 2 START TRANSFER commands with BIT[15:14] combinations 'b00 and 'b01 to
1303  * deduce the smaller successful combination.
1304  *
1305  * Let test0 = test status for combination 'b00 and test1 = test status for 'b01
1306  * of BIT[15:14]. The correct combination is as follow:
1307  *
1308  * if test0 fails and test1 passes, BIT[15:14] is 'b01
1309  * if test0 fails and test1 fails, BIT[15:14] is 'b10
1310  * if test0 passes and test1 fails, BIT[15:14] is 'b11
1311  * if test0 passes and test1 passes, BIT[15:14] is 'b00
1312  *
1313  * Synopsys STAR 9001202023: Wrong microframe number for isochronous IN
1314  * endpoints.
1315  */
1316 static int dwc3_gadget_start_isoc_quirk(struct dwc3_ep *dep)
1317 {
1318 	int cmd_status = 0;
1319 	bool test0;
1320 	bool test1;
1321 
1322 	while (dep->combo_num < 2) {
1323 		struct dwc3_gadget_ep_cmd_params params;
1324 		u32 test_frame_number;
1325 		u32 cmd;
1326 
1327 		/*
1328 		 * Check if we can start isoc transfer on the next interval or
1329 		 * 4 uframes in the future with BIT[15:14] as dep->combo_num
1330 		 */
1331 		test_frame_number = dep->frame_number & 0x3fff;
1332 		test_frame_number |= dep->combo_num << 14;
1333 		test_frame_number += max_t(u32, 4, dep->interval);
1334 
1335 		params.param0 = upper_32_bits(dep->dwc->bounce_addr);
1336 		params.param1 = lower_32_bits(dep->dwc->bounce_addr);
1337 
1338 		cmd = DWC3_DEPCMD_STARTTRANSFER;
1339 		cmd |= DWC3_DEPCMD_PARAM(test_frame_number);
1340 		cmd_status = dwc3_send_gadget_ep_cmd(dep, cmd, &params);
1341 
1342 		/* Redo if some other failure beside bus-expiry is received */
1343 		if (cmd_status && cmd_status != -EAGAIN) {
1344 			dep->start_cmd_status = 0;
1345 			dep->combo_num = 0;
1346 			return 0;
1347 		}
1348 
1349 		/* Store the first test status */
1350 		if (dep->combo_num == 0)
1351 			dep->start_cmd_status = cmd_status;
1352 
1353 		dep->combo_num++;
1354 
1355 		/*
1356 		 * End the transfer if the START_TRANSFER command is successful
1357 		 * to wait for the next XferNotReady to test the command again
1358 		 */
1359 		if (cmd_status == 0) {
1360 			dwc3_stop_active_transfer(dep, true, true);
1361 			return 0;
1362 		}
1363 	}
1364 
1365 	/* test0 and test1 are both completed at this point */
1366 	test0 = (dep->start_cmd_status == 0);
1367 	test1 = (cmd_status == 0);
1368 
1369 	if (!test0 && test1)
1370 		dep->combo_num = 1;
1371 	else if (!test0 && !test1)
1372 		dep->combo_num = 2;
1373 	else if (test0 && !test1)
1374 		dep->combo_num = 3;
1375 	else if (test0 && test1)
1376 		dep->combo_num = 0;
1377 
1378 	dep->frame_number &= 0x3fff;
1379 	dep->frame_number |= dep->combo_num << 14;
1380 	dep->frame_number += max_t(u32, 4, dep->interval);
1381 
1382 	/* Reinitialize test variables */
1383 	dep->start_cmd_status = 0;
1384 	dep->combo_num = 0;
1385 
1386 	return __dwc3_gadget_kick_transfer(dep);
1387 }
1388 
1389 static int __dwc3_gadget_start_isoc(struct dwc3_ep *dep)
1390 {
1391 	struct dwc3 *dwc = dep->dwc;
1392 	int ret;
1393 	int i;
1394 
1395 	if (list_empty(&dep->pending_list)) {
1396 		dep->flags |= DWC3_EP_PENDING_REQUEST;
1397 		return -EAGAIN;
1398 	}
1399 
1400 	if (!dwc->dis_start_transfer_quirk && dwc3_is_usb31(dwc) &&
1401 	    (dwc->revision <= DWC3_USB31_REVISION_160A ||
1402 	     (dwc->revision == DWC3_USB31_REVISION_170A &&
1403 	      dwc->version_type >= DWC31_VERSIONTYPE_EA01 &&
1404 	      dwc->version_type <= DWC31_VERSIONTYPE_EA06))) {
1405 
1406 		if (dwc->gadget.speed <= USB_SPEED_HIGH && dep->direction)
1407 			return dwc3_gadget_start_isoc_quirk(dep);
1408 	}
1409 
1410 	for (i = 0; i < DWC3_ISOC_MAX_RETRIES; i++) {
1411 		dep->frame_number = DWC3_ALIGN_FRAME(dep, i + 1);
1412 
1413 		ret = __dwc3_gadget_kick_transfer(dep);
1414 		if (ret != -EAGAIN)
1415 			break;
1416 	}
1417 
1418 	return ret;
1419 }
1420 
1421 static int __dwc3_gadget_ep_queue(struct dwc3_ep *dep, struct dwc3_request *req)
1422 {
1423 	struct dwc3		*dwc = dep->dwc;
1424 
1425 	if (!dep->endpoint.desc) {
1426 		dev_err(dwc->dev, "%s: can't queue to disabled endpoint\n",
1427 				dep->name);
1428 		return -ESHUTDOWN;
1429 	}
1430 
1431 	if (WARN(req->dep != dep, "request %pK belongs to '%s'\n",
1432 				&req->request, req->dep->name))
1433 		return -EINVAL;
1434 
1435 	if (WARN(req->status < DWC3_REQUEST_STATUS_COMPLETED,
1436 				"%s: request %pK already in flight\n",
1437 				dep->name, &req->request))
1438 		return -EINVAL;
1439 
1440 	pm_runtime_get(dwc->dev);
1441 
1442 	req->request.actual	= 0;
1443 	req->request.status	= -EINPROGRESS;
1444 
1445 	trace_dwc3_ep_queue(req);
1446 
1447 	list_add_tail(&req->list, &dep->pending_list);
1448 	req->status = DWC3_REQUEST_STATUS_QUEUED;
1449 
1450 	/*
1451 	 * NOTICE: Isochronous endpoints should NEVER be prestarted. We must
1452 	 * wait for a XferNotReady event so we will know what's the current
1453 	 * (micro-)frame number.
1454 	 *
1455 	 * Without this trick, we are very, very likely gonna get Bus Expiry
1456 	 * errors which will force us issue EndTransfer command.
1457 	 */
1458 	if (usb_endpoint_xfer_isoc(dep->endpoint.desc)) {
1459 		if (!(dep->flags & DWC3_EP_PENDING_REQUEST) &&
1460 				!(dep->flags & DWC3_EP_TRANSFER_STARTED))
1461 			return 0;
1462 
1463 		if ((dep->flags & DWC3_EP_PENDING_REQUEST)) {
1464 			if (!(dep->flags & DWC3_EP_TRANSFER_STARTED)) {
1465 				return __dwc3_gadget_start_isoc(dep);
1466 			}
1467 		}
1468 	}
1469 
1470 	return __dwc3_gadget_kick_transfer(dep);
1471 }
1472 
1473 static int dwc3_gadget_ep_queue(struct usb_ep *ep, struct usb_request *request,
1474 	gfp_t gfp_flags)
1475 {
1476 	struct dwc3_request		*req = to_dwc3_request(request);
1477 	struct dwc3_ep			*dep = to_dwc3_ep(ep);
1478 	struct dwc3			*dwc = dep->dwc;
1479 
1480 	unsigned long			flags;
1481 
1482 	int				ret;
1483 
1484 	spin_lock_irqsave(&dwc->lock, flags);
1485 	ret = __dwc3_gadget_ep_queue(dep, req);
1486 	spin_unlock_irqrestore(&dwc->lock, flags);
1487 
1488 	return ret;
1489 }
1490 
1491 static void dwc3_gadget_ep_skip_trbs(struct dwc3_ep *dep, struct dwc3_request *req)
1492 {
1493 	int i;
1494 
1495 	/*
1496 	 * If request was already started, this means we had to
1497 	 * stop the transfer. With that we also need to ignore
1498 	 * all TRBs used by the request, however TRBs can only
1499 	 * be modified after completion of END_TRANSFER
1500 	 * command. So what we do here is that we wait for
1501 	 * END_TRANSFER completion and only after that, we jump
1502 	 * over TRBs by clearing HWO and incrementing dequeue
1503 	 * pointer.
1504 	 */
1505 	for (i = 0; i < req->num_trbs; i++) {
1506 		struct dwc3_trb *trb;
1507 
1508 		trb = req->trb + i;
1509 		trb->ctrl &= ~DWC3_TRB_CTRL_HWO;
1510 		dwc3_ep_inc_deq(dep);
1511 	}
1512 
1513 	req->num_trbs = 0;
1514 }
1515 
1516 static void dwc3_gadget_ep_cleanup_cancelled_requests(struct dwc3_ep *dep)
1517 {
1518 	struct dwc3_request		*req;
1519 	struct dwc3_request		*tmp;
1520 
1521 	list_for_each_entry_safe(req, tmp, &dep->cancelled_list, list) {
1522 		dwc3_gadget_ep_skip_trbs(dep, req);
1523 		dwc3_gadget_giveback(dep, req, -ECONNRESET);
1524 	}
1525 }
1526 
1527 static int dwc3_gadget_ep_dequeue(struct usb_ep *ep,
1528 		struct usb_request *request)
1529 {
1530 	struct dwc3_request		*req = to_dwc3_request(request);
1531 	struct dwc3_request		*r = NULL;
1532 
1533 	struct dwc3_ep			*dep = to_dwc3_ep(ep);
1534 	struct dwc3			*dwc = dep->dwc;
1535 
1536 	unsigned long			flags;
1537 	int				ret = 0;
1538 
1539 	trace_dwc3_ep_dequeue(req);
1540 
1541 	spin_lock_irqsave(&dwc->lock, flags);
1542 
1543 	list_for_each_entry(r, &dep->pending_list, list) {
1544 		if (r == req)
1545 			break;
1546 	}
1547 
1548 	if (r != req) {
1549 		list_for_each_entry(r, &dep->started_list, list) {
1550 			if (r == req)
1551 				break;
1552 		}
1553 		if (r == req) {
1554 			/* wait until it is processed */
1555 			dwc3_stop_active_transfer(dep, true, true);
1556 
1557 			if (!r->trb)
1558 				goto out0;
1559 
1560 			dwc3_gadget_move_cancelled_request(req);
1561 			if (dep->flags & DWC3_EP_TRANSFER_STARTED)
1562 				goto out0;
1563 			else
1564 				goto out1;
1565 		}
1566 		dev_err(dwc->dev, "request %pK was not queued to %s\n",
1567 				request, ep->name);
1568 		ret = -EINVAL;
1569 		goto out0;
1570 	}
1571 
1572 out1:
1573 	dwc3_gadget_giveback(dep, req, -ECONNRESET);
1574 
1575 out0:
1576 	spin_unlock_irqrestore(&dwc->lock, flags);
1577 
1578 	return ret;
1579 }
1580 
1581 int __dwc3_gadget_ep_set_halt(struct dwc3_ep *dep, int value, int protocol)
1582 {
1583 	struct dwc3_gadget_ep_cmd_params	params;
1584 	struct dwc3				*dwc = dep->dwc;
1585 	int					ret;
1586 
1587 	if (usb_endpoint_xfer_isoc(dep->endpoint.desc)) {
1588 		dev_err(dwc->dev, "%s is of Isochronous type\n", dep->name);
1589 		return -EINVAL;
1590 	}
1591 
1592 	memset(&params, 0x00, sizeof(params));
1593 
1594 	if (value) {
1595 		struct dwc3_trb *trb;
1596 
1597 		unsigned transfer_in_flight;
1598 		unsigned started;
1599 
1600 		if (dep->number > 1)
1601 			trb = dwc3_ep_prev_trb(dep, dep->trb_enqueue);
1602 		else
1603 			trb = &dwc->ep0_trb[dep->trb_enqueue];
1604 
1605 		transfer_in_flight = trb->ctrl & DWC3_TRB_CTRL_HWO;
1606 		started = !list_empty(&dep->started_list);
1607 
1608 		if (!protocol && ((dep->direction && transfer_in_flight) ||
1609 				(!dep->direction && started))) {
1610 			return -EAGAIN;
1611 		}
1612 
1613 		ret = dwc3_send_gadget_ep_cmd(dep, DWC3_DEPCMD_SETSTALL,
1614 				&params);
1615 		if (ret)
1616 			dev_err(dwc->dev, "failed to set STALL on %s\n",
1617 					dep->name);
1618 		else
1619 			dep->flags |= DWC3_EP_STALL;
1620 	} else {
1621 
1622 		ret = dwc3_send_clear_stall_ep_cmd(dep);
1623 		if (ret)
1624 			dev_err(dwc->dev, "failed to clear STALL on %s\n",
1625 					dep->name);
1626 		else
1627 			dep->flags &= ~(DWC3_EP_STALL | DWC3_EP_WEDGE);
1628 	}
1629 
1630 	return ret;
1631 }
1632 
1633 static int dwc3_gadget_ep_set_halt(struct usb_ep *ep, int value)
1634 {
1635 	struct dwc3_ep			*dep = to_dwc3_ep(ep);
1636 	struct dwc3			*dwc = dep->dwc;
1637 
1638 	unsigned long			flags;
1639 
1640 	int				ret;
1641 
1642 	spin_lock_irqsave(&dwc->lock, flags);
1643 	ret = __dwc3_gadget_ep_set_halt(dep, value, false);
1644 	spin_unlock_irqrestore(&dwc->lock, flags);
1645 
1646 	return ret;
1647 }
1648 
1649 static int dwc3_gadget_ep_set_wedge(struct usb_ep *ep)
1650 {
1651 	struct dwc3_ep			*dep = to_dwc3_ep(ep);
1652 	struct dwc3			*dwc = dep->dwc;
1653 	unsigned long			flags;
1654 	int				ret;
1655 
1656 	spin_lock_irqsave(&dwc->lock, flags);
1657 	dep->flags |= DWC3_EP_WEDGE;
1658 
1659 	if (dep->number == 0 || dep->number == 1)
1660 		ret = __dwc3_gadget_ep0_set_halt(ep, 1);
1661 	else
1662 		ret = __dwc3_gadget_ep_set_halt(dep, 1, false);
1663 	spin_unlock_irqrestore(&dwc->lock, flags);
1664 
1665 	return ret;
1666 }
1667 
1668 /* -------------------------------------------------------------------------- */
1669 
1670 static struct usb_endpoint_descriptor dwc3_gadget_ep0_desc = {
1671 	.bLength	= USB_DT_ENDPOINT_SIZE,
1672 	.bDescriptorType = USB_DT_ENDPOINT,
1673 	.bmAttributes	= USB_ENDPOINT_XFER_CONTROL,
1674 };
1675 
1676 static const struct usb_ep_ops dwc3_gadget_ep0_ops = {
1677 	.enable		= dwc3_gadget_ep0_enable,
1678 	.disable	= dwc3_gadget_ep0_disable,
1679 	.alloc_request	= dwc3_gadget_ep_alloc_request,
1680 	.free_request	= dwc3_gadget_ep_free_request,
1681 	.queue		= dwc3_gadget_ep0_queue,
1682 	.dequeue	= dwc3_gadget_ep_dequeue,
1683 	.set_halt	= dwc3_gadget_ep0_set_halt,
1684 	.set_wedge	= dwc3_gadget_ep_set_wedge,
1685 };
1686 
1687 static const struct usb_ep_ops dwc3_gadget_ep_ops = {
1688 	.enable		= dwc3_gadget_ep_enable,
1689 	.disable	= dwc3_gadget_ep_disable,
1690 	.alloc_request	= dwc3_gadget_ep_alloc_request,
1691 	.free_request	= dwc3_gadget_ep_free_request,
1692 	.queue		= dwc3_gadget_ep_queue,
1693 	.dequeue	= dwc3_gadget_ep_dequeue,
1694 	.set_halt	= dwc3_gadget_ep_set_halt,
1695 	.set_wedge	= dwc3_gadget_ep_set_wedge,
1696 };
1697 
1698 /* -------------------------------------------------------------------------- */
1699 
1700 static int dwc3_gadget_get_frame(struct usb_gadget *g)
1701 {
1702 	struct dwc3		*dwc = gadget_to_dwc(g);
1703 
1704 	return __dwc3_gadget_get_frame(dwc);
1705 }
1706 
1707 static int __dwc3_gadget_wakeup(struct dwc3 *dwc)
1708 {
1709 	int			retries;
1710 
1711 	int			ret;
1712 	u32			reg;
1713 
1714 	u8			link_state;
1715 	u8			speed;
1716 
1717 	/*
1718 	 * According to the Databook Remote wakeup request should
1719 	 * be issued only when the device is in early suspend state.
1720 	 *
1721 	 * We can check that via USB Link State bits in DSTS register.
1722 	 */
1723 	reg = dwc3_readl(dwc->regs, DWC3_DSTS);
1724 
1725 	speed = reg & DWC3_DSTS_CONNECTSPD;
1726 	if ((speed == DWC3_DSTS_SUPERSPEED) ||
1727 	    (speed == DWC3_DSTS_SUPERSPEED_PLUS))
1728 		return 0;
1729 
1730 	link_state = DWC3_DSTS_USBLNKST(reg);
1731 
1732 	switch (link_state) {
1733 	case DWC3_LINK_STATE_RX_DET:	/* in HS, means Early Suspend */
1734 	case DWC3_LINK_STATE_U3:	/* in HS, means SUSPEND */
1735 		break;
1736 	default:
1737 		return -EINVAL;
1738 	}
1739 
1740 	ret = dwc3_gadget_set_link_state(dwc, DWC3_LINK_STATE_RECOV);
1741 	if (ret < 0) {
1742 		dev_err(dwc->dev, "failed to put link in Recovery\n");
1743 		return ret;
1744 	}
1745 
1746 	/* Recent versions do this automatically */
1747 	if (dwc->revision < DWC3_REVISION_194A) {
1748 		/* write zeroes to Link Change Request */
1749 		reg = dwc3_readl(dwc->regs, DWC3_DCTL);
1750 		reg &= ~DWC3_DCTL_ULSTCHNGREQ_MASK;
1751 		dwc3_writel(dwc->regs, DWC3_DCTL, reg);
1752 	}
1753 
1754 	/* poll until Link State changes to ON */
1755 	retries = 20000;
1756 
1757 	while (retries--) {
1758 		reg = dwc3_readl(dwc->regs, DWC3_DSTS);
1759 
1760 		/* in HS, means ON */
1761 		if (DWC3_DSTS_USBLNKST(reg) == DWC3_LINK_STATE_U0)
1762 			break;
1763 	}
1764 
1765 	if (DWC3_DSTS_USBLNKST(reg) != DWC3_LINK_STATE_U0) {
1766 		dev_err(dwc->dev, "failed to send remote wakeup\n");
1767 		return -EINVAL;
1768 	}
1769 
1770 	return 0;
1771 }
1772 
1773 static int dwc3_gadget_wakeup(struct usb_gadget *g)
1774 {
1775 	struct dwc3		*dwc = gadget_to_dwc(g);
1776 	unsigned long		flags;
1777 	int			ret;
1778 
1779 	spin_lock_irqsave(&dwc->lock, flags);
1780 	ret = __dwc3_gadget_wakeup(dwc);
1781 	spin_unlock_irqrestore(&dwc->lock, flags);
1782 
1783 	return ret;
1784 }
1785 
1786 static int dwc3_gadget_set_selfpowered(struct usb_gadget *g,
1787 		int is_selfpowered)
1788 {
1789 	struct dwc3		*dwc = gadget_to_dwc(g);
1790 	unsigned long		flags;
1791 
1792 	spin_lock_irqsave(&dwc->lock, flags);
1793 	g->is_selfpowered = !!is_selfpowered;
1794 	spin_unlock_irqrestore(&dwc->lock, flags);
1795 
1796 	return 0;
1797 }
1798 
1799 static int dwc3_gadget_run_stop(struct dwc3 *dwc, int is_on, int suspend)
1800 {
1801 	u32			reg;
1802 	u32			timeout = 500;
1803 
1804 	if (pm_runtime_suspended(dwc->dev))
1805 		return 0;
1806 
1807 	reg = dwc3_readl(dwc->regs, DWC3_DCTL);
1808 	if (is_on) {
1809 		if (dwc->revision <= DWC3_REVISION_187A) {
1810 			reg &= ~DWC3_DCTL_TRGTULST_MASK;
1811 			reg |= DWC3_DCTL_TRGTULST_RX_DET;
1812 		}
1813 
1814 		if (dwc->revision >= DWC3_REVISION_194A)
1815 			reg &= ~DWC3_DCTL_KEEP_CONNECT;
1816 		reg |= DWC3_DCTL_RUN_STOP;
1817 
1818 		if (dwc->has_hibernation)
1819 			reg |= DWC3_DCTL_KEEP_CONNECT;
1820 
1821 		dwc->pullups_connected = true;
1822 	} else {
1823 		reg &= ~DWC3_DCTL_RUN_STOP;
1824 
1825 		if (dwc->has_hibernation && !suspend)
1826 			reg &= ~DWC3_DCTL_KEEP_CONNECT;
1827 
1828 		dwc->pullups_connected = false;
1829 	}
1830 
1831 	dwc3_writel(dwc->regs, DWC3_DCTL, reg);
1832 
1833 	do {
1834 		reg = dwc3_readl(dwc->regs, DWC3_DSTS);
1835 		reg &= DWC3_DSTS_DEVCTRLHLT;
1836 	} while (--timeout && !(!is_on ^ !reg));
1837 
1838 	if (!timeout)
1839 		return -ETIMEDOUT;
1840 
1841 	return 0;
1842 }
1843 
1844 static int dwc3_gadget_pullup(struct usb_gadget *g, int is_on)
1845 {
1846 	struct dwc3		*dwc = gadget_to_dwc(g);
1847 	unsigned long		flags;
1848 	int			ret;
1849 
1850 	is_on = !!is_on;
1851 
1852 	/*
1853 	 * Per databook, when we want to stop the gadget, if a control transfer
1854 	 * is still in process, complete it and get the core into setup phase.
1855 	 */
1856 	if (!is_on && dwc->ep0state != EP0_SETUP_PHASE) {
1857 		reinit_completion(&dwc->ep0_in_setup);
1858 
1859 		ret = wait_for_completion_timeout(&dwc->ep0_in_setup,
1860 				msecs_to_jiffies(DWC3_PULL_UP_TIMEOUT));
1861 		if (ret == 0) {
1862 			dev_err(dwc->dev, "timed out waiting for SETUP phase\n");
1863 			return -ETIMEDOUT;
1864 		}
1865 	}
1866 
1867 	spin_lock_irqsave(&dwc->lock, flags);
1868 	ret = dwc3_gadget_run_stop(dwc, is_on, false);
1869 	spin_unlock_irqrestore(&dwc->lock, flags);
1870 
1871 	return ret;
1872 }
1873 
1874 static void dwc3_gadget_enable_irq(struct dwc3 *dwc)
1875 {
1876 	u32			reg;
1877 
1878 	/* Enable all but Start and End of Frame IRQs */
1879 	reg = (DWC3_DEVTEN_VNDRDEVTSTRCVEDEN |
1880 			DWC3_DEVTEN_EVNTOVERFLOWEN |
1881 			DWC3_DEVTEN_CMDCMPLTEN |
1882 			DWC3_DEVTEN_ERRTICERREN |
1883 			DWC3_DEVTEN_WKUPEVTEN |
1884 			DWC3_DEVTEN_CONNECTDONEEN |
1885 			DWC3_DEVTEN_USBRSTEN |
1886 			DWC3_DEVTEN_DISCONNEVTEN);
1887 
1888 	if (dwc->revision < DWC3_REVISION_250A)
1889 		reg |= DWC3_DEVTEN_ULSTCNGEN;
1890 
1891 	dwc3_writel(dwc->regs, DWC3_DEVTEN, reg);
1892 }
1893 
1894 static void dwc3_gadget_disable_irq(struct dwc3 *dwc)
1895 {
1896 	/* mask all interrupts */
1897 	dwc3_writel(dwc->regs, DWC3_DEVTEN, 0x00);
1898 }
1899 
1900 static irqreturn_t dwc3_interrupt(int irq, void *_dwc);
1901 static irqreturn_t dwc3_thread_interrupt(int irq, void *_dwc);
1902 
1903 /**
1904  * dwc3_gadget_setup_nump - calculate and initialize NUMP field of %DWC3_DCFG
1905  * @dwc: pointer to our context structure
1906  *
1907  * The following looks like complex but it's actually very simple. In order to
1908  * calculate the number of packets we can burst at once on OUT transfers, we're
1909  * gonna use RxFIFO size.
1910  *
1911  * To calculate RxFIFO size we need two numbers:
1912  * MDWIDTH = size, in bits, of the internal memory bus
1913  * RAM2_DEPTH = depth, in MDWIDTH, of internal RAM2 (where RxFIFO sits)
1914  *
1915  * Given these two numbers, the formula is simple:
1916  *
1917  * RxFIFO Size = (RAM2_DEPTH * MDWIDTH / 8) - 24 - 16;
1918  *
1919  * 24 bytes is for 3x SETUP packets
1920  * 16 bytes is a clock domain crossing tolerance
1921  *
1922  * Given RxFIFO Size, NUMP = RxFIFOSize / 1024;
1923  */
1924 static void dwc3_gadget_setup_nump(struct dwc3 *dwc)
1925 {
1926 	u32 ram2_depth;
1927 	u32 mdwidth;
1928 	u32 nump;
1929 	u32 reg;
1930 
1931 	ram2_depth = DWC3_GHWPARAMS7_RAM2_DEPTH(dwc->hwparams.hwparams7);
1932 	mdwidth = DWC3_GHWPARAMS0_MDWIDTH(dwc->hwparams.hwparams0);
1933 
1934 	nump = ((ram2_depth * mdwidth / 8) - 24 - 16) / 1024;
1935 	nump = min_t(u32, nump, 16);
1936 
1937 	/* update NumP */
1938 	reg = dwc3_readl(dwc->regs, DWC3_DCFG);
1939 	reg &= ~DWC3_DCFG_NUMP_MASK;
1940 	reg |= nump << DWC3_DCFG_NUMP_SHIFT;
1941 	dwc3_writel(dwc->regs, DWC3_DCFG, reg);
1942 }
1943 
1944 static int __dwc3_gadget_start(struct dwc3 *dwc)
1945 {
1946 	struct dwc3_ep		*dep;
1947 	int			ret = 0;
1948 	u32			reg;
1949 
1950 	/*
1951 	 * Use IMOD if enabled via dwc->imod_interval. Otherwise, if
1952 	 * the core supports IMOD, disable it.
1953 	 */
1954 	if (dwc->imod_interval) {
1955 		dwc3_writel(dwc->regs, DWC3_DEV_IMOD(0), dwc->imod_interval);
1956 		dwc3_writel(dwc->regs, DWC3_GEVNTCOUNT(0), DWC3_GEVNTCOUNT_EHB);
1957 	} else if (dwc3_has_imod(dwc)) {
1958 		dwc3_writel(dwc->regs, DWC3_DEV_IMOD(0), 0);
1959 	}
1960 
1961 	/*
1962 	 * We are telling dwc3 that we want to use DCFG.NUMP as ACK TP's NUMP
1963 	 * field instead of letting dwc3 itself calculate that automatically.
1964 	 *
1965 	 * This way, we maximize the chances that we'll be able to get several
1966 	 * bursts of data without going through any sort of endpoint throttling.
1967 	 */
1968 	reg = dwc3_readl(dwc->regs, DWC3_GRXTHRCFG);
1969 	if (dwc3_is_usb31(dwc))
1970 		reg &= ~DWC31_GRXTHRCFG_PKTCNTSEL;
1971 	else
1972 		reg &= ~DWC3_GRXTHRCFG_PKTCNTSEL;
1973 
1974 	dwc3_writel(dwc->regs, DWC3_GRXTHRCFG, reg);
1975 
1976 	dwc3_gadget_setup_nump(dwc);
1977 
1978 	/* Start with SuperSpeed Default */
1979 	dwc3_gadget_ep0_desc.wMaxPacketSize = cpu_to_le16(512);
1980 
1981 	dep = dwc->eps[0];
1982 	ret = __dwc3_gadget_ep_enable(dep, DWC3_DEPCFG_ACTION_INIT);
1983 	if (ret) {
1984 		dev_err(dwc->dev, "failed to enable %s\n", dep->name);
1985 		goto err0;
1986 	}
1987 
1988 	dep = dwc->eps[1];
1989 	ret = __dwc3_gadget_ep_enable(dep, DWC3_DEPCFG_ACTION_INIT);
1990 	if (ret) {
1991 		dev_err(dwc->dev, "failed to enable %s\n", dep->name);
1992 		goto err1;
1993 	}
1994 
1995 	/* begin to receive SETUP packets */
1996 	dwc->ep0state = EP0_SETUP_PHASE;
1997 	dwc->link_state = DWC3_LINK_STATE_SS_DIS;
1998 	dwc3_ep0_out_start(dwc);
1999 
2000 	dwc3_gadget_enable_irq(dwc);
2001 
2002 	return 0;
2003 
2004 err1:
2005 	__dwc3_gadget_ep_disable(dwc->eps[0]);
2006 
2007 err0:
2008 	return ret;
2009 }
2010 
2011 static int dwc3_gadget_start(struct usb_gadget *g,
2012 		struct usb_gadget_driver *driver)
2013 {
2014 	struct dwc3		*dwc = gadget_to_dwc(g);
2015 	unsigned long		flags;
2016 	int			ret = 0;
2017 	int			irq;
2018 
2019 	irq = dwc->irq_gadget;
2020 	ret = request_threaded_irq(irq, dwc3_interrupt, dwc3_thread_interrupt,
2021 			IRQF_SHARED, "dwc3", dwc->ev_buf);
2022 	if (ret) {
2023 		dev_err(dwc->dev, "failed to request irq #%d --> %d\n",
2024 				irq, ret);
2025 		goto err0;
2026 	}
2027 
2028 	spin_lock_irqsave(&dwc->lock, flags);
2029 	if (dwc->gadget_driver) {
2030 		dev_err(dwc->dev, "%s is already bound to %s\n",
2031 				dwc->gadget.name,
2032 				dwc->gadget_driver->driver.name);
2033 		ret = -EBUSY;
2034 		goto err1;
2035 	}
2036 
2037 	dwc->gadget_driver	= driver;
2038 
2039 	if (pm_runtime_active(dwc->dev))
2040 		__dwc3_gadget_start(dwc);
2041 
2042 	spin_unlock_irqrestore(&dwc->lock, flags);
2043 
2044 	return 0;
2045 
2046 err1:
2047 	spin_unlock_irqrestore(&dwc->lock, flags);
2048 	free_irq(irq, dwc);
2049 
2050 err0:
2051 	return ret;
2052 }
2053 
2054 static void __dwc3_gadget_stop(struct dwc3 *dwc)
2055 {
2056 	dwc3_gadget_disable_irq(dwc);
2057 	__dwc3_gadget_ep_disable(dwc->eps[0]);
2058 	__dwc3_gadget_ep_disable(dwc->eps[1]);
2059 }
2060 
2061 static int dwc3_gadget_stop(struct usb_gadget *g)
2062 {
2063 	struct dwc3		*dwc = gadget_to_dwc(g);
2064 	unsigned long		flags;
2065 
2066 	spin_lock_irqsave(&dwc->lock, flags);
2067 
2068 	if (pm_runtime_suspended(dwc->dev))
2069 		goto out;
2070 
2071 	__dwc3_gadget_stop(dwc);
2072 
2073 out:
2074 	dwc->gadget_driver	= NULL;
2075 	spin_unlock_irqrestore(&dwc->lock, flags);
2076 
2077 	free_irq(dwc->irq_gadget, dwc->ev_buf);
2078 
2079 	return 0;
2080 }
2081 
2082 static void dwc3_gadget_config_params(struct usb_gadget *g,
2083 				      struct usb_dcd_config_params *params)
2084 {
2085 	struct dwc3		*dwc = gadget_to_dwc(g);
2086 
2087 	params->besl_baseline = USB_DEFAULT_BESL_UNSPECIFIED;
2088 	params->besl_deep = USB_DEFAULT_BESL_UNSPECIFIED;
2089 
2090 	/* Recommended BESL */
2091 	if (!dwc->dis_enblslpm_quirk) {
2092 		/*
2093 		 * If the recommended BESL baseline is 0 or if the BESL deep is
2094 		 * less than 2, Microsoft's Windows 10 host usb stack will issue
2095 		 * a usb reset immediately after it receives the extended BOS
2096 		 * descriptor and the enumeration will fail. To maintain
2097 		 * compatibility with the Windows' usb stack, let's set the
2098 		 * recommended BESL baseline to 1 and clamp the BESL deep to be
2099 		 * within 2 to 15.
2100 		 */
2101 		params->besl_baseline = 1;
2102 		if (dwc->is_utmi_l1_suspend)
2103 			params->besl_deep =
2104 				clamp_t(u8, dwc->hird_threshold, 2, 15);
2105 	}
2106 
2107 	/* U1 Device exit Latency */
2108 	if (dwc->dis_u1_entry_quirk)
2109 		params->bU1devExitLat = 0;
2110 	else
2111 		params->bU1devExitLat = DWC3_DEFAULT_U1_DEV_EXIT_LAT;
2112 
2113 	/* U2 Device exit Latency */
2114 	if (dwc->dis_u2_entry_quirk)
2115 		params->bU2DevExitLat = 0;
2116 	else
2117 		params->bU2DevExitLat =
2118 				cpu_to_le16(DWC3_DEFAULT_U2_DEV_EXIT_LAT);
2119 }
2120 
2121 static void dwc3_gadget_set_speed(struct usb_gadget *g,
2122 				  enum usb_device_speed speed)
2123 {
2124 	struct dwc3		*dwc = gadget_to_dwc(g);
2125 	unsigned long		flags;
2126 	u32			reg;
2127 
2128 	spin_lock_irqsave(&dwc->lock, flags);
2129 	reg = dwc3_readl(dwc->regs, DWC3_DCFG);
2130 	reg &= ~(DWC3_DCFG_SPEED_MASK);
2131 
2132 	/*
2133 	 * WORKAROUND: DWC3 revision < 2.20a have an issue
2134 	 * which would cause metastability state on Run/Stop
2135 	 * bit if we try to force the IP to USB2-only mode.
2136 	 *
2137 	 * Because of that, we cannot configure the IP to any
2138 	 * speed other than the SuperSpeed
2139 	 *
2140 	 * Refers to:
2141 	 *
2142 	 * STAR#9000525659: Clock Domain Crossing on DCTL in
2143 	 * USB 2.0 Mode
2144 	 */
2145 	if (dwc->revision < DWC3_REVISION_220A &&
2146 	    !dwc->dis_metastability_quirk) {
2147 		reg |= DWC3_DCFG_SUPERSPEED;
2148 	} else {
2149 		switch (speed) {
2150 		case USB_SPEED_LOW:
2151 			reg |= DWC3_DCFG_LOWSPEED;
2152 			break;
2153 		case USB_SPEED_FULL:
2154 			reg |= DWC3_DCFG_FULLSPEED;
2155 			break;
2156 		case USB_SPEED_HIGH:
2157 			reg |= DWC3_DCFG_HIGHSPEED;
2158 			break;
2159 		case USB_SPEED_SUPER:
2160 			reg |= DWC3_DCFG_SUPERSPEED;
2161 			break;
2162 		case USB_SPEED_SUPER_PLUS:
2163 			if (dwc3_is_usb31(dwc))
2164 				reg |= DWC3_DCFG_SUPERSPEED_PLUS;
2165 			else
2166 				reg |= DWC3_DCFG_SUPERSPEED;
2167 			break;
2168 		default:
2169 			dev_err(dwc->dev, "invalid speed (%d)\n", speed);
2170 
2171 			if (dwc->revision & DWC3_REVISION_IS_DWC31)
2172 				reg |= DWC3_DCFG_SUPERSPEED_PLUS;
2173 			else
2174 				reg |= DWC3_DCFG_SUPERSPEED;
2175 		}
2176 	}
2177 	dwc3_writel(dwc->regs, DWC3_DCFG, reg);
2178 
2179 	spin_unlock_irqrestore(&dwc->lock, flags);
2180 }
2181 
2182 static const struct usb_gadget_ops dwc3_gadget_ops = {
2183 	.get_frame		= dwc3_gadget_get_frame,
2184 	.wakeup			= dwc3_gadget_wakeup,
2185 	.set_selfpowered	= dwc3_gadget_set_selfpowered,
2186 	.pullup			= dwc3_gadget_pullup,
2187 	.udc_start		= dwc3_gadget_start,
2188 	.udc_stop		= dwc3_gadget_stop,
2189 	.udc_set_speed		= dwc3_gadget_set_speed,
2190 	.get_config_params	= dwc3_gadget_config_params,
2191 };
2192 
2193 /* -------------------------------------------------------------------------- */
2194 
2195 static int dwc3_gadget_init_control_endpoint(struct dwc3_ep *dep)
2196 {
2197 	struct dwc3 *dwc = dep->dwc;
2198 
2199 	usb_ep_set_maxpacket_limit(&dep->endpoint, 512);
2200 	dep->endpoint.maxburst = 1;
2201 	dep->endpoint.ops = &dwc3_gadget_ep0_ops;
2202 	if (!dep->direction)
2203 		dwc->gadget.ep0 = &dep->endpoint;
2204 
2205 	dep->endpoint.caps.type_control = true;
2206 
2207 	return 0;
2208 }
2209 
2210 static int dwc3_gadget_init_in_endpoint(struct dwc3_ep *dep)
2211 {
2212 	struct dwc3 *dwc = dep->dwc;
2213 	int mdwidth;
2214 	int kbytes;
2215 	int size;
2216 
2217 	mdwidth = DWC3_MDWIDTH(dwc->hwparams.hwparams0);
2218 	/* MDWIDTH is represented in bits, we need it in bytes */
2219 	mdwidth /= 8;
2220 
2221 	size = dwc3_readl(dwc->regs, DWC3_GTXFIFOSIZ(dep->number >> 1));
2222 	if (dwc3_is_usb31(dwc))
2223 		size = DWC31_GTXFIFOSIZ_TXFDEF(size);
2224 	else
2225 		size = DWC3_GTXFIFOSIZ_TXFDEF(size);
2226 
2227 	/* FIFO Depth is in MDWDITH bytes. Multiply */
2228 	size *= mdwidth;
2229 
2230 	kbytes = size / 1024;
2231 	if (kbytes == 0)
2232 		kbytes = 1;
2233 
2234 	/*
2235 	 * FIFO sizes account an extra MDWIDTH * (kbytes + 1) bytes for
2236 	 * internal overhead. We don't really know how these are used,
2237 	 * but documentation say it exists.
2238 	 */
2239 	size -= mdwidth * (kbytes + 1);
2240 	size /= kbytes;
2241 
2242 	usb_ep_set_maxpacket_limit(&dep->endpoint, size);
2243 
2244 	dep->endpoint.max_streams = 15;
2245 	dep->endpoint.ops = &dwc3_gadget_ep_ops;
2246 	list_add_tail(&dep->endpoint.ep_list,
2247 			&dwc->gadget.ep_list);
2248 	dep->endpoint.caps.type_iso = true;
2249 	dep->endpoint.caps.type_bulk = true;
2250 	dep->endpoint.caps.type_int = true;
2251 
2252 	return dwc3_alloc_trb_pool(dep);
2253 }
2254 
2255 static int dwc3_gadget_init_out_endpoint(struct dwc3_ep *dep)
2256 {
2257 	struct dwc3 *dwc = dep->dwc;
2258 
2259 	usb_ep_set_maxpacket_limit(&dep->endpoint, 1024);
2260 	dep->endpoint.max_streams = 15;
2261 	dep->endpoint.ops = &dwc3_gadget_ep_ops;
2262 	list_add_tail(&dep->endpoint.ep_list,
2263 			&dwc->gadget.ep_list);
2264 	dep->endpoint.caps.type_iso = true;
2265 	dep->endpoint.caps.type_bulk = true;
2266 	dep->endpoint.caps.type_int = true;
2267 
2268 	return dwc3_alloc_trb_pool(dep);
2269 }
2270 
2271 static int dwc3_gadget_init_endpoint(struct dwc3 *dwc, u8 epnum)
2272 {
2273 	struct dwc3_ep			*dep;
2274 	bool				direction = epnum & 1;
2275 	int				ret;
2276 	u8				num = epnum >> 1;
2277 
2278 	dep = kzalloc(sizeof(*dep), GFP_KERNEL);
2279 	if (!dep)
2280 		return -ENOMEM;
2281 
2282 	dep->dwc = dwc;
2283 	dep->number = epnum;
2284 	dep->direction = direction;
2285 	dep->regs = dwc->regs + DWC3_DEP_BASE(epnum);
2286 	dwc->eps[epnum] = dep;
2287 	dep->combo_num = 0;
2288 	dep->start_cmd_status = 0;
2289 
2290 	snprintf(dep->name, sizeof(dep->name), "ep%u%s", num,
2291 			direction ? "in" : "out");
2292 
2293 	dep->endpoint.name = dep->name;
2294 
2295 	if (!(dep->number > 1)) {
2296 		dep->endpoint.desc = &dwc3_gadget_ep0_desc;
2297 		dep->endpoint.comp_desc = NULL;
2298 	}
2299 
2300 	if (num == 0)
2301 		ret = dwc3_gadget_init_control_endpoint(dep);
2302 	else if (direction)
2303 		ret = dwc3_gadget_init_in_endpoint(dep);
2304 	else
2305 		ret = dwc3_gadget_init_out_endpoint(dep);
2306 
2307 	if (ret)
2308 		return ret;
2309 
2310 	dep->endpoint.caps.dir_in = direction;
2311 	dep->endpoint.caps.dir_out = !direction;
2312 
2313 	INIT_LIST_HEAD(&dep->pending_list);
2314 	INIT_LIST_HEAD(&dep->started_list);
2315 	INIT_LIST_HEAD(&dep->cancelled_list);
2316 
2317 	return 0;
2318 }
2319 
2320 static int dwc3_gadget_init_endpoints(struct dwc3 *dwc, u8 total)
2321 {
2322 	u8				epnum;
2323 
2324 	INIT_LIST_HEAD(&dwc->gadget.ep_list);
2325 
2326 	for (epnum = 0; epnum < total; epnum++) {
2327 		int			ret;
2328 
2329 		ret = dwc3_gadget_init_endpoint(dwc, epnum);
2330 		if (ret)
2331 			return ret;
2332 	}
2333 
2334 	return 0;
2335 }
2336 
2337 static void dwc3_gadget_free_endpoints(struct dwc3 *dwc)
2338 {
2339 	struct dwc3_ep			*dep;
2340 	u8				epnum;
2341 
2342 	for (epnum = 0; epnum < DWC3_ENDPOINTS_NUM; epnum++) {
2343 		dep = dwc->eps[epnum];
2344 		if (!dep)
2345 			continue;
2346 		/*
2347 		 * Physical endpoints 0 and 1 are special; they form the
2348 		 * bi-directional USB endpoint 0.
2349 		 *
2350 		 * For those two physical endpoints, we don't allocate a TRB
2351 		 * pool nor do we add them the endpoints list. Due to that, we
2352 		 * shouldn't do these two operations otherwise we would end up
2353 		 * with all sorts of bugs when removing dwc3.ko.
2354 		 */
2355 		if (epnum != 0 && epnum != 1) {
2356 			dwc3_free_trb_pool(dep);
2357 			list_del(&dep->endpoint.ep_list);
2358 		}
2359 
2360 		kfree(dep);
2361 	}
2362 }
2363 
2364 /* -------------------------------------------------------------------------- */
2365 
2366 static int dwc3_gadget_ep_reclaim_completed_trb(struct dwc3_ep *dep,
2367 		struct dwc3_request *req, struct dwc3_trb *trb,
2368 		const struct dwc3_event_depevt *event, int status, int chain)
2369 {
2370 	unsigned int		count;
2371 
2372 	dwc3_ep_inc_deq(dep);
2373 
2374 	trace_dwc3_complete_trb(dep, trb);
2375 	req->num_trbs--;
2376 
2377 	/*
2378 	 * If we're in the middle of series of chained TRBs and we
2379 	 * receive a short transfer along the way, DWC3 will skip
2380 	 * through all TRBs including the last TRB in the chain (the
2381 	 * where CHN bit is zero. DWC3 will also avoid clearing HWO
2382 	 * bit and SW has to do it manually.
2383 	 *
2384 	 * We're going to do that here to avoid problems of HW trying
2385 	 * to use bogus TRBs for transfers.
2386 	 */
2387 	if (chain && (trb->ctrl & DWC3_TRB_CTRL_HWO))
2388 		trb->ctrl &= ~DWC3_TRB_CTRL_HWO;
2389 
2390 	/*
2391 	 * For isochronous transfers, the first TRB in a service interval must
2392 	 * have the Isoc-First type. Track and report its interval frame number.
2393 	 */
2394 	if (usb_endpoint_xfer_isoc(dep->endpoint.desc) &&
2395 	    (trb->ctrl & DWC3_TRBCTL_ISOCHRONOUS_FIRST)) {
2396 		unsigned int frame_number;
2397 
2398 		frame_number = DWC3_TRB_CTRL_GET_SID_SOFN(trb->ctrl);
2399 		frame_number &= ~(dep->interval - 1);
2400 		req->request.frame_number = frame_number;
2401 	}
2402 
2403 	/*
2404 	 * If we're dealing with unaligned size OUT transfer, we will be left
2405 	 * with one TRB pending in the ring. We need to manually clear HWO bit
2406 	 * from that TRB.
2407 	 */
2408 
2409 	if (req->needs_extra_trb && !(trb->ctrl & DWC3_TRB_CTRL_CHN)) {
2410 		trb->ctrl &= ~DWC3_TRB_CTRL_HWO;
2411 		return 1;
2412 	}
2413 
2414 	count = trb->size & DWC3_TRB_SIZE_MASK;
2415 	req->remaining += count;
2416 
2417 	if ((trb->ctrl & DWC3_TRB_CTRL_HWO) && status != -ESHUTDOWN)
2418 		return 1;
2419 
2420 	if (event->status & DEPEVT_STATUS_SHORT && !chain)
2421 		return 1;
2422 
2423 	if (event->status & DEPEVT_STATUS_IOC)
2424 		return 1;
2425 
2426 	return 0;
2427 }
2428 
2429 static int dwc3_gadget_ep_reclaim_trb_sg(struct dwc3_ep *dep,
2430 		struct dwc3_request *req, const struct dwc3_event_depevt *event,
2431 		int status)
2432 {
2433 	struct dwc3_trb *trb = &dep->trb_pool[dep->trb_dequeue];
2434 	struct scatterlist *sg = req->sg;
2435 	struct scatterlist *s;
2436 	unsigned int pending = req->num_pending_sgs;
2437 	unsigned int i;
2438 	int ret = 0;
2439 
2440 	for_each_sg(sg, s, pending, i) {
2441 		trb = &dep->trb_pool[dep->trb_dequeue];
2442 
2443 		if (trb->ctrl & DWC3_TRB_CTRL_HWO)
2444 			break;
2445 
2446 		req->sg = sg_next(s);
2447 		req->num_pending_sgs--;
2448 
2449 		ret = dwc3_gadget_ep_reclaim_completed_trb(dep, req,
2450 				trb, event, status, true);
2451 		if (ret)
2452 			break;
2453 	}
2454 
2455 	return ret;
2456 }
2457 
2458 static int dwc3_gadget_ep_reclaim_trb_linear(struct dwc3_ep *dep,
2459 		struct dwc3_request *req, const struct dwc3_event_depevt *event,
2460 		int status)
2461 {
2462 	struct dwc3_trb *trb = &dep->trb_pool[dep->trb_dequeue];
2463 
2464 	return dwc3_gadget_ep_reclaim_completed_trb(dep, req, trb,
2465 			event, status, false);
2466 }
2467 
2468 static bool dwc3_gadget_ep_request_completed(struct dwc3_request *req)
2469 {
2470 	/*
2471 	 * For OUT direction, host may send less than the setup
2472 	 * length. Return true for all OUT requests.
2473 	 */
2474 	if (!req->direction)
2475 		return true;
2476 
2477 	return req->request.actual == req->request.length;
2478 }
2479 
2480 static int dwc3_gadget_ep_cleanup_completed_request(struct dwc3_ep *dep,
2481 		const struct dwc3_event_depevt *event,
2482 		struct dwc3_request *req, int status)
2483 {
2484 	int ret;
2485 
2486 	if (req->num_pending_sgs)
2487 		ret = dwc3_gadget_ep_reclaim_trb_sg(dep, req, event,
2488 				status);
2489 	else
2490 		ret = dwc3_gadget_ep_reclaim_trb_linear(dep, req, event,
2491 				status);
2492 
2493 	if (req->needs_extra_trb) {
2494 		ret = dwc3_gadget_ep_reclaim_trb_linear(dep, req, event,
2495 				status);
2496 		req->needs_extra_trb = false;
2497 	}
2498 
2499 	req->request.actual = req->request.length - req->remaining;
2500 
2501 	if (!dwc3_gadget_ep_request_completed(req) ||
2502 			req->num_pending_sgs) {
2503 		__dwc3_gadget_kick_transfer(dep);
2504 		goto out;
2505 	}
2506 
2507 	dwc3_gadget_giveback(dep, req, status);
2508 
2509 out:
2510 	return ret;
2511 }
2512 
2513 static void dwc3_gadget_ep_cleanup_completed_requests(struct dwc3_ep *dep,
2514 		const struct dwc3_event_depevt *event, int status)
2515 {
2516 	struct dwc3_request	*req;
2517 	struct dwc3_request	*tmp;
2518 
2519 	list_for_each_entry_safe(req, tmp, &dep->started_list, list) {
2520 		int ret;
2521 
2522 		ret = dwc3_gadget_ep_cleanup_completed_request(dep, event,
2523 				req, status);
2524 		if (ret)
2525 			break;
2526 	}
2527 }
2528 
2529 static void dwc3_gadget_endpoint_frame_from_event(struct dwc3_ep *dep,
2530 		const struct dwc3_event_depevt *event)
2531 {
2532 	dep->frame_number = event->parameters;
2533 }
2534 
2535 static void dwc3_gadget_endpoint_transfer_in_progress(struct dwc3_ep *dep,
2536 		const struct dwc3_event_depevt *event)
2537 {
2538 	struct dwc3		*dwc = dep->dwc;
2539 	unsigned		status = 0;
2540 	bool			stop = false;
2541 
2542 	dwc3_gadget_endpoint_frame_from_event(dep, event);
2543 
2544 	if (event->status & DEPEVT_STATUS_BUSERR)
2545 		status = -ECONNRESET;
2546 
2547 	if (event->status & DEPEVT_STATUS_MISSED_ISOC) {
2548 		status = -EXDEV;
2549 
2550 		if (list_empty(&dep->started_list))
2551 			stop = true;
2552 	}
2553 
2554 	dwc3_gadget_ep_cleanup_completed_requests(dep, event, status);
2555 
2556 	if (stop) {
2557 		dwc3_stop_active_transfer(dep, true, true);
2558 		dep->flags = DWC3_EP_ENABLED;
2559 	}
2560 
2561 	/*
2562 	 * WORKAROUND: This is the 2nd half of U1/U2 -> U0 workaround.
2563 	 * See dwc3_gadget_linksts_change_interrupt() for 1st half.
2564 	 */
2565 	if (dwc->revision < DWC3_REVISION_183A) {
2566 		u32		reg;
2567 		int		i;
2568 
2569 		for (i = 0; i < DWC3_ENDPOINTS_NUM; i++) {
2570 			dep = dwc->eps[i];
2571 
2572 			if (!(dep->flags & DWC3_EP_ENABLED))
2573 				continue;
2574 
2575 			if (!list_empty(&dep->started_list))
2576 				return;
2577 		}
2578 
2579 		reg = dwc3_readl(dwc->regs, DWC3_DCTL);
2580 		reg |= dwc->u1u2;
2581 		dwc3_writel(dwc->regs, DWC3_DCTL, reg);
2582 
2583 		dwc->u1u2 = 0;
2584 	}
2585 }
2586 
2587 static void dwc3_gadget_endpoint_transfer_not_ready(struct dwc3_ep *dep,
2588 		const struct dwc3_event_depevt *event)
2589 {
2590 	dwc3_gadget_endpoint_frame_from_event(dep, event);
2591 	(void) __dwc3_gadget_start_isoc(dep);
2592 }
2593 
2594 static void dwc3_endpoint_interrupt(struct dwc3 *dwc,
2595 		const struct dwc3_event_depevt *event)
2596 {
2597 	struct dwc3_ep		*dep;
2598 	u8			epnum = event->endpoint_number;
2599 	u8			cmd;
2600 
2601 	dep = dwc->eps[epnum];
2602 
2603 	if (!(dep->flags & DWC3_EP_ENABLED)) {
2604 		if (!(dep->flags & DWC3_EP_TRANSFER_STARTED))
2605 			return;
2606 
2607 		/* Handle only EPCMDCMPLT when EP disabled */
2608 		if (event->endpoint_event != DWC3_DEPEVT_EPCMDCMPLT)
2609 			return;
2610 	}
2611 
2612 	if (epnum == 0 || epnum == 1) {
2613 		dwc3_ep0_interrupt(dwc, event);
2614 		return;
2615 	}
2616 
2617 	switch (event->endpoint_event) {
2618 	case DWC3_DEPEVT_XFERINPROGRESS:
2619 		dwc3_gadget_endpoint_transfer_in_progress(dep, event);
2620 		break;
2621 	case DWC3_DEPEVT_XFERNOTREADY:
2622 		dwc3_gadget_endpoint_transfer_not_ready(dep, event);
2623 		break;
2624 	case DWC3_DEPEVT_EPCMDCMPLT:
2625 		cmd = DEPEVT_PARAMETER_CMD(event->parameters);
2626 
2627 		if (cmd == DWC3_DEPCMD_ENDTRANSFER) {
2628 			dep->flags &= ~DWC3_EP_TRANSFER_STARTED;
2629 			dwc3_gadget_ep_cleanup_cancelled_requests(dep);
2630 		}
2631 		break;
2632 	case DWC3_DEPEVT_STREAMEVT:
2633 	case DWC3_DEPEVT_XFERCOMPLETE:
2634 	case DWC3_DEPEVT_RXTXFIFOEVT:
2635 		break;
2636 	}
2637 }
2638 
2639 static void dwc3_disconnect_gadget(struct dwc3 *dwc)
2640 {
2641 	if (dwc->gadget_driver && dwc->gadget_driver->disconnect) {
2642 		spin_unlock(&dwc->lock);
2643 		dwc->gadget_driver->disconnect(&dwc->gadget);
2644 		spin_lock(&dwc->lock);
2645 	}
2646 }
2647 
2648 static void dwc3_suspend_gadget(struct dwc3 *dwc)
2649 {
2650 	if (dwc->gadget_driver && dwc->gadget_driver->suspend) {
2651 		spin_unlock(&dwc->lock);
2652 		dwc->gadget_driver->suspend(&dwc->gadget);
2653 		spin_lock(&dwc->lock);
2654 	}
2655 }
2656 
2657 static void dwc3_resume_gadget(struct dwc3 *dwc)
2658 {
2659 	if (dwc->gadget_driver && dwc->gadget_driver->resume) {
2660 		spin_unlock(&dwc->lock);
2661 		dwc->gadget_driver->resume(&dwc->gadget);
2662 		spin_lock(&dwc->lock);
2663 	}
2664 }
2665 
2666 static void dwc3_reset_gadget(struct dwc3 *dwc)
2667 {
2668 	if (!dwc->gadget_driver)
2669 		return;
2670 
2671 	if (dwc->gadget.speed != USB_SPEED_UNKNOWN) {
2672 		spin_unlock(&dwc->lock);
2673 		usb_gadget_udc_reset(&dwc->gadget, dwc->gadget_driver);
2674 		spin_lock(&dwc->lock);
2675 	}
2676 }
2677 
2678 static void dwc3_stop_active_transfer(struct dwc3_ep *dep, bool force,
2679 	bool interrupt)
2680 {
2681 	struct dwc3 *dwc = dep->dwc;
2682 	struct dwc3_gadget_ep_cmd_params params;
2683 	u32 cmd;
2684 	int ret;
2685 
2686 	if (!(dep->flags & DWC3_EP_TRANSFER_STARTED))
2687 		return;
2688 
2689 	/*
2690 	 * NOTICE: We are violating what the Databook says about the
2691 	 * EndTransfer command. Ideally we would _always_ wait for the
2692 	 * EndTransfer Command Completion IRQ, but that's causing too
2693 	 * much trouble synchronizing between us and gadget driver.
2694 	 *
2695 	 * We have discussed this with the IP Provider and it was
2696 	 * suggested to giveback all requests here, but give HW some
2697 	 * extra time to synchronize with the interconnect. We're using
2698 	 * an arbitrary 100us delay for that.
2699 	 *
2700 	 * Note also that a similar handling was tested by Synopsys
2701 	 * (thanks a lot Paul) and nothing bad has come out of it.
2702 	 * In short, what we're doing is:
2703 	 *
2704 	 * - Issue EndTransfer WITH CMDIOC bit set
2705 	 * - Wait 100us
2706 	 *
2707 	 * As of IP version 3.10a of the DWC_usb3 IP, the controller
2708 	 * supports a mode to work around the above limitation. The
2709 	 * software can poll the CMDACT bit in the DEPCMD register
2710 	 * after issuing a EndTransfer command. This mode is enabled
2711 	 * by writing GUCTL2[14]. This polling is already done in the
2712 	 * dwc3_send_gadget_ep_cmd() function so if the mode is
2713 	 * enabled, the EndTransfer command will have completed upon
2714 	 * returning from this function and we don't need to delay for
2715 	 * 100us.
2716 	 *
2717 	 * This mode is NOT available on the DWC_usb31 IP.
2718 	 */
2719 
2720 	cmd = DWC3_DEPCMD_ENDTRANSFER;
2721 	cmd |= force ? DWC3_DEPCMD_HIPRI_FORCERM : 0;
2722 	cmd |= interrupt ? DWC3_DEPCMD_CMDIOC : 0;
2723 	cmd |= DWC3_DEPCMD_PARAM(dep->resource_index);
2724 	memset(&params, 0, sizeof(params));
2725 	ret = dwc3_send_gadget_ep_cmd(dep, cmd, &params);
2726 	WARN_ON_ONCE(ret);
2727 	dep->resource_index = 0;
2728 
2729 	if (!interrupt)
2730 		dep->flags &= ~DWC3_EP_TRANSFER_STARTED;
2731 
2732 	if (dwc3_is_usb31(dwc) || dwc->revision < DWC3_REVISION_310A)
2733 		udelay(100);
2734 }
2735 
2736 static void dwc3_clear_stall_all_ep(struct dwc3 *dwc)
2737 {
2738 	u32 epnum;
2739 
2740 	for (epnum = 1; epnum < DWC3_ENDPOINTS_NUM; epnum++) {
2741 		struct dwc3_ep *dep;
2742 		int ret;
2743 
2744 		dep = dwc->eps[epnum];
2745 		if (!dep)
2746 			continue;
2747 
2748 		if (!(dep->flags & DWC3_EP_STALL))
2749 			continue;
2750 
2751 		dep->flags &= ~DWC3_EP_STALL;
2752 
2753 		ret = dwc3_send_clear_stall_ep_cmd(dep);
2754 		WARN_ON_ONCE(ret);
2755 	}
2756 }
2757 
2758 static void dwc3_gadget_disconnect_interrupt(struct dwc3 *dwc)
2759 {
2760 	int			reg;
2761 
2762 	reg = dwc3_readl(dwc->regs, DWC3_DCTL);
2763 	reg &= ~DWC3_DCTL_INITU1ENA;
2764 	dwc3_writel(dwc->regs, DWC3_DCTL, reg);
2765 
2766 	reg &= ~DWC3_DCTL_INITU2ENA;
2767 	dwc3_writel(dwc->regs, DWC3_DCTL, reg);
2768 
2769 	dwc3_disconnect_gadget(dwc);
2770 
2771 	dwc->gadget.speed = USB_SPEED_UNKNOWN;
2772 	dwc->setup_packet_pending = false;
2773 	usb_gadget_set_state(&dwc->gadget, USB_STATE_NOTATTACHED);
2774 
2775 	dwc->connected = false;
2776 }
2777 
2778 static void dwc3_gadget_reset_interrupt(struct dwc3 *dwc)
2779 {
2780 	u32			reg;
2781 
2782 	dwc->connected = true;
2783 
2784 	/*
2785 	 * WORKAROUND: DWC3 revisions <1.88a have an issue which
2786 	 * would cause a missing Disconnect Event if there's a
2787 	 * pending Setup Packet in the FIFO.
2788 	 *
2789 	 * There's no suggested workaround on the official Bug
2790 	 * report, which states that "unless the driver/application
2791 	 * is doing any special handling of a disconnect event,
2792 	 * there is no functional issue".
2793 	 *
2794 	 * Unfortunately, it turns out that we _do_ some special
2795 	 * handling of a disconnect event, namely complete all
2796 	 * pending transfers, notify gadget driver of the
2797 	 * disconnection, and so on.
2798 	 *
2799 	 * Our suggested workaround is to follow the Disconnect
2800 	 * Event steps here, instead, based on a setup_packet_pending
2801 	 * flag. Such flag gets set whenever we have a SETUP_PENDING
2802 	 * status for EP0 TRBs and gets cleared on XferComplete for the
2803 	 * same endpoint.
2804 	 *
2805 	 * Refers to:
2806 	 *
2807 	 * STAR#9000466709: RTL: Device : Disconnect event not
2808 	 * generated if setup packet pending in FIFO
2809 	 */
2810 	if (dwc->revision < DWC3_REVISION_188A) {
2811 		if (dwc->setup_packet_pending)
2812 			dwc3_gadget_disconnect_interrupt(dwc);
2813 	}
2814 
2815 	dwc3_reset_gadget(dwc);
2816 
2817 	reg = dwc3_readl(dwc->regs, DWC3_DCTL);
2818 	reg &= ~DWC3_DCTL_TSTCTRL_MASK;
2819 	dwc3_writel(dwc->regs, DWC3_DCTL, reg);
2820 	dwc->test_mode = false;
2821 	dwc3_clear_stall_all_ep(dwc);
2822 
2823 	/* Reset device address to zero */
2824 	reg = dwc3_readl(dwc->regs, DWC3_DCFG);
2825 	reg &= ~(DWC3_DCFG_DEVADDR_MASK);
2826 	dwc3_writel(dwc->regs, DWC3_DCFG, reg);
2827 }
2828 
2829 static void dwc3_gadget_conndone_interrupt(struct dwc3 *dwc)
2830 {
2831 	struct dwc3_ep		*dep;
2832 	int			ret;
2833 	u32			reg;
2834 	u8			speed;
2835 
2836 	reg = dwc3_readl(dwc->regs, DWC3_DSTS);
2837 	speed = reg & DWC3_DSTS_CONNECTSPD;
2838 	dwc->speed = speed;
2839 
2840 	/*
2841 	 * RAMClkSel is reset to 0 after USB reset, so it must be reprogrammed
2842 	 * each time on Connect Done.
2843 	 *
2844 	 * Currently we always use the reset value. If any platform
2845 	 * wants to set this to a different value, we need to add a
2846 	 * setting and update GCTL.RAMCLKSEL here.
2847 	 */
2848 
2849 	switch (speed) {
2850 	case DWC3_DSTS_SUPERSPEED_PLUS:
2851 		dwc3_gadget_ep0_desc.wMaxPacketSize = cpu_to_le16(512);
2852 		dwc->gadget.ep0->maxpacket = 512;
2853 		dwc->gadget.speed = USB_SPEED_SUPER_PLUS;
2854 		break;
2855 	case DWC3_DSTS_SUPERSPEED:
2856 		/*
2857 		 * WORKAROUND: DWC3 revisions <1.90a have an issue which
2858 		 * would cause a missing USB3 Reset event.
2859 		 *
2860 		 * In such situations, we should force a USB3 Reset
2861 		 * event by calling our dwc3_gadget_reset_interrupt()
2862 		 * routine.
2863 		 *
2864 		 * Refers to:
2865 		 *
2866 		 * STAR#9000483510: RTL: SS : USB3 reset event may
2867 		 * not be generated always when the link enters poll
2868 		 */
2869 		if (dwc->revision < DWC3_REVISION_190A)
2870 			dwc3_gadget_reset_interrupt(dwc);
2871 
2872 		dwc3_gadget_ep0_desc.wMaxPacketSize = cpu_to_le16(512);
2873 		dwc->gadget.ep0->maxpacket = 512;
2874 		dwc->gadget.speed = USB_SPEED_SUPER;
2875 		break;
2876 	case DWC3_DSTS_HIGHSPEED:
2877 		dwc3_gadget_ep0_desc.wMaxPacketSize = cpu_to_le16(64);
2878 		dwc->gadget.ep0->maxpacket = 64;
2879 		dwc->gadget.speed = USB_SPEED_HIGH;
2880 		break;
2881 	case DWC3_DSTS_FULLSPEED:
2882 		dwc3_gadget_ep0_desc.wMaxPacketSize = cpu_to_le16(64);
2883 		dwc->gadget.ep0->maxpacket = 64;
2884 		dwc->gadget.speed = USB_SPEED_FULL;
2885 		break;
2886 	case DWC3_DSTS_LOWSPEED:
2887 		dwc3_gadget_ep0_desc.wMaxPacketSize = cpu_to_le16(8);
2888 		dwc->gadget.ep0->maxpacket = 8;
2889 		dwc->gadget.speed = USB_SPEED_LOW;
2890 		break;
2891 	}
2892 
2893 	dwc->eps[1]->endpoint.maxpacket = dwc->gadget.ep0->maxpacket;
2894 
2895 	/* Enable USB2 LPM Capability */
2896 
2897 	if ((dwc->revision > DWC3_REVISION_194A) &&
2898 	    (speed != DWC3_DSTS_SUPERSPEED) &&
2899 	    (speed != DWC3_DSTS_SUPERSPEED_PLUS)) {
2900 		reg = dwc3_readl(dwc->regs, DWC3_DCFG);
2901 		reg |= DWC3_DCFG_LPM_CAP;
2902 		dwc3_writel(dwc->regs, DWC3_DCFG, reg);
2903 
2904 		reg = dwc3_readl(dwc->regs, DWC3_DCTL);
2905 		reg &= ~(DWC3_DCTL_HIRD_THRES_MASK | DWC3_DCTL_L1_HIBER_EN);
2906 
2907 		reg |= DWC3_DCTL_HIRD_THRES(dwc->hird_threshold |
2908 					    (dwc->is_utmi_l1_suspend << 4));
2909 
2910 		/*
2911 		 * When dwc3 revisions >= 2.40a, LPM Erratum is enabled and
2912 		 * DCFG.LPMCap is set, core responses with an ACK and the
2913 		 * BESL value in the LPM token is less than or equal to LPM
2914 		 * NYET threshold.
2915 		 */
2916 		WARN_ONCE(dwc->revision < DWC3_REVISION_240A
2917 				&& dwc->has_lpm_erratum,
2918 				"LPM Erratum not available on dwc3 revisions < 2.40a\n");
2919 
2920 		if (dwc->has_lpm_erratum && dwc->revision >= DWC3_REVISION_240A)
2921 			reg |= DWC3_DCTL_NYET_THRES(dwc->lpm_nyet_threshold);
2922 
2923 		dwc3_writel(dwc->regs, DWC3_DCTL, reg);
2924 	} else {
2925 		reg = dwc3_readl(dwc->regs, DWC3_DCTL);
2926 		reg &= ~DWC3_DCTL_HIRD_THRES_MASK;
2927 		dwc3_writel(dwc->regs, DWC3_DCTL, reg);
2928 	}
2929 
2930 	dep = dwc->eps[0];
2931 	ret = __dwc3_gadget_ep_enable(dep, DWC3_DEPCFG_ACTION_MODIFY);
2932 	if (ret) {
2933 		dev_err(dwc->dev, "failed to enable %s\n", dep->name);
2934 		return;
2935 	}
2936 
2937 	dep = dwc->eps[1];
2938 	ret = __dwc3_gadget_ep_enable(dep, DWC3_DEPCFG_ACTION_MODIFY);
2939 	if (ret) {
2940 		dev_err(dwc->dev, "failed to enable %s\n", dep->name);
2941 		return;
2942 	}
2943 
2944 	/*
2945 	 * Configure PHY via GUSB3PIPECTLn if required.
2946 	 *
2947 	 * Update GTXFIFOSIZn
2948 	 *
2949 	 * In both cases reset values should be sufficient.
2950 	 */
2951 }
2952 
2953 static void dwc3_gadget_wakeup_interrupt(struct dwc3 *dwc)
2954 {
2955 	/*
2956 	 * TODO take core out of low power mode when that's
2957 	 * implemented.
2958 	 */
2959 
2960 	if (dwc->gadget_driver && dwc->gadget_driver->resume) {
2961 		spin_unlock(&dwc->lock);
2962 		dwc->gadget_driver->resume(&dwc->gadget);
2963 		spin_lock(&dwc->lock);
2964 	}
2965 }
2966 
2967 static void dwc3_gadget_linksts_change_interrupt(struct dwc3 *dwc,
2968 		unsigned int evtinfo)
2969 {
2970 	enum dwc3_link_state	next = evtinfo & DWC3_LINK_STATE_MASK;
2971 	unsigned int		pwropt;
2972 
2973 	/*
2974 	 * WORKAROUND: DWC3 < 2.50a have an issue when configured without
2975 	 * Hibernation mode enabled which would show up when device detects
2976 	 * host-initiated U3 exit.
2977 	 *
2978 	 * In that case, device will generate a Link State Change Interrupt
2979 	 * from U3 to RESUME which is only necessary if Hibernation is
2980 	 * configured in.
2981 	 *
2982 	 * There are no functional changes due to such spurious event and we
2983 	 * just need to ignore it.
2984 	 *
2985 	 * Refers to:
2986 	 *
2987 	 * STAR#9000570034 RTL: SS Resume event generated in non-Hibernation
2988 	 * operational mode
2989 	 */
2990 	pwropt = DWC3_GHWPARAMS1_EN_PWROPT(dwc->hwparams.hwparams1);
2991 	if ((dwc->revision < DWC3_REVISION_250A) &&
2992 			(pwropt != DWC3_GHWPARAMS1_EN_PWROPT_HIB)) {
2993 		if ((dwc->link_state == DWC3_LINK_STATE_U3) &&
2994 				(next == DWC3_LINK_STATE_RESUME)) {
2995 			return;
2996 		}
2997 	}
2998 
2999 	/*
3000 	 * WORKAROUND: DWC3 Revisions <1.83a have an issue which, depending
3001 	 * on the link partner, the USB session might do multiple entry/exit
3002 	 * of low power states before a transfer takes place.
3003 	 *
3004 	 * Due to this problem, we might experience lower throughput. The
3005 	 * suggested workaround is to disable DCTL[12:9] bits if we're
3006 	 * transitioning from U1/U2 to U0 and enable those bits again
3007 	 * after a transfer completes and there are no pending transfers
3008 	 * on any of the enabled endpoints.
3009 	 *
3010 	 * This is the first half of that workaround.
3011 	 *
3012 	 * Refers to:
3013 	 *
3014 	 * STAR#9000446952: RTL: Device SS : if U1/U2 ->U0 takes >128us
3015 	 * core send LGO_Ux entering U0
3016 	 */
3017 	if (dwc->revision < DWC3_REVISION_183A) {
3018 		if (next == DWC3_LINK_STATE_U0) {
3019 			u32	u1u2;
3020 			u32	reg;
3021 
3022 			switch (dwc->link_state) {
3023 			case DWC3_LINK_STATE_U1:
3024 			case DWC3_LINK_STATE_U2:
3025 				reg = dwc3_readl(dwc->regs, DWC3_DCTL);
3026 				u1u2 = reg & (DWC3_DCTL_INITU2ENA
3027 						| DWC3_DCTL_ACCEPTU2ENA
3028 						| DWC3_DCTL_INITU1ENA
3029 						| DWC3_DCTL_ACCEPTU1ENA);
3030 
3031 				if (!dwc->u1u2)
3032 					dwc->u1u2 = reg & u1u2;
3033 
3034 				reg &= ~u1u2;
3035 
3036 				dwc3_writel(dwc->regs, DWC3_DCTL, reg);
3037 				break;
3038 			default:
3039 				/* do nothing */
3040 				break;
3041 			}
3042 		}
3043 	}
3044 
3045 	switch (next) {
3046 	case DWC3_LINK_STATE_U1:
3047 		if (dwc->speed == USB_SPEED_SUPER)
3048 			dwc3_suspend_gadget(dwc);
3049 		break;
3050 	case DWC3_LINK_STATE_U2:
3051 	case DWC3_LINK_STATE_U3:
3052 		dwc3_suspend_gadget(dwc);
3053 		break;
3054 	case DWC3_LINK_STATE_RESUME:
3055 		dwc3_resume_gadget(dwc);
3056 		break;
3057 	default:
3058 		/* do nothing */
3059 		break;
3060 	}
3061 
3062 	dwc->link_state = next;
3063 }
3064 
3065 static void dwc3_gadget_suspend_interrupt(struct dwc3 *dwc,
3066 					  unsigned int evtinfo)
3067 {
3068 	enum dwc3_link_state next = evtinfo & DWC3_LINK_STATE_MASK;
3069 
3070 	if (dwc->link_state != next && next == DWC3_LINK_STATE_U3)
3071 		dwc3_suspend_gadget(dwc);
3072 
3073 	dwc->link_state = next;
3074 }
3075 
3076 static void dwc3_gadget_hibernation_interrupt(struct dwc3 *dwc,
3077 		unsigned int evtinfo)
3078 {
3079 	unsigned int is_ss = evtinfo & BIT(4);
3080 
3081 	/*
3082 	 * WORKAROUND: DWC3 revison 2.20a with hibernation support
3083 	 * have a known issue which can cause USB CV TD.9.23 to fail
3084 	 * randomly.
3085 	 *
3086 	 * Because of this issue, core could generate bogus hibernation
3087 	 * events which SW needs to ignore.
3088 	 *
3089 	 * Refers to:
3090 	 *
3091 	 * STAR#9000546576: Device Mode Hibernation: Issue in USB 2.0
3092 	 * Device Fallback from SuperSpeed
3093 	 */
3094 	if (is_ss ^ (dwc->speed == USB_SPEED_SUPER))
3095 		return;
3096 
3097 	/* enter hibernation here */
3098 }
3099 
3100 static void dwc3_gadget_interrupt(struct dwc3 *dwc,
3101 		const struct dwc3_event_devt *event)
3102 {
3103 	switch (event->type) {
3104 	case DWC3_DEVICE_EVENT_DISCONNECT:
3105 		dwc3_gadget_disconnect_interrupt(dwc);
3106 		break;
3107 	case DWC3_DEVICE_EVENT_RESET:
3108 		dwc3_gadget_reset_interrupt(dwc);
3109 		break;
3110 	case DWC3_DEVICE_EVENT_CONNECT_DONE:
3111 		dwc3_gadget_conndone_interrupt(dwc);
3112 		break;
3113 	case DWC3_DEVICE_EVENT_WAKEUP:
3114 		dwc3_gadget_wakeup_interrupt(dwc);
3115 		break;
3116 	case DWC3_DEVICE_EVENT_HIBER_REQ:
3117 		if (dev_WARN_ONCE(dwc->dev, !dwc->has_hibernation,
3118 					"unexpected hibernation event\n"))
3119 			break;
3120 
3121 		dwc3_gadget_hibernation_interrupt(dwc, event->event_info);
3122 		break;
3123 	case DWC3_DEVICE_EVENT_LINK_STATUS_CHANGE:
3124 		dwc3_gadget_linksts_change_interrupt(dwc, event->event_info);
3125 		break;
3126 	case DWC3_DEVICE_EVENT_EOPF:
3127 		/* It changed to be suspend event for version 2.30a and above */
3128 		if (dwc->revision >= DWC3_REVISION_230A) {
3129 			/*
3130 			 * Ignore suspend event until the gadget enters into
3131 			 * USB_STATE_CONFIGURED state.
3132 			 */
3133 			if (dwc->gadget.state >= USB_STATE_CONFIGURED)
3134 				dwc3_gadget_suspend_interrupt(dwc,
3135 						event->event_info);
3136 		}
3137 		break;
3138 	case DWC3_DEVICE_EVENT_SOF:
3139 	case DWC3_DEVICE_EVENT_ERRATIC_ERROR:
3140 	case DWC3_DEVICE_EVENT_CMD_CMPL:
3141 	case DWC3_DEVICE_EVENT_OVERFLOW:
3142 		break;
3143 	default:
3144 		dev_WARN(dwc->dev, "UNKNOWN IRQ %d\n", event->type);
3145 	}
3146 }
3147 
3148 static void dwc3_process_event_entry(struct dwc3 *dwc,
3149 		const union dwc3_event *event)
3150 {
3151 	trace_dwc3_event(event->raw, dwc);
3152 
3153 	if (!event->type.is_devspec)
3154 		dwc3_endpoint_interrupt(dwc, &event->depevt);
3155 	else if (event->type.type == DWC3_EVENT_TYPE_DEV)
3156 		dwc3_gadget_interrupt(dwc, &event->devt);
3157 	else
3158 		dev_err(dwc->dev, "UNKNOWN IRQ type %d\n", event->raw);
3159 }
3160 
3161 static irqreturn_t dwc3_process_event_buf(struct dwc3_event_buffer *evt)
3162 {
3163 	struct dwc3 *dwc = evt->dwc;
3164 	irqreturn_t ret = IRQ_NONE;
3165 	int left;
3166 	u32 reg;
3167 
3168 	left = evt->count;
3169 
3170 	if (!(evt->flags & DWC3_EVENT_PENDING))
3171 		return IRQ_NONE;
3172 
3173 	while (left > 0) {
3174 		union dwc3_event event;
3175 
3176 		event.raw = *(u32 *) (evt->cache + evt->lpos);
3177 
3178 		dwc3_process_event_entry(dwc, &event);
3179 
3180 		/*
3181 		 * FIXME we wrap around correctly to the next entry as
3182 		 * almost all entries are 4 bytes in size. There is one
3183 		 * entry which has 12 bytes which is a regular entry
3184 		 * followed by 8 bytes data. ATM I don't know how
3185 		 * things are organized if we get next to the a
3186 		 * boundary so I worry about that once we try to handle
3187 		 * that.
3188 		 */
3189 		evt->lpos = (evt->lpos + 4) % evt->length;
3190 		left -= 4;
3191 	}
3192 
3193 	evt->count = 0;
3194 	evt->flags &= ~DWC3_EVENT_PENDING;
3195 	ret = IRQ_HANDLED;
3196 
3197 	/* Unmask interrupt */
3198 	reg = dwc3_readl(dwc->regs, DWC3_GEVNTSIZ(0));
3199 	reg &= ~DWC3_GEVNTSIZ_INTMASK;
3200 	dwc3_writel(dwc->regs, DWC3_GEVNTSIZ(0), reg);
3201 
3202 	if (dwc->imod_interval) {
3203 		dwc3_writel(dwc->regs, DWC3_GEVNTCOUNT(0), DWC3_GEVNTCOUNT_EHB);
3204 		dwc3_writel(dwc->regs, DWC3_DEV_IMOD(0), dwc->imod_interval);
3205 	}
3206 
3207 	return ret;
3208 }
3209 
3210 static irqreturn_t dwc3_thread_interrupt(int irq, void *_evt)
3211 {
3212 	struct dwc3_event_buffer *evt = _evt;
3213 	struct dwc3 *dwc = evt->dwc;
3214 	unsigned long flags;
3215 	irqreturn_t ret = IRQ_NONE;
3216 
3217 	spin_lock_irqsave(&dwc->lock, flags);
3218 	ret = dwc3_process_event_buf(evt);
3219 	spin_unlock_irqrestore(&dwc->lock, flags);
3220 
3221 	return ret;
3222 }
3223 
3224 static irqreturn_t dwc3_check_event_buf(struct dwc3_event_buffer *evt)
3225 {
3226 	struct dwc3 *dwc = evt->dwc;
3227 	u32 amount;
3228 	u32 count;
3229 	u32 reg;
3230 
3231 	if (pm_runtime_suspended(dwc->dev)) {
3232 		pm_runtime_get(dwc->dev);
3233 		disable_irq_nosync(dwc->irq_gadget);
3234 		dwc->pending_events = true;
3235 		return IRQ_HANDLED;
3236 	}
3237 
3238 	/*
3239 	 * With PCIe legacy interrupt, test shows that top-half irq handler can
3240 	 * be called again after HW interrupt deassertion. Check if bottom-half
3241 	 * irq event handler completes before caching new event to prevent
3242 	 * losing events.
3243 	 */
3244 	if (evt->flags & DWC3_EVENT_PENDING)
3245 		return IRQ_HANDLED;
3246 
3247 	count = dwc3_readl(dwc->regs, DWC3_GEVNTCOUNT(0));
3248 	count &= DWC3_GEVNTCOUNT_MASK;
3249 	if (!count)
3250 		return IRQ_NONE;
3251 
3252 	evt->count = count;
3253 	evt->flags |= DWC3_EVENT_PENDING;
3254 
3255 	/* Mask interrupt */
3256 	reg = dwc3_readl(dwc->regs, DWC3_GEVNTSIZ(0));
3257 	reg |= DWC3_GEVNTSIZ_INTMASK;
3258 	dwc3_writel(dwc->regs, DWC3_GEVNTSIZ(0), reg);
3259 
3260 	amount = min(count, evt->length - evt->lpos);
3261 	memcpy(evt->cache + evt->lpos, evt->buf + evt->lpos, amount);
3262 
3263 	if (amount < count)
3264 		memcpy(evt->cache, evt->buf, count - amount);
3265 
3266 	dwc3_writel(dwc->regs, DWC3_GEVNTCOUNT(0), count);
3267 
3268 	return IRQ_WAKE_THREAD;
3269 }
3270 
3271 static irqreturn_t dwc3_interrupt(int irq, void *_evt)
3272 {
3273 	struct dwc3_event_buffer	*evt = _evt;
3274 
3275 	return dwc3_check_event_buf(evt);
3276 }
3277 
3278 static int dwc3_gadget_get_irq(struct dwc3 *dwc)
3279 {
3280 	struct platform_device *dwc3_pdev = to_platform_device(dwc->dev);
3281 	int irq;
3282 
3283 	irq = platform_get_irq_byname_optional(dwc3_pdev, "peripheral");
3284 	if (irq > 0)
3285 		goto out;
3286 
3287 	if (irq == -EPROBE_DEFER)
3288 		goto out;
3289 
3290 	irq = platform_get_irq_byname_optional(dwc3_pdev, "dwc_usb3");
3291 	if (irq > 0)
3292 		goto out;
3293 
3294 	if (irq == -EPROBE_DEFER)
3295 		goto out;
3296 
3297 	irq = platform_get_irq(dwc3_pdev, 0);
3298 	if (irq > 0)
3299 		goto out;
3300 
3301 	if (!irq)
3302 		irq = -EINVAL;
3303 
3304 out:
3305 	return irq;
3306 }
3307 
3308 /**
3309  * dwc3_gadget_init - initializes gadget related registers
3310  * @dwc: pointer to our controller context structure
3311  *
3312  * Returns 0 on success otherwise negative errno.
3313  */
3314 int dwc3_gadget_init(struct dwc3 *dwc)
3315 {
3316 	int ret;
3317 	int irq;
3318 
3319 	irq = dwc3_gadget_get_irq(dwc);
3320 	if (irq < 0) {
3321 		ret = irq;
3322 		goto err0;
3323 	}
3324 
3325 	dwc->irq_gadget = irq;
3326 
3327 	dwc->ep0_trb = dma_alloc_coherent(dwc->sysdev,
3328 					  sizeof(*dwc->ep0_trb) * 2,
3329 					  &dwc->ep0_trb_addr, GFP_KERNEL);
3330 	if (!dwc->ep0_trb) {
3331 		dev_err(dwc->dev, "failed to allocate ep0 trb\n");
3332 		ret = -ENOMEM;
3333 		goto err0;
3334 	}
3335 
3336 	dwc->setup_buf = kzalloc(DWC3_EP0_SETUP_SIZE, GFP_KERNEL);
3337 	if (!dwc->setup_buf) {
3338 		ret = -ENOMEM;
3339 		goto err1;
3340 	}
3341 
3342 	dwc->bounce = dma_alloc_coherent(dwc->sysdev, DWC3_BOUNCE_SIZE,
3343 			&dwc->bounce_addr, GFP_KERNEL);
3344 	if (!dwc->bounce) {
3345 		ret = -ENOMEM;
3346 		goto err2;
3347 	}
3348 
3349 	init_completion(&dwc->ep0_in_setup);
3350 
3351 	dwc->gadget.ops			= &dwc3_gadget_ops;
3352 	dwc->gadget.speed		= USB_SPEED_UNKNOWN;
3353 	dwc->gadget.sg_supported	= true;
3354 	dwc->gadget.name		= "dwc3-gadget";
3355 	dwc->gadget.lpm_capable		= true;
3356 
3357 	/*
3358 	 * FIXME We might be setting max_speed to <SUPER, however versions
3359 	 * <2.20a of dwc3 have an issue with metastability (documented
3360 	 * elsewhere in this driver) which tells us we can't set max speed to
3361 	 * anything lower than SUPER.
3362 	 *
3363 	 * Because gadget.max_speed is only used by composite.c and function
3364 	 * drivers (i.e. it won't go into dwc3's registers) we are allowing this
3365 	 * to happen so we avoid sending SuperSpeed Capability descriptor
3366 	 * together with our BOS descriptor as that could confuse host into
3367 	 * thinking we can handle super speed.
3368 	 *
3369 	 * Note that, in fact, we won't even support GetBOS requests when speed
3370 	 * is less than super speed because we don't have means, yet, to tell
3371 	 * composite.c that we are USB 2.0 + LPM ECN.
3372 	 */
3373 	if (dwc->revision < DWC3_REVISION_220A &&
3374 	    !dwc->dis_metastability_quirk)
3375 		dev_info(dwc->dev, "changing max_speed on rev %08x\n",
3376 				dwc->revision);
3377 
3378 	dwc->gadget.max_speed		= dwc->maximum_speed;
3379 
3380 	/*
3381 	 * REVISIT: Here we should clear all pending IRQs to be
3382 	 * sure we're starting from a well known location.
3383 	 */
3384 
3385 	ret = dwc3_gadget_init_endpoints(dwc, dwc->num_eps);
3386 	if (ret)
3387 		goto err3;
3388 
3389 	ret = usb_add_gadget_udc(dwc->dev, &dwc->gadget);
3390 	if (ret) {
3391 		dev_err(dwc->dev, "failed to register udc\n");
3392 		goto err4;
3393 	}
3394 
3395 	dwc3_gadget_set_speed(&dwc->gadget, dwc->maximum_speed);
3396 
3397 	return 0;
3398 
3399 err4:
3400 	dwc3_gadget_free_endpoints(dwc);
3401 
3402 err3:
3403 	dma_free_coherent(dwc->sysdev, DWC3_BOUNCE_SIZE, dwc->bounce,
3404 			dwc->bounce_addr);
3405 
3406 err2:
3407 	kfree(dwc->setup_buf);
3408 
3409 err1:
3410 	dma_free_coherent(dwc->sysdev, sizeof(*dwc->ep0_trb) * 2,
3411 			dwc->ep0_trb, dwc->ep0_trb_addr);
3412 
3413 err0:
3414 	return ret;
3415 }
3416 
3417 /* -------------------------------------------------------------------------- */
3418 
3419 void dwc3_gadget_exit(struct dwc3 *dwc)
3420 {
3421 	usb_del_gadget_udc(&dwc->gadget);
3422 	dwc3_gadget_free_endpoints(dwc);
3423 	dma_free_coherent(dwc->sysdev, DWC3_BOUNCE_SIZE, dwc->bounce,
3424 			  dwc->bounce_addr);
3425 	kfree(dwc->setup_buf);
3426 	dma_free_coherent(dwc->sysdev, sizeof(*dwc->ep0_trb) * 2,
3427 			  dwc->ep0_trb, dwc->ep0_trb_addr);
3428 }
3429 
3430 int dwc3_gadget_suspend(struct dwc3 *dwc)
3431 {
3432 	if (!dwc->gadget_driver)
3433 		return 0;
3434 
3435 	dwc3_gadget_run_stop(dwc, false, false);
3436 	dwc3_disconnect_gadget(dwc);
3437 	__dwc3_gadget_stop(dwc);
3438 
3439 	return 0;
3440 }
3441 
3442 int dwc3_gadget_resume(struct dwc3 *dwc)
3443 {
3444 	int			ret;
3445 
3446 	if (!dwc->gadget_driver)
3447 		return 0;
3448 
3449 	ret = __dwc3_gadget_start(dwc);
3450 	if (ret < 0)
3451 		goto err0;
3452 
3453 	ret = dwc3_gadget_run_stop(dwc, true, false);
3454 	if (ret < 0)
3455 		goto err1;
3456 
3457 	return 0;
3458 
3459 err1:
3460 	__dwc3_gadget_stop(dwc);
3461 
3462 err0:
3463 	return ret;
3464 }
3465 
3466 void dwc3_gadget_process_pending_events(struct dwc3 *dwc)
3467 {
3468 	if (dwc->pending_events) {
3469 		dwc3_interrupt(dwc->irq_gadget, dwc->ev_buf);
3470 		dwc->pending_events = false;
3471 		enable_irq(dwc->irq_gadget);
3472 	}
3473 }
3474