1 /** 2 * ep0.c - DesignWare USB3 DRD Controller Endpoint 0 Handling 3 * 4 * Copyright (C) 2010-2011 Texas Instruments Incorporated - http://www.ti.com 5 * 6 * Authors: Felipe Balbi <balbi@ti.com>, 7 * Sebastian Andrzej Siewior <bigeasy@linutronix.de> 8 * 9 * Redistribution and use in source and binary forms, with or without 10 * modification, are permitted provided that the following conditions 11 * are met: 12 * 1. Redistributions of source code must retain the above copyright 13 * notice, this list of conditions, and the following disclaimer, 14 * without modification. 15 * 2. Redistributions in binary form must reproduce the above copyright 16 * notice, this list of conditions and the following disclaimer in the 17 * documentation and/or other materials provided with the distribution. 18 * 3. The names of the above-listed copyright holders may not be used 19 * to endorse or promote products derived from this software without 20 * specific prior written permission. 21 * 22 * ALTERNATIVELY, this software may be distributed under the terms of the 23 * GNU General Public License ("GPL") version 2, as published by the Free 24 * Software Foundation. 25 * 26 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS 27 * IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, 28 * THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR 29 * PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR 30 * CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, 31 * EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, 32 * PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR 33 * PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF 34 * LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING 35 * NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS 36 * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. 37 */ 38 39 #include <linux/kernel.h> 40 #include <linux/slab.h> 41 #include <linux/spinlock.h> 42 #include <linux/platform_device.h> 43 #include <linux/pm_runtime.h> 44 #include <linux/interrupt.h> 45 #include <linux/io.h> 46 #include <linux/list.h> 47 #include <linux/dma-mapping.h> 48 49 #include <linux/usb/ch9.h> 50 #include <linux/usb/gadget.h> 51 #include <linux/usb/composite.h> 52 53 #include "core.h" 54 #include "gadget.h" 55 #include "io.h" 56 57 static void dwc3_ep0_do_control_status(struct dwc3 *dwc, u32 epnum); 58 59 static const char *dwc3_ep0_state_string(enum dwc3_ep0_state state) 60 { 61 switch (state) { 62 case EP0_UNCONNECTED: 63 return "Unconnected"; 64 case EP0_SETUP_PHASE: 65 return "Setup Phase"; 66 case EP0_DATA_PHASE: 67 return "Data Phase"; 68 case EP0_STATUS_PHASE: 69 return "Status Phase"; 70 default: 71 return "UNKNOWN"; 72 } 73 } 74 75 static int dwc3_ep0_start_trans(struct dwc3 *dwc, u8 epnum, dma_addr_t buf_dma, 76 u32 len, u32 type) 77 { 78 struct dwc3_gadget_ep_cmd_params params; 79 struct dwc3_trb *trb; 80 struct dwc3_ep *dep; 81 82 int ret; 83 84 dep = dwc->eps[epnum]; 85 if (dep->flags & DWC3_EP_BUSY) { 86 dev_vdbg(dwc->dev, "%s: still busy\n", dep->name); 87 return 0; 88 } 89 90 trb = dwc->ep0_trb; 91 92 trb->bpl = lower_32_bits(buf_dma); 93 trb->bph = upper_32_bits(buf_dma); 94 trb->size = len; 95 trb->ctrl = type; 96 97 trb->ctrl |= (DWC3_TRB_CTRL_HWO 98 | DWC3_TRB_CTRL_LST 99 | DWC3_TRB_CTRL_IOC 100 | DWC3_TRB_CTRL_ISP_IMI); 101 102 memset(¶ms, 0, sizeof(params)); 103 params.param0 = upper_32_bits(dwc->ep0_trb_addr); 104 params.param1 = lower_32_bits(dwc->ep0_trb_addr); 105 106 ret = dwc3_send_gadget_ep_cmd(dwc, dep->number, 107 DWC3_DEPCMD_STARTTRANSFER, ¶ms); 108 if (ret < 0) { 109 dev_dbg(dwc->dev, "failed to send STARTTRANSFER command\n"); 110 return ret; 111 } 112 113 dep->flags |= DWC3_EP_BUSY; 114 dep->res_trans_idx = dwc3_gadget_ep_get_transfer_index(dwc, 115 dep->number); 116 117 dwc->ep0_next_event = DWC3_EP0_COMPLETE; 118 119 return 0; 120 } 121 122 static int __dwc3_gadget_ep0_queue(struct dwc3_ep *dep, 123 struct dwc3_request *req) 124 { 125 struct dwc3 *dwc = dep->dwc; 126 int ret = 0; 127 128 req->request.actual = 0; 129 req->request.status = -EINPROGRESS; 130 req->epnum = dep->number; 131 132 list_add_tail(&req->list, &dep->request_list); 133 134 /* 135 * Gadget driver might not be quick enough to queue a request 136 * before we get a Transfer Not Ready event on this endpoint. 137 * 138 * In that case, we will set DWC3_EP_PENDING_REQUEST. When that 139 * flag is set, it's telling us that as soon as Gadget queues the 140 * required request, we should kick the transfer here because the 141 * IRQ we were waiting for is long gone. 142 */ 143 if (dep->flags & DWC3_EP_PENDING_REQUEST) { 144 unsigned direction; 145 146 direction = !!(dep->flags & DWC3_EP0_DIR_IN); 147 148 if (dwc->ep0state != EP0_DATA_PHASE) { 149 dev_WARN(dwc->dev, "Unexpected pending request\n"); 150 return 0; 151 } 152 153 ret = dwc3_ep0_start_trans(dwc, direction, 154 req->request.dma, req->request.length, 155 DWC3_TRBCTL_CONTROL_DATA); 156 dep->flags &= ~(DWC3_EP_PENDING_REQUEST | 157 DWC3_EP0_DIR_IN); 158 } else if (dwc->delayed_status) { 159 dwc->delayed_status = false; 160 161 if (dwc->ep0state == EP0_STATUS_PHASE) 162 dwc3_ep0_do_control_status(dwc, 1); 163 else 164 dev_dbg(dwc->dev, "too early for delayed status\n"); 165 } 166 167 return ret; 168 } 169 170 int dwc3_gadget_ep0_queue(struct usb_ep *ep, struct usb_request *request, 171 gfp_t gfp_flags) 172 { 173 struct dwc3_request *req = to_dwc3_request(request); 174 struct dwc3_ep *dep = to_dwc3_ep(ep); 175 struct dwc3 *dwc = dep->dwc; 176 177 unsigned long flags; 178 179 int ret; 180 181 spin_lock_irqsave(&dwc->lock, flags); 182 if (!dep->desc) { 183 dev_dbg(dwc->dev, "trying to queue request %p to disabled %s\n", 184 request, dep->name); 185 ret = -ESHUTDOWN; 186 goto out; 187 } 188 189 /* we share one TRB for ep0/1 */ 190 if (!list_empty(&dep->request_list)) { 191 ret = -EBUSY; 192 goto out; 193 } 194 195 dev_vdbg(dwc->dev, "queueing request %p to %s length %d, state '%s'\n", 196 request, dep->name, request->length, 197 dwc3_ep0_state_string(dwc->ep0state)); 198 199 ret = __dwc3_gadget_ep0_queue(dep, req); 200 201 out: 202 spin_unlock_irqrestore(&dwc->lock, flags); 203 204 return ret; 205 } 206 207 static void dwc3_ep0_stall_and_restart(struct dwc3 *dwc) 208 { 209 struct dwc3_ep *dep = dwc->eps[0]; 210 211 /* stall is always issued on EP0 */ 212 __dwc3_gadget_ep_set_halt(dep, 1); 213 dep->flags = DWC3_EP_ENABLED; 214 dwc->delayed_status = false; 215 216 if (!list_empty(&dep->request_list)) { 217 struct dwc3_request *req; 218 219 req = next_request(&dep->request_list); 220 dwc3_gadget_giveback(dep, req, -ECONNRESET); 221 } 222 223 dwc->ep0state = EP0_SETUP_PHASE; 224 dwc3_ep0_out_start(dwc); 225 } 226 227 void dwc3_ep0_out_start(struct dwc3 *dwc) 228 { 229 int ret; 230 231 ret = dwc3_ep0_start_trans(dwc, 0, dwc->ctrl_req_addr, 8, 232 DWC3_TRBCTL_CONTROL_SETUP); 233 WARN_ON(ret < 0); 234 } 235 236 static struct dwc3_ep *dwc3_wIndex_to_dep(struct dwc3 *dwc, __le16 wIndex_le) 237 { 238 struct dwc3_ep *dep; 239 u32 windex = le16_to_cpu(wIndex_le); 240 u32 epnum; 241 242 epnum = (windex & USB_ENDPOINT_NUMBER_MASK) << 1; 243 if ((windex & USB_ENDPOINT_DIR_MASK) == USB_DIR_IN) 244 epnum |= 1; 245 246 dep = dwc->eps[epnum]; 247 if (dep->flags & DWC3_EP_ENABLED) 248 return dep; 249 250 return NULL; 251 } 252 253 static void dwc3_ep0_status_cmpl(struct usb_ep *ep, struct usb_request *req) 254 { 255 } 256 /* 257 * ch 9.4.5 258 */ 259 static int dwc3_ep0_handle_status(struct dwc3 *dwc, 260 struct usb_ctrlrequest *ctrl) 261 { 262 struct dwc3_ep *dep; 263 u32 recip; 264 u16 usb_status = 0; 265 __le16 *response_pkt; 266 267 recip = ctrl->bRequestType & USB_RECIP_MASK; 268 switch (recip) { 269 case USB_RECIP_DEVICE: 270 /* 271 * We are self-powered. U1/U2/LTM will be set later 272 * once we handle this states. RemoteWakeup is 0 on SS 273 */ 274 usb_status |= dwc->is_selfpowered << USB_DEVICE_SELF_POWERED; 275 break; 276 277 case USB_RECIP_INTERFACE: 278 /* 279 * Function Remote Wake Capable D0 280 * Function Remote Wakeup D1 281 */ 282 break; 283 284 case USB_RECIP_ENDPOINT: 285 dep = dwc3_wIndex_to_dep(dwc, ctrl->wIndex); 286 if (!dep) 287 return -EINVAL; 288 289 if (dep->flags & DWC3_EP_STALL) 290 usb_status = 1 << USB_ENDPOINT_HALT; 291 break; 292 default: 293 return -EINVAL; 294 }; 295 296 response_pkt = (__le16 *) dwc->setup_buf; 297 *response_pkt = cpu_to_le16(usb_status); 298 299 dep = dwc->eps[0]; 300 dwc->ep0_usb_req.dep = dep; 301 dwc->ep0_usb_req.request.length = sizeof(*response_pkt); 302 dwc->ep0_usb_req.request.buf = dwc->setup_buf; 303 dwc->ep0_usb_req.request.complete = dwc3_ep0_status_cmpl; 304 305 return __dwc3_gadget_ep0_queue(dep, &dwc->ep0_usb_req); 306 } 307 308 static int dwc3_ep0_handle_feature(struct dwc3 *dwc, 309 struct usb_ctrlrequest *ctrl, int set) 310 { 311 struct dwc3_ep *dep; 312 u32 recip; 313 u32 wValue; 314 u32 wIndex; 315 int ret; 316 317 wValue = le16_to_cpu(ctrl->wValue); 318 wIndex = le16_to_cpu(ctrl->wIndex); 319 recip = ctrl->bRequestType & USB_RECIP_MASK; 320 switch (recip) { 321 case USB_RECIP_DEVICE: 322 323 /* 324 * 9.4.1 says only only for SS, in AddressState only for 325 * default control pipe 326 */ 327 switch (wValue) { 328 case USB_DEVICE_U1_ENABLE: 329 case USB_DEVICE_U2_ENABLE: 330 case USB_DEVICE_LTM_ENABLE: 331 if (dwc->dev_state != DWC3_CONFIGURED_STATE) 332 return -EINVAL; 333 if (dwc->speed != DWC3_DSTS_SUPERSPEED) 334 return -EINVAL; 335 } 336 337 /* XXX add U[12] & LTM */ 338 switch (wValue) { 339 case USB_DEVICE_REMOTE_WAKEUP: 340 break; 341 case USB_DEVICE_U1_ENABLE: 342 break; 343 case USB_DEVICE_U2_ENABLE: 344 break; 345 case USB_DEVICE_LTM_ENABLE: 346 break; 347 348 case USB_DEVICE_TEST_MODE: 349 if ((wIndex & 0xff) != 0) 350 return -EINVAL; 351 if (!set) 352 return -EINVAL; 353 354 dwc->test_mode_nr = wIndex >> 8; 355 dwc->test_mode = true; 356 break; 357 default: 358 return -EINVAL; 359 } 360 break; 361 362 case USB_RECIP_INTERFACE: 363 switch (wValue) { 364 case USB_INTRF_FUNC_SUSPEND: 365 if (wIndex & USB_INTRF_FUNC_SUSPEND_LP) 366 /* XXX enable Low power suspend */ 367 ; 368 if (wIndex & USB_INTRF_FUNC_SUSPEND_RW) 369 /* XXX enable remote wakeup */ 370 ; 371 break; 372 default: 373 return -EINVAL; 374 } 375 break; 376 377 case USB_RECIP_ENDPOINT: 378 switch (wValue) { 379 case USB_ENDPOINT_HALT: 380 dep = dwc3_wIndex_to_dep(dwc, wIndex); 381 if (!dep) 382 return -EINVAL; 383 ret = __dwc3_gadget_ep_set_halt(dep, set); 384 if (ret) 385 return -EINVAL; 386 break; 387 default: 388 return -EINVAL; 389 } 390 break; 391 392 default: 393 return -EINVAL; 394 }; 395 396 return 0; 397 } 398 399 static int dwc3_ep0_set_address(struct dwc3 *dwc, struct usb_ctrlrequest *ctrl) 400 { 401 u32 addr; 402 u32 reg; 403 404 addr = le16_to_cpu(ctrl->wValue); 405 if (addr > 127) { 406 dev_dbg(dwc->dev, "invalid device address %d\n", addr); 407 return -EINVAL; 408 } 409 410 if (dwc->dev_state == DWC3_CONFIGURED_STATE) { 411 dev_dbg(dwc->dev, "trying to set address when configured\n"); 412 return -EINVAL; 413 } 414 415 reg = dwc3_readl(dwc->regs, DWC3_DCFG); 416 reg &= ~(DWC3_DCFG_DEVADDR_MASK); 417 reg |= DWC3_DCFG_DEVADDR(addr); 418 dwc3_writel(dwc->regs, DWC3_DCFG, reg); 419 420 if (addr) 421 dwc->dev_state = DWC3_ADDRESS_STATE; 422 else 423 dwc->dev_state = DWC3_DEFAULT_STATE; 424 425 return 0; 426 } 427 428 static int dwc3_ep0_delegate_req(struct dwc3 *dwc, struct usb_ctrlrequest *ctrl) 429 { 430 int ret; 431 432 spin_unlock(&dwc->lock); 433 ret = dwc->gadget_driver->setup(&dwc->gadget, ctrl); 434 spin_lock(&dwc->lock); 435 return ret; 436 } 437 438 static int dwc3_ep0_set_config(struct dwc3 *dwc, struct usb_ctrlrequest *ctrl) 439 { 440 u32 cfg; 441 int ret; 442 443 dwc->start_config_issued = false; 444 cfg = le16_to_cpu(ctrl->wValue); 445 446 switch (dwc->dev_state) { 447 case DWC3_DEFAULT_STATE: 448 return -EINVAL; 449 break; 450 451 case DWC3_ADDRESS_STATE: 452 ret = dwc3_ep0_delegate_req(dwc, ctrl); 453 /* if the cfg matches and the cfg is non zero */ 454 if (cfg && (!ret || (ret == USB_GADGET_DELAYED_STATUS))) { 455 dwc->dev_state = DWC3_CONFIGURED_STATE; 456 dwc->resize_fifos = true; 457 dev_dbg(dwc->dev, "resize fifos flag SET\n"); 458 } 459 break; 460 461 case DWC3_CONFIGURED_STATE: 462 ret = dwc3_ep0_delegate_req(dwc, ctrl); 463 if (!cfg) 464 dwc->dev_state = DWC3_ADDRESS_STATE; 465 break; 466 default: 467 ret = -EINVAL; 468 } 469 return ret; 470 } 471 472 static int dwc3_ep0_std_request(struct dwc3 *dwc, struct usb_ctrlrequest *ctrl) 473 { 474 int ret; 475 476 switch (ctrl->bRequest) { 477 case USB_REQ_GET_STATUS: 478 dev_vdbg(dwc->dev, "USB_REQ_GET_STATUS\n"); 479 ret = dwc3_ep0_handle_status(dwc, ctrl); 480 break; 481 case USB_REQ_CLEAR_FEATURE: 482 dev_vdbg(dwc->dev, "USB_REQ_CLEAR_FEATURE\n"); 483 ret = dwc3_ep0_handle_feature(dwc, ctrl, 0); 484 break; 485 case USB_REQ_SET_FEATURE: 486 dev_vdbg(dwc->dev, "USB_REQ_SET_FEATURE\n"); 487 ret = dwc3_ep0_handle_feature(dwc, ctrl, 1); 488 break; 489 case USB_REQ_SET_ADDRESS: 490 dev_vdbg(dwc->dev, "USB_REQ_SET_ADDRESS\n"); 491 ret = dwc3_ep0_set_address(dwc, ctrl); 492 break; 493 case USB_REQ_SET_CONFIGURATION: 494 dev_vdbg(dwc->dev, "USB_REQ_SET_CONFIGURATION\n"); 495 ret = dwc3_ep0_set_config(dwc, ctrl); 496 break; 497 default: 498 dev_vdbg(dwc->dev, "Forwarding to gadget driver\n"); 499 ret = dwc3_ep0_delegate_req(dwc, ctrl); 500 break; 501 }; 502 503 return ret; 504 } 505 506 static void dwc3_ep0_inspect_setup(struct dwc3 *dwc, 507 const struct dwc3_event_depevt *event) 508 { 509 struct usb_ctrlrequest *ctrl = dwc->ctrl_req; 510 int ret; 511 u32 len; 512 513 if (!dwc->gadget_driver) 514 goto err; 515 516 len = le16_to_cpu(ctrl->wLength); 517 if (!len) { 518 dwc->three_stage_setup = false; 519 dwc->ep0_expect_in = false; 520 dwc->ep0_next_event = DWC3_EP0_NRDY_STATUS; 521 } else { 522 dwc->three_stage_setup = true; 523 dwc->ep0_expect_in = !!(ctrl->bRequestType & USB_DIR_IN); 524 dwc->ep0_next_event = DWC3_EP0_NRDY_DATA; 525 } 526 527 if ((ctrl->bRequestType & USB_TYPE_MASK) == USB_TYPE_STANDARD) 528 ret = dwc3_ep0_std_request(dwc, ctrl); 529 else 530 ret = dwc3_ep0_delegate_req(dwc, ctrl); 531 532 if (ret == USB_GADGET_DELAYED_STATUS) 533 dwc->delayed_status = true; 534 535 if (ret >= 0) 536 return; 537 538 err: 539 dwc3_ep0_stall_and_restart(dwc); 540 } 541 542 static void dwc3_ep0_complete_data(struct dwc3 *dwc, 543 const struct dwc3_event_depevt *event) 544 { 545 struct dwc3_request *r = NULL; 546 struct usb_request *ur; 547 struct dwc3_trb *trb; 548 struct dwc3_ep *ep0; 549 u32 transferred; 550 u32 length; 551 u8 epnum; 552 553 epnum = event->endpoint_number; 554 ep0 = dwc->eps[0]; 555 556 dwc->ep0_next_event = DWC3_EP0_NRDY_STATUS; 557 558 r = next_request(&ep0->request_list); 559 ur = &r->request; 560 561 trb = dwc->ep0_trb; 562 length = trb->size & DWC3_TRB_SIZE_MASK; 563 564 if (dwc->ep0_bounced) { 565 unsigned transfer_size = ur->length; 566 unsigned maxp = ep0->endpoint.maxpacket; 567 568 transfer_size += (maxp - (transfer_size % maxp)); 569 transferred = min_t(u32, ur->length, 570 transfer_size - length); 571 memcpy(ur->buf, dwc->ep0_bounce, transferred); 572 dwc->ep0_bounced = false; 573 } else { 574 transferred = ur->length - length; 575 } 576 577 ur->actual += transferred; 578 579 if ((epnum & 1) && ur->actual < ur->length) { 580 /* for some reason we did not get everything out */ 581 582 dwc3_ep0_stall_and_restart(dwc); 583 } else { 584 /* 585 * handle the case where we have to send a zero packet. This 586 * seems to be case when req.length > maxpacket. Could it be? 587 */ 588 if (r) 589 dwc3_gadget_giveback(ep0, r, 0); 590 } 591 } 592 593 static void dwc3_ep0_complete_req(struct dwc3 *dwc, 594 const struct dwc3_event_depevt *event) 595 { 596 struct dwc3_request *r; 597 struct dwc3_ep *dep; 598 599 dep = dwc->eps[0]; 600 601 if (!list_empty(&dep->request_list)) { 602 r = next_request(&dep->request_list); 603 604 dwc3_gadget_giveback(dep, r, 0); 605 } 606 607 if (dwc->test_mode) { 608 int ret; 609 610 ret = dwc3_gadget_set_test_mode(dwc, dwc->test_mode_nr); 611 if (ret < 0) { 612 dev_dbg(dwc->dev, "Invalid Test #%d\n", 613 dwc->test_mode_nr); 614 dwc3_ep0_stall_and_restart(dwc); 615 } 616 } 617 618 dwc->ep0state = EP0_SETUP_PHASE; 619 dwc3_ep0_out_start(dwc); 620 } 621 622 static void dwc3_ep0_xfer_complete(struct dwc3 *dwc, 623 const struct dwc3_event_depevt *event) 624 { 625 struct dwc3_ep *dep = dwc->eps[event->endpoint_number]; 626 627 dep->flags &= ~DWC3_EP_BUSY; 628 dep->res_trans_idx = 0; 629 dwc->setup_packet_pending = false; 630 631 switch (dwc->ep0state) { 632 case EP0_SETUP_PHASE: 633 dev_vdbg(dwc->dev, "Inspecting Setup Bytes\n"); 634 dwc3_ep0_inspect_setup(dwc, event); 635 break; 636 637 case EP0_DATA_PHASE: 638 dev_vdbg(dwc->dev, "Data Phase\n"); 639 dwc3_ep0_complete_data(dwc, event); 640 break; 641 642 case EP0_STATUS_PHASE: 643 dev_vdbg(dwc->dev, "Status Phase\n"); 644 dwc3_ep0_complete_req(dwc, event); 645 break; 646 default: 647 WARN(true, "UNKNOWN ep0state %d\n", dwc->ep0state); 648 } 649 } 650 651 static void dwc3_ep0_do_control_setup(struct dwc3 *dwc, 652 const struct dwc3_event_depevt *event) 653 { 654 dwc3_ep0_out_start(dwc); 655 } 656 657 static void dwc3_ep0_do_control_data(struct dwc3 *dwc, 658 const struct dwc3_event_depevt *event) 659 { 660 struct dwc3_ep *dep; 661 struct dwc3_request *req; 662 int ret; 663 664 dep = dwc->eps[0]; 665 666 if (list_empty(&dep->request_list)) { 667 dev_vdbg(dwc->dev, "pending request for EP0 Data phase\n"); 668 dep->flags |= DWC3_EP_PENDING_REQUEST; 669 670 if (event->endpoint_number) 671 dep->flags |= DWC3_EP0_DIR_IN; 672 return; 673 } 674 675 req = next_request(&dep->request_list); 676 req->direction = !!event->endpoint_number; 677 678 if (req->request.length == 0) { 679 ret = dwc3_ep0_start_trans(dwc, event->endpoint_number, 680 dwc->ctrl_req_addr, 0, 681 DWC3_TRBCTL_CONTROL_DATA); 682 } else if ((req->request.length % dep->endpoint.maxpacket) 683 && (event->endpoint_number == 0)) { 684 ret = usb_gadget_map_request(&dwc->gadget, &req->request, 685 event->endpoint_number); 686 if (ret) { 687 dev_dbg(dwc->dev, "failed to map request\n"); 688 return; 689 } 690 691 WARN_ON(req->request.length > dep->endpoint.maxpacket); 692 693 dwc->ep0_bounced = true; 694 695 /* 696 * REVISIT in case request length is bigger than EP0 697 * wMaxPacketSize, we will need two chained TRBs to handle 698 * the transfer. 699 */ 700 ret = dwc3_ep0_start_trans(dwc, event->endpoint_number, 701 dwc->ep0_bounce_addr, dep->endpoint.maxpacket, 702 DWC3_TRBCTL_CONTROL_DATA); 703 } else { 704 ret = usb_gadget_map_request(&dwc->gadget, &req->request, 705 event->endpoint_number); 706 if (ret) { 707 dev_dbg(dwc->dev, "failed to map request\n"); 708 return; 709 } 710 711 ret = dwc3_ep0_start_trans(dwc, event->endpoint_number, 712 req->request.dma, req->request.length, 713 DWC3_TRBCTL_CONTROL_DATA); 714 } 715 716 WARN_ON(ret < 0); 717 } 718 719 static int dwc3_ep0_start_control_status(struct dwc3_ep *dep) 720 { 721 struct dwc3 *dwc = dep->dwc; 722 u32 type; 723 724 type = dwc->three_stage_setup ? DWC3_TRBCTL_CONTROL_STATUS3 725 : DWC3_TRBCTL_CONTROL_STATUS2; 726 727 return dwc3_ep0_start_trans(dwc, dep->number, 728 dwc->ctrl_req_addr, 0, type); 729 } 730 731 static void dwc3_ep0_do_control_status(struct dwc3 *dwc, u32 epnum) 732 { 733 struct dwc3_ep *dep = dwc->eps[epnum]; 734 735 if (dwc->resize_fifos) { 736 dev_dbg(dwc->dev, "starting to resize fifos\n"); 737 dwc3_gadget_resize_tx_fifos(dwc); 738 dwc->resize_fifos = 0; 739 } 740 741 WARN_ON(dwc3_ep0_start_control_status(dep)); 742 } 743 744 static void dwc3_ep0_xfernotready(struct dwc3 *dwc, 745 const struct dwc3_event_depevt *event) 746 { 747 dwc->setup_packet_pending = true; 748 749 /* 750 * This part is very tricky: If we has just handled 751 * XferNotReady(Setup) and we're now expecting a 752 * XferComplete but, instead, we receive another 753 * XferNotReady(Setup), we should STALL and restart 754 * the state machine. 755 * 756 * In all other cases, we just continue waiting 757 * for the XferComplete event. 758 * 759 * We are a little bit unsafe here because we're 760 * not trying to ensure that last event was, indeed, 761 * XferNotReady(Setup). 762 * 763 * Still, we don't expect any condition where that 764 * should happen and, even if it does, it would be 765 * another error condition. 766 */ 767 if (dwc->ep0_next_event == DWC3_EP0_COMPLETE) { 768 switch (event->status) { 769 case DEPEVT_STATUS_CONTROL_SETUP: 770 dev_vdbg(dwc->dev, "Unexpected XferNotReady(Setup)\n"); 771 dwc3_ep0_stall_and_restart(dwc); 772 break; 773 case DEPEVT_STATUS_CONTROL_DATA: 774 /* FALLTHROUGH */ 775 case DEPEVT_STATUS_CONTROL_STATUS: 776 /* FALLTHROUGH */ 777 default: 778 dev_vdbg(dwc->dev, "waiting for XferComplete\n"); 779 } 780 781 return; 782 } 783 784 switch (event->status) { 785 case DEPEVT_STATUS_CONTROL_SETUP: 786 dev_vdbg(dwc->dev, "Control Setup\n"); 787 788 dwc->ep0state = EP0_SETUP_PHASE; 789 790 dwc3_ep0_do_control_setup(dwc, event); 791 break; 792 793 case DEPEVT_STATUS_CONTROL_DATA: 794 dev_vdbg(dwc->dev, "Control Data\n"); 795 796 dwc->ep0state = EP0_DATA_PHASE; 797 798 if (dwc->ep0_next_event != DWC3_EP0_NRDY_DATA) { 799 dev_vdbg(dwc->dev, "Expected %d got %d\n", 800 dwc->ep0_next_event, 801 DWC3_EP0_NRDY_DATA); 802 803 dwc3_ep0_stall_and_restart(dwc); 804 return; 805 } 806 807 /* 808 * One of the possible error cases is when Host _does_ 809 * request for Data Phase, but it does so on the wrong 810 * direction. 811 * 812 * Here, we already know ep0_next_event is DATA (see above), 813 * so we only need to check for direction. 814 */ 815 if (dwc->ep0_expect_in != event->endpoint_number) { 816 dev_vdbg(dwc->dev, "Wrong direction for Data phase\n"); 817 dwc3_ep0_stall_and_restart(dwc); 818 return; 819 } 820 821 dwc3_ep0_do_control_data(dwc, event); 822 break; 823 824 case DEPEVT_STATUS_CONTROL_STATUS: 825 dev_vdbg(dwc->dev, "Control Status\n"); 826 827 dwc->ep0state = EP0_STATUS_PHASE; 828 829 if (dwc->ep0_next_event != DWC3_EP0_NRDY_STATUS) { 830 dev_vdbg(dwc->dev, "Expected %d got %d\n", 831 dwc->ep0_next_event, 832 DWC3_EP0_NRDY_STATUS); 833 834 dwc3_ep0_stall_and_restart(dwc); 835 return; 836 } 837 838 if (dwc->delayed_status) { 839 WARN_ON_ONCE(event->endpoint_number != 1); 840 dev_vdbg(dwc->dev, "Mass Storage delayed status\n"); 841 return; 842 } 843 844 dwc3_ep0_do_control_status(dwc, event->endpoint_number); 845 } 846 } 847 848 void dwc3_ep0_interrupt(struct dwc3 *dwc, 849 const struct dwc3_event_depevt *event) 850 { 851 u8 epnum = event->endpoint_number; 852 853 dev_dbg(dwc->dev, "%s while ep%d%s in state '%s'\n", 854 dwc3_ep_event_string(event->endpoint_event), 855 epnum >> 1, (epnum & 1) ? "in" : "out", 856 dwc3_ep0_state_string(dwc->ep0state)); 857 858 switch (event->endpoint_event) { 859 case DWC3_DEPEVT_XFERCOMPLETE: 860 dwc3_ep0_xfer_complete(dwc, event); 861 break; 862 863 case DWC3_DEPEVT_XFERNOTREADY: 864 dwc3_ep0_xfernotready(dwc, event); 865 break; 866 867 case DWC3_DEPEVT_XFERINPROGRESS: 868 case DWC3_DEPEVT_RXTXFIFOEVT: 869 case DWC3_DEPEVT_STREAMEVT: 870 case DWC3_DEPEVT_EPCMDCMPLT: 871 break; 872 } 873 } 874