1 /** 2 * ep0.c - DesignWare USB3 DRD Controller Endpoint 0 Handling 3 * 4 * Copyright (C) 2010-2011 Texas Instruments Incorporated - http://www.ti.com 5 * 6 * Authors: Felipe Balbi <balbi@ti.com>, 7 * Sebastian Andrzej Siewior <bigeasy@linutronix.de> 8 * 9 * This program is free software: you can redistribute it and/or modify 10 * it under the terms of the GNU General Public License version 2 of 11 * the License as published by the Free Software Foundation. 12 * 13 * This program is distributed in the hope that it will be useful, 14 * but WITHOUT ANY WARRANTY; without even the implied warranty of 15 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the 16 * GNU General Public License for more details. 17 */ 18 19 #include <linux/kernel.h> 20 #include <linux/slab.h> 21 #include <linux/spinlock.h> 22 #include <linux/platform_device.h> 23 #include <linux/pm_runtime.h> 24 #include <linux/interrupt.h> 25 #include <linux/io.h> 26 #include <linux/list.h> 27 #include <linux/dma-mapping.h> 28 29 #include <linux/usb/ch9.h> 30 #include <linux/usb/gadget.h> 31 #include <linux/usb/composite.h> 32 33 #include "core.h" 34 #include "debug.h" 35 #include "gadget.h" 36 #include "io.h" 37 38 static void __dwc3_ep0_do_control_status(struct dwc3 *dwc, struct dwc3_ep *dep); 39 static void __dwc3_ep0_do_control_data(struct dwc3 *dwc, 40 struct dwc3_ep *dep, struct dwc3_request *req); 41 42 static int dwc3_ep0_start_trans(struct dwc3 *dwc, u8 epnum, dma_addr_t buf_dma, 43 u32 len, u32 type, bool chain) 44 { 45 struct dwc3_gadget_ep_cmd_params params; 46 struct dwc3_trb *trb; 47 struct dwc3_ep *dep; 48 49 int ret; 50 51 dep = dwc->eps[epnum]; 52 if (dep->flags & DWC3_EP_BUSY) 53 return 0; 54 55 trb = &dwc->ep0_trb[dep->trb_enqueue]; 56 57 if (chain) 58 dep->trb_enqueue++; 59 60 trb->bpl = lower_32_bits(buf_dma); 61 trb->bph = upper_32_bits(buf_dma); 62 trb->size = len; 63 trb->ctrl = type; 64 65 trb->ctrl |= (DWC3_TRB_CTRL_HWO 66 | DWC3_TRB_CTRL_ISP_IMI); 67 68 if (chain) 69 trb->ctrl |= DWC3_TRB_CTRL_CHN; 70 else 71 trb->ctrl |= (DWC3_TRB_CTRL_IOC 72 | DWC3_TRB_CTRL_LST); 73 74 if (chain) 75 return 0; 76 77 memset(¶ms, 0, sizeof(params)); 78 params.param0 = upper_32_bits(dwc->ep0_trb_addr); 79 params.param1 = lower_32_bits(dwc->ep0_trb_addr); 80 81 trace_dwc3_prepare_trb(dep, trb); 82 83 ret = dwc3_send_gadget_ep_cmd(dep, DWC3_DEPCMD_STARTTRANSFER, ¶ms); 84 if (ret < 0) 85 return ret; 86 87 dep->flags |= DWC3_EP_BUSY; 88 dep->resource_index = dwc3_gadget_ep_get_transfer_index(dep); 89 dwc->ep0_next_event = DWC3_EP0_COMPLETE; 90 91 return 0; 92 } 93 94 static int __dwc3_gadget_ep0_queue(struct dwc3_ep *dep, 95 struct dwc3_request *req) 96 { 97 struct dwc3 *dwc = dep->dwc; 98 99 req->request.actual = 0; 100 req->request.status = -EINPROGRESS; 101 req->epnum = dep->number; 102 103 list_add_tail(&req->list, &dep->pending_list); 104 105 /* 106 * Gadget driver might not be quick enough to queue a request 107 * before we get a Transfer Not Ready event on this endpoint. 108 * 109 * In that case, we will set DWC3_EP_PENDING_REQUEST. When that 110 * flag is set, it's telling us that as soon as Gadget queues the 111 * required request, we should kick the transfer here because the 112 * IRQ we were waiting for is long gone. 113 */ 114 if (dep->flags & DWC3_EP_PENDING_REQUEST) { 115 unsigned direction; 116 117 direction = !!(dep->flags & DWC3_EP0_DIR_IN); 118 119 if (dwc->ep0state != EP0_DATA_PHASE) { 120 dev_WARN(dwc->dev, "Unexpected pending request\n"); 121 return 0; 122 } 123 124 __dwc3_ep0_do_control_data(dwc, dwc->eps[direction], req); 125 126 dep->flags &= ~(DWC3_EP_PENDING_REQUEST | 127 DWC3_EP0_DIR_IN); 128 129 return 0; 130 } 131 132 /* 133 * In case gadget driver asked us to delay the STATUS phase, 134 * handle it here. 135 */ 136 if (dwc->delayed_status) { 137 unsigned direction; 138 139 direction = !dwc->ep0_expect_in; 140 dwc->delayed_status = false; 141 usb_gadget_set_state(&dwc->gadget, USB_STATE_CONFIGURED); 142 143 if (dwc->ep0state == EP0_STATUS_PHASE) 144 __dwc3_ep0_do_control_status(dwc, dwc->eps[direction]); 145 146 return 0; 147 } 148 149 /* 150 * Unfortunately we have uncovered a limitation wrt the Data Phase. 151 * 152 * Section 9.4 says we can wait for the XferNotReady(DATA) event to 153 * come before issueing Start Transfer command, but if we do, we will 154 * miss situations where the host starts another SETUP phase instead of 155 * the DATA phase. Such cases happen at least on TD.7.6 of the Link 156 * Layer Compliance Suite. 157 * 158 * The problem surfaces due to the fact that in case of back-to-back 159 * SETUP packets there will be no XferNotReady(DATA) generated and we 160 * will be stuck waiting for XferNotReady(DATA) forever. 161 * 162 * By looking at tables 9-13 and 9-14 of the Databook, we can see that 163 * it tells us to start Data Phase right away. It also mentions that if 164 * we receive a SETUP phase instead of the DATA phase, core will issue 165 * XferComplete for the DATA phase, before actually initiating it in 166 * the wire, with the TRB's status set to "SETUP_PENDING". Such status 167 * can only be used to print some debugging logs, as the core expects 168 * us to go through to the STATUS phase and start a CONTROL_STATUS TRB, 169 * just so it completes right away, without transferring anything and, 170 * only then, we can go back to the SETUP phase. 171 * 172 * Because of this scenario, SNPS decided to change the programming 173 * model of control transfers and support on-demand transfers only for 174 * the STATUS phase. To fix the issue we have now, we will always wait 175 * for gadget driver to queue the DATA phase's struct usb_request, then 176 * start it right away. 177 * 178 * If we're actually in a 2-stage transfer, we will wait for 179 * XferNotReady(STATUS). 180 */ 181 if (dwc->three_stage_setup) { 182 unsigned direction; 183 184 direction = dwc->ep0_expect_in; 185 dwc->ep0state = EP0_DATA_PHASE; 186 187 __dwc3_ep0_do_control_data(dwc, dwc->eps[direction], req); 188 189 dep->flags &= ~DWC3_EP0_DIR_IN; 190 } 191 192 return 0; 193 } 194 195 int dwc3_gadget_ep0_queue(struct usb_ep *ep, struct usb_request *request, 196 gfp_t gfp_flags) 197 { 198 struct dwc3_request *req = to_dwc3_request(request); 199 struct dwc3_ep *dep = to_dwc3_ep(ep); 200 struct dwc3 *dwc = dep->dwc; 201 202 unsigned long flags; 203 204 int ret; 205 206 spin_lock_irqsave(&dwc->lock, flags); 207 if (!dep->endpoint.desc) { 208 dev_err(dwc->dev, "%s: can't queue to disabled endpoint\n", 209 dep->name); 210 ret = -ESHUTDOWN; 211 goto out; 212 } 213 214 /* we share one TRB for ep0/1 */ 215 if (!list_empty(&dep->pending_list)) { 216 ret = -EBUSY; 217 goto out; 218 } 219 220 ret = __dwc3_gadget_ep0_queue(dep, req); 221 222 out: 223 spin_unlock_irqrestore(&dwc->lock, flags); 224 225 return ret; 226 } 227 228 static void dwc3_ep0_stall_and_restart(struct dwc3 *dwc) 229 { 230 struct dwc3_ep *dep; 231 232 /* reinitialize physical ep1 */ 233 dep = dwc->eps[1]; 234 dep->flags = DWC3_EP_ENABLED; 235 236 /* stall is always issued on EP0 */ 237 dep = dwc->eps[0]; 238 __dwc3_gadget_ep_set_halt(dep, 1, false); 239 dep->flags = DWC3_EP_ENABLED; 240 dwc->delayed_status = false; 241 242 if (!list_empty(&dep->pending_list)) { 243 struct dwc3_request *req; 244 245 req = next_request(&dep->pending_list); 246 dwc3_gadget_giveback(dep, req, -ECONNRESET); 247 } 248 249 dwc->ep0state = EP0_SETUP_PHASE; 250 dwc3_ep0_out_start(dwc); 251 } 252 253 int __dwc3_gadget_ep0_set_halt(struct usb_ep *ep, int value) 254 { 255 struct dwc3_ep *dep = to_dwc3_ep(ep); 256 struct dwc3 *dwc = dep->dwc; 257 258 dwc3_ep0_stall_and_restart(dwc); 259 260 return 0; 261 } 262 263 int dwc3_gadget_ep0_set_halt(struct usb_ep *ep, int value) 264 { 265 struct dwc3_ep *dep = to_dwc3_ep(ep); 266 struct dwc3 *dwc = dep->dwc; 267 unsigned long flags; 268 int ret; 269 270 spin_lock_irqsave(&dwc->lock, flags); 271 ret = __dwc3_gadget_ep0_set_halt(ep, value); 272 spin_unlock_irqrestore(&dwc->lock, flags); 273 274 return ret; 275 } 276 277 void dwc3_ep0_out_start(struct dwc3 *dwc) 278 { 279 int ret; 280 281 complete(&dwc->ep0_in_setup); 282 283 ret = dwc3_ep0_start_trans(dwc, 0, dwc->ctrl_req_addr, 8, 284 DWC3_TRBCTL_CONTROL_SETUP, false); 285 WARN_ON(ret < 0); 286 } 287 288 static struct dwc3_ep *dwc3_wIndex_to_dep(struct dwc3 *dwc, __le16 wIndex_le) 289 { 290 struct dwc3_ep *dep; 291 u32 windex = le16_to_cpu(wIndex_le); 292 u32 epnum; 293 294 epnum = (windex & USB_ENDPOINT_NUMBER_MASK) << 1; 295 if ((windex & USB_ENDPOINT_DIR_MASK) == USB_DIR_IN) 296 epnum |= 1; 297 298 dep = dwc->eps[epnum]; 299 if (dep->flags & DWC3_EP_ENABLED) 300 return dep; 301 302 return NULL; 303 } 304 305 static void dwc3_ep0_status_cmpl(struct usb_ep *ep, struct usb_request *req) 306 { 307 } 308 /* 309 * ch 9.4.5 310 */ 311 static int dwc3_ep0_handle_status(struct dwc3 *dwc, 312 struct usb_ctrlrequest *ctrl) 313 { 314 struct dwc3_ep *dep; 315 u32 recip; 316 u32 reg; 317 u16 usb_status = 0; 318 __le16 *response_pkt; 319 320 recip = ctrl->bRequestType & USB_RECIP_MASK; 321 switch (recip) { 322 case USB_RECIP_DEVICE: 323 /* 324 * LTM will be set once we know how to set this in HW. 325 */ 326 usb_status |= dwc->gadget.is_selfpowered; 327 328 if ((dwc->speed == DWC3_DSTS_SUPERSPEED) || 329 (dwc->speed == DWC3_DSTS_SUPERSPEED_PLUS)) { 330 reg = dwc3_readl(dwc->regs, DWC3_DCTL); 331 if (reg & DWC3_DCTL_INITU1ENA) 332 usb_status |= 1 << USB_DEV_STAT_U1_ENABLED; 333 if (reg & DWC3_DCTL_INITU2ENA) 334 usb_status |= 1 << USB_DEV_STAT_U2_ENABLED; 335 } 336 337 break; 338 339 case USB_RECIP_INTERFACE: 340 /* 341 * Function Remote Wake Capable D0 342 * Function Remote Wakeup D1 343 */ 344 break; 345 346 case USB_RECIP_ENDPOINT: 347 dep = dwc3_wIndex_to_dep(dwc, ctrl->wIndex); 348 if (!dep) 349 return -EINVAL; 350 351 if (dep->flags & DWC3_EP_STALL) 352 usb_status = 1 << USB_ENDPOINT_HALT; 353 break; 354 default: 355 return -EINVAL; 356 } 357 358 response_pkt = (__le16 *) dwc->setup_buf; 359 *response_pkt = cpu_to_le16(usb_status); 360 361 dep = dwc->eps[0]; 362 dwc->ep0_usb_req.dep = dep; 363 dwc->ep0_usb_req.request.length = sizeof(*response_pkt); 364 dwc->ep0_usb_req.request.buf = dwc->setup_buf; 365 dwc->ep0_usb_req.request.complete = dwc3_ep0_status_cmpl; 366 367 return __dwc3_gadget_ep0_queue(dep, &dwc->ep0_usb_req); 368 } 369 370 static int dwc3_ep0_handle_u1(struct dwc3 *dwc, enum usb_device_state state, 371 int set) 372 { 373 u32 reg; 374 375 if (state != USB_STATE_CONFIGURED) 376 return -EINVAL; 377 if ((dwc->speed != DWC3_DSTS_SUPERSPEED) && 378 (dwc->speed != DWC3_DSTS_SUPERSPEED_PLUS)) 379 return -EINVAL; 380 381 reg = dwc3_readl(dwc->regs, DWC3_DCTL); 382 if (set) 383 reg |= DWC3_DCTL_INITU1ENA; 384 else 385 reg &= ~DWC3_DCTL_INITU1ENA; 386 dwc3_writel(dwc->regs, DWC3_DCTL, reg); 387 388 return 0; 389 } 390 391 static int dwc3_ep0_handle_u2(struct dwc3 *dwc, enum usb_device_state state, 392 int set) 393 { 394 u32 reg; 395 396 397 if (state != USB_STATE_CONFIGURED) 398 return -EINVAL; 399 if ((dwc->speed != DWC3_DSTS_SUPERSPEED) && 400 (dwc->speed != DWC3_DSTS_SUPERSPEED_PLUS)) 401 return -EINVAL; 402 403 reg = dwc3_readl(dwc->regs, DWC3_DCTL); 404 if (set) 405 reg |= DWC3_DCTL_INITU2ENA; 406 else 407 reg &= ~DWC3_DCTL_INITU2ENA; 408 dwc3_writel(dwc->regs, DWC3_DCTL, reg); 409 410 return 0; 411 } 412 413 static int dwc3_ep0_handle_test(struct dwc3 *dwc, enum usb_device_state state, 414 u32 wIndex, int set) 415 { 416 if ((wIndex & 0xff) != 0) 417 return -EINVAL; 418 if (!set) 419 return -EINVAL; 420 421 switch (wIndex >> 8) { 422 case TEST_J: 423 case TEST_K: 424 case TEST_SE0_NAK: 425 case TEST_PACKET: 426 case TEST_FORCE_EN: 427 dwc->test_mode_nr = wIndex >> 8; 428 dwc->test_mode = true; 429 break; 430 default: 431 return -EINVAL; 432 } 433 434 return 0; 435 } 436 437 static int dwc3_ep0_handle_device(struct dwc3 *dwc, 438 struct usb_ctrlrequest *ctrl, int set) 439 { 440 enum usb_device_state state; 441 u32 wValue; 442 u32 wIndex; 443 int ret = 0; 444 445 wValue = le16_to_cpu(ctrl->wValue); 446 wIndex = le16_to_cpu(ctrl->wIndex); 447 state = dwc->gadget.state; 448 449 switch (wValue) { 450 case USB_DEVICE_REMOTE_WAKEUP: 451 break; 452 /* 453 * 9.4.1 says only only for SS, in AddressState only for 454 * default control pipe 455 */ 456 case USB_DEVICE_U1_ENABLE: 457 ret = dwc3_ep0_handle_u1(dwc, state, set); 458 break; 459 case USB_DEVICE_U2_ENABLE: 460 ret = dwc3_ep0_handle_u2(dwc, state, set); 461 break; 462 case USB_DEVICE_LTM_ENABLE: 463 ret = -EINVAL; 464 break; 465 case USB_DEVICE_TEST_MODE: 466 ret = dwc3_ep0_handle_test(dwc, state, wIndex, set); 467 break; 468 default: 469 ret = -EINVAL; 470 } 471 472 return ret; 473 } 474 475 static int dwc3_ep0_handle_intf(struct dwc3 *dwc, 476 struct usb_ctrlrequest *ctrl, int set) 477 { 478 enum usb_device_state state; 479 u32 wValue; 480 u32 wIndex; 481 int ret = 0; 482 483 wValue = le16_to_cpu(ctrl->wValue); 484 wIndex = le16_to_cpu(ctrl->wIndex); 485 state = dwc->gadget.state; 486 487 switch (wValue) { 488 case USB_INTRF_FUNC_SUSPEND: 489 /* 490 * REVISIT: Ideally we would enable some low power mode here, 491 * however it's unclear what we should be doing here. 492 * 493 * For now, we're not doing anything, just making sure we return 494 * 0 so USB Command Verifier tests pass without any errors. 495 */ 496 break; 497 default: 498 ret = -EINVAL; 499 } 500 501 return ret; 502 } 503 504 static int dwc3_ep0_handle_endpoint(struct dwc3 *dwc, 505 struct usb_ctrlrequest *ctrl, int set) 506 { 507 struct dwc3_ep *dep; 508 enum usb_device_state state; 509 u32 wValue; 510 u32 wIndex; 511 int ret; 512 513 wValue = le16_to_cpu(ctrl->wValue); 514 wIndex = le16_to_cpu(ctrl->wIndex); 515 state = dwc->gadget.state; 516 517 switch (wValue) { 518 case USB_ENDPOINT_HALT: 519 dep = dwc3_wIndex_to_dep(dwc, ctrl->wIndex); 520 if (!dep) 521 return -EINVAL; 522 523 if (set == 0 && (dep->flags & DWC3_EP_WEDGE)) 524 break; 525 526 ret = __dwc3_gadget_ep_set_halt(dep, set, true); 527 if (ret) 528 return -EINVAL; 529 break; 530 default: 531 return -EINVAL; 532 } 533 534 return 0; 535 } 536 537 static int dwc3_ep0_handle_feature(struct dwc3 *dwc, 538 struct usb_ctrlrequest *ctrl, int set) 539 { 540 u32 recip; 541 int ret; 542 enum usb_device_state state; 543 544 recip = ctrl->bRequestType & USB_RECIP_MASK; 545 state = dwc->gadget.state; 546 547 switch (recip) { 548 case USB_RECIP_DEVICE: 549 ret = dwc3_ep0_handle_device(dwc, ctrl, set); 550 break; 551 case USB_RECIP_INTERFACE: 552 ret = dwc3_ep0_handle_intf(dwc, ctrl, set); 553 break; 554 case USB_RECIP_ENDPOINT: 555 ret = dwc3_ep0_handle_endpoint(dwc, ctrl, set); 556 break; 557 default: 558 ret = -EINVAL; 559 } 560 561 return ret; 562 } 563 564 static int dwc3_ep0_set_address(struct dwc3 *dwc, struct usb_ctrlrequest *ctrl) 565 { 566 enum usb_device_state state = dwc->gadget.state; 567 u32 addr; 568 u32 reg; 569 570 addr = le16_to_cpu(ctrl->wValue); 571 if (addr > 127) { 572 dev_err(dwc->dev, "invalid device address %d\n", addr); 573 return -EINVAL; 574 } 575 576 if (state == USB_STATE_CONFIGURED) { 577 dev_err(dwc->dev, "can't SetAddress() from Configured State\n"); 578 return -EINVAL; 579 } 580 581 reg = dwc3_readl(dwc->regs, DWC3_DCFG); 582 reg &= ~(DWC3_DCFG_DEVADDR_MASK); 583 reg |= DWC3_DCFG_DEVADDR(addr); 584 dwc3_writel(dwc->regs, DWC3_DCFG, reg); 585 586 if (addr) 587 usb_gadget_set_state(&dwc->gadget, USB_STATE_ADDRESS); 588 else 589 usb_gadget_set_state(&dwc->gadget, USB_STATE_DEFAULT); 590 591 return 0; 592 } 593 594 static int dwc3_ep0_delegate_req(struct dwc3 *dwc, struct usb_ctrlrequest *ctrl) 595 { 596 int ret; 597 598 spin_unlock(&dwc->lock); 599 ret = dwc->gadget_driver->setup(&dwc->gadget, ctrl); 600 spin_lock(&dwc->lock); 601 return ret; 602 } 603 604 static int dwc3_ep0_set_config(struct dwc3 *dwc, struct usb_ctrlrequest *ctrl) 605 { 606 enum usb_device_state state = dwc->gadget.state; 607 u32 cfg; 608 int ret; 609 u32 reg; 610 611 cfg = le16_to_cpu(ctrl->wValue); 612 613 switch (state) { 614 case USB_STATE_DEFAULT: 615 return -EINVAL; 616 617 case USB_STATE_ADDRESS: 618 ret = dwc3_ep0_delegate_req(dwc, ctrl); 619 /* if the cfg matches and the cfg is non zero */ 620 if (cfg && (!ret || (ret == USB_GADGET_DELAYED_STATUS))) { 621 622 /* 623 * only change state if set_config has already 624 * been processed. If gadget driver returns 625 * USB_GADGET_DELAYED_STATUS, we will wait 626 * to change the state on the next usb_ep_queue() 627 */ 628 if (ret == 0) 629 usb_gadget_set_state(&dwc->gadget, 630 USB_STATE_CONFIGURED); 631 632 /* 633 * Enable transition to U1/U2 state when 634 * nothing is pending from application. 635 */ 636 reg = dwc3_readl(dwc->regs, DWC3_DCTL); 637 reg |= (DWC3_DCTL_ACCEPTU1ENA | DWC3_DCTL_ACCEPTU2ENA); 638 dwc3_writel(dwc->regs, DWC3_DCTL, reg); 639 } 640 break; 641 642 case USB_STATE_CONFIGURED: 643 ret = dwc3_ep0_delegate_req(dwc, ctrl); 644 if (!cfg && !ret) 645 usb_gadget_set_state(&dwc->gadget, 646 USB_STATE_ADDRESS); 647 break; 648 default: 649 ret = -EINVAL; 650 } 651 return ret; 652 } 653 654 static void dwc3_ep0_set_sel_cmpl(struct usb_ep *ep, struct usb_request *req) 655 { 656 struct dwc3_ep *dep = to_dwc3_ep(ep); 657 struct dwc3 *dwc = dep->dwc; 658 659 u32 param = 0; 660 u32 reg; 661 662 struct timing { 663 u8 u1sel; 664 u8 u1pel; 665 __le16 u2sel; 666 __le16 u2pel; 667 } __packed timing; 668 669 int ret; 670 671 memcpy(&timing, req->buf, sizeof(timing)); 672 673 dwc->u1sel = timing.u1sel; 674 dwc->u1pel = timing.u1pel; 675 dwc->u2sel = le16_to_cpu(timing.u2sel); 676 dwc->u2pel = le16_to_cpu(timing.u2pel); 677 678 reg = dwc3_readl(dwc->regs, DWC3_DCTL); 679 if (reg & DWC3_DCTL_INITU2ENA) 680 param = dwc->u2pel; 681 if (reg & DWC3_DCTL_INITU1ENA) 682 param = dwc->u1pel; 683 684 /* 685 * According to Synopsys Databook, if parameter is 686 * greater than 125, a value of zero should be 687 * programmed in the register. 688 */ 689 if (param > 125) 690 param = 0; 691 692 /* now that we have the time, issue DGCMD Set Sel */ 693 ret = dwc3_send_gadget_generic_command(dwc, 694 DWC3_DGCMD_SET_PERIODIC_PAR, param); 695 WARN_ON(ret < 0); 696 } 697 698 static int dwc3_ep0_set_sel(struct dwc3 *dwc, struct usb_ctrlrequest *ctrl) 699 { 700 struct dwc3_ep *dep; 701 enum usb_device_state state = dwc->gadget.state; 702 u16 wLength; 703 u16 wValue; 704 705 if (state == USB_STATE_DEFAULT) 706 return -EINVAL; 707 708 wValue = le16_to_cpu(ctrl->wValue); 709 wLength = le16_to_cpu(ctrl->wLength); 710 711 if (wLength != 6) { 712 dev_err(dwc->dev, "Set SEL should be 6 bytes, got %d\n", 713 wLength); 714 return -EINVAL; 715 } 716 717 /* 718 * To handle Set SEL we need to receive 6 bytes from Host. So let's 719 * queue a usb_request for 6 bytes. 720 * 721 * Remember, though, this controller can't handle non-wMaxPacketSize 722 * aligned transfers on the OUT direction, so we queue a request for 723 * wMaxPacketSize instead. 724 */ 725 dep = dwc->eps[0]; 726 dwc->ep0_usb_req.dep = dep; 727 dwc->ep0_usb_req.request.length = dep->endpoint.maxpacket; 728 dwc->ep0_usb_req.request.buf = dwc->setup_buf; 729 dwc->ep0_usb_req.request.complete = dwc3_ep0_set_sel_cmpl; 730 731 return __dwc3_gadget_ep0_queue(dep, &dwc->ep0_usb_req); 732 } 733 734 static int dwc3_ep0_set_isoch_delay(struct dwc3 *dwc, struct usb_ctrlrequest *ctrl) 735 { 736 u16 wLength; 737 u16 wValue; 738 u16 wIndex; 739 740 wValue = le16_to_cpu(ctrl->wValue); 741 wLength = le16_to_cpu(ctrl->wLength); 742 wIndex = le16_to_cpu(ctrl->wIndex); 743 744 if (wIndex || wLength) 745 return -EINVAL; 746 747 /* 748 * REVISIT It's unclear from Databook what to do with this 749 * value. For now, just cache it. 750 */ 751 dwc->isoch_delay = wValue; 752 753 return 0; 754 } 755 756 static int dwc3_ep0_std_request(struct dwc3 *dwc, struct usb_ctrlrequest *ctrl) 757 { 758 int ret; 759 760 switch (ctrl->bRequest) { 761 case USB_REQ_GET_STATUS: 762 ret = dwc3_ep0_handle_status(dwc, ctrl); 763 break; 764 case USB_REQ_CLEAR_FEATURE: 765 ret = dwc3_ep0_handle_feature(dwc, ctrl, 0); 766 break; 767 case USB_REQ_SET_FEATURE: 768 ret = dwc3_ep0_handle_feature(dwc, ctrl, 1); 769 break; 770 case USB_REQ_SET_ADDRESS: 771 ret = dwc3_ep0_set_address(dwc, ctrl); 772 break; 773 case USB_REQ_SET_CONFIGURATION: 774 ret = dwc3_ep0_set_config(dwc, ctrl); 775 break; 776 case USB_REQ_SET_SEL: 777 ret = dwc3_ep0_set_sel(dwc, ctrl); 778 break; 779 case USB_REQ_SET_ISOCH_DELAY: 780 ret = dwc3_ep0_set_isoch_delay(dwc, ctrl); 781 break; 782 default: 783 ret = dwc3_ep0_delegate_req(dwc, ctrl); 784 break; 785 } 786 787 return ret; 788 } 789 790 static void dwc3_ep0_inspect_setup(struct dwc3 *dwc, 791 const struct dwc3_event_depevt *event) 792 { 793 struct usb_ctrlrequest *ctrl = dwc->ctrl_req; 794 int ret = -EINVAL; 795 u32 len; 796 797 if (!dwc->gadget_driver) 798 goto out; 799 800 trace_dwc3_ctrl_req(ctrl); 801 802 len = le16_to_cpu(ctrl->wLength); 803 if (!len) { 804 dwc->three_stage_setup = false; 805 dwc->ep0_expect_in = false; 806 dwc->ep0_next_event = DWC3_EP0_NRDY_STATUS; 807 } else { 808 dwc->three_stage_setup = true; 809 dwc->ep0_expect_in = !!(ctrl->bRequestType & USB_DIR_IN); 810 dwc->ep0_next_event = DWC3_EP0_NRDY_DATA; 811 } 812 813 if ((ctrl->bRequestType & USB_TYPE_MASK) == USB_TYPE_STANDARD) 814 ret = dwc3_ep0_std_request(dwc, ctrl); 815 else 816 ret = dwc3_ep0_delegate_req(dwc, ctrl); 817 818 if (ret == USB_GADGET_DELAYED_STATUS) 819 dwc->delayed_status = true; 820 821 out: 822 if (ret < 0) 823 dwc3_ep0_stall_and_restart(dwc); 824 } 825 826 static void dwc3_ep0_complete_data(struct dwc3 *dwc, 827 const struct dwc3_event_depevt *event) 828 { 829 struct dwc3_request *r = NULL; 830 struct usb_request *ur; 831 struct dwc3_trb *trb; 832 struct dwc3_ep *ep0; 833 unsigned transfer_size = 0; 834 unsigned maxp; 835 unsigned remaining_ur_length; 836 void *buf; 837 u32 transferred = 0; 838 u32 status; 839 u32 length; 840 u8 epnum; 841 842 epnum = event->endpoint_number; 843 ep0 = dwc->eps[0]; 844 845 dwc->ep0_next_event = DWC3_EP0_NRDY_STATUS; 846 847 trb = dwc->ep0_trb; 848 849 trace_dwc3_complete_trb(ep0, trb); 850 851 r = next_request(&ep0->pending_list); 852 if (!r) 853 return; 854 855 status = DWC3_TRB_SIZE_TRBSTS(trb->size); 856 if (status == DWC3_TRBSTS_SETUP_PENDING) { 857 dwc->setup_packet_pending = true; 858 if (r) 859 dwc3_gadget_giveback(ep0, r, -ECONNRESET); 860 861 return; 862 } 863 864 ur = &r->request; 865 buf = ur->buf; 866 remaining_ur_length = ur->length; 867 868 length = trb->size & DWC3_TRB_SIZE_MASK; 869 870 maxp = ep0->endpoint.maxpacket; 871 872 if (dwc->ep0_bounced) { 873 /* 874 * Handle the first TRB before handling the bounce buffer if 875 * the request length is greater than the bounce buffer size 876 */ 877 if (ur->length > DWC3_EP0_BOUNCE_SIZE) { 878 transfer_size = ALIGN(ur->length - maxp, maxp); 879 transferred = transfer_size - length; 880 buf = (u8 *)buf + transferred; 881 ur->actual += transferred; 882 remaining_ur_length -= transferred; 883 884 trb++; 885 length = trb->size & DWC3_TRB_SIZE_MASK; 886 887 ep0->trb_enqueue = 0; 888 } 889 890 transfer_size = roundup((ur->length - transfer_size), 891 maxp); 892 893 transferred = min_t(u32, remaining_ur_length, 894 transfer_size - length); 895 memcpy(buf, dwc->ep0_bounce, transferred); 896 } else { 897 transferred = ur->length - length; 898 } 899 900 ur->actual += transferred; 901 902 if ((epnum & 1) && ur->actual < ur->length) { 903 /* for some reason we did not get everything out */ 904 905 dwc3_ep0_stall_and_restart(dwc); 906 } else { 907 dwc3_gadget_giveback(ep0, r, 0); 908 909 if (IS_ALIGNED(ur->length, ep0->endpoint.maxpacket) && 910 ur->length && ur->zero) { 911 int ret; 912 913 dwc->ep0_next_event = DWC3_EP0_COMPLETE; 914 915 ret = dwc3_ep0_start_trans(dwc, epnum, 916 dwc->ctrl_req_addr, 0, 917 DWC3_TRBCTL_CONTROL_DATA, false); 918 WARN_ON(ret < 0); 919 } 920 } 921 } 922 923 static void dwc3_ep0_complete_status(struct dwc3 *dwc, 924 const struct dwc3_event_depevt *event) 925 { 926 struct dwc3_request *r; 927 struct dwc3_ep *dep; 928 struct dwc3_trb *trb; 929 u32 status; 930 931 dep = dwc->eps[0]; 932 trb = dwc->ep0_trb; 933 934 trace_dwc3_complete_trb(dep, trb); 935 936 if (!list_empty(&dep->pending_list)) { 937 r = next_request(&dep->pending_list); 938 939 dwc3_gadget_giveback(dep, r, 0); 940 } 941 942 if (dwc->test_mode) { 943 int ret; 944 945 ret = dwc3_gadget_set_test_mode(dwc, dwc->test_mode_nr); 946 if (ret < 0) { 947 dev_err(dwc->dev, "invalid test #%d\n", 948 dwc->test_mode_nr); 949 dwc3_ep0_stall_and_restart(dwc); 950 return; 951 } 952 } 953 954 status = DWC3_TRB_SIZE_TRBSTS(trb->size); 955 if (status == DWC3_TRBSTS_SETUP_PENDING) 956 dwc->setup_packet_pending = true; 957 958 dwc->ep0state = EP0_SETUP_PHASE; 959 dwc3_ep0_out_start(dwc); 960 } 961 962 static void dwc3_ep0_xfer_complete(struct dwc3 *dwc, 963 const struct dwc3_event_depevt *event) 964 { 965 struct dwc3_ep *dep = dwc->eps[event->endpoint_number]; 966 967 dep->flags &= ~DWC3_EP_BUSY; 968 dep->resource_index = 0; 969 dwc->setup_packet_pending = false; 970 971 switch (dwc->ep0state) { 972 case EP0_SETUP_PHASE: 973 dwc3_ep0_inspect_setup(dwc, event); 974 break; 975 976 case EP0_DATA_PHASE: 977 dwc3_ep0_complete_data(dwc, event); 978 break; 979 980 case EP0_STATUS_PHASE: 981 dwc3_ep0_complete_status(dwc, event); 982 break; 983 default: 984 WARN(true, "UNKNOWN ep0state %d\n", dwc->ep0state); 985 } 986 } 987 988 static void __dwc3_ep0_do_control_data(struct dwc3 *dwc, 989 struct dwc3_ep *dep, struct dwc3_request *req) 990 { 991 int ret; 992 993 req->direction = !!dep->number; 994 995 if (req->request.length == 0) { 996 ret = dwc3_ep0_start_trans(dwc, dep->number, 997 dwc->ctrl_req_addr, 0, 998 DWC3_TRBCTL_CONTROL_DATA, false); 999 } else if (!IS_ALIGNED(req->request.length, dep->endpoint.maxpacket) 1000 && (dep->number == 0)) { 1001 u32 transfer_size = 0; 1002 u32 maxpacket; 1003 1004 ret = usb_gadget_map_request_by_dev(dwc->sysdev, 1005 &req->request, dep->number); 1006 if (ret) 1007 return; 1008 1009 maxpacket = dep->endpoint.maxpacket; 1010 1011 if (req->request.length > DWC3_EP0_BOUNCE_SIZE) { 1012 transfer_size = ALIGN(req->request.length - maxpacket, 1013 maxpacket); 1014 ret = dwc3_ep0_start_trans(dwc, dep->number, 1015 req->request.dma, 1016 transfer_size, 1017 DWC3_TRBCTL_CONTROL_DATA, 1018 true); 1019 } 1020 1021 transfer_size = roundup((req->request.length - transfer_size), 1022 maxpacket); 1023 1024 dwc->ep0_bounced = true; 1025 1026 ret = dwc3_ep0_start_trans(dwc, dep->number, 1027 dwc->ep0_bounce_addr, transfer_size, 1028 DWC3_TRBCTL_CONTROL_DATA, false); 1029 } else { 1030 ret = usb_gadget_map_request_by_dev(dwc->sysdev, 1031 &req->request, dep->number); 1032 if (ret) 1033 return; 1034 1035 ret = dwc3_ep0_start_trans(dwc, dep->number, req->request.dma, 1036 req->request.length, DWC3_TRBCTL_CONTROL_DATA, 1037 false); 1038 } 1039 1040 WARN_ON(ret < 0); 1041 } 1042 1043 static int dwc3_ep0_start_control_status(struct dwc3_ep *dep) 1044 { 1045 struct dwc3 *dwc = dep->dwc; 1046 u32 type; 1047 1048 type = dwc->three_stage_setup ? DWC3_TRBCTL_CONTROL_STATUS3 1049 : DWC3_TRBCTL_CONTROL_STATUS2; 1050 1051 return dwc3_ep0_start_trans(dwc, dep->number, 1052 dwc->ctrl_req_addr, 0, type, false); 1053 } 1054 1055 static void __dwc3_ep0_do_control_status(struct dwc3 *dwc, struct dwc3_ep *dep) 1056 { 1057 WARN_ON(dwc3_ep0_start_control_status(dep)); 1058 } 1059 1060 static void dwc3_ep0_do_control_status(struct dwc3 *dwc, 1061 const struct dwc3_event_depevt *event) 1062 { 1063 struct dwc3_ep *dep = dwc->eps[event->endpoint_number]; 1064 1065 __dwc3_ep0_do_control_status(dwc, dep); 1066 } 1067 1068 static void dwc3_ep0_end_control_data(struct dwc3 *dwc, struct dwc3_ep *dep) 1069 { 1070 struct dwc3_gadget_ep_cmd_params params; 1071 u32 cmd; 1072 int ret; 1073 1074 if (!dep->resource_index) 1075 return; 1076 1077 cmd = DWC3_DEPCMD_ENDTRANSFER; 1078 cmd |= DWC3_DEPCMD_CMDIOC; 1079 cmd |= DWC3_DEPCMD_PARAM(dep->resource_index); 1080 memset(¶ms, 0, sizeof(params)); 1081 ret = dwc3_send_gadget_ep_cmd(dep, cmd, ¶ms); 1082 WARN_ON_ONCE(ret); 1083 dep->resource_index = 0; 1084 } 1085 1086 static void dwc3_ep0_xfernotready(struct dwc3 *dwc, 1087 const struct dwc3_event_depevt *event) 1088 { 1089 switch (event->status) { 1090 case DEPEVT_STATUS_CONTROL_DATA: 1091 /* 1092 * We already have a DATA transfer in the controller's cache, 1093 * if we receive a XferNotReady(DATA) we will ignore it, unless 1094 * it's for the wrong direction. 1095 * 1096 * In that case, we must issue END_TRANSFER command to the Data 1097 * Phase we already have started and issue SetStall on the 1098 * control endpoint. 1099 */ 1100 if (dwc->ep0_expect_in != event->endpoint_number) { 1101 struct dwc3_ep *dep = dwc->eps[dwc->ep0_expect_in]; 1102 1103 dev_err(dwc->dev, "unexpected direction for Data Phase\n"); 1104 dwc3_ep0_end_control_data(dwc, dep); 1105 dwc3_ep0_stall_and_restart(dwc); 1106 return; 1107 } 1108 1109 break; 1110 1111 case DEPEVT_STATUS_CONTROL_STATUS: 1112 if (dwc->ep0_next_event != DWC3_EP0_NRDY_STATUS) 1113 return; 1114 1115 dwc->ep0state = EP0_STATUS_PHASE; 1116 1117 if (dwc->delayed_status) { 1118 WARN_ON_ONCE(event->endpoint_number != 1); 1119 return; 1120 } 1121 1122 dwc3_ep0_do_control_status(dwc, event); 1123 } 1124 } 1125 1126 void dwc3_ep0_interrupt(struct dwc3 *dwc, 1127 const struct dwc3_event_depevt *event) 1128 { 1129 switch (event->endpoint_event) { 1130 case DWC3_DEPEVT_XFERCOMPLETE: 1131 dwc3_ep0_xfer_complete(dwc, event); 1132 break; 1133 1134 case DWC3_DEPEVT_XFERNOTREADY: 1135 dwc3_ep0_xfernotready(dwc, event); 1136 break; 1137 1138 case DWC3_DEPEVT_XFERINPROGRESS: 1139 case DWC3_DEPEVT_RXTXFIFOEVT: 1140 case DWC3_DEPEVT_STREAMEVT: 1141 case DWC3_DEPEVT_EPCMDCMPLT: 1142 break; 1143 } 1144 } 1145