1 // SPDX-License-Identifier: GPL-2.0 2 /* 3 * ep0.c - DesignWare USB3 DRD Controller Endpoint 0 Handling 4 * 5 * Copyright (C) 2010-2011 Texas Instruments Incorporated - https://www.ti.com 6 * 7 * Authors: Felipe Balbi <balbi@ti.com>, 8 * Sebastian Andrzej Siewior <bigeasy@linutronix.de> 9 */ 10 11 #include <linux/kernel.h> 12 #include <linux/slab.h> 13 #include <linux/spinlock.h> 14 #include <linux/platform_device.h> 15 #include <linux/pm_runtime.h> 16 #include <linux/interrupt.h> 17 #include <linux/io.h> 18 #include <linux/list.h> 19 #include <linux/dma-mapping.h> 20 21 #include <linux/usb/ch9.h> 22 #include <linux/usb/gadget.h> 23 #include <linux/usb/composite.h> 24 25 #include "core.h" 26 #include "debug.h" 27 #include "gadget.h" 28 #include "io.h" 29 30 static void __dwc3_ep0_do_control_status(struct dwc3 *dwc, struct dwc3_ep *dep); 31 static void __dwc3_ep0_do_control_data(struct dwc3 *dwc, 32 struct dwc3_ep *dep, struct dwc3_request *req); 33 34 static void dwc3_ep0_prepare_one_trb(struct dwc3_ep *dep, 35 dma_addr_t buf_dma, u32 len, u32 type, bool chain) 36 { 37 struct dwc3_trb *trb; 38 struct dwc3 *dwc; 39 40 dwc = dep->dwc; 41 trb = &dwc->ep0_trb[dep->trb_enqueue]; 42 43 if (chain) 44 dep->trb_enqueue++; 45 46 trb->bpl = lower_32_bits(buf_dma); 47 trb->bph = upper_32_bits(buf_dma); 48 trb->size = len; 49 trb->ctrl = type; 50 51 trb->ctrl |= (DWC3_TRB_CTRL_HWO 52 | DWC3_TRB_CTRL_ISP_IMI); 53 54 if (chain) 55 trb->ctrl |= DWC3_TRB_CTRL_CHN; 56 else 57 trb->ctrl |= (DWC3_TRB_CTRL_IOC 58 | DWC3_TRB_CTRL_LST); 59 60 trace_dwc3_prepare_trb(dep, trb); 61 } 62 63 static int dwc3_ep0_start_trans(struct dwc3_ep *dep) 64 { 65 struct dwc3_gadget_ep_cmd_params params; 66 struct dwc3 *dwc; 67 int ret; 68 69 if (dep->flags & DWC3_EP_TRANSFER_STARTED) 70 return 0; 71 72 dwc = dep->dwc; 73 74 memset(¶ms, 0, sizeof(params)); 75 params.param0 = upper_32_bits(dwc->ep0_trb_addr); 76 params.param1 = lower_32_bits(dwc->ep0_trb_addr); 77 78 ret = dwc3_send_gadget_ep_cmd(dep, DWC3_DEPCMD_STARTTRANSFER, ¶ms); 79 if (ret < 0) 80 return ret; 81 82 dwc->ep0_next_event = DWC3_EP0_COMPLETE; 83 84 return 0; 85 } 86 87 static int __dwc3_gadget_ep0_queue(struct dwc3_ep *dep, 88 struct dwc3_request *req) 89 { 90 struct dwc3 *dwc = dep->dwc; 91 92 req->request.actual = 0; 93 req->request.status = -EINPROGRESS; 94 req->epnum = dep->number; 95 96 list_add_tail(&req->list, &dep->pending_list); 97 98 /* 99 * Gadget driver might not be quick enough to queue a request 100 * before we get a Transfer Not Ready event on this endpoint. 101 * 102 * In that case, we will set DWC3_EP_PENDING_REQUEST. When that 103 * flag is set, it's telling us that as soon as Gadget queues the 104 * required request, we should kick the transfer here because the 105 * IRQ we were waiting for is long gone. 106 */ 107 if (dep->flags & DWC3_EP_PENDING_REQUEST) { 108 unsigned int direction; 109 110 direction = !!(dep->flags & DWC3_EP0_DIR_IN); 111 112 if (dwc->ep0state != EP0_DATA_PHASE) { 113 dev_WARN(dwc->dev, "Unexpected pending request\n"); 114 return 0; 115 } 116 117 __dwc3_ep0_do_control_data(dwc, dwc->eps[direction], req); 118 119 dep->flags &= ~(DWC3_EP_PENDING_REQUEST | 120 DWC3_EP0_DIR_IN); 121 122 return 0; 123 } 124 125 /* 126 * In case gadget driver asked us to delay the STATUS phase, 127 * handle it here. 128 */ 129 if (dwc->delayed_status) { 130 unsigned int direction; 131 132 direction = !dwc->ep0_expect_in; 133 dwc->delayed_status = false; 134 usb_gadget_set_state(dwc->gadget, USB_STATE_CONFIGURED); 135 136 if (dwc->ep0state == EP0_STATUS_PHASE) 137 __dwc3_ep0_do_control_status(dwc, dwc->eps[direction]); 138 139 return 0; 140 } 141 142 /* 143 * Unfortunately we have uncovered a limitation wrt the Data Phase. 144 * 145 * Section 9.4 says we can wait for the XferNotReady(DATA) event to 146 * come before issueing Start Transfer command, but if we do, we will 147 * miss situations where the host starts another SETUP phase instead of 148 * the DATA phase. Such cases happen at least on TD.7.6 of the Link 149 * Layer Compliance Suite. 150 * 151 * The problem surfaces due to the fact that in case of back-to-back 152 * SETUP packets there will be no XferNotReady(DATA) generated and we 153 * will be stuck waiting for XferNotReady(DATA) forever. 154 * 155 * By looking at tables 9-13 and 9-14 of the Databook, we can see that 156 * it tells us to start Data Phase right away. It also mentions that if 157 * we receive a SETUP phase instead of the DATA phase, core will issue 158 * XferComplete for the DATA phase, before actually initiating it in 159 * the wire, with the TRB's status set to "SETUP_PENDING". Such status 160 * can only be used to print some debugging logs, as the core expects 161 * us to go through to the STATUS phase and start a CONTROL_STATUS TRB, 162 * just so it completes right away, without transferring anything and, 163 * only then, we can go back to the SETUP phase. 164 * 165 * Because of this scenario, SNPS decided to change the programming 166 * model of control transfers and support on-demand transfers only for 167 * the STATUS phase. To fix the issue we have now, we will always wait 168 * for gadget driver to queue the DATA phase's struct usb_request, then 169 * start it right away. 170 * 171 * If we're actually in a 2-stage transfer, we will wait for 172 * XferNotReady(STATUS). 173 */ 174 if (dwc->three_stage_setup) { 175 unsigned int direction; 176 177 direction = dwc->ep0_expect_in; 178 dwc->ep0state = EP0_DATA_PHASE; 179 180 __dwc3_ep0_do_control_data(dwc, dwc->eps[direction], req); 181 182 dep->flags &= ~DWC3_EP0_DIR_IN; 183 } 184 185 return 0; 186 } 187 188 int dwc3_gadget_ep0_queue(struct usb_ep *ep, struct usb_request *request, 189 gfp_t gfp_flags) 190 { 191 struct dwc3_request *req = to_dwc3_request(request); 192 struct dwc3_ep *dep = to_dwc3_ep(ep); 193 struct dwc3 *dwc = dep->dwc; 194 195 unsigned long flags; 196 197 int ret; 198 199 spin_lock_irqsave(&dwc->lock, flags); 200 if (!dep->endpoint.desc || !dwc->pullups_connected) { 201 dev_err(dwc->dev, "%s: can't queue to disabled endpoint\n", 202 dep->name); 203 ret = -ESHUTDOWN; 204 goto out; 205 } 206 207 /* we share one TRB for ep0/1 */ 208 if (!list_empty(&dep->pending_list)) { 209 ret = -EBUSY; 210 goto out; 211 } 212 213 ret = __dwc3_gadget_ep0_queue(dep, req); 214 215 out: 216 spin_unlock_irqrestore(&dwc->lock, flags); 217 218 return ret; 219 } 220 221 static void dwc3_ep0_stall_and_restart(struct dwc3 *dwc) 222 { 223 struct dwc3_ep *dep; 224 225 /* reinitialize physical ep1 */ 226 dep = dwc->eps[1]; 227 dep->flags = DWC3_EP_ENABLED; 228 229 /* stall is always issued on EP0 */ 230 dep = dwc->eps[0]; 231 __dwc3_gadget_ep_set_halt(dep, 1, false); 232 dep->flags = DWC3_EP_ENABLED; 233 dwc->delayed_status = false; 234 235 if (!list_empty(&dep->pending_list)) { 236 struct dwc3_request *req; 237 238 req = next_request(&dep->pending_list); 239 dwc3_gadget_giveback(dep, req, -ECONNRESET); 240 } 241 242 dwc->ep0state = EP0_SETUP_PHASE; 243 dwc3_ep0_out_start(dwc); 244 } 245 246 int __dwc3_gadget_ep0_set_halt(struct usb_ep *ep, int value) 247 { 248 struct dwc3_ep *dep = to_dwc3_ep(ep); 249 struct dwc3 *dwc = dep->dwc; 250 251 dwc3_ep0_stall_and_restart(dwc); 252 253 return 0; 254 } 255 256 int dwc3_gadget_ep0_set_halt(struct usb_ep *ep, int value) 257 { 258 struct dwc3_ep *dep = to_dwc3_ep(ep); 259 struct dwc3 *dwc = dep->dwc; 260 unsigned long flags; 261 int ret; 262 263 spin_lock_irqsave(&dwc->lock, flags); 264 ret = __dwc3_gadget_ep0_set_halt(ep, value); 265 spin_unlock_irqrestore(&dwc->lock, flags); 266 267 return ret; 268 } 269 270 void dwc3_ep0_out_start(struct dwc3 *dwc) 271 { 272 struct dwc3_ep *dep; 273 int ret; 274 275 complete(&dwc->ep0_in_setup); 276 277 dep = dwc->eps[0]; 278 dwc3_ep0_prepare_one_trb(dep, dwc->ep0_trb_addr, 8, 279 DWC3_TRBCTL_CONTROL_SETUP, false); 280 ret = dwc3_ep0_start_trans(dep); 281 WARN_ON(ret < 0); 282 } 283 284 static struct dwc3_ep *dwc3_wIndex_to_dep(struct dwc3 *dwc, __le16 wIndex_le) 285 { 286 struct dwc3_ep *dep; 287 u32 windex = le16_to_cpu(wIndex_le); 288 u32 epnum; 289 290 epnum = (windex & USB_ENDPOINT_NUMBER_MASK) << 1; 291 if ((windex & USB_ENDPOINT_DIR_MASK) == USB_DIR_IN) 292 epnum |= 1; 293 294 dep = dwc->eps[epnum]; 295 if (dep == NULL) 296 return NULL; 297 298 if (dep->flags & DWC3_EP_ENABLED) 299 return dep; 300 301 return NULL; 302 } 303 304 static void dwc3_ep0_status_cmpl(struct usb_ep *ep, struct usb_request *req) 305 { 306 } 307 /* 308 * ch 9.4.5 309 */ 310 static int dwc3_ep0_handle_status(struct dwc3 *dwc, 311 struct usb_ctrlrequest *ctrl) 312 { 313 struct dwc3_ep *dep; 314 u32 recip; 315 u32 value; 316 u32 reg; 317 u16 usb_status = 0; 318 __le16 *response_pkt; 319 320 /* We don't support PTM_STATUS */ 321 value = le16_to_cpu(ctrl->wValue); 322 if (value != 0) 323 return -EINVAL; 324 325 recip = ctrl->bRequestType & USB_RECIP_MASK; 326 switch (recip) { 327 case USB_RECIP_DEVICE: 328 /* 329 * LTM will be set once we know how to set this in HW. 330 */ 331 usb_status |= dwc->gadget->is_selfpowered; 332 333 if ((dwc->speed == DWC3_DSTS_SUPERSPEED) || 334 (dwc->speed == DWC3_DSTS_SUPERSPEED_PLUS)) { 335 reg = dwc3_readl(dwc->regs, DWC3_DCTL); 336 if (reg & DWC3_DCTL_INITU1ENA) 337 usb_status |= 1 << USB_DEV_STAT_U1_ENABLED; 338 if (reg & DWC3_DCTL_INITU2ENA) 339 usb_status |= 1 << USB_DEV_STAT_U2_ENABLED; 340 } 341 342 break; 343 344 case USB_RECIP_INTERFACE: 345 /* 346 * Function Remote Wake Capable D0 347 * Function Remote Wakeup D1 348 */ 349 break; 350 351 case USB_RECIP_ENDPOINT: 352 dep = dwc3_wIndex_to_dep(dwc, ctrl->wIndex); 353 if (!dep) 354 return -EINVAL; 355 356 if (dep->flags & DWC3_EP_STALL) 357 usb_status = 1 << USB_ENDPOINT_HALT; 358 break; 359 default: 360 return -EINVAL; 361 } 362 363 response_pkt = (__le16 *) dwc->setup_buf; 364 *response_pkt = cpu_to_le16(usb_status); 365 366 dep = dwc->eps[0]; 367 dwc->ep0_usb_req.dep = dep; 368 dwc->ep0_usb_req.request.length = sizeof(*response_pkt); 369 dwc->ep0_usb_req.request.buf = dwc->setup_buf; 370 dwc->ep0_usb_req.request.complete = dwc3_ep0_status_cmpl; 371 372 return __dwc3_gadget_ep0_queue(dep, &dwc->ep0_usb_req); 373 } 374 375 static int dwc3_ep0_handle_u1(struct dwc3 *dwc, enum usb_device_state state, 376 int set) 377 { 378 u32 reg; 379 380 if (state != USB_STATE_CONFIGURED) 381 return -EINVAL; 382 if ((dwc->speed != DWC3_DSTS_SUPERSPEED) && 383 (dwc->speed != DWC3_DSTS_SUPERSPEED_PLUS)) 384 return -EINVAL; 385 if (set && dwc->dis_u1_entry_quirk) 386 return -EINVAL; 387 388 reg = dwc3_readl(dwc->regs, DWC3_DCTL); 389 if (set) 390 reg |= DWC3_DCTL_INITU1ENA; 391 else 392 reg &= ~DWC3_DCTL_INITU1ENA; 393 dwc3_writel(dwc->regs, DWC3_DCTL, reg); 394 395 return 0; 396 } 397 398 static int dwc3_ep0_handle_u2(struct dwc3 *dwc, enum usb_device_state state, 399 int set) 400 { 401 u32 reg; 402 403 404 if (state != USB_STATE_CONFIGURED) 405 return -EINVAL; 406 if ((dwc->speed != DWC3_DSTS_SUPERSPEED) && 407 (dwc->speed != DWC3_DSTS_SUPERSPEED_PLUS)) 408 return -EINVAL; 409 if (set && dwc->dis_u2_entry_quirk) 410 return -EINVAL; 411 412 reg = dwc3_readl(dwc->regs, DWC3_DCTL); 413 if (set) 414 reg |= DWC3_DCTL_INITU2ENA; 415 else 416 reg &= ~DWC3_DCTL_INITU2ENA; 417 dwc3_writel(dwc->regs, DWC3_DCTL, reg); 418 419 return 0; 420 } 421 422 static int dwc3_ep0_handle_test(struct dwc3 *dwc, enum usb_device_state state, 423 u32 wIndex, int set) 424 { 425 if ((wIndex & 0xff) != 0) 426 return -EINVAL; 427 if (!set) 428 return -EINVAL; 429 430 switch (wIndex >> 8) { 431 case USB_TEST_J: 432 case USB_TEST_K: 433 case USB_TEST_SE0_NAK: 434 case USB_TEST_PACKET: 435 case USB_TEST_FORCE_ENABLE: 436 dwc->test_mode_nr = wIndex >> 8; 437 dwc->test_mode = true; 438 break; 439 default: 440 return -EINVAL; 441 } 442 443 return 0; 444 } 445 446 static int dwc3_ep0_handle_device(struct dwc3 *dwc, 447 struct usb_ctrlrequest *ctrl, int set) 448 { 449 enum usb_device_state state; 450 u32 wValue; 451 u32 wIndex; 452 int ret = 0; 453 454 wValue = le16_to_cpu(ctrl->wValue); 455 wIndex = le16_to_cpu(ctrl->wIndex); 456 state = dwc->gadget->state; 457 458 switch (wValue) { 459 case USB_DEVICE_REMOTE_WAKEUP: 460 break; 461 /* 462 * 9.4.1 says only only for SS, in AddressState only for 463 * default control pipe 464 */ 465 case USB_DEVICE_U1_ENABLE: 466 ret = dwc3_ep0_handle_u1(dwc, state, set); 467 break; 468 case USB_DEVICE_U2_ENABLE: 469 ret = dwc3_ep0_handle_u2(dwc, state, set); 470 break; 471 case USB_DEVICE_LTM_ENABLE: 472 ret = -EINVAL; 473 break; 474 case USB_DEVICE_TEST_MODE: 475 ret = dwc3_ep0_handle_test(dwc, state, wIndex, set); 476 break; 477 default: 478 ret = -EINVAL; 479 } 480 481 return ret; 482 } 483 484 static int dwc3_ep0_handle_intf(struct dwc3 *dwc, 485 struct usb_ctrlrequest *ctrl, int set) 486 { 487 u32 wValue; 488 int ret = 0; 489 490 wValue = le16_to_cpu(ctrl->wValue); 491 492 switch (wValue) { 493 case USB_INTRF_FUNC_SUSPEND: 494 /* 495 * REVISIT: Ideally we would enable some low power mode here, 496 * however it's unclear what we should be doing here. 497 * 498 * For now, we're not doing anything, just making sure we return 499 * 0 so USB Command Verifier tests pass without any errors. 500 */ 501 break; 502 default: 503 ret = -EINVAL; 504 } 505 506 return ret; 507 } 508 509 static int dwc3_ep0_handle_endpoint(struct dwc3 *dwc, 510 struct usb_ctrlrequest *ctrl, int set) 511 { 512 struct dwc3_ep *dep; 513 u32 wValue; 514 int ret; 515 516 wValue = le16_to_cpu(ctrl->wValue); 517 518 switch (wValue) { 519 case USB_ENDPOINT_HALT: 520 dep = dwc3_wIndex_to_dep(dwc, ctrl->wIndex); 521 if (!dep) 522 return -EINVAL; 523 524 if (set == 0 && (dep->flags & DWC3_EP_WEDGE)) 525 break; 526 527 ret = __dwc3_gadget_ep_set_halt(dep, set, true); 528 if (ret) 529 return -EINVAL; 530 531 /* ClearFeature(Halt) may need delayed status */ 532 if (!set && (dep->flags & DWC3_EP_END_TRANSFER_PENDING)) 533 return USB_GADGET_DELAYED_STATUS; 534 535 break; 536 default: 537 return -EINVAL; 538 } 539 540 return 0; 541 } 542 543 static int dwc3_ep0_handle_feature(struct dwc3 *dwc, 544 struct usb_ctrlrequest *ctrl, int set) 545 { 546 u32 recip; 547 int ret; 548 549 recip = ctrl->bRequestType & USB_RECIP_MASK; 550 551 switch (recip) { 552 case USB_RECIP_DEVICE: 553 ret = dwc3_ep0_handle_device(dwc, ctrl, set); 554 break; 555 case USB_RECIP_INTERFACE: 556 ret = dwc3_ep0_handle_intf(dwc, ctrl, set); 557 break; 558 case USB_RECIP_ENDPOINT: 559 ret = dwc3_ep0_handle_endpoint(dwc, ctrl, set); 560 break; 561 default: 562 ret = -EINVAL; 563 } 564 565 return ret; 566 } 567 568 static int dwc3_ep0_set_address(struct dwc3 *dwc, struct usb_ctrlrequest *ctrl) 569 { 570 enum usb_device_state state = dwc->gadget->state; 571 u32 addr; 572 u32 reg; 573 574 addr = le16_to_cpu(ctrl->wValue); 575 if (addr > 127) { 576 dev_err(dwc->dev, "invalid device address %d\n", addr); 577 return -EINVAL; 578 } 579 580 if (state == USB_STATE_CONFIGURED) { 581 dev_err(dwc->dev, "can't SetAddress() from Configured State\n"); 582 return -EINVAL; 583 } 584 585 reg = dwc3_readl(dwc->regs, DWC3_DCFG); 586 reg &= ~(DWC3_DCFG_DEVADDR_MASK); 587 reg |= DWC3_DCFG_DEVADDR(addr); 588 dwc3_writel(dwc->regs, DWC3_DCFG, reg); 589 590 if (addr) 591 usb_gadget_set_state(dwc->gadget, USB_STATE_ADDRESS); 592 else 593 usb_gadget_set_state(dwc->gadget, USB_STATE_DEFAULT); 594 595 return 0; 596 } 597 598 static int dwc3_ep0_delegate_req(struct dwc3 *dwc, struct usb_ctrlrequest *ctrl) 599 { 600 int ret; 601 602 spin_unlock(&dwc->lock); 603 ret = dwc->gadget_driver->setup(dwc->gadget, ctrl); 604 spin_lock(&dwc->lock); 605 return ret; 606 } 607 608 static int dwc3_ep0_set_config(struct dwc3 *dwc, struct usb_ctrlrequest *ctrl) 609 { 610 enum usb_device_state state = dwc->gadget->state; 611 u32 cfg; 612 int ret; 613 u32 reg; 614 615 cfg = le16_to_cpu(ctrl->wValue); 616 617 switch (state) { 618 case USB_STATE_DEFAULT: 619 return -EINVAL; 620 621 case USB_STATE_ADDRESS: 622 ret = dwc3_ep0_delegate_req(dwc, ctrl); 623 /* if the cfg matches and the cfg is non zero */ 624 if (cfg && (!ret || (ret == USB_GADGET_DELAYED_STATUS))) { 625 626 /* 627 * only change state if set_config has already 628 * been processed. If gadget driver returns 629 * USB_GADGET_DELAYED_STATUS, we will wait 630 * to change the state on the next usb_ep_queue() 631 */ 632 if (ret == 0) 633 usb_gadget_set_state(dwc->gadget, 634 USB_STATE_CONFIGURED); 635 636 /* 637 * Enable transition to U1/U2 state when 638 * nothing is pending from application. 639 */ 640 reg = dwc3_readl(dwc->regs, DWC3_DCTL); 641 if (!dwc->dis_u1_entry_quirk) 642 reg |= DWC3_DCTL_ACCEPTU1ENA; 643 if (!dwc->dis_u2_entry_quirk) 644 reg |= DWC3_DCTL_ACCEPTU2ENA; 645 dwc3_writel(dwc->regs, DWC3_DCTL, reg); 646 } 647 break; 648 649 case USB_STATE_CONFIGURED: 650 ret = dwc3_ep0_delegate_req(dwc, ctrl); 651 if (!cfg && !ret) 652 usb_gadget_set_state(dwc->gadget, 653 USB_STATE_ADDRESS); 654 break; 655 default: 656 ret = -EINVAL; 657 } 658 return ret; 659 } 660 661 static void dwc3_ep0_set_sel_cmpl(struct usb_ep *ep, struct usb_request *req) 662 { 663 struct dwc3_ep *dep = to_dwc3_ep(ep); 664 struct dwc3 *dwc = dep->dwc; 665 666 u32 param = 0; 667 u32 reg; 668 669 struct timing { 670 u8 u1sel; 671 u8 u1pel; 672 __le16 u2sel; 673 __le16 u2pel; 674 } __packed timing; 675 676 int ret; 677 678 memcpy(&timing, req->buf, sizeof(timing)); 679 680 dwc->u1sel = timing.u1sel; 681 dwc->u1pel = timing.u1pel; 682 dwc->u2sel = le16_to_cpu(timing.u2sel); 683 dwc->u2pel = le16_to_cpu(timing.u2pel); 684 685 reg = dwc3_readl(dwc->regs, DWC3_DCTL); 686 if (reg & DWC3_DCTL_INITU2ENA) 687 param = dwc->u2pel; 688 if (reg & DWC3_DCTL_INITU1ENA) 689 param = dwc->u1pel; 690 691 /* 692 * According to Synopsys Databook, if parameter is 693 * greater than 125, a value of zero should be 694 * programmed in the register. 695 */ 696 if (param > 125) 697 param = 0; 698 699 /* now that we have the time, issue DGCMD Set Sel */ 700 ret = dwc3_send_gadget_generic_command(dwc, 701 DWC3_DGCMD_SET_PERIODIC_PAR, param); 702 WARN_ON(ret < 0); 703 } 704 705 static int dwc3_ep0_set_sel(struct dwc3 *dwc, struct usb_ctrlrequest *ctrl) 706 { 707 struct dwc3_ep *dep; 708 enum usb_device_state state = dwc->gadget->state; 709 u16 wLength; 710 711 if (state == USB_STATE_DEFAULT) 712 return -EINVAL; 713 714 wLength = le16_to_cpu(ctrl->wLength); 715 716 if (wLength != 6) { 717 dev_err(dwc->dev, "Set SEL should be 6 bytes, got %d\n", 718 wLength); 719 return -EINVAL; 720 } 721 722 /* 723 * To handle Set SEL we need to receive 6 bytes from Host. So let's 724 * queue a usb_request for 6 bytes. 725 * 726 * Remember, though, this controller can't handle non-wMaxPacketSize 727 * aligned transfers on the OUT direction, so we queue a request for 728 * wMaxPacketSize instead. 729 */ 730 dep = dwc->eps[0]; 731 dwc->ep0_usb_req.dep = dep; 732 dwc->ep0_usb_req.request.length = dep->endpoint.maxpacket; 733 dwc->ep0_usb_req.request.buf = dwc->setup_buf; 734 dwc->ep0_usb_req.request.complete = dwc3_ep0_set_sel_cmpl; 735 736 return __dwc3_gadget_ep0_queue(dep, &dwc->ep0_usb_req); 737 } 738 739 static int dwc3_ep0_set_isoch_delay(struct dwc3 *dwc, struct usb_ctrlrequest *ctrl) 740 { 741 u16 wLength; 742 u16 wValue; 743 u16 wIndex; 744 745 wValue = le16_to_cpu(ctrl->wValue); 746 wLength = le16_to_cpu(ctrl->wLength); 747 wIndex = le16_to_cpu(ctrl->wIndex); 748 749 if (wIndex || wLength) 750 return -EINVAL; 751 752 dwc->gadget->isoch_delay = wValue; 753 754 return 0; 755 } 756 757 static int dwc3_ep0_std_request(struct dwc3 *dwc, struct usb_ctrlrequest *ctrl) 758 { 759 int ret; 760 761 switch (ctrl->bRequest) { 762 case USB_REQ_GET_STATUS: 763 ret = dwc3_ep0_handle_status(dwc, ctrl); 764 break; 765 case USB_REQ_CLEAR_FEATURE: 766 ret = dwc3_ep0_handle_feature(dwc, ctrl, 0); 767 break; 768 case USB_REQ_SET_FEATURE: 769 ret = dwc3_ep0_handle_feature(dwc, ctrl, 1); 770 break; 771 case USB_REQ_SET_ADDRESS: 772 ret = dwc3_ep0_set_address(dwc, ctrl); 773 break; 774 case USB_REQ_SET_CONFIGURATION: 775 ret = dwc3_ep0_set_config(dwc, ctrl); 776 break; 777 case USB_REQ_SET_SEL: 778 ret = dwc3_ep0_set_sel(dwc, ctrl); 779 break; 780 case USB_REQ_SET_ISOCH_DELAY: 781 ret = dwc3_ep0_set_isoch_delay(dwc, ctrl); 782 break; 783 default: 784 ret = dwc3_ep0_delegate_req(dwc, ctrl); 785 break; 786 } 787 788 return ret; 789 } 790 791 static void dwc3_ep0_inspect_setup(struct dwc3 *dwc, 792 const struct dwc3_event_depevt *event) 793 { 794 struct usb_ctrlrequest *ctrl = (void *) dwc->ep0_trb; 795 int ret = -EINVAL; 796 u32 len; 797 798 if (!dwc->gadget_driver) 799 goto out; 800 801 trace_dwc3_ctrl_req(ctrl); 802 803 len = le16_to_cpu(ctrl->wLength); 804 if (!len) { 805 dwc->three_stage_setup = false; 806 dwc->ep0_expect_in = false; 807 dwc->ep0_next_event = DWC3_EP0_NRDY_STATUS; 808 } else { 809 dwc->three_stage_setup = true; 810 dwc->ep0_expect_in = !!(ctrl->bRequestType & USB_DIR_IN); 811 dwc->ep0_next_event = DWC3_EP0_NRDY_DATA; 812 } 813 814 if ((ctrl->bRequestType & USB_TYPE_MASK) == USB_TYPE_STANDARD) 815 ret = dwc3_ep0_std_request(dwc, ctrl); 816 else 817 ret = dwc3_ep0_delegate_req(dwc, ctrl); 818 819 if (ret == USB_GADGET_DELAYED_STATUS) 820 dwc->delayed_status = true; 821 822 out: 823 if (ret < 0) 824 dwc3_ep0_stall_and_restart(dwc); 825 } 826 827 static void dwc3_ep0_complete_data(struct dwc3 *dwc, 828 const struct dwc3_event_depevt *event) 829 { 830 struct dwc3_request *r; 831 struct usb_request *ur; 832 struct dwc3_trb *trb; 833 struct dwc3_ep *ep0; 834 u32 transferred = 0; 835 u32 status; 836 u32 length; 837 u8 epnum; 838 839 epnum = event->endpoint_number; 840 ep0 = dwc->eps[0]; 841 842 dwc->ep0_next_event = DWC3_EP0_NRDY_STATUS; 843 trb = dwc->ep0_trb; 844 trace_dwc3_complete_trb(ep0, trb); 845 846 r = next_request(&ep0->pending_list); 847 if (!r) 848 return; 849 850 status = DWC3_TRB_SIZE_TRBSTS(trb->size); 851 if (status == DWC3_TRBSTS_SETUP_PENDING) { 852 dwc->setup_packet_pending = true; 853 if (r) 854 dwc3_gadget_giveback(ep0, r, -ECONNRESET); 855 856 return; 857 } 858 859 ur = &r->request; 860 861 length = trb->size & DWC3_TRB_SIZE_MASK; 862 transferred = ur->length - length; 863 ur->actual += transferred; 864 865 if ((IS_ALIGNED(ur->length, ep0->endpoint.maxpacket) && 866 ur->length && ur->zero) || dwc->ep0_bounced) { 867 trb++; 868 trb->ctrl &= ~DWC3_TRB_CTRL_HWO; 869 trace_dwc3_complete_trb(ep0, trb); 870 871 if (r->direction) 872 dwc->eps[1]->trb_enqueue = 0; 873 else 874 dwc->eps[0]->trb_enqueue = 0; 875 876 dwc->ep0_bounced = false; 877 } 878 879 if ((epnum & 1) && ur->actual < ur->length) 880 dwc3_ep0_stall_and_restart(dwc); 881 else 882 dwc3_gadget_giveback(ep0, r, 0); 883 } 884 885 static void dwc3_ep0_complete_status(struct dwc3 *dwc, 886 const struct dwc3_event_depevt *event) 887 { 888 struct dwc3_request *r; 889 struct dwc3_ep *dep; 890 struct dwc3_trb *trb; 891 u32 status; 892 893 dep = dwc->eps[0]; 894 trb = dwc->ep0_trb; 895 896 trace_dwc3_complete_trb(dep, trb); 897 898 if (!list_empty(&dep->pending_list)) { 899 r = next_request(&dep->pending_list); 900 901 dwc3_gadget_giveback(dep, r, 0); 902 } 903 904 if (dwc->test_mode) { 905 int ret; 906 907 ret = dwc3_gadget_set_test_mode(dwc, dwc->test_mode_nr); 908 if (ret < 0) { 909 dev_err(dwc->dev, "invalid test #%d\n", 910 dwc->test_mode_nr); 911 dwc3_ep0_stall_and_restart(dwc); 912 return; 913 } 914 } 915 916 status = DWC3_TRB_SIZE_TRBSTS(trb->size); 917 if (status == DWC3_TRBSTS_SETUP_PENDING) 918 dwc->setup_packet_pending = true; 919 920 dwc->ep0state = EP0_SETUP_PHASE; 921 dwc3_ep0_out_start(dwc); 922 } 923 924 static void dwc3_ep0_xfer_complete(struct dwc3 *dwc, 925 const struct dwc3_event_depevt *event) 926 { 927 struct dwc3_ep *dep = dwc->eps[event->endpoint_number]; 928 929 dep->flags &= ~DWC3_EP_TRANSFER_STARTED; 930 dep->resource_index = 0; 931 dwc->setup_packet_pending = false; 932 933 switch (dwc->ep0state) { 934 case EP0_SETUP_PHASE: 935 dwc3_ep0_inspect_setup(dwc, event); 936 break; 937 938 case EP0_DATA_PHASE: 939 dwc3_ep0_complete_data(dwc, event); 940 break; 941 942 case EP0_STATUS_PHASE: 943 dwc3_ep0_complete_status(dwc, event); 944 break; 945 default: 946 WARN(true, "UNKNOWN ep0state %d\n", dwc->ep0state); 947 } 948 } 949 950 static void __dwc3_ep0_do_control_data(struct dwc3 *dwc, 951 struct dwc3_ep *dep, struct dwc3_request *req) 952 { 953 unsigned int trb_length = 0; 954 int ret; 955 956 req->direction = !!dep->number; 957 958 if (req->request.length == 0) { 959 if (!req->direction) 960 trb_length = dep->endpoint.maxpacket; 961 962 dwc3_ep0_prepare_one_trb(dep, dwc->bounce_addr, trb_length, 963 DWC3_TRBCTL_CONTROL_DATA, false); 964 ret = dwc3_ep0_start_trans(dep); 965 } else if (!IS_ALIGNED(req->request.length, dep->endpoint.maxpacket) 966 && (dep->number == 0)) { 967 u32 maxpacket; 968 u32 rem; 969 970 ret = usb_gadget_map_request_by_dev(dwc->sysdev, 971 &req->request, dep->number); 972 if (ret) 973 return; 974 975 maxpacket = dep->endpoint.maxpacket; 976 rem = req->request.length % maxpacket; 977 dwc->ep0_bounced = true; 978 979 /* prepare normal TRB */ 980 dwc3_ep0_prepare_one_trb(dep, req->request.dma, 981 req->request.length, 982 DWC3_TRBCTL_CONTROL_DATA, 983 true); 984 985 req->trb = &dwc->ep0_trb[dep->trb_enqueue - 1]; 986 987 /* Now prepare one extra TRB to align transfer size */ 988 dwc3_ep0_prepare_one_trb(dep, dwc->bounce_addr, 989 maxpacket - rem, 990 DWC3_TRBCTL_CONTROL_DATA, 991 false); 992 ret = dwc3_ep0_start_trans(dep); 993 } else if (IS_ALIGNED(req->request.length, dep->endpoint.maxpacket) && 994 req->request.length && req->request.zero) { 995 996 ret = usb_gadget_map_request_by_dev(dwc->sysdev, 997 &req->request, dep->number); 998 if (ret) 999 return; 1000 1001 /* prepare normal TRB */ 1002 dwc3_ep0_prepare_one_trb(dep, req->request.dma, 1003 req->request.length, 1004 DWC3_TRBCTL_CONTROL_DATA, 1005 true); 1006 1007 req->trb = &dwc->ep0_trb[dep->trb_enqueue - 1]; 1008 1009 if (!req->direction) 1010 trb_length = dep->endpoint.maxpacket; 1011 1012 /* Now prepare one extra TRB to align transfer size */ 1013 dwc3_ep0_prepare_one_trb(dep, dwc->bounce_addr, 1014 trb_length, DWC3_TRBCTL_CONTROL_DATA, 1015 false); 1016 ret = dwc3_ep0_start_trans(dep); 1017 } else { 1018 ret = usb_gadget_map_request_by_dev(dwc->sysdev, 1019 &req->request, dep->number); 1020 if (ret) 1021 return; 1022 1023 dwc3_ep0_prepare_one_trb(dep, req->request.dma, 1024 req->request.length, DWC3_TRBCTL_CONTROL_DATA, 1025 false); 1026 1027 req->trb = &dwc->ep0_trb[dep->trb_enqueue]; 1028 1029 ret = dwc3_ep0_start_trans(dep); 1030 } 1031 1032 WARN_ON(ret < 0); 1033 } 1034 1035 static int dwc3_ep0_start_control_status(struct dwc3_ep *dep) 1036 { 1037 struct dwc3 *dwc = dep->dwc; 1038 u32 type; 1039 1040 type = dwc->three_stage_setup ? DWC3_TRBCTL_CONTROL_STATUS3 1041 : DWC3_TRBCTL_CONTROL_STATUS2; 1042 1043 dwc3_ep0_prepare_one_trb(dep, dwc->ep0_trb_addr, 0, type, false); 1044 return dwc3_ep0_start_trans(dep); 1045 } 1046 1047 static void __dwc3_ep0_do_control_status(struct dwc3 *dwc, struct dwc3_ep *dep) 1048 { 1049 WARN_ON(dwc3_ep0_start_control_status(dep)); 1050 } 1051 1052 static void dwc3_ep0_do_control_status(struct dwc3 *dwc, 1053 const struct dwc3_event_depevt *event) 1054 { 1055 struct dwc3_ep *dep = dwc->eps[event->endpoint_number]; 1056 1057 __dwc3_ep0_do_control_status(dwc, dep); 1058 } 1059 1060 void dwc3_ep0_send_delayed_status(struct dwc3 *dwc) 1061 { 1062 unsigned int direction = !dwc->ep0_expect_in; 1063 1064 dwc->delayed_status = false; 1065 1066 if (dwc->ep0state != EP0_STATUS_PHASE) 1067 return; 1068 1069 __dwc3_ep0_do_control_status(dwc, dwc->eps[direction]); 1070 } 1071 1072 static void dwc3_ep0_end_control_data(struct dwc3 *dwc, struct dwc3_ep *dep) 1073 { 1074 struct dwc3_gadget_ep_cmd_params params; 1075 u32 cmd; 1076 int ret; 1077 1078 if (!dep->resource_index) 1079 return; 1080 1081 cmd = DWC3_DEPCMD_ENDTRANSFER; 1082 cmd |= DWC3_DEPCMD_CMDIOC; 1083 cmd |= DWC3_DEPCMD_PARAM(dep->resource_index); 1084 memset(¶ms, 0, sizeof(params)); 1085 ret = dwc3_send_gadget_ep_cmd(dep, cmd, ¶ms); 1086 WARN_ON_ONCE(ret); 1087 dep->resource_index = 0; 1088 } 1089 1090 static void dwc3_ep0_xfernotready(struct dwc3 *dwc, 1091 const struct dwc3_event_depevt *event) 1092 { 1093 switch (event->status) { 1094 case DEPEVT_STATUS_CONTROL_DATA: 1095 /* 1096 * We already have a DATA transfer in the controller's cache, 1097 * if we receive a XferNotReady(DATA) we will ignore it, unless 1098 * it's for the wrong direction. 1099 * 1100 * In that case, we must issue END_TRANSFER command to the Data 1101 * Phase we already have started and issue SetStall on the 1102 * control endpoint. 1103 */ 1104 if (dwc->ep0_expect_in != event->endpoint_number) { 1105 struct dwc3_ep *dep = dwc->eps[dwc->ep0_expect_in]; 1106 1107 dev_err(dwc->dev, "unexpected direction for Data Phase\n"); 1108 dwc3_ep0_end_control_data(dwc, dep); 1109 dwc3_ep0_stall_and_restart(dwc); 1110 return; 1111 } 1112 1113 break; 1114 1115 case DEPEVT_STATUS_CONTROL_STATUS: 1116 if (dwc->ep0_next_event != DWC3_EP0_NRDY_STATUS) 1117 return; 1118 1119 dwc->ep0state = EP0_STATUS_PHASE; 1120 1121 if (dwc->delayed_status) { 1122 struct dwc3_ep *dep = dwc->eps[0]; 1123 1124 WARN_ON_ONCE(event->endpoint_number != 1); 1125 /* 1126 * We should handle the delay STATUS phase here if the 1127 * request for handling delay STATUS has been queued 1128 * into the list. 1129 */ 1130 if (!list_empty(&dep->pending_list)) { 1131 dwc->delayed_status = false; 1132 usb_gadget_set_state(dwc->gadget, 1133 USB_STATE_CONFIGURED); 1134 dwc3_ep0_do_control_status(dwc, event); 1135 } 1136 1137 return; 1138 } 1139 1140 dwc3_ep0_do_control_status(dwc, event); 1141 } 1142 } 1143 1144 void dwc3_ep0_interrupt(struct dwc3 *dwc, 1145 const struct dwc3_event_depevt *event) 1146 { 1147 struct dwc3_ep *dep = dwc->eps[event->endpoint_number]; 1148 u8 cmd; 1149 1150 switch (event->endpoint_event) { 1151 case DWC3_DEPEVT_XFERCOMPLETE: 1152 dwc3_ep0_xfer_complete(dwc, event); 1153 break; 1154 1155 case DWC3_DEPEVT_XFERNOTREADY: 1156 dwc3_ep0_xfernotready(dwc, event); 1157 break; 1158 1159 case DWC3_DEPEVT_XFERINPROGRESS: 1160 case DWC3_DEPEVT_RXTXFIFOEVT: 1161 case DWC3_DEPEVT_STREAMEVT: 1162 break; 1163 case DWC3_DEPEVT_EPCMDCMPLT: 1164 cmd = DEPEVT_PARAMETER_CMD(event->parameters); 1165 1166 if (cmd == DWC3_DEPCMD_ENDTRANSFER) { 1167 dep->flags &= ~DWC3_EP_END_TRANSFER_PENDING; 1168 dep->flags &= ~DWC3_EP_TRANSFER_STARTED; 1169 } 1170 break; 1171 } 1172 } 1173