1 /** 2 * ep0.c - DesignWare USB3 DRD Controller Endpoint 0 Handling 3 * 4 * Copyright (C) 2010-2011 Texas Instruments Incorporated - http://www.ti.com 5 * 6 * Authors: Felipe Balbi <balbi@ti.com>, 7 * Sebastian Andrzej Siewior <bigeasy@linutronix.de> 8 * 9 * Redistribution and use in source and binary forms, with or without 10 * modification, are permitted provided that the following conditions 11 * are met: 12 * 1. Redistributions of source code must retain the above copyright 13 * notice, this list of conditions, and the following disclaimer, 14 * without modification. 15 * 2. Redistributions in binary form must reproduce the above copyright 16 * notice, this list of conditions and the following disclaimer in the 17 * documentation and/or other materials provided with the distribution. 18 * 3. The names of the above-listed copyright holders may not be used 19 * to endorse or promote products derived from this software without 20 * specific prior written permission. 21 * 22 * ALTERNATIVELY, this software may be distributed under the terms of the 23 * GNU General Public License ("GPL") version 2, as published by the Free 24 * Software Foundation. 25 * 26 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS 27 * IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, 28 * THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR 29 * PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR 30 * CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, 31 * EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, 32 * PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR 33 * PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF 34 * LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING 35 * NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS 36 * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. 37 */ 38 39 #include <linux/kernel.h> 40 #include <linux/slab.h> 41 #include <linux/spinlock.h> 42 #include <linux/platform_device.h> 43 #include <linux/pm_runtime.h> 44 #include <linux/interrupt.h> 45 #include <linux/io.h> 46 #include <linux/list.h> 47 #include <linux/dma-mapping.h> 48 49 #include <linux/usb/ch9.h> 50 #include <linux/usb/gadget.h> 51 #include <linux/usb/composite.h> 52 53 #include "core.h" 54 #include "gadget.h" 55 #include "io.h" 56 57 static void dwc3_ep0_do_control_status(struct dwc3 *dwc, u32 epnum); 58 59 static const char *dwc3_ep0_state_string(enum dwc3_ep0_state state) 60 { 61 switch (state) { 62 case EP0_UNCONNECTED: 63 return "Unconnected"; 64 case EP0_SETUP_PHASE: 65 return "Setup Phase"; 66 case EP0_DATA_PHASE: 67 return "Data Phase"; 68 case EP0_STATUS_PHASE: 69 return "Status Phase"; 70 default: 71 return "UNKNOWN"; 72 } 73 } 74 75 static int dwc3_ep0_start_trans(struct dwc3 *dwc, u8 epnum, dma_addr_t buf_dma, 76 u32 len, u32 type) 77 { 78 struct dwc3_gadget_ep_cmd_params params; 79 struct dwc3_trb_hw *trb_hw; 80 struct dwc3_trb trb; 81 struct dwc3_ep *dep; 82 83 int ret; 84 85 dep = dwc->eps[epnum]; 86 if (dep->flags & DWC3_EP_BUSY) { 87 dev_vdbg(dwc->dev, "%s: still busy\n", dep->name); 88 return 0; 89 } 90 91 trb_hw = dwc->ep0_trb; 92 memset(&trb, 0, sizeof(trb)); 93 94 trb.trbctl = type; 95 trb.bplh = buf_dma; 96 trb.length = len; 97 98 trb.hwo = 1; 99 trb.lst = 1; 100 trb.ioc = 1; 101 trb.isp_imi = 1; 102 103 dwc3_trb_to_hw(&trb, trb_hw); 104 105 memset(¶ms, 0, sizeof(params)); 106 params.param0 = upper_32_bits(dwc->ep0_trb_addr); 107 params.param1 = lower_32_bits(dwc->ep0_trb_addr); 108 109 ret = dwc3_send_gadget_ep_cmd(dwc, dep->number, 110 DWC3_DEPCMD_STARTTRANSFER, ¶ms); 111 if (ret < 0) { 112 dev_dbg(dwc->dev, "failed to send STARTTRANSFER command\n"); 113 return ret; 114 } 115 116 dep->flags |= DWC3_EP_BUSY; 117 dep->res_trans_idx = dwc3_gadget_ep_get_transfer_index(dwc, 118 dep->number); 119 120 dwc->ep0_next_event = DWC3_EP0_COMPLETE; 121 122 return 0; 123 } 124 125 static int __dwc3_gadget_ep0_queue(struct dwc3_ep *dep, 126 struct dwc3_request *req) 127 { 128 struct dwc3 *dwc = dep->dwc; 129 int ret = 0; 130 131 req->request.actual = 0; 132 req->request.status = -EINPROGRESS; 133 req->epnum = dep->number; 134 135 list_add_tail(&req->list, &dep->request_list); 136 137 /* 138 * Gadget driver might not be quick enough to queue a request 139 * before we get a Transfer Not Ready event on this endpoint. 140 * 141 * In that case, we will set DWC3_EP_PENDING_REQUEST. When that 142 * flag is set, it's telling us that as soon as Gadget queues the 143 * required request, we should kick the transfer here because the 144 * IRQ we were waiting for is long gone. 145 */ 146 if (dep->flags & DWC3_EP_PENDING_REQUEST) { 147 unsigned direction; 148 149 direction = !!(dep->flags & DWC3_EP0_DIR_IN); 150 151 if (dwc->ep0state != EP0_DATA_PHASE) { 152 dev_WARN(dwc->dev, "Unexpected pending request\n"); 153 return 0; 154 } 155 156 ret = dwc3_ep0_start_trans(dwc, direction, 157 req->request.dma, req->request.length, 158 DWC3_TRBCTL_CONTROL_DATA); 159 dep->flags &= ~(DWC3_EP_PENDING_REQUEST | 160 DWC3_EP0_DIR_IN); 161 } else if (dwc->delayed_status) { 162 dwc->delayed_status = false; 163 164 if (dwc->ep0state == EP0_STATUS_PHASE) 165 dwc3_ep0_do_control_status(dwc, 1); 166 else 167 dev_dbg(dwc->dev, "too early for delayed status\n"); 168 } 169 170 return ret; 171 } 172 173 int dwc3_gadget_ep0_queue(struct usb_ep *ep, struct usb_request *request, 174 gfp_t gfp_flags) 175 { 176 struct dwc3_request *req = to_dwc3_request(request); 177 struct dwc3_ep *dep = to_dwc3_ep(ep); 178 struct dwc3 *dwc = dep->dwc; 179 180 unsigned long flags; 181 182 int ret; 183 184 spin_lock_irqsave(&dwc->lock, flags); 185 if (!dep->desc) { 186 dev_dbg(dwc->dev, "trying to queue request %p to disabled %s\n", 187 request, dep->name); 188 ret = -ESHUTDOWN; 189 goto out; 190 } 191 192 /* we share one TRB for ep0/1 */ 193 if (!list_empty(&dep->request_list)) { 194 ret = -EBUSY; 195 goto out; 196 } 197 198 dev_vdbg(dwc->dev, "queueing request %p to %s length %d, state '%s'\n", 199 request, dep->name, request->length, 200 dwc3_ep0_state_string(dwc->ep0state)); 201 202 ret = __dwc3_gadget_ep0_queue(dep, req); 203 204 out: 205 spin_unlock_irqrestore(&dwc->lock, flags); 206 207 return ret; 208 } 209 210 static void dwc3_ep0_stall_and_restart(struct dwc3 *dwc) 211 { 212 struct dwc3_ep *dep = dwc->eps[0]; 213 214 /* stall is always issued on EP0 */ 215 __dwc3_gadget_ep_set_halt(dep, 1); 216 dep->flags = DWC3_EP_ENABLED; 217 dwc->delayed_status = false; 218 219 if (!list_empty(&dep->request_list)) { 220 struct dwc3_request *req; 221 222 req = next_request(&dep->request_list); 223 dwc3_gadget_giveback(dep, req, -ECONNRESET); 224 } 225 226 dwc->ep0state = EP0_SETUP_PHASE; 227 dwc3_ep0_out_start(dwc); 228 } 229 230 void dwc3_ep0_out_start(struct dwc3 *dwc) 231 { 232 int ret; 233 234 ret = dwc3_ep0_start_trans(dwc, 0, dwc->ctrl_req_addr, 8, 235 DWC3_TRBCTL_CONTROL_SETUP); 236 WARN_ON(ret < 0); 237 } 238 239 static struct dwc3_ep *dwc3_wIndex_to_dep(struct dwc3 *dwc, __le16 wIndex_le) 240 { 241 struct dwc3_ep *dep; 242 u32 windex = le16_to_cpu(wIndex_le); 243 u32 epnum; 244 245 epnum = (windex & USB_ENDPOINT_NUMBER_MASK) << 1; 246 if ((windex & USB_ENDPOINT_DIR_MASK) == USB_DIR_IN) 247 epnum |= 1; 248 249 dep = dwc->eps[epnum]; 250 if (dep->flags & DWC3_EP_ENABLED) 251 return dep; 252 253 return NULL; 254 } 255 256 static void dwc3_ep0_status_cmpl(struct usb_ep *ep, struct usb_request *req) 257 { 258 } 259 /* 260 * ch 9.4.5 261 */ 262 static int dwc3_ep0_handle_status(struct dwc3 *dwc, 263 struct usb_ctrlrequest *ctrl) 264 { 265 struct dwc3_ep *dep; 266 u32 recip; 267 u16 usb_status = 0; 268 __le16 *response_pkt; 269 270 recip = ctrl->bRequestType & USB_RECIP_MASK; 271 switch (recip) { 272 case USB_RECIP_DEVICE: 273 /* 274 * We are self-powered. U1/U2/LTM will be set later 275 * once we handle this states. RemoteWakeup is 0 on SS 276 */ 277 usb_status |= dwc->is_selfpowered << USB_DEVICE_SELF_POWERED; 278 break; 279 280 case USB_RECIP_INTERFACE: 281 /* 282 * Function Remote Wake Capable D0 283 * Function Remote Wakeup D1 284 */ 285 break; 286 287 case USB_RECIP_ENDPOINT: 288 dep = dwc3_wIndex_to_dep(dwc, ctrl->wIndex); 289 if (!dep) 290 return -EINVAL; 291 292 if (dep->flags & DWC3_EP_STALL) 293 usb_status = 1 << USB_ENDPOINT_HALT; 294 break; 295 default: 296 return -EINVAL; 297 }; 298 299 response_pkt = (__le16 *) dwc->setup_buf; 300 *response_pkt = cpu_to_le16(usb_status); 301 302 dep = dwc->eps[0]; 303 dwc->ep0_usb_req.dep = dep; 304 dwc->ep0_usb_req.request.length = sizeof(*response_pkt); 305 dwc->ep0_usb_req.request.dma = dwc->setup_buf_addr; 306 dwc->ep0_usb_req.request.complete = dwc3_ep0_status_cmpl; 307 308 return __dwc3_gadget_ep0_queue(dep, &dwc->ep0_usb_req); 309 } 310 311 static int dwc3_ep0_handle_feature(struct dwc3 *dwc, 312 struct usb_ctrlrequest *ctrl, int set) 313 { 314 struct dwc3_ep *dep; 315 u32 recip; 316 u32 wValue; 317 u32 wIndex; 318 u32 reg; 319 int ret; 320 u32 mode; 321 322 wValue = le16_to_cpu(ctrl->wValue); 323 wIndex = le16_to_cpu(ctrl->wIndex); 324 recip = ctrl->bRequestType & USB_RECIP_MASK; 325 switch (recip) { 326 case USB_RECIP_DEVICE: 327 328 /* 329 * 9.4.1 says only only for SS, in AddressState only for 330 * default control pipe 331 */ 332 switch (wValue) { 333 case USB_DEVICE_U1_ENABLE: 334 case USB_DEVICE_U2_ENABLE: 335 case USB_DEVICE_LTM_ENABLE: 336 if (dwc->dev_state != DWC3_CONFIGURED_STATE) 337 return -EINVAL; 338 if (dwc->speed != DWC3_DSTS_SUPERSPEED) 339 return -EINVAL; 340 } 341 342 /* XXX add U[12] & LTM */ 343 switch (wValue) { 344 case USB_DEVICE_REMOTE_WAKEUP: 345 break; 346 case USB_DEVICE_U1_ENABLE: 347 break; 348 case USB_DEVICE_U2_ENABLE: 349 break; 350 case USB_DEVICE_LTM_ENABLE: 351 break; 352 353 case USB_DEVICE_TEST_MODE: 354 if ((wIndex & 0xff) != 0) 355 return -EINVAL; 356 if (!set) 357 return -EINVAL; 358 359 mode = wIndex >> 8; 360 reg = dwc3_readl(dwc->regs, DWC3_DCTL); 361 reg &= ~DWC3_DCTL_TSTCTRL_MASK; 362 363 switch (mode) { 364 case TEST_J: 365 case TEST_K: 366 case TEST_SE0_NAK: 367 case TEST_PACKET: 368 case TEST_FORCE_EN: 369 reg |= mode << 1; 370 break; 371 default: 372 return -EINVAL; 373 } 374 dwc3_writel(dwc->regs, DWC3_DCTL, reg); 375 break; 376 default: 377 return -EINVAL; 378 } 379 break; 380 381 case USB_RECIP_INTERFACE: 382 switch (wValue) { 383 case USB_INTRF_FUNC_SUSPEND: 384 if (wIndex & USB_INTRF_FUNC_SUSPEND_LP) 385 /* XXX enable Low power suspend */ 386 ; 387 if (wIndex & USB_INTRF_FUNC_SUSPEND_RW) 388 /* XXX enable remote wakeup */ 389 ; 390 break; 391 default: 392 return -EINVAL; 393 } 394 break; 395 396 case USB_RECIP_ENDPOINT: 397 switch (wValue) { 398 case USB_ENDPOINT_HALT: 399 dep = dwc3_wIndex_to_dep(dwc, wIndex); 400 if (!dep) 401 return -EINVAL; 402 ret = __dwc3_gadget_ep_set_halt(dep, set); 403 if (ret) 404 return -EINVAL; 405 break; 406 default: 407 return -EINVAL; 408 } 409 break; 410 411 default: 412 return -EINVAL; 413 }; 414 415 return 0; 416 } 417 418 static int dwc3_ep0_set_address(struct dwc3 *dwc, struct usb_ctrlrequest *ctrl) 419 { 420 u32 addr; 421 u32 reg; 422 423 addr = le16_to_cpu(ctrl->wValue); 424 if (addr > 127) { 425 dev_dbg(dwc->dev, "invalid device address %d\n", addr); 426 return -EINVAL; 427 } 428 429 if (dwc->dev_state == DWC3_CONFIGURED_STATE) { 430 dev_dbg(dwc->dev, "trying to set address when configured\n"); 431 return -EINVAL; 432 } 433 434 reg = dwc3_readl(dwc->regs, DWC3_DCFG); 435 reg &= ~(DWC3_DCFG_DEVADDR_MASK); 436 reg |= DWC3_DCFG_DEVADDR(addr); 437 dwc3_writel(dwc->regs, DWC3_DCFG, reg); 438 439 if (addr) 440 dwc->dev_state = DWC3_ADDRESS_STATE; 441 else 442 dwc->dev_state = DWC3_DEFAULT_STATE; 443 444 return 0; 445 } 446 447 static int dwc3_ep0_delegate_req(struct dwc3 *dwc, struct usb_ctrlrequest *ctrl) 448 { 449 int ret; 450 451 spin_unlock(&dwc->lock); 452 ret = dwc->gadget_driver->setup(&dwc->gadget, ctrl); 453 spin_lock(&dwc->lock); 454 return ret; 455 } 456 457 static int dwc3_ep0_set_config(struct dwc3 *dwc, struct usb_ctrlrequest *ctrl) 458 { 459 u32 cfg; 460 int ret; 461 462 dwc->start_config_issued = false; 463 cfg = le16_to_cpu(ctrl->wValue); 464 465 switch (dwc->dev_state) { 466 case DWC3_DEFAULT_STATE: 467 return -EINVAL; 468 break; 469 470 case DWC3_ADDRESS_STATE: 471 ret = dwc3_ep0_delegate_req(dwc, ctrl); 472 /* if the cfg matches and the cfg is non zero */ 473 if (!ret && cfg) 474 dwc->dev_state = DWC3_CONFIGURED_STATE; 475 break; 476 477 case DWC3_CONFIGURED_STATE: 478 ret = dwc3_ep0_delegate_req(dwc, ctrl); 479 if (!cfg) 480 dwc->dev_state = DWC3_ADDRESS_STATE; 481 break; 482 default: 483 ret = -EINVAL; 484 } 485 return ret; 486 } 487 488 static int dwc3_ep0_std_request(struct dwc3 *dwc, struct usb_ctrlrequest *ctrl) 489 { 490 int ret; 491 492 switch (ctrl->bRequest) { 493 case USB_REQ_GET_STATUS: 494 dev_vdbg(dwc->dev, "USB_REQ_GET_STATUS\n"); 495 ret = dwc3_ep0_handle_status(dwc, ctrl); 496 break; 497 case USB_REQ_CLEAR_FEATURE: 498 dev_vdbg(dwc->dev, "USB_REQ_CLEAR_FEATURE\n"); 499 ret = dwc3_ep0_handle_feature(dwc, ctrl, 0); 500 break; 501 case USB_REQ_SET_FEATURE: 502 dev_vdbg(dwc->dev, "USB_REQ_SET_FEATURE\n"); 503 ret = dwc3_ep0_handle_feature(dwc, ctrl, 1); 504 break; 505 case USB_REQ_SET_ADDRESS: 506 dev_vdbg(dwc->dev, "USB_REQ_SET_ADDRESS\n"); 507 ret = dwc3_ep0_set_address(dwc, ctrl); 508 break; 509 case USB_REQ_SET_CONFIGURATION: 510 dev_vdbg(dwc->dev, "USB_REQ_SET_CONFIGURATION\n"); 511 ret = dwc3_ep0_set_config(dwc, ctrl); 512 break; 513 default: 514 dev_vdbg(dwc->dev, "Forwarding to gadget driver\n"); 515 ret = dwc3_ep0_delegate_req(dwc, ctrl); 516 break; 517 }; 518 519 return ret; 520 } 521 522 static void dwc3_ep0_inspect_setup(struct dwc3 *dwc, 523 const struct dwc3_event_depevt *event) 524 { 525 struct usb_ctrlrequest *ctrl = dwc->ctrl_req; 526 int ret; 527 u32 len; 528 529 if (!dwc->gadget_driver) 530 goto err; 531 532 len = le16_to_cpu(ctrl->wLength); 533 if (!len) { 534 dwc->three_stage_setup = false; 535 dwc->ep0_expect_in = false; 536 dwc->ep0_next_event = DWC3_EP0_NRDY_STATUS; 537 } else { 538 dwc->three_stage_setup = true; 539 dwc->ep0_expect_in = !!(ctrl->bRequestType & USB_DIR_IN); 540 dwc->ep0_next_event = DWC3_EP0_NRDY_DATA; 541 } 542 543 if ((ctrl->bRequestType & USB_TYPE_MASK) == USB_TYPE_STANDARD) 544 ret = dwc3_ep0_std_request(dwc, ctrl); 545 else 546 ret = dwc3_ep0_delegate_req(dwc, ctrl); 547 548 if (ret == USB_GADGET_DELAYED_STATUS) 549 dwc->delayed_status = true; 550 551 if (ret >= 0) 552 return; 553 554 err: 555 dwc3_ep0_stall_and_restart(dwc); 556 } 557 558 static void dwc3_ep0_complete_data(struct dwc3 *dwc, 559 const struct dwc3_event_depevt *event) 560 { 561 struct dwc3_request *r = NULL; 562 struct usb_request *ur; 563 struct dwc3_trb trb; 564 struct dwc3_ep *ep0; 565 u32 transferred; 566 u8 epnum; 567 568 epnum = event->endpoint_number; 569 ep0 = dwc->eps[0]; 570 571 dwc->ep0_next_event = DWC3_EP0_NRDY_STATUS; 572 573 r = next_request(&ep0->request_list); 574 ur = &r->request; 575 576 dwc3_trb_to_nat(dwc->ep0_trb, &trb); 577 578 if (dwc->ep0_bounced) { 579 580 transferred = min_t(u32, ur->length, 581 ep0->endpoint.maxpacket - trb.length); 582 memcpy(ur->buf, dwc->ep0_bounce, transferred); 583 dwc->ep0_bounced = false; 584 } else { 585 transferred = ur->length - trb.length; 586 ur->actual += transferred; 587 } 588 589 if ((epnum & 1) && ur->actual < ur->length) { 590 /* for some reason we did not get everything out */ 591 592 dwc3_ep0_stall_and_restart(dwc); 593 } else { 594 /* 595 * handle the case where we have to send a zero packet. This 596 * seems to be case when req.length > maxpacket. Could it be? 597 */ 598 if (r) 599 dwc3_gadget_giveback(ep0, r, 0); 600 } 601 } 602 603 static void dwc3_ep0_complete_req(struct dwc3 *dwc, 604 const struct dwc3_event_depevt *event) 605 { 606 struct dwc3_request *r; 607 struct dwc3_ep *dep; 608 609 dep = dwc->eps[0]; 610 611 if (!list_empty(&dep->request_list)) { 612 r = next_request(&dep->request_list); 613 614 dwc3_gadget_giveback(dep, r, 0); 615 } 616 617 dwc->ep0state = EP0_SETUP_PHASE; 618 dwc3_ep0_out_start(dwc); 619 } 620 621 static void dwc3_ep0_xfer_complete(struct dwc3 *dwc, 622 const struct dwc3_event_depevt *event) 623 { 624 struct dwc3_ep *dep = dwc->eps[event->endpoint_number]; 625 626 dep->flags &= ~DWC3_EP_BUSY; 627 dwc->setup_packet_pending = false; 628 629 switch (dwc->ep0state) { 630 case EP0_SETUP_PHASE: 631 dev_vdbg(dwc->dev, "Inspecting Setup Bytes\n"); 632 dwc3_ep0_inspect_setup(dwc, event); 633 break; 634 635 case EP0_DATA_PHASE: 636 dev_vdbg(dwc->dev, "Data Phase\n"); 637 dwc3_ep0_complete_data(dwc, event); 638 break; 639 640 case EP0_STATUS_PHASE: 641 dev_vdbg(dwc->dev, "Status Phase\n"); 642 dwc3_ep0_complete_req(dwc, event); 643 break; 644 default: 645 WARN(true, "UNKNOWN ep0state %d\n", dwc->ep0state); 646 } 647 } 648 649 static void dwc3_ep0_do_control_setup(struct dwc3 *dwc, 650 const struct dwc3_event_depevt *event) 651 { 652 dwc3_ep0_out_start(dwc); 653 } 654 655 static void dwc3_ep0_do_control_data(struct dwc3 *dwc, 656 const struct dwc3_event_depevt *event) 657 { 658 struct dwc3_ep *dep; 659 struct dwc3_request *req; 660 int ret; 661 662 dep = dwc->eps[0]; 663 664 if (list_empty(&dep->request_list)) { 665 dev_vdbg(dwc->dev, "pending request for EP0 Data phase\n"); 666 dep->flags |= DWC3_EP_PENDING_REQUEST; 667 668 if (event->endpoint_number) 669 dep->flags |= DWC3_EP0_DIR_IN; 670 return; 671 } 672 673 req = next_request(&dep->request_list); 674 req->direction = !!event->endpoint_number; 675 676 if (req->request.length == 0) { 677 ret = dwc3_ep0_start_trans(dwc, event->endpoint_number, 678 dwc->ctrl_req_addr, 0, 679 DWC3_TRBCTL_CONTROL_DATA); 680 } else if ((req->request.length % dep->endpoint.maxpacket) 681 && (event->endpoint_number == 0)) { 682 dwc3_map_buffer_to_dma(req); 683 684 WARN_ON(req->request.length > dep->endpoint.maxpacket); 685 686 dwc->ep0_bounced = true; 687 688 /* 689 * REVISIT in case request length is bigger than EP0 690 * wMaxPacketSize, we will need two chained TRBs to handle 691 * the transfer. 692 */ 693 ret = dwc3_ep0_start_trans(dwc, event->endpoint_number, 694 dwc->ep0_bounce_addr, dep->endpoint.maxpacket, 695 DWC3_TRBCTL_CONTROL_DATA); 696 } else { 697 dwc3_map_buffer_to_dma(req); 698 699 ret = dwc3_ep0_start_trans(dwc, event->endpoint_number, 700 req->request.dma, req->request.length, 701 DWC3_TRBCTL_CONTROL_DATA); 702 } 703 704 WARN_ON(ret < 0); 705 } 706 707 static int dwc3_ep0_start_control_status(struct dwc3_ep *dep) 708 { 709 struct dwc3 *dwc = dep->dwc; 710 u32 type; 711 712 type = dwc->three_stage_setup ? DWC3_TRBCTL_CONTROL_STATUS3 713 : DWC3_TRBCTL_CONTROL_STATUS2; 714 715 return dwc3_ep0_start_trans(dwc, dep->number, 716 dwc->ctrl_req_addr, 0, type); 717 } 718 719 static void dwc3_ep0_do_control_status(struct dwc3 *dwc, u32 epnum) 720 { 721 struct dwc3_ep *dep = dwc->eps[epnum]; 722 723 WARN_ON(dwc3_ep0_start_control_status(dep)); 724 } 725 726 static void dwc3_ep0_xfernotready(struct dwc3 *dwc, 727 const struct dwc3_event_depevt *event) 728 { 729 dwc->setup_packet_pending = true; 730 731 /* 732 * This part is very tricky: If we has just handled 733 * XferNotReady(Setup) and we're now expecting a 734 * XferComplete but, instead, we receive another 735 * XferNotReady(Setup), we should STALL and restart 736 * the state machine. 737 * 738 * In all other cases, we just continue waiting 739 * for the XferComplete event. 740 * 741 * We are a little bit unsafe here because we're 742 * not trying to ensure that last event was, indeed, 743 * XferNotReady(Setup). 744 * 745 * Still, we don't expect any condition where that 746 * should happen and, even if it does, it would be 747 * another error condition. 748 */ 749 if (dwc->ep0_next_event == DWC3_EP0_COMPLETE) { 750 switch (event->status) { 751 case DEPEVT_STATUS_CONTROL_SETUP: 752 dev_vdbg(dwc->dev, "Unexpected XferNotReady(Setup)\n"); 753 dwc3_ep0_stall_and_restart(dwc); 754 break; 755 case DEPEVT_STATUS_CONTROL_DATA: 756 /* FALLTHROUGH */ 757 case DEPEVT_STATUS_CONTROL_STATUS: 758 /* FALLTHROUGH */ 759 default: 760 dev_vdbg(dwc->dev, "waiting for XferComplete\n"); 761 } 762 763 return; 764 } 765 766 switch (event->status) { 767 case DEPEVT_STATUS_CONTROL_SETUP: 768 dev_vdbg(dwc->dev, "Control Setup\n"); 769 770 dwc->ep0state = EP0_SETUP_PHASE; 771 772 dwc3_ep0_do_control_setup(dwc, event); 773 break; 774 775 case DEPEVT_STATUS_CONTROL_DATA: 776 dev_vdbg(dwc->dev, "Control Data\n"); 777 778 dwc->ep0state = EP0_DATA_PHASE; 779 780 if (dwc->ep0_next_event != DWC3_EP0_NRDY_DATA) { 781 dev_vdbg(dwc->dev, "Expected %d got %d\n", 782 dwc->ep0_next_event, 783 DWC3_EP0_NRDY_DATA); 784 785 dwc3_ep0_stall_and_restart(dwc); 786 return; 787 } 788 789 /* 790 * One of the possible error cases is when Host _does_ 791 * request for Data Phase, but it does so on the wrong 792 * direction. 793 * 794 * Here, we already know ep0_next_event is DATA (see above), 795 * so we only need to check for direction. 796 */ 797 if (dwc->ep0_expect_in != event->endpoint_number) { 798 dev_vdbg(dwc->dev, "Wrong direction for Data phase\n"); 799 dwc3_ep0_stall_and_restart(dwc); 800 return; 801 } 802 803 dwc3_ep0_do_control_data(dwc, event); 804 break; 805 806 case DEPEVT_STATUS_CONTROL_STATUS: 807 dev_vdbg(dwc->dev, "Control Status\n"); 808 809 dwc->ep0state = EP0_STATUS_PHASE; 810 811 if (dwc->ep0_next_event != DWC3_EP0_NRDY_STATUS) { 812 dev_vdbg(dwc->dev, "Expected %d got %d\n", 813 dwc->ep0_next_event, 814 DWC3_EP0_NRDY_STATUS); 815 816 dwc3_ep0_stall_and_restart(dwc); 817 return; 818 } 819 820 if (dwc->delayed_status) { 821 WARN_ON_ONCE(event->endpoint_number != 1); 822 dev_vdbg(dwc->dev, "Mass Storage delayed status\n"); 823 return; 824 } 825 826 dwc3_ep0_do_control_status(dwc, event->endpoint_number); 827 } 828 } 829 830 void dwc3_ep0_interrupt(struct dwc3 *dwc, 831 const struct dwc3_event_depevt *event) 832 { 833 u8 epnum = event->endpoint_number; 834 835 dev_dbg(dwc->dev, "%s while ep%d%s in state '%s'\n", 836 dwc3_ep_event_string(event->endpoint_event), 837 epnum >> 1, (epnum & 1) ? "in" : "out", 838 dwc3_ep0_state_string(dwc->ep0state)); 839 840 switch (event->endpoint_event) { 841 case DWC3_DEPEVT_XFERCOMPLETE: 842 dwc3_ep0_xfer_complete(dwc, event); 843 break; 844 845 case DWC3_DEPEVT_XFERNOTREADY: 846 dwc3_ep0_xfernotready(dwc, event); 847 break; 848 849 case DWC3_DEPEVT_XFERINPROGRESS: 850 case DWC3_DEPEVT_RXTXFIFOEVT: 851 case DWC3_DEPEVT_STREAMEVT: 852 case DWC3_DEPEVT_EPCMDCMPLT: 853 break; 854 } 855 } 856