1 // SPDX-License-Identifier: GPL-2.0 2 /* 3 * ep0.c - DesignWare USB3 DRD Controller Endpoint 0 Handling 4 * 5 * Copyright (C) 2010-2011 Texas Instruments Incorporated - https://www.ti.com 6 * 7 * Authors: Felipe Balbi <balbi@ti.com>, 8 * Sebastian Andrzej Siewior <bigeasy@linutronix.de> 9 */ 10 11 #include <linux/kernel.h> 12 #include <linux/slab.h> 13 #include <linux/spinlock.h> 14 #include <linux/platform_device.h> 15 #include <linux/pm_runtime.h> 16 #include <linux/interrupt.h> 17 #include <linux/io.h> 18 #include <linux/list.h> 19 #include <linux/dma-mapping.h> 20 21 #include <linux/usb/ch9.h> 22 #include <linux/usb/gadget.h> 23 #include <linux/usb/composite.h> 24 25 #include "core.h" 26 #include "debug.h" 27 #include "gadget.h" 28 #include "io.h" 29 30 static void __dwc3_ep0_do_control_status(struct dwc3 *dwc, struct dwc3_ep *dep); 31 static void __dwc3_ep0_do_control_data(struct dwc3 *dwc, 32 struct dwc3_ep *dep, struct dwc3_request *req); 33 static int dwc3_ep0_delegate_req(struct dwc3 *dwc, 34 struct usb_ctrlrequest *ctrl); 35 36 static void dwc3_ep0_prepare_one_trb(struct dwc3_ep *dep, 37 dma_addr_t buf_dma, u32 len, u32 type, bool chain) 38 { 39 struct dwc3_trb *trb; 40 struct dwc3 *dwc; 41 42 dwc = dep->dwc; 43 trb = &dwc->ep0_trb[dep->trb_enqueue]; 44 45 if (chain) 46 dep->trb_enqueue++; 47 48 trb->bpl = lower_32_bits(buf_dma); 49 trb->bph = upper_32_bits(buf_dma); 50 trb->size = len; 51 trb->ctrl = type; 52 53 trb->ctrl |= (DWC3_TRB_CTRL_HWO 54 | DWC3_TRB_CTRL_ISP_IMI); 55 56 if (chain) 57 trb->ctrl |= DWC3_TRB_CTRL_CHN; 58 else 59 trb->ctrl |= (DWC3_TRB_CTRL_IOC 60 | DWC3_TRB_CTRL_LST); 61 62 trace_dwc3_prepare_trb(dep, trb); 63 } 64 65 static int dwc3_ep0_start_trans(struct dwc3_ep *dep) 66 { 67 struct dwc3_gadget_ep_cmd_params params; 68 struct dwc3 *dwc; 69 int ret; 70 71 if (dep->flags & DWC3_EP_TRANSFER_STARTED) 72 return 0; 73 74 dwc = dep->dwc; 75 76 memset(¶ms, 0, sizeof(params)); 77 params.param0 = upper_32_bits(dwc->ep0_trb_addr); 78 params.param1 = lower_32_bits(dwc->ep0_trb_addr); 79 80 ret = dwc3_send_gadget_ep_cmd(dep, DWC3_DEPCMD_STARTTRANSFER, ¶ms); 81 if (ret < 0) 82 return ret; 83 84 dwc->ep0_next_event = DWC3_EP0_COMPLETE; 85 86 return 0; 87 } 88 89 static int __dwc3_gadget_ep0_queue(struct dwc3_ep *dep, 90 struct dwc3_request *req) 91 { 92 struct dwc3 *dwc = dep->dwc; 93 94 req->request.actual = 0; 95 req->request.status = -EINPROGRESS; 96 req->epnum = dep->number; 97 98 list_add_tail(&req->list, &dep->pending_list); 99 100 /* 101 * Gadget driver might not be quick enough to queue a request 102 * before we get a Transfer Not Ready event on this endpoint. 103 * 104 * In that case, we will set DWC3_EP_PENDING_REQUEST. When that 105 * flag is set, it's telling us that as soon as Gadget queues the 106 * required request, we should kick the transfer here because the 107 * IRQ we were waiting for is long gone. 108 */ 109 if (dep->flags & DWC3_EP_PENDING_REQUEST) { 110 unsigned int direction; 111 112 direction = !!(dep->flags & DWC3_EP0_DIR_IN); 113 114 if (dwc->ep0state != EP0_DATA_PHASE) { 115 dev_WARN(dwc->dev, "Unexpected pending request\n"); 116 return 0; 117 } 118 119 __dwc3_ep0_do_control_data(dwc, dwc->eps[direction], req); 120 121 dep->flags &= ~(DWC3_EP_PENDING_REQUEST | 122 DWC3_EP0_DIR_IN); 123 124 return 0; 125 } 126 127 /* 128 * In case gadget driver asked us to delay the STATUS phase, 129 * handle it here. 130 */ 131 if (dwc->delayed_status) { 132 unsigned int direction; 133 134 direction = !dwc->ep0_expect_in; 135 dwc->delayed_status = false; 136 usb_gadget_set_state(dwc->gadget, USB_STATE_CONFIGURED); 137 138 if (dwc->ep0state == EP0_STATUS_PHASE) 139 __dwc3_ep0_do_control_status(dwc, dwc->eps[direction]); 140 141 return 0; 142 } 143 144 /* 145 * Unfortunately we have uncovered a limitation wrt the Data Phase. 146 * 147 * Section 9.4 says we can wait for the XferNotReady(DATA) event to 148 * come before issueing Start Transfer command, but if we do, we will 149 * miss situations where the host starts another SETUP phase instead of 150 * the DATA phase. Such cases happen at least on TD.7.6 of the Link 151 * Layer Compliance Suite. 152 * 153 * The problem surfaces due to the fact that in case of back-to-back 154 * SETUP packets there will be no XferNotReady(DATA) generated and we 155 * will be stuck waiting for XferNotReady(DATA) forever. 156 * 157 * By looking at tables 9-13 and 9-14 of the Databook, we can see that 158 * it tells us to start Data Phase right away. It also mentions that if 159 * we receive a SETUP phase instead of the DATA phase, core will issue 160 * XferComplete for the DATA phase, before actually initiating it in 161 * the wire, with the TRB's status set to "SETUP_PENDING". Such status 162 * can only be used to print some debugging logs, as the core expects 163 * us to go through to the STATUS phase and start a CONTROL_STATUS TRB, 164 * just so it completes right away, without transferring anything and, 165 * only then, we can go back to the SETUP phase. 166 * 167 * Because of this scenario, SNPS decided to change the programming 168 * model of control transfers and support on-demand transfers only for 169 * the STATUS phase. To fix the issue we have now, we will always wait 170 * for gadget driver to queue the DATA phase's struct usb_request, then 171 * start it right away. 172 * 173 * If we're actually in a 2-stage transfer, we will wait for 174 * XferNotReady(STATUS). 175 */ 176 if (dwc->three_stage_setup) { 177 unsigned int direction; 178 179 direction = dwc->ep0_expect_in; 180 dwc->ep0state = EP0_DATA_PHASE; 181 182 __dwc3_ep0_do_control_data(dwc, dwc->eps[direction], req); 183 184 dep->flags &= ~DWC3_EP0_DIR_IN; 185 } 186 187 return 0; 188 } 189 190 int dwc3_gadget_ep0_queue(struct usb_ep *ep, struct usb_request *request, 191 gfp_t gfp_flags) 192 { 193 struct dwc3_request *req = to_dwc3_request(request); 194 struct dwc3_ep *dep = to_dwc3_ep(ep); 195 struct dwc3 *dwc = dep->dwc; 196 197 unsigned long flags; 198 199 int ret; 200 201 spin_lock_irqsave(&dwc->lock, flags); 202 if (!dep->endpoint.desc || !dwc->pullups_connected || !dwc->connected) { 203 dev_err(dwc->dev, "%s: can't queue to disabled endpoint\n", 204 dep->name); 205 ret = -ESHUTDOWN; 206 goto out; 207 } 208 209 /* we share one TRB for ep0/1 */ 210 if (!list_empty(&dep->pending_list)) { 211 ret = -EBUSY; 212 goto out; 213 } 214 215 ret = __dwc3_gadget_ep0_queue(dep, req); 216 217 out: 218 spin_unlock_irqrestore(&dwc->lock, flags); 219 220 return ret; 221 } 222 223 void dwc3_ep0_stall_and_restart(struct dwc3 *dwc) 224 { 225 struct dwc3_ep *dep; 226 227 /* reinitialize physical ep1 */ 228 dep = dwc->eps[1]; 229 dep->flags = DWC3_EP_ENABLED; 230 231 /* stall is always issued on EP0 */ 232 dep = dwc->eps[0]; 233 __dwc3_gadget_ep_set_halt(dep, 1, false); 234 dep->flags = DWC3_EP_ENABLED; 235 dwc->delayed_status = false; 236 237 if (!list_empty(&dep->pending_list)) { 238 struct dwc3_request *req; 239 240 req = next_request(&dep->pending_list); 241 if (!dwc->connected) 242 dwc3_gadget_giveback(dep, req, -ESHUTDOWN); 243 else 244 dwc3_gadget_giveback(dep, req, -ECONNRESET); 245 } 246 247 dwc->eps[0]->trb_enqueue = 0; 248 dwc->eps[1]->trb_enqueue = 0; 249 dwc->ep0state = EP0_SETUP_PHASE; 250 dwc3_ep0_out_start(dwc); 251 } 252 253 int __dwc3_gadget_ep0_set_halt(struct usb_ep *ep, int value) 254 { 255 struct dwc3_ep *dep = to_dwc3_ep(ep); 256 struct dwc3 *dwc = dep->dwc; 257 258 dwc3_ep0_stall_and_restart(dwc); 259 260 return 0; 261 } 262 263 int dwc3_gadget_ep0_set_halt(struct usb_ep *ep, int value) 264 { 265 struct dwc3_ep *dep = to_dwc3_ep(ep); 266 struct dwc3 *dwc = dep->dwc; 267 unsigned long flags; 268 int ret; 269 270 spin_lock_irqsave(&dwc->lock, flags); 271 ret = __dwc3_gadget_ep0_set_halt(ep, value); 272 spin_unlock_irqrestore(&dwc->lock, flags); 273 274 return ret; 275 } 276 277 void dwc3_ep0_out_start(struct dwc3 *dwc) 278 { 279 struct dwc3_ep *dep; 280 int ret; 281 int i; 282 283 complete(&dwc->ep0_in_setup); 284 285 dep = dwc->eps[0]; 286 dwc3_ep0_prepare_one_trb(dep, dwc->ep0_trb_addr, 8, 287 DWC3_TRBCTL_CONTROL_SETUP, false); 288 ret = dwc3_ep0_start_trans(dep); 289 WARN_ON(ret < 0); 290 for (i = 2; i < DWC3_ENDPOINTS_NUM; i++) { 291 struct dwc3_ep *dwc3_ep; 292 293 dwc3_ep = dwc->eps[i]; 294 if (!dwc3_ep) 295 continue; 296 297 if (!(dwc3_ep->flags & DWC3_EP_DELAY_STOP)) 298 continue; 299 300 dwc3_ep->flags &= ~DWC3_EP_DELAY_STOP; 301 if (dwc->connected) 302 dwc3_stop_active_transfer(dwc3_ep, true, true); 303 else 304 dwc3_remove_requests(dwc, dwc3_ep, -ESHUTDOWN); 305 } 306 } 307 308 static struct dwc3_ep *dwc3_wIndex_to_dep(struct dwc3 *dwc, __le16 wIndex_le) 309 { 310 struct dwc3_ep *dep; 311 u32 windex = le16_to_cpu(wIndex_le); 312 u32 epnum; 313 314 epnum = (windex & USB_ENDPOINT_NUMBER_MASK) << 1; 315 if ((windex & USB_ENDPOINT_DIR_MASK) == USB_DIR_IN) 316 epnum |= 1; 317 318 dep = dwc->eps[epnum]; 319 if (dep == NULL) 320 return NULL; 321 322 if (dep->flags & DWC3_EP_ENABLED) 323 return dep; 324 325 return NULL; 326 } 327 328 static void dwc3_ep0_status_cmpl(struct usb_ep *ep, struct usb_request *req) 329 { 330 } 331 /* 332 * ch 9.4.5 333 */ 334 static int dwc3_ep0_handle_status(struct dwc3 *dwc, 335 struct usb_ctrlrequest *ctrl) 336 { 337 struct dwc3_ep *dep; 338 u32 recip; 339 u32 value; 340 u32 reg; 341 u16 usb_status = 0; 342 __le16 *response_pkt; 343 344 /* We don't support PTM_STATUS */ 345 value = le16_to_cpu(ctrl->wValue); 346 if (value != 0) 347 return -EINVAL; 348 349 recip = ctrl->bRequestType & USB_RECIP_MASK; 350 switch (recip) { 351 case USB_RECIP_DEVICE: 352 /* 353 * LTM will be set once we know how to set this in HW. 354 */ 355 usb_status |= dwc->gadget->is_selfpowered; 356 357 if ((dwc->speed == DWC3_DSTS_SUPERSPEED) || 358 (dwc->speed == DWC3_DSTS_SUPERSPEED_PLUS)) { 359 reg = dwc3_readl(dwc->regs, DWC3_DCTL); 360 if (reg & DWC3_DCTL_INITU1ENA) 361 usb_status |= 1 << USB_DEV_STAT_U1_ENABLED; 362 if (reg & DWC3_DCTL_INITU2ENA) 363 usb_status |= 1 << USB_DEV_STAT_U2_ENABLED; 364 } else { 365 usb_status |= dwc->gadget->wakeup_armed << 366 USB_DEVICE_REMOTE_WAKEUP; 367 } 368 369 break; 370 371 case USB_RECIP_INTERFACE: 372 /* 373 * Function Remote Wake Capable D0 374 * Function Remote Wakeup D1 375 */ 376 return dwc3_ep0_delegate_req(dwc, ctrl); 377 378 case USB_RECIP_ENDPOINT: 379 dep = dwc3_wIndex_to_dep(dwc, ctrl->wIndex); 380 if (!dep) 381 return -EINVAL; 382 383 if (dep->flags & DWC3_EP_STALL) 384 usb_status = 1 << USB_ENDPOINT_HALT; 385 break; 386 default: 387 return -EINVAL; 388 } 389 390 response_pkt = (__le16 *) dwc->setup_buf; 391 *response_pkt = cpu_to_le16(usb_status); 392 393 dep = dwc->eps[0]; 394 dwc->ep0_usb_req.dep = dep; 395 dwc->ep0_usb_req.request.length = sizeof(*response_pkt); 396 dwc->ep0_usb_req.request.buf = dwc->setup_buf; 397 dwc->ep0_usb_req.request.complete = dwc3_ep0_status_cmpl; 398 399 return __dwc3_gadget_ep0_queue(dep, &dwc->ep0_usb_req); 400 } 401 402 static int dwc3_ep0_handle_u1(struct dwc3 *dwc, enum usb_device_state state, 403 int set) 404 { 405 u32 reg; 406 407 if (state != USB_STATE_CONFIGURED) 408 return -EINVAL; 409 if ((dwc->speed != DWC3_DSTS_SUPERSPEED) && 410 (dwc->speed != DWC3_DSTS_SUPERSPEED_PLUS)) 411 return -EINVAL; 412 if (set && dwc->dis_u1_entry_quirk) 413 return -EINVAL; 414 415 reg = dwc3_readl(dwc->regs, DWC3_DCTL); 416 if (set) 417 reg |= DWC3_DCTL_INITU1ENA; 418 else 419 reg &= ~DWC3_DCTL_INITU1ENA; 420 dwc3_writel(dwc->regs, DWC3_DCTL, reg); 421 422 return 0; 423 } 424 425 static int dwc3_ep0_handle_u2(struct dwc3 *dwc, enum usb_device_state state, 426 int set) 427 { 428 u32 reg; 429 430 431 if (state != USB_STATE_CONFIGURED) 432 return -EINVAL; 433 if ((dwc->speed != DWC3_DSTS_SUPERSPEED) && 434 (dwc->speed != DWC3_DSTS_SUPERSPEED_PLUS)) 435 return -EINVAL; 436 if (set && dwc->dis_u2_entry_quirk) 437 return -EINVAL; 438 439 reg = dwc3_readl(dwc->regs, DWC3_DCTL); 440 if (set) 441 reg |= DWC3_DCTL_INITU2ENA; 442 else 443 reg &= ~DWC3_DCTL_INITU2ENA; 444 dwc3_writel(dwc->regs, DWC3_DCTL, reg); 445 446 return 0; 447 } 448 449 static int dwc3_ep0_handle_test(struct dwc3 *dwc, enum usb_device_state state, 450 u32 wIndex, int set) 451 { 452 if ((wIndex & 0xff) != 0) 453 return -EINVAL; 454 if (!set) 455 return -EINVAL; 456 457 switch (wIndex >> 8) { 458 case USB_TEST_J: 459 case USB_TEST_K: 460 case USB_TEST_SE0_NAK: 461 case USB_TEST_PACKET: 462 case USB_TEST_FORCE_ENABLE: 463 dwc->test_mode_nr = wIndex >> 8; 464 dwc->test_mode = true; 465 break; 466 default: 467 return -EINVAL; 468 } 469 470 return 0; 471 } 472 473 static int dwc3_ep0_handle_device(struct dwc3 *dwc, 474 struct usb_ctrlrequest *ctrl, int set) 475 { 476 enum usb_device_state state; 477 u32 wValue; 478 u32 wIndex; 479 int ret = 0; 480 481 wValue = le16_to_cpu(ctrl->wValue); 482 wIndex = le16_to_cpu(ctrl->wIndex); 483 state = dwc->gadget->state; 484 485 switch (wValue) { 486 case USB_DEVICE_REMOTE_WAKEUP: 487 if (dwc->wakeup_configured) 488 dwc->gadget->wakeup_armed = set; 489 else 490 ret = -EINVAL; 491 break; 492 /* 493 * 9.4.1 says only for SS, in AddressState only for 494 * default control pipe 495 */ 496 case USB_DEVICE_U1_ENABLE: 497 ret = dwc3_ep0_handle_u1(dwc, state, set); 498 break; 499 case USB_DEVICE_U2_ENABLE: 500 ret = dwc3_ep0_handle_u2(dwc, state, set); 501 break; 502 case USB_DEVICE_LTM_ENABLE: 503 ret = -EINVAL; 504 break; 505 case USB_DEVICE_TEST_MODE: 506 ret = dwc3_ep0_handle_test(dwc, state, wIndex, set); 507 break; 508 default: 509 ret = -EINVAL; 510 } 511 512 return ret; 513 } 514 515 static int dwc3_ep0_handle_intf(struct dwc3 *dwc, 516 struct usb_ctrlrequest *ctrl, int set) 517 { 518 u32 wValue; 519 int ret = 0; 520 521 wValue = le16_to_cpu(ctrl->wValue); 522 523 switch (wValue) { 524 case USB_INTRF_FUNC_SUSPEND: 525 ret = dwc3_ep0_delegate_req(dwc, ctrl); 526 break; 527 default: 528 ret = -EINVAL; 529 } 530 531 return ret; 532 } 533 534 static int dwc3_ep0_handle_endpoint(struct dwc3 *dwc, 535 struct usb_ctrlrequest *ctrl, int set) 536 { 537 struct dwc3_ep *dep; 538 u32 wValue; 539 int ret; 540 541 wValue = le16_to_cpu(ctrl->wValue); 542 543 switch (wValue) { 544 case USB_ENDPOINT_HALT: 545 dep = dwc3_wIndex_to_dep(dwc, ctrl->wIndex); 546 if (!dep) 547 return -EINVAL; 548 549 if (set == 0 && (dep->flags & DWC3_EP_WEDGE)) 550 break; 551 552 ret = __dwc3_gadget_ep_set_halt(dep, set, true); 553 if (ret) 554 return -EINVAL; 555 556 /* ClearFeature(Halt) may need delayed status */ 557 if (!set && (dep->flags & DWC3_EP_END_TRANSFER_PENDING)) 558 return USB_GADGET_DELAYED_STATUS; 559 560 break; 561 default: 562 return -EINVAL; 563 } 564 565 return 0; 566 } 567 568 static int dwc3_ep0_handle_feature(struct dwc3 *dwc, 569 struct usb_ctrlrequest *ctrl, int set) 570 { 571 u32 recip; 572 int ret; 573 574 recip = ctrl->bRequestType & USB_RECIP_MASK; 575 576 switch (recip) { 577 case USB_RECIP_DEVICE: 578 ret = dwc3_ep0_handle_device(dwc, ctrl, set); 579 break; 580 case USB_RECIP_INTERFACE: 581 ret = dwc3_ep0_handle_intf(dwc, ctrl, set); 582 break; 583 case USB_RECIP_ENDPOINT: 584 ret = dwc3_ep0_handle_endpoint(dwc, ctrl, set); 585 break; 586 default: 587 ret = -EINVAL; 588 } 589 590 return ret; 591 } 592 593 static int dwc3_ep0_set_address(struct dwc3 *dwc, struct usb_ctrlrequest *ctrl) 594 { 595 enum usb_device_state state = dwc->gadget->state; 596 u32 addr; 597 u32 reg; 598 599 addr = le16_to_cpu(ctrl->wValue); 600 if (addr > 127) { 601 dev_err(dwc->dev, "invalid device address %d\n", addr); 602 return -EINVAL; 603 } 604 605 if (state == USB_STATE_CONFIGURED) { 606 dev_err(dwc->dev, "can't SetAddress() from Configured State\n"); 607 return -EINVAL; 608 } 609 610 reg = dwc3_readl(dwc->regs, DWC3_DCFG); 611 reg &= ~(DWC3_DCFG_DEVADDR_MASK); 612 reg |= DWC3_DCFG_DEVADDR(addr); 613 dwc3_writel(dwc->regs, DWC3_DCFG, reg); 614 615 if (addr) 616 usb_gadget_set_state(dwc->gadget, USB_STATE_ADDRESS); 617 else 618 usb_gadget_set_state(dwc->gadget, USB_STATE_DEFAULT); 619 620 return 0; 621 } 622 623 static int dwc3_ep0_delegate_req(struct dwc3 *dwc, struct usb_ctrlrequest *ctrl) 624 { 625 int ret = -EINVAL; 626 627 if (dwc->async_callbacks) { 628 spin_unlock(&dwc->lock); 629 ret = dwc->gadget_driver->setup(dwc->gadget, ctrl); 630 spin_lock(&dwc->lock); 631 } 632 return ret; 633 } 634 635 static int dwc3_ep0_set_config(struct dwc3 *dwc, struct usb_ctrlrequest *ctrl) 636 { 637 enum usb_device_state state = dwc->gadget->state; 638 u32 cfg; 639 int ret; 640 u32 reg; 641 642 cfg = le16_to_cpu(ctrl->wValue); 643 644 switch (state) { 645 case USB_STATE_DEFAULT: 646 return -EINVAL; 647 648 case USB_STATE_ADDRESS: 649 dwc3_gadget_clear_tx_fifos(dwc); 650 651 ret = dwc3_ep0_delegate_req(dwc, ctrl); 652 /* if the cfg matches and the cfg is non zero */ 653 if (cfg && (!ret || (ret == USB_GADGET_DELAYED_STATUS))) { 654 655 /* 656 * only change state if set_config has already 657 * been processed. If gadget driver returns 658 * USB_GADGET_DELAYED_STATUS, we will wait 659 * to change the state on the next usb_ep_queue() 660 */ 661 if (ret == 0) 662 usb_gadget_set_state(dwc->gadget, 663 USB_STATE_CONFIGURED); 664 665 /* 666 * Enable transition to U1/U2 state when 667 * nothing is pending from application. 668 */ 669 reg = dwc3_readl(dwc->regs, DWC3_DCTL); 670 if (!dwc->dis_u1_entry_quirk) 671 reg |= DWC3_DCTL_ACCEPTU1ENA; 672 if (!dwc->dis_u2_entry_quirk) 673 reg |= DWC3_DCTL_ACCEPTU2ENA; 674 dwc3_writel(dwc->regs, DWC3_DCTL, reg); 675 } 676 break; 677 678 case USB_STATE_CONFIGURED: 679 ret = dwc3_ep0_delegate_req(dwc, ctrl); 680 if (!cfg && !ret) 681 usb_gadget_set_state(dwc->gadget, 682 USB_STATE_ADDRESS); 683 break; 684 default: 685 ret = -EINVAL; 686 } 687 return ret; 688 } 689 690 static void dwc3_ep0_set_sel_cmpl(struct usb_ep *ep, struct usb_request *req) 691 { 692 struct dwc3_ep *dep = to_dwc3_ep(ep); 693 struct dwc3 *dwc = dep->dwc; 694 695 u32 param = 0; 696 u32 reg; 697 698 struct timing { 699 u8 u1sel; 700 u8 u1pel; 701 __le16 u2sel; 702 __le16 u2pel; 703 } __packed timing; 704 705 int ret; 706 707 memcpy(&timing, req->buf, sizeof(timing)); 708 709 dwc->u1sel = timing.u1sel; 710 dwc->u1pel = timing.u1pel; 711 dwc->u2sel = le16_to_cpu(timing.u2sel); 712 dwc->u2pel = le16_to_cpu(timing.u2pel); 713 714 reg = dwc3_readl(dwc->regs, DWC3_DCTL); 715 if (reg & DWC3_DCTL_INITU2ENA) 716 param = dwc->u2pel; 717 if (reg & DWC3_DCTL_INITU1ENA) 718 param = dwc->u1pel; 719 720 /* 721 * According to Synopsys Databook, if parameter is 722 * greater than 125, a value of zero should be 723 * programmed in the register. 724 */ 725 if (param > 125) 726 param = 0; 727 728 /* now that we have the time, issue DGCMD Set Sel */ 729 ret = dwc3_send_gadget_generic_command(dwc, 730 DWC3_DGCMD_SET_PERIODIC_PAR, param); 731 WARN_ON(ret < 0); 732 } 733 734 static int dwc3_ep0_set_sel(struct dwc3 *dwc, struct usb_ctrlrequest *ctrl) 735 { 736 struct dwc3_ep *dep; 737 enum usb_device_state state = dwc->gadget->state; 738 u16 wLength; 739 740 if (state == USB_STATE_DEFAULT) 741 return -EINVAL; 742 743 wLength = le16_to_cpu(ctrl->wLength); 744 745 if (wLength != 6) { 746 dev_err(dwc->dev, "Set SEL should be 6 bytes, got %d\n", 747 wLength); 748 return -EINVAL; 749 } 750 751 /* 752 * To handle Set SEL we need to receive 6 bytes from Host. So let's 753 * queue a usb_request for 6 bytes. 754 * 755 * Remember, though, this controller can't handle non-wMaxPacketSize 756 * aligned transfers on the OUT direction, so we queue a request for 757 * wMaxPacketSize instead. 758 */ 759 dep = dwc->eps[0]; 760 dwc->ep0_usb_req.dep = dep; 761 dwc->ep0_usb_req.request.length = dep->endpoint.maxpacket; 762 dwc->ep0_usb_req.request.buf = dwc->setup_buf; 763 dwc->ep0_usb_req.request.complete = dwc3_ep0_set_sel_cmpl; 764 765 return __dwc3_gadget_ep0_queue(dep, &dwc->ep0_usb_req); 766 } 767 768 static int dwc3_ep0_set_isoch_delay(struct dwc3 *dwc, struct usb_ctrlrequest *ctrl) 769 { 770 u16 wLength; 771 u16 wValue; 772 u16 wIndex; 773 774 wValue = le16_to_cpu(ctrl->wValue); 775 wLength = le16_to_cpu(ctrl->wLength); 776 wIndex = le16_to_cpu(ctrl->wIndex); 777 778 if (wIndex || wLength) 779 return -EINVAL; 780 781 dwc->gadget->isoch_delay = wValue; 782 783 return 0; 784 } 785 786 static int dwc3_ep0_std_request(struct dwc3 *dwc, struct usb_ctrlrequest *ctrl) 787 { 788 int ret; 789 790 switch (ctrl->bRequest) { 791 case USB_REQ_GET_STATUS: 792 ret = dwc3_ep0_handle_status(dwc, ctrl); 793 break; 794 case USB_REQ_CLEAR_FEATURE: 795 ret = dwc3_ep0_handle_feature(dwc, ctrl, 0); 796 break; 797 case USB_REQ_SET_FEATURE: 798 ret = dwc3_ep0_handle_feature(dwc, ctrl, 1); 799 break; 800 case USB_REQ_SET_ADDRESS: 801 ret = dwc3_ep0_set_address(dwc, ctrl); 802 break; 803 case USB_REQ_SET_CONFIGURATION: 804 ret = dwc3_ep0_set_config(dwc, ctrl); 805 break; 806 case USB_REQ_SET_SEL: 807 ret = dwc3_ep0_set_sel(dwc, ctrl); 808 break; 809 case USB_REQ_SET_ISOCH_DELAY: 810 ret = dwc3_ep0_set_isoch_delay(dwc, ctrl); 811 break; 812 default: 813 ret = dwc3_ep0_delegate_req(dwc, ctrl); 814 break; 815 } 816 817 return ret; 818 } 819 820 static void dwc3_ep0_inspect_setup(struct dwc3 *dwc, 821 const struct dwc3_event_depevt *event) 822 { 823 struct usb_ctrlrequest *ctrl = (void *) dwc->ep0_trb; 824 int ret = -EINVAL; 825 u32 len; 826 827 if (!dwc->gadget_driver || !dwc->softconnect || !dwc->connected) 828 goto out; 829 830 trace_dwc3_ctrl_req(ctrl); 831 832 len = le16_to_cpu(ctrl->wLength); 833 if (!len) { 834 dwc->three_stage_setup = false; 835 dwc->ep0_expect_in = false; 836 dwc->ep0_next_event = DWC3_EP0_NRDY_STATUS; 837 } else { 838 dwc->three_stage_setup = true; 839 dwc->ep0_expect_in = !!(ctrl->bRequestType & USB_DIR_IN); 840 dwc->ep0_next_event = DWC3_EP0_NRDY_DATA; 841 } 842 843 if ((ctrl->bRequestType & USB_TYPE_MASK) == USB_TYPE_STANDARD) 844 ret = dwc3_ep0_std_request(dwc, ctrl); 845 else 846 ret = dwc3_ep0_delegate_req(dwc, ctrl); 847 848 if (ret == USB_GADGET_DELAYED_STATUS) 849 dwc->delayed_status = true; 850 851 out: 852 if (ret < 0) 853 dwc3_ep0_stall_and_restart(dwc); 854 } 855 856 static void dwc3_ep0_complete_data(struct dwc3 *dwc, 857 const struct dwc3_event_depevt *event) 858 { 859 struct dwc3_request *r; 860 struct usb_request *ur; 861 struct dwc3_trb *trb; 862 struct dwc3_ep *ep0; 863 u32 transferred = 0; 864 u32 status; 865 u32 length; 866 u8 epnum; 867 868 epnum = event->endpoint_number; 869 ep0 = dwc->eps[0]; 870 871 dwc->ep0_next_event = DWC3_EP0_NRDY_STATUS; 872 trb = dwc->ep0_trb; 873 trace_dwc3_complete_trb(ep0, trb); 874 875 r = next_request(&ep0->pending_list); 876 if (!r) 877 return; 878 879 status = DWC3_TRB_SIZE_TRBSTS(trb->size); 880 if (status == DWC3_TRBSTS_SETUP_PENDING) { 881 dwc->setup_packet_pending = true; 882 if (r) 883 dwc3_gadget_giveback(ep0, r, -ECONNRESET); 884 885 return; 886 } 887 888 ur = &r->request; 889 890 length = trb->size & DWC3_TRB_SIZE_MASK; 891 transferred = ur->length - length; 892 ur->actual += transferred; 893 894 if ((IS_ALIGNED(ur->length, ep0->endpoint.maxpacket) && 895 ur->length && ur->zero) || dwc->ep0_bounced) { 896 trb++; 897 trb->ctrl &= ~DWC3_TRB_CTRL_HWO; 898 trace_dwc3_complete_trb(ep0, trb); 899 900 if (r->direction) 901 dwc->eps[1]->trb_enqueue = 0; 902 else 903 dwc->eps[0]->trb_enqueue = 0; 904 905 dwc->ep0_bounced = false; 906 } 907 908 if ((epnum & 1) && ur->actual < ur->length) 909 dwc3_ep0_stall_and_restart(dwc); 910 else 911 dwc3_gadget_giveback(ep0, r, 0); 912 } 913 914 static void dwc3_ep0_complete_status(struct dwc3 *dwc, 915 const struct dwc3_event_depevt *event) 916 { 917 struct dwc3_request *r; 918 struct dwc3_ep *dep; 919 struct dwc3_trb *trb; 920 u32 status; 921 922 dep = dwc->eps[0]; 923 trb = dwc->ep0_trb; 924 925 trace_dwc3_complete_trb(dep, trb); 926 927 if (!list_empty(&dep->pending_list)) { 928 r = next_request(&dep->pending_list); 929 930 dwc3_gadget_giveback(dep, r, 0); 931 } 932 933 if (dwc->test_mode) { 934 int ret; 935 936 ret = dwc3_gadget_set_test_mode(dwc, dwc->test_mode_nr); 937 if (ret < 0) { 938 dev_err(dwc->dev, "invalid test #%d\n", 939 dwc->test_mode_nr); 940 dwc3_ep0_stall_and_restart(dwc); 941 return; 942 } 943 } 944 945 status = DWC3_TRB_SIZE_TRBSTS(trb->size); 946 if (status == DWC3_TRBSTS_SETUP_PENDING) 947 dwc->setup_packet_pending = true; 948 949 dwc->ep0state = EP0_SETUP_PHASE; 950 dwc3_ep0_out_start(dwc); 951 } 952 953 static void dwc3_ep0_xfer_complete(struct dwc3 *dwc, 954 const struct dwc3_event_depevt *event) 955 { 956 struct dwc3_ep *dep = dwc->eps[event->endpoint_number]; 957 958 dep->flags &= ~DWC3_EP_TRANSFER_STARTED; 959 dep->resource_index = 0; 960 dwc->setup_packet_pending = false; 961 962 switch (dwc->ep0state) { 963 case EP0_SETUP_PHASE: 964 dwc3_ep0_inspect_setup(dwc, event); 965 break; 966 967 case EP0_DATA_PHASE: 968 dwc3_ep0_complete_data(dwc, event); 969 break; 970 971 case EP0_STATUS_PHASE: 972 dwc3_ep0_complete_status(dwc, event); 973 break; 974 default: 975 WARN(true, "UNKNOWN ep0state %d\n", dwc->ep0state); 976 } 977 } 978 979 static void __dwc3_ep0_do_control_data(struct dwc3 *dwc, 980 struct dwc3_ep *dep, struct dwc3_request *req) 981 { 982 unsigned int trb_length = 0; 983 int ret; 984 985 req->direction = !!dep->number; 986 987 if (req->request.length == 0) { 988 if (!req->direction) 989 trb_length = dep->endpoint.maxpacket; 990 991 dwc3_ep0_prepare_one_trb(dep, dwc->bounce_addr, trb_length, 992 DWC3_TRBCTL_CONTROL_DATA, false); 993 ret = dwc3_ep0_start_trans(dep); 994 } else if (!IS_ALIGNED(req->request.length, dep->endpoint.maxpacket) 995 && (dep->number == 0)) { 996 u32 maxpacket; 997 u32 rem; 998 999 ret = usb_gadget_map_request_by_dev(dwc->sysdev, 1000 &req->request, dep->number); 1001 if (ret) 1002 return; 1003 1004 maxpacket = dep->endpoint.maxpacket; 1005 rem = req->request.length % maxpacket; 1006 dwc->ep0_bounced = true; 1007 1008 /* prepare normal TRB */ 1009 dwc3_ep0_prepare_one_trb(dep, req->request.dma, 1010 req->request.length, 1011 DWC3_TRBCTL_CONTROL_DATA, 1012 true); 1013 1014 req->trb = &dwc->ep0_trb[dep->trb_enqueue - 1]; 1015 1016 /* Now prepare one extra TRB to align transfer size */ 1017 dwc3_ep0_prepare_one_trb(dep, dwc->bounce_addr, 1018 maxpacket - rem, 1019 DWC3_TRBCTL_CONTROL_DATA, 1020 false); 1021 ret = dwc3_ep0_start_trans(dep); 1022 } else if (IS_ALIGNED(req->request.length, dep->endpoint.maxpacket) && 1023 req->request.length && req->request.zero) { 1024 1025 ret = usb_gadget_map_request_by_dev(dwc->sysdev, 1026 &req->request, dep->number); 1027 if (ret) 1028 return; 1029 1030 /* prepare normal TRB */ 1031 dwc3_ep0_prepare_one_trb(dep, req->request.dma, 1032 req->request.length, 1033 DWC3_TRBCTL_CONTROL_DATA, 1034 true); 1035 1036 req->trb = &dwc->ep0_trb[dep->trb_enqueue - 1]; 1037 1038 if (!req->direction) 1039 trb_length = dep->endpoint.maxpacket; 1040 1041 /* Now prepare one extra TRB to align transfer size */ 1042 dwc3_ep0_prepare_one_trb(dep, dwc->bounce_addr, 1043 trb_length, DWC3_TRBCTL_CONTROL_DATA, 1044 false); 1045 ret = dwc3_ep0_start_trans(dep); 1046 } else { 1047 ret = usb_gadget_map_request_by_dev(dwc->sysdev, 1048 &req->request, dep->number); 1049 if (ret) 1050 return; 1051 1052 dwc3_ep0_prepare_one_trb(dep, req->request.dma, 1053 req->request.length, DWC3_TRBCTL_CONTROL_DATA, 1054 false); 1055 1056 req->trb = &dwc->ep0_trb[dep->trb_enqueue]; 1057 1058 ret = dwc3_ep0_start_trans(dep); 1059 } 1060 1061 WARN_ON(ret < 0); 1062 } 1063 1064 static int dwc3_ep0_start_control_status(struct dwc3_ep *dep) 1065 { 1066 struct dwc3 *dwc = dep->dwc; 1067 u32 type; 1068 1069 type = dwc->three_stage_setup ? DWC3_TRBCTL_CONTROL_STATUS3 1070 : DWC3_TRBCTL_CONTROL_STATUS2; 1071 1072 dwc3_ep0_prepare_one_trb(dep, dwc->ep0_trb_addr, 0, type, false); 1073 return dwc3_ep0_start_trans(dep); 1074 } 1075 1076 static void __dwc3_ep0_do_control_status(struct dwc3 *dwc, struct dwc3_ep *dep) 1077 { 1078 WARN_ON(dwc3_ep0_start_control_status(dep)); 1079 } 1080 1081 static void dwc3_ep0_do_control_status(struct dwc3 *dwc, 1082 const struct dwc3_event_depevt *event) 1083 { 1084 struct dwc3_ep *dep = dwc->eps[event->endpoint_number]; 1085 1086 __dwc3_ep0_do_control_status(dwc, dep); 1087 } 1088 1089 void dwc3_ep0_send_delayed_status(struct dwc3 *dwc) 1090 { 1091 unsigned int direction = !dwc->ep0_expect_in; 1092 1093 dwc->delayed_status = false; 1094 dwc->clear_stall_protocol = 0; 1095 1096 if (dwc->ep0state != EP0_STATUS_PHASE) 1097 return; 1098 1099 __dwc3_ep0_do_control_status(dwc, dwc->eps[direction]); 1100 } 1101 1102 void dwc3_ep0_end_control_data(struct dwc3 *dwc, struct dwc3_ep *dep) 1103 { 1104 struct dwc3_gadget_ep_cmd_params params; 1105 u32 cmd; 1106 int ret; 1107 1108 /* 1109 * For status/DATA OUT stage, TRB will be queued on ep0 out 1110 * endpoint for which resource index is zero. Hence allow 1111 * queuing ENDXFER command for ep0 out endpoint. 1112 */ 1113 if (!dep->resource_index && dep->number) 1114 return; 1115 1116 cmd = DWC3_DEPCMD_ENDTRANSFER; 1117 cmd |= DWC3_DEPCMD_CMDIOC; 1118 cmd |= DWC3_DEPCMD_PARAM(dep->resource_index); 1119 memset(¶ms, 0, sizeof(params)); 1120 ret = dwc3_send_gadget_ep_cmd(dep, cmd, ¶ms); 1121 WARN_ON_ONCE(ret); 1122 dep->resource_index = 0; 1123 } 1124 1125 static void dwc3_ep0_xfernotready(struct dwc3 *dwc, 1126 const struct dwc3_event_depevt *event) 1127 { 1128 switch (event->status) { 1129 case DEPEVT_STATUS_CONTROL_DATA: 1130 if (!dwc->softconnect || !dwc->connected) 1131 return; 1132 /* 1133 * We already have a DATA transfer in the controller's cache, 1134 * if we receive a XferNotReady(DATA) we will ignore it, unless 1135 * it's for the wrong direction. 1136 * 1137 * In that case, we must issue END_TRANSFER command to the Data 1138 * Phase we already have started and issue SetStall on the 1139 * control endpoint. 1140 */ 1141 if (dwc->ep0_expect_in != event->endpoint_number) { 1142 struct dwc3_ep *dep = dwc->eps[dwc->ep0_expect_in]; 1143 1144 dev_err(dwc->dev, "unexpected direction for Data Phase\n"); 1145 dwc3_ep0_end_control_data(dwc, dep); 1146 dwc3_ep0_stall_and_restart(dwc); 1147 return; 1148 } 1149 1150 break; 1151 1152 case DEPEVT_STATUS_CONTROL_STATUS: 1153 if (dwc->ep0_next_event != DWC3_EP0_NRDY_STATUS) 1154 return; 1155 1156 if (dwc->setup_packet_pending) { 1157 dwc3_ep0_stall_and_restart(dwc); 1158 return; 1159 } 1160 1161 dwc->ep0state = EP0_STATUS_PHASE; 1162 1163 if (dwc->delayed_status) { 1164 struct dwc3_ep *dep = dwc->eps[0]; 1165 1166 WARN_ON_ONCE(event->endpoint_number != 1); 1167 /* 1168 * We should handle the delay STATUS phase here if the 1169 * request for handling delay STATUS has been queued 1170 * into the list. 1171 */ 1172 if (!list_empty(&dep->pending_list)) { 1173 dwc->delayed_status = false; 1174 usb_gadget_set_state(dwc->gadget, 1175 USB_STATE_CONFIGURED); 1176 dwc3_ep0_do_control_status(dwc, event); 1177 } 1178 1179 return; 1180 } 1181 1182 dwc3_ep0_do_control_status(dwc, event); 1183 } 1184 } 1185 1186 void dwc3_ep0_interrupt(struct dwc3 *dwc, 1187 const struct dwc3_event_depevt *event) 1188 { 1189 struct dwc3_ep *dep = dwc->eps[event->endpoint_number]; 1190 u8 cmd; 1191 1192 switch (event->endpoint_event) { 1193 case DWC3_DEPEVT_XFERCOMPLETE: 1194 dwc3_ep0_xfer_complete(dwc, event); 1195 break; 1196 1197 case DWC3_DEPEVT_XFERNOTREADY: 1198 dwc3_ep0_xfernotready(dwc, event); 1199 break; 1200 1201 case DWC3_DEPEVT_XFERINPROGRESS: 1202 case DWC3_DEPEVT_RXTXFIFOEVT: 1203 case DWC3_DEPEVT_STREAMEVT: 1204 break; 1205 case DWC3_DEPEVT_EPCMDCMPLT: 1206 cmd = DEPEVT_PARAMETER_CMD(event->parameters); 1207 1208 if (cmd == DWC3_DEPCMD_ENDTRANSFER) { 1209 dep->flags &= ~DWC3_EP_END_TRANSFER_PENDING; 1210 dep->flags &= ~DWC3_EP_TRANSFER_STARTED; 1211 } 1212 break; 1213 default: 1214 dev_err(dwc->dev, "unknown endpoint event %d\n", event->endpoint_event); 1215 break; 1216 } 1217 } 1218