1 // SPDX-License-Identifier: GPL-2.0 2 /* 3 * dwc3-xilinx.c - Xilinx DWC3 controller specific glue driver 4 * 5 * Authors: Manish Narani <manish.narani@xilinx.com> 6 * Anurag Kumar Vulisha <anurag.kumar.vulisha@xilinx.com> 7 */ 8 9 #include <linux/module.h> 10 #include <linux/kernel.h> 11 #include <linux/slab.h> 12 #include <linux/clk.h> 13 #include <linux/of.h> 14 #include <linux/platform_device.h> 15 #include <linux/dma-mapping.h> 16 #include <linux/gpio/consumer.h> 17 #include <linux/of_gpio.h> 18 #include <linux/of_platform.h> 19 #include <linux/pm_runtime.h> 20 #include <linux/reset.h> 21 #include <linux/of_address.h> 22 #include <linux/delay.h> 23 #include <linux/firmware/xlnx-zynqmp.h> 24 #include <linux/io.h> 25 26 #include <linux/phy/phy.h> 27 28 /* USB phy reset mask register */ 29 #define XLNX_USB_PHY_RST_EN 0x001C 30 #define XLNX_PHY_RST_MASK 0x1 31 32 /* Xilinx USB 3.0 IP Register */ 33 #define XLNX_USB_TRAFFIC_ROUTE_CONFIG 0x005C 34 #define XLNX_USB_TRAFFIC_ROUTE_FPD 0x1 35 36 /* Versal USB Reset ID */ 37 #define VERSAL_USB_RESET_ID 0xC104036 38 39 #define XLNX_USB_FPD_PIPE_CLK 0x7c 40 #define PIPE_CLK_DESELECT 1 41 #define PIPE_CLK_SELECT 0 42 #define XLNX_USB_FPD_POWER_PRSNT 0x80 43 #define FPD_POWER_PRSNT_OPTION BIT(0) 44 45 struct dwc3_xlnx { 46 int num_clocks; 47 struct clk_bulk_data *clks; 48 struct device *dev; 49 void __iomem *regs; 50 int (*pltfm_init)(struct dwc3_xlnx *data); 51 struct phy *usb3_phy; 52 }; 53 54 static void dwc3_xlnx_mask_phy_rst(struct dwc3_xlnx *priv_data, bool mask) 55 { 56 u32 reg; 57 58 /* 59 * Enable or disable ULPI PHY reset from USB Controller. 60 * This does not actually reset the phy, but just controls 61 * whether USB controller can or cannot reset ULPI PHY. 62 */ 63 reg = readl(priv_data->regs + XLNX_USB_PHY_RST_EN); 64 65 if (mask) 66 reg &= ~XLNX_PHY_RST_MASK; 67 else 68 reg |= XLNX_PHY_RST_MASK; 69 70 writel(reg, priv_data->regs + XLNX_USB_PHY_RST_EN); 71 } 72 73 static int dwc3_xlnx_init_versal(struct dwc3_xlnx *priv_data) 74 { 75 struct device *dev = priv_data->dev; 76 int ret; 77 78 dwc3_xlnx_mask_phy_rst(priv_data, false); 79 80 /* Assert and De-assert reset */ 81 ret = zynqmp_pm_reset_assert(VERSAL_USB_RESET_ID, 82 PM_RESET_ACTION_ASSERT); 83 if (ret < 0) { 84 dev_err_probe(dev, ret, "failed to assert Reset\n"); 85 return ret; 86 } 87 88 ret = zynqmp_pm_reset_assert(VERSAL_USB_RESET_ID, 89 PM_RESET_ACTION_RELEASE); 90 if (ret < 0) { 91 dev_err_probe(dev, ret, "failed to De-assert Reset\n"); 92 return ret; 93 } 94 95 dwc3_xlnx_mask_phy_rst(priv_data, true); 96 97 return 0; 98 } 99 100 static int dwc3_xlnx_init_zynqmp(struct dwc3_xlnx *priv_data) 101 { 102 struct device *dev = priv_data->dev; 103 struct reset_control *crst, *hibrst, *apbrst; 104 struct gpio_desc *reset_gpio; 105 int ret = 0; 106 u32 reg; 107 108 priv_data->usb3_phy = devm_phy_optional_get(dev, "usb3-phy"); 109 if (IS_ERR(priv_data->usb3_phy)) { 110 ret = PTR_ERR(priv_data->usb3_phy); 111 dev_err_probe(dev, ret, 112 "failed to get USB3 PHY\n"); 113 goto err; 114 } 115 116 /* 117 * The following core resets are not required unless a USB3 PHY 118 * is used, and the subsequent register settings are not required 119 * unless a core reset is performed (they should be set properly 120 * by the first-stage boot loader, but may be reverted by a core 121 * reset). They may also break the configuration if USB3 is actually 122 * in use but the usb3-phy entry is missing from the device tree. 123 * Therefore, skip these operations in this case. 124 */ 125 if (!priv_data->usb3_phy) 126 goto skip_usb3_phy; 127 128 crst = devm_reset_control_get_exclusive(dev, "usb_crst"); 129 if (IS_ERR(crst)) { 130 ret = PTR_ERR(crst); 131 dev_err_probe(dev, ret, 132 "failed to get core reset signal\n"); 133 goto err; 134 } 135 136 hibrst = devm_reset_control_get_exclusive(dev, "usb_hibrst"); 137 if (IS_ERR(hibrst)) { 138 ret = PTR_ERR(hibrst); 139 dev_err_probe(dev, ret, 140 "failed to get hibernation reset signal\n"); 141 goto err; 142 } 143 144 apbrst = devm_reset_control_get_exclusive(dev, "usb_apbrst"); 145 if (IS_ERR(apbrst)) { 146 ret = PTR_ERR(apbrst); 147 dev_err_probe(dev, ret, 148 "failed to get APB reset signal\n"); 149 goto err; 150 } 151 152 ret = reset_control_assert(crst); 153 if (ret < 0) { 154 dev_err(dev, "Failed to assert core reset\n"); 155 goto err; 156 } 157 158 ret = reset_control_assert(hibrst); 159 if (ret < 0) { 160 dev_err(dev, "Failed to assert hibernation reset\n"); 161 goto err; 162 } 163 164 ret = reset_control_assert(apbrst); 165 if (ret < 0) { 166 dev_err(dev, "Failed to assert APB reset\n"); 167 goto err; 168 } 169 170 ret = phy_init(priv_data->usb3_phy); 171 if (ret < 0) { 172 phy_exit(priv_data->usb3_phy); 173 goto err; 174 } 175 176 ret = reset_control_deassert(apbrst); 177 if (ret < 0) { 178 dev_err(dev, "Failed to release APB reset\n"); 179 goto err; 180 } 181 182 /* Set PIPE Power Present signal in FPD Power Present Register*/ 183 writel(FPD_POWER_PRSNT_OPTION, priv_data->regs + XLNX_USB_FPD_POWER_PRSNT); 184 185 /* Set the PIPE Clock Select bit in FPD PIPE Clock register */ 186 writel(PIPE_CLK_SELECT, priv_data->regs + XLNX_USB_FPD_PIPE_CLK); 187 188 ret = reset_control_deassert(crst); 189 if (ret < 0) { 190 dev_err(dev, "Failed to release core reset\n"); 191 goto err; 192 } 193 194 ret = reset_control_deassert(hibrst); 195 if (ret < 0) { 196 dev_err(dev, "Failed to release hibernation reset\n"); 197 goto err; 198 } 199 200 ret = phy_power_on(priv_data->usb3_phy); 201 if (ret < 0) { 202 phy_exit(priv_data->usb3_phy); 203 goto err; 204 } 205 206 skip_usb3_phy: 207 /* ulpi reset via gpio-modepin or gpio-framework driver */ 208 reset_gpio = devm_gpiod_get_optional(dev, "reset", GPIOD_OUT_LOW); 209 if (IS_ERR(reset_gpio)) { 210 return dev_err_probe(dev, PTR_ERR(reset_gpio), 211 "Failed to request reset GPIO\n"); 212 } 213 214 if (reset_gpio) { 215 /* Toggle ulpi to reset the phy. */ 216 gpiod_set_value_cansleep(reset_gpio, 1); 217 usleep_range(5000, 10000); 218 gpiod_set_value_cansleep(reset_gpio, 0); 219 usleep_range(5000, 10000); 220 } 221 222 /* 223 * This routes the USB DMA traffic to go through FPD path instead 224 * of reaching DDR directly. This traffic routing is needed to 225 * make SMMU and CCI work with USB DMA. 226 */ 227 if (of_dma_is_coherent(dev->of_node) || device_iommu_mapped(dev)) { 228 reg = readl(priv_data->regs + XLNX_USB_TRAFFIC_ROUTE_CONFIG); 229 reg |= XLNX_USB_TRAFFIC_ROUTE_FPD; 230 writel(reg, priv_data->regs + XLNX_USB_TRAFFIC_ROUTE_CONFIG); 231 } 232 233 err: 234 return ret; 235 } 236 237 static const struct of_device_id dwc3_xlnx_of_match[] = { 238 { 239 .compatible = "xlnx,zynqmp-dwc3", 240 .data = &dwc3_xlnx_init_zynqmp, 241 }, 242 { 243 .compatible = "xlnx,versal-dwc3", 244 .data = &dwc3_xlnx_init_versal, 245 }, 246 { /* Sentinel */ } 247 }; 248 MODULE_DEVICE_TABLE(of, dwc3_xlnx_of_match); 249 250 static int dwc3_xlnx_probe(struct platform_device *pdev) 251 { 252 struct dwc3_xlnx *priv_data; 253 struct device *dev = &pdev->dev; 254 struct device_node *np = dev->of_node; 255 const struct of_device_id *match; 256 void __iomem *regs; 257 int ret; 258 259 priv_data = devm_kzalloc(dev, sizeof(*priv_data), GFP_KERNEL); 260 if (!priv_data) 261 return -ENOMEM; 262 263 regs = devm_platform_ioremap_resource(pdev, 0); 264 if (IS_ERR(regs)) { 265 ret = PTR_ERR(regs); 266 dev_err_probe(dev, ret, "failed to map registers\n"); 267 return ret; 268 } 269 270 match = of_match_node(dwc3_xlnx_of_match, pdev->dev.of_node); 271 272 priv_data->pltfm_init = match->data; 273 priv_data->regs = regs; 274 priv_data->dev = dev; 275 276 platform_set_drvdata(pdev, priv_data); 277 278 ret = devm_clk_bulk_get_all(priv_data->dev, &priv_data->clks); 279 if (ret < 0) 280 return ret; 281 282 priv_data->num_clocks = ret; 283 284 ret = clk_bulk_prepare_enable(priv_data->num_clocks, priv_data->clks); 285 if (ret) 286 return ret; 287 288 ret = priv_data->pltfm_init(priv_data); 289 if (ret) 290 goto err_clk_put; 291 292 ret = of_platform_populate(np, NULL, NULL, dev); 293 if (ret) 294 goto err_clk_put; 295 296 pm_runtime_set_active(dev); 297 pm_runtime_enable(dev); 298 pm_suspend_ignore_children(dev, false); 299 pm_runtime_get_sync(dev); 300 301 return 0; 302 303 err_clk_put: 304 clk_bulk_disable_unprepare(priv_data->num_clocks, priv_data->clks); 305 306 return ret; 307 } 308 309 static int dwc3_xlnx_remove(struct platform_device *pdev) 310 { 311 struct dwc3_xlnx *priv_data = platform_get_drvdata(pdev); 312 struct device *dev = &pdev->dev; 313 314 of_platform_depopulate(dev); 315 316 clk_bulk_disable_unprepare(priv_data->num_clocks, priv_data->clks); 317 priv_data->num_clocks = 0; 318 319 pm_runtime_disable(dev); 320 pm_runtime_put_noidle(dev); 321 pm_runtime_set_suspended(dev); 322 323 return 0; 324 } 325 326 static int __maybe_unused dwc3_xlnx_runtime_suspend(struct device *dev) 327 { 328 struct dwc3_xlnx *priv_data = dev_get_drvdata(dev); 329 330 clk_bulk_disable(priv_data->num_clocks, priv_data->clks); 331 332 return 0; 333 } 334 335 static int __maybe_unused dwc3_xlnx_runtime_resume(struct device *dev) 336 { 337 struct dwc3_xlnx *priv_data = dev_get_drvdata(dev); 338 339 return clk_bulk_enable(priv_data->num_clocks, priv_data->clks); 340 } 341 342 static int __maybe_unused dwc3_xlnx_runtime_idle(struct device *dev) 343 { 344 pm_runtime_mark_last_busy(dev); 345 pm_runtime_autosuspend(dev); 346 347 return 0; 348 } 349 350 static int __maybe_unused dwc3_xlnx_suspend(struct device *dev) 351 { 352 struct dwc3_xlnx *priv_data = dev_get_drvdata(dev); 353 354 phy_exit(priv_data->usb3_phy); 355 356 /* Disable the clocks */ 357 clk_bulk_disable(priv_data->num_clocks, priv_data->clks); 358 359 return 0; 360 } 361 362 static int __maybe_unused dwc3_xlnx_resume(struct device *dev) 363 { 364 struct dwc3_xlnx *priv_data = dev_get_drvdata(dev); 365 int ret; 366 367 ret = clk_bulk_enable(priv_data->num_clocks, priv_data->clks); 368 if (ret) 369 return ret; 370 371 ret = phy_init(priv_data->usb3_phy); 372 if (ret < 0) 373 return ret; 374 375 ret = phy_power_on(priv_data->usb3_phy); 376 if (ret < 0) { 377 phy_exit(priv_data->usb3_phy); 378 return ret; 379 } 380 381 return 0; 382 } 383 384 static const struct dev_pm_ops dwc3_xlnx_dev_pm_ops = { 385 SET_SYSTEM_SLEEP_PM_OPS(dwc3_xlnx_suspend, dwc3_xlnx_resume) 386 SET_RUNTIME_PM_OPS(dwc3_xlnx_runtime_suspend, 387 dwc3_xlnx_runtime_resume, dwc3_xlnx_runtime_idle) 388 }; 389 390 static struct platform_driver dwc3_xlnx_driver = { 391 .probe = dwc3_xlnx_probe, 392 .remove = dwc3_xlnx_remove, 393 .driver = { 394 .name = "dwc3-xilinx", 395 .of_match_table = dwc3_xlnx_of_match, 396 .pm = &dwc3_xlnx_dev_pm_ops, 397 }, 398 }; 399 400 module_platform_driver(dwc3_xlnx_driver); 401 402 MODULE_LICENSE("GPL v2"); 403 MODULE_DESCRIPTION("Xilinx DWC3 controller specific glue driver"); 404 MODULE_AUTHOR("Manish Narani <manish.narani@xilinx.com>"); 405 MODULE_AUTHOR("Anurag Kumar Vulisha <anurag.kumar.vulisha@xilinx.com>"); 406