1 // SPDX-License-Identifier: GPL-2.0 2 /* 3 * dwc3-xilinx.c - Xilinx DWC3 controller specific glue driver 4 * 5 * Authors: Manish Narani <manish.narani@xilinx.com> 6 * Anurag Kumar Vulisha <anurag.kumar.vulisha@xilinx.com> 7 */ 8 9 #include <linux/module.h> 10 #include <linux/kernel.h> 11 #include <linux/slab.h> 12 #include <linux/clk.h> 13 #include <linux/of.h> 14 #include <linux/platform_device.h> 15 #include <linux/dma-mapping.h> 16 #include <linux/gpio/consumer.h> 17 #include <linux/of_platform.h> 18 #include <linux/pm_runtime.h> 19 #include <linux/reset.h> 20 #include <linux/of_address.h> 21 #include <linux/delay.h> 22 #include <linux/firmware/xlnx-zynqmp.h> 23 #include <linux/io.h> 24 25 #include <linux/phy/phy.h> 26 27 /* USB phy reset mask register */ 28 #define XLNX_USB_PHY_RST_EN 0x001C 29 #define XLNX_PHY_RST_MASK 0x1 30 31 /* Xilinx USB 3.0 IP Register */ 32 #define XLNX_USB_TRAFFIC_ROUTE_CONFIG 0x005C 33 #define XLNX_USB_TRAFFIC_ROUTE_FPD 0x1 34 35 /* Versal USB Reset ID */ 36 #define VERSAL_USB_RESET_ID 0xC104036 37 38 #define XLNX_USB_FPD_PIPE_CLK 0x7c 39 #define PIPE_CLK_DESELECT 1 40 #define PIPE_CLK_SELECT 0 41 #define XLNX_USB_FPD_POWER_PRSNT 0x80 42 #define FPD_POWER_PRSNT_OPTION BIT(0) 43 44 struct dwc3_xlnx { 45 int num_clocks; 46 struct clk_bulk_data *clks; 47 struct device *dev; 48 void __iomem *regs; 49 int (*pltfm_init)(struct dwc3_xlnx *data); 50 struct phy *usb3_phy; 51 }; 52 53 static void dwc3_xlnx_mask_phy_rst(struct dwc3_xlnx *priv_data, bool mask) 54 { 55 u32 reg; 56 57 /* 58 * Enable or disable ULPI PHY reset from USB Controller. 59 * This does not actually reset the phy, but just controls 60 * whether USB controller can or cannot reset ULPI PHY. 61 */ 62 reg = readl(priv_data->regs + XLNX_USB_PHY_RST_EN); 63 64 if (mask) 65 reg &= ~XLNX_PHY_RST_MASK; 66 else 67 reg |= XLNX_PHY_RST_MASK; 68 69 writel(reg, priv_data->regs + XLNX_USB_PHY_RST_EN); 70 } 71 72 static int dwc3_xlnx_init_versal(struct dwc3_xlnx *priv_data) 73 { 74 struct device *dev = priv_data->dev; 75 int ret; 76 77 dwc3_xlnx_mask_phy_rst(priv_data, false); 78 79 /* Assert and De-assert reset */ 80 ret = zynqmp_pm_reset_assert(VERSAL_USB_RESET_ID, 81 PM_RESET_ACTION_ASSERT); 82 if (ret < 0) { 83 dev_err_probe(dev, ret, "failed to assert Reset\n"); 84 return ret; 85 } 86 87 ret = zynqmp_pm_reset_assert(VERSAL_USB_RESET_ID, 88 PM_RESET_ACTION_RELEASE); 89 if (ret < 0) { 90 dev_err_probe(dev, ret, "failed to De-assert Reset\n"); 91 return ret; 92 } 93 94 dwc3_xlnx_mask_phy_rst(priv_data, true); 95 96 return 0; 97 } 98 99 static int dwc3_xlnx_init_zynqmp(struct dwc3_xlnx *priv_data) 100 { 101 struct device *dev = priv_data->dev; 102 struct reset_control *crst, *hibrst, *apbrst; 103 struct gpio_desc *reset_gpio; 104 int ret = 0; 105 u32 reg; 106 107 priv_data->usb3_phy = devm_phy_optional_get(dev, "usb3-phy"); 108 if (IS_ERR(priv_data->usb3_phy)) { 109 ret = PTR_ERR(priv_data->usb3_phy); 110 dev_err_probe(dev, ret, 111 "failed to get USB3 PHY\n"); 112 goto err; 113 } 114 115 /* 116 * The following core resets are not required unless a USB3 PHY 117 * is used, and the subsequent register settings are not required 118 * unless a core reset is performed (they should be set properly 119 * by the first-stage boot loader, but may be reverted by a core 120 * reset). They may also break the configuration if USB3 is actually 121 * in use but the usb3-phy entry is missing from the device tree. 122 * Therefore, skip these operations in this case. 123 */ 124 if (!priv_data->usb3_phy) { 125 /* Deselect the PIPE Clock Select bit in FPD PIPE Clock register */ 126 writel(PIPE_CLK_DESELECT, priv_data->regs + XLNX_USB_FPD_PIPE_CLK); 127 goto skip_usb3_phy; 128 } 129 130 crst = devm_reset_control_get_exclusive(dev, "usb_crst"); 131 if (IS_ERR(crst)) { 132 ret = PTR_ERR(crst); 133 dev_err_probe(dev, ret, 134 "failed to get core reset signal\n"); 135 goto err; 136 } 137 138 hibrst = devm_reset_control_get_exclusive(dev, "usb_hibrst"); 139 if (IS_ERR(hibrst)) { 140 ret = PTR_ERR(hibrst); 141 dev_err_probe(dev, ret, 142 "failed to get hibernation reset signal\n"); 143 goto err; 144 } 145 146 apbrst = devm_reset_control_get_exclusive(dev, "usb_apbrst"); 147 if (IS_ERR(apbrst)) { 148 ret = PTR_ERR(apbrst); 149 dev_err_probe(dev, ret, 150 "failed to get APB reset signal\n"); 151 goto err; 152 } 153 154 ret = reset_control_assert(crst); 155 if (ret < 0) { 156 dev_err(dev, "Failed to assert core reset\n"); 157 goto err; 158 } 159 160 ret = reset_control_assert(hibrst); 161 if (ret < 0) { 162 dev_err(dev, "Failed to assert hibernation reset\n"); 163 goto err; 164 } 165 166 ret = reset_control_assert(apbrst); 167 if (ret < 0) { 168 dev_err(dev, "Failed to assert APB reset\n"); 169 goto err; 170 } 171 172 ret = phy_init(priv_data->usb3_phy); 173 if (ret < 0) { 174 phy_exit(priv_data->usb3_phy); 175 goto err; 176 } 177 178 ret = reset_control_deassert(apbrst); 179 if (ret < 0) { 180 dev_err(dev, "Failed to release APB reset\n"); 181 goto err; 182 } 183 184 /* Set PIPE Power Present signal in FPD Power Present Register*/ 185 writel(FPD_POWER_PRSNT_OPTION, priv_data->regs + XLNX_USB_FPD_POWER_PRSNT); 186 187 /* Set the PIPE Clock Select bit in FPD PIPE Clock register */ 188 writel(PIPE_CLK_SELECT, priv_data->regs + XLNX_USB_FPD_PIPE_CLK); 189 190 ret = reset_control_deassert(crst); 191 if (ret < 0) { 192 dev_err(dev, "Failed to release core reset\n"); 193 goto err; 194 } 195 196 ret = reset_control_deassert(hibrst); 197 if (ret < 0) { 198 dev_err(dev, "Failed to release hibernation reset\n"); 199 goto err; 200 } 201 202 ret = phy_power_on(priv_data->usb3_phy); 203 if (ret < 0) { 204 phy_exit(priv_data->usb3_phy); 205 goto err; 206 } 207 208 skip_usb3_phy: 209 /* ulpi reset via gpio-modepin or gpio-framework driver */ 210 reset_gpio = devm_gpiod_get_optional(dev, "reset", GPIOD_OUT_LOW); 211 if (IS_ERR(reset_gpio)) { 212 return dev_err_probe(dev, PTR_ERR(reset_gpio), 213 "Failed to request reset GPIO\n"); 214 } 215 216 if (reset_gpio) { 217 /* Toggle ulpi to reset the phy. */ 218 gpiod_set_value_cansleep(reset_gpio, 1); 219 usleep_range(5000, 10000); 220 gpiod_set_value_cansleep(reset_gpio, 0); 221 usleep_range(5000, 10000); 222 } 223 224 /* 225 * This routes the USB DMA traffic to go through FPD path instead 226 * of reaching DDR directly. This traffic routing is needed to 227 * make SMMU and CCI work with USB DMA. 228 */ 229 if (of_dma_is_coherent(dev->of_node) || device_iommu_mapped(dev)) { 230 reg = readl(priv_data->regs + XLNX_USB_TRAFFIC_ROUTE_CONFIG); 231 reg |= XLNX_USB_TRAFFIC_ROUTE_FPD; 232 writel(reg, priv_data->regs + XLNX_USB_TRAFFIC_ROUTE_CONFIG); 233 } 234 235 err: 236 return ret; 237 } 238 239 static const struct of_device_id dwc3_xlnx_of_match[] = { 240 { 241 .compatible = "xlnx,zynqmp-dwc3", 242 .data = &dwc3_xlnx_init_zynqmp, 243 }, 244 { 245 .compatible = "xlnx,versal-dwc3", 246 .data = &dwc3_xlnx_init_versal, 247 }, 248 { /* Sentinel */ } 249 }; 250 MODULE_DEVICE_TABLE(of, dwc3_xlnx_of_match); 251 252 static int dwc3_xlnx_probe(struct platform_device *pdev) 253 { 254 struct dwc3_xlnx *priv_data; 255 struct device *dev = &pdev->dev; 256 struct device_node *np = dev->of_node; 257 const struct of_device_id *match; 258 void __iomem *regs; 259 int ret; 260 261 priv_data = devm_kzalloc(dev, sizeof(*priv_data), GFP_KERNEL); 262 if (!priv_data) 263 return -ENOMEM; 264 265 regs = devm_platform_ioremap_resource(pdev, 0); 266 if (IS_ERR(regs)) { 267 ret = PTR_ERR(regs); 268 dev_err_probe(dev, ret, "failed to map registers\n"); 269 return ret; 270 } 271 272 match = of_match_node(dwc3_xlnx_of_match, pdev->dev.of_node); 273 274 priv_data->pltfm_init = match->data; 275 priv_data->regs = regs; 276 priv_data->dev = dev; 277 278 platform_set_drvdata(pdev, priv_data); 279 280 ret = devm_clk_bulk_get_all(priv_data->dev, &priv_data->clks); 281 if (ret < 0) 282 return ret; 283 284 priv_data->num_clocks = ret; 285 286 ret = clk_bulk_prepare_enable(priv_data->num_clocks, priv_data->clks); 287 if (ret) 288 return ret; 289 290 ret = priv_data->pltfm_init(priv_data); 291 if (ret) 292 goto err_clk_put; 293 294 ret = of_platform_populate(np, NULL, NULL, dev); 295 if (ret) 296 goto err_clk_put; 297 298 pm_runtime_set_active(dev); 299 pm_runtime_enable(dev); 300 pm_suspend_ignore_children(dev, false); 301 pm_runtime_get_sync(dev); 302 303 return 0; 304 305 err_clk_put: 306 clk_bulk_disable_unprepare(priv_data->num_clocks, priv_data->clks); 307 308 return ret; 309 } 310 311 static void dwc3_xlnx_remove(struct platform_device *pdev) 312 { 313 struct dwc3_xlnx *priv_data = platform_get_drvdata(pdev); 314 struct device *dev = &pdev->dev; 315 316 of_platform_depopulate(dev); 317 318 clk_bulk_disable_unprepare(priv_data->num_clocks, priv_data->clks); 319 priv_data->num_clocks = 0; 320 321 pm_runtime_disable(dev); 322 pm_runtime_put_noidle(dev); 323 pm_runtime_set_suspended(dev); 324 } 325 326 static int __maybe_unused dwc3_xlnx_runtime_suspend(struct device *dev) 327 { 328 struct dwc3_xlnx *priv_data = dev_get_drvdata(dev); 329 330 clk_bulk_disable(priv_data->num_clocks, priv_data->clks); 331 332 return 0; 333 } 334 335 static int __maybe_unused dwc3_xlnx_runtime_resume(struct device *dev) 336 { 337 struct dwc3_xlnx *priv_data = dev_get_drvdata(dev); 338 339 return clk_bulk_enable(priv_data->num_clocks, priv_data->clks); 340 } 341 342 static int __maybe_unused dwc3_xlnx_runtime_idle(struct device *dev) 343 { 344 pm_runtime_mark_last_busy(dev); 345 pm_runtime_autosuspend(dev); 346 347 return 0; 348 } 349 350 static int __maybe_unused dwc3_xlnx_suspend(struct device *dev) 351 { 352 struct dwc3_xlnx *priv_data = dev_get_drvdata(dev); 353 354 phy_exit(priv_data->usb3_phy); 355 356 /* Disable the clocks */ 357 clk_bulk_disable(priv_data->num_clocks, priv_data->clks); 358 359 return 0; 360 } 361 362 static int __maybe_unused dwc3_xlnx_resume(struct device *dev) 363 { 364 struct dwc3_xlnx *priv_data = dev_get_drvdata(dev); 365 int ret; 366 367 ret = clk_bulk_enable(priv_data->num_clocks, priv_data->clks); 368 if (ret) 369 return ret; 370 371 ret = phy_init(priv_data->usb3_phy); 372 if (ret < 0) 373 return ret; 374 375 ret = phy_power_on(priv_data->usb3_phy); 376 if (ret < 0) { 377 phy_exit(priv_data->usb3_phy); 378 return ret; 379 } 380 381 return 0; 382 } 383 384 static const struct dev_pm_ops dwc3_xlnx_dev_pm_ops = { 385 SET_SYSTEM_SLEEP_PM_OPS(dwc3_xlnx_suspend, dwc3_xlnx_resume) 386 SET_RUNTIME_PM_OPS(dwc3_xlnx_runtime_suspend, 387 dwc3_xlnx_runtime_resume, dwc3_xlnx_runtime_idle) 388 }; 389 390 static struct platform_driver dwc3_xlnx_driver = { 391 .probe = dwc3_xlnx_probe, 392 .remove_new = dwc3_xlnx_remove, 393 .driver = { 394 .name = "dwc3-xilinx", 395 .of_match_table = dwc3_xlnx_of_match, 396 .pm = &dwc3_xlnx_dev_pm_ops, 397 }, 398 }; 399 400 module_platform_driver(dwc3_xlnx_driver); 401 402 MODULE_LICENSE("GPL v2"); 403 MODULE_DESCRIPTION("Xilinx DWC3 controller specific glue driver"); 404 MODULE_AUTHOR("Manish Narani <manish.narani@xilinx.com>"); 405 MODULE_AUTHOR("Anurag Kumar Vulisha <anurag.kumar.vulisha@xilinx.com>"); 406