1 /** 2 * dwc3-st.c Support for dwc3 platform devices on ST Microelectronics platforms 3 * 4 * This is a small driver for the dwc3 to provide the glue logic 5 * to configure the controller. Tested on STi platforms. 6 * 7 * Copyright (C) 2014 Stmicroelectronics 8 * 9 * Author: Giuseppe Cavallaro <peppe.cavallaro@st.com> 10 * Contributors: Aymen Bouattay <aymen.bouattay@st.com> 11 * Peter Griffin <peter.griffin@linaro.org> 12 * 13 * This program is free software; you can redistribute it and/or modify 14 * it under the terms of the GNU General Public License as published by 15 * the Free Software Foundation; either version 2 of the License, or 16 * (at your option) any later version. 17 * 18 * Inspired by dwc3-omap.c and dwc3-exynos.c. 19 */ 20 21 #include <linux/delay.h> 22 #include <linux/interrupt.h> 23 #include <linux/io.h> 24 #include <linux/ioport.h> 25 #include <linux/kernel.h> 26 #include <linux/mfd/syscon.h> 27 #include <linux/module.h> 28 #include <linux/of.h> 29 #include <linux/of_platform.h> 30 #include <linux/platform_device.h> 31 #include <linux/slab.h> 32 #include <linux/regmap.h> 33 #include <linux/reset.h> 34 #include <linux/pinctrl/consumer.h> 35 #include <linux/usb/of.h> 36 37 #include "core.h" 38 #include "io.h" 39 40 /* glue registers */ 41 #define CLKRST_CTRL 0x00 42 #define AUX_CLK_EN BIT(0) 43 #define SW_PIPEW_RESET_N BIT(4) 44 #define EXT_CFG_RESET_N BIT(8) 45 /* 46 * 1'b0 : The host controller complies with the xHCI revision 0.96 47 * 1'b1 : The host controller complies with the xHCI revision 1.0 48 */ 49 #define XHCI_REVISION BIT(12) 50 51 #define USB2_VBUS_MNGMNT_SEL1 0x2C 52 /* 53 * For all fields in USB2_VBUS_MNGMNT_SEL1 54 * 2’b00 : Override value from Reg 0x30 is selected 55 * 2’b01 : utmiotg_<signal_name> from usb3_top is selected 56 * 2’b10 : pipew_<signal_name> from PIPEW instance is selected 57 * 2’b11 : value is 1'b0 58 */ 59 #define USB2_VBUS_REG30 0x0 60 #define USB2_VBUS_UTMIOTG 0x1 61 #define USB2_VBUS_PIPEW 0x2 62 #define USB2_VBUS_ZERO 0x3 63 64 #define SEL_OVERRIDE_VBUSVALID(n) (n << 0) 65 #define SEL_OVERRIDE_POWERPRESENT(n) (n << 4) 66 #define SEL_OVERRIDE_BVALID(n) (n << 8) 67 68 /* Static DRD configuration */ 69 #define USB3_CONTROL_MASK 0xf77 70 71 #define USB3_DEVICE_NOT_HOST BIT(0) 72 #define USB3_FORCE_VBUSVALID BIT(1) 73 #define USB3_DELAY_VBUSVALID BIT(2) 74 #define USB3_SEL_FORCE_OPMODE BIT(4) 75 #define USB3_FORCE_OPMODE(n) (n << 5) 76 #define USB3_SEL_FORCE_DPPULLDOWN2 BIT(8) 77 #define USB3_FORCE_DPPULLDOWN2 BIT(9) 78 #define USB3_SEL_FORCE_DMPULLDOWN2 BIT(10) 79 #define USB3_FORCE_DMPULLDOWN2 BIT(11) 80 81 /** 82 * struct st_dwc3 - dwc3-st driver private structure 83 * @dev: device pointer 84 * @glue_base: ioaddr for the glue registers 85 * @regmap: regmap pointer for getting syscfg 86 * @syscfg_reg_off: usb syscfg control offset 87 * @dr_mode: drd static host/device config 88 * @rstc_pwrdn: rest controller for powerdown signal 89 * @rstc_rst: reset controller for softreset signal 90 */ 91 92 struct st_dwc3 { 93 struct device *dev; 94 void __iomem *glue_base; 95 struct regmap *regmap; 96 int syscfg_reg_off; 97 enum usb_dr_mode dr_mode; 98 struct reset_control *rstc_pwrdn; 99 struct reset_control *rstc_rst; 100 }; 101 102 static inline u32 st_dwc3_readl(void __iomem *base, u32 offset) 103 { 104 return readl_relaxed(base + offset); 105 } 106 107 static inline void st_dwc3_writel(void __iomem *base, u32 offset, u32 value) 108 { 109 writel_relaxed(value, base + offset); 110 } 111 112 /** 113 * st_dwc3_drd_init: program the port 114 * @dwc3_data: driver private structure 115 * Description: this function is to program the port as either host or device 116 * according to the static configuration passed from devicetree. 117 * OTG and dual role are not yet supported! 118 */ 119 static int st_dwc3_drd_init(struct st_dwc3 *dwc3_data) 120 { 121 u32 val; 122 int err; 123 124 err = regmap_read(dwc3_data->regmap, dwc3_data->syscfg_reg_off, &val); 125 if (err) 126 return err; 127 128 val &= USB3_CONTROL_MASK; 129 130 switch (dwc3_data->dr_mode) { 131 case USB_DR_MODE_PERIPHERAL: 132 133 val &= ~(USB3_DELAY_VBUSVALID 134 | USB3_SEL_FORCE_OPMODE | USB3_FORCE_OPMODE(0x3) 135 | USB3_SEL_FORCE_DPPULLDOWN2 | USB3_FORCE_DPPULLDOWN2 136 | USB3_SEL_FORCE_DMPULLDOWN2 | USB3_FORCE_DMPULLDOWN2); 137 138 /* 139 * USB3_PORT2_FORCE_VBUSVALID When '1' and when 140 * USB3_PORT2_DEVICE_NOT_HOST = 1, forces VBUSVLDEXT2 input 141 * of the pico PHY to 1. 142 */ 143 144 val |= USB3_DEVICE_NOT_HOST | USB3_FORCE_VBUSVALID; 145 break; 146 147 case USB_DR_MODE_HOST: 148 149 val &= ~(USB3_DEVICE_NOT_HOST | USB3_FORCE_VBUSVALID 150 | USB3_SEL_FORCE_OPMODE | USB3_FORCE_OPMODE(0x3) 151 | USB3_SEL_FORCE_DPPULLDOWN2 | USB3_FORCE_DPPULLDOWN2 152 | USB3_SEL_FORCE_DMPULLDOWN2 | USB3_FORCE_DMPULLDOWN2); 153 154 /* 155 * USB3_DELAY_VBUSVALID is ANDed with USB_C_VBUSVALID. Thus, 156 * when set to ‘0‘, it can delay the arrival of VBUSVALID 157 * information to VBUSVLDEXT2 input of the pico PHY. 158 * We don't want to do that so we set the bit to '1'. 159 */ 160 161 val |= USB3_DELAY_VBUSVALID; 162 break; 163 164 default: 165 dev_err(dwc3_data->dev, "Unsupported mode of operation %d\n", 166 dwc3_data->dr_mode); 167 return -EINVAL; 168 } 169 170 return regmap_write(dwc3_data->regmap, dwc3_data->syscfg_reg_off, val); 171 } 172 173 /** 174 * st_dwc3_init: init the controller via glue logic 175 * @dwc3_data: driver private structure 176 */ 177 static void st_dwc3_init(struct st_dwc3 *dwc3_data) 178 { 179 u32 reg = st_dwc3_readl(dwc3_data->glue_base, CLKRST_CTRL); 180 181 reg |= AUX_CLK_EN | EXT_CFG_RESET_N | XHCI_REVISION; 182 reg &= ~SW_PIPEW_RESET_N; 183 st_dwc3_writel(dwc3_data->glue_base, CLKRST_CTRL, reg); 184 185 /* configure mux for vbus, powerpresent and bvalid signals */ 186 reg = st_dwc3_readl(dwc3_data->glue_base, USB2_VBUS_MNGMNT_SEL1); 187 188 reg |= SEL_OVERRIDE_VBUSVALID(USB2_VBUS_UTMIOTG) | 189 SEL_OVERRIDE_POWERPRESENT(USB2_VBUS_UTMIOTG) | 190 SEL_OVERRIDE_BVALID(USB2_VBUS_UTMIOTG); 191 192 st_dwc3_writel(dwc3_data->glue_base, USB2_VBUS_MNGMNT_SEL1, reg); 193 194 reg = st_dwc3_readl(dwc3_data->glue_base, CLKRST_CTRL); 195 reg |= SW_PIPEW_RESET_N; 196 st_dwc3_writel(dwc3_data->glue_base, CLKRST_CTRL, reg); 197 } 198 199 static int st_dwc3_probe(struct platform_device *pdev) 200 { 201 struct st_dwc3 *dwc3_data; 202 struct resource *res; 203 struct device *dev = &pdev->dev; 204 struct device_node *node = dev->of_node, *child; 205 struct platform_device *child_pdev; 206 struct regmap *regmap; 207 int ret; 208 209 dwc3_data = devm_kzalloc(dev, sizeof(*dwc3_data), GFP_KERNEL); 210 if (!dwc3_data) 211 return -ENOMEM; 212 213 res = platform_get_resource_byname(pdev, IORESOURCE_MEM, "reg-glue"); 214 dwc3_data->glue_base = devm_ioremap_resource(dev, res); 215 if (IS_ERR(dwc3_data->glue_base)) 216 return PTR_ERR(dwc3_data->glue_base); 217 218 regmap = syscon_regmap_lookup_by_phandle(node, "st,syscfg"); 219 if (IS_ERR(regmap)) 220 return PTR_ERR(regmap); 221 222 dma_set_coherent_mask(dev, dev->coherent_dma_mask); 223 dwc3_data->dev = dev; 224 dwc3_data->regmap = regmap; 225 226 res = platform_get_resource_byname(pdev, IORESOURCE_MEM, "syscfg-reg"); 227 if (!res) { 228 ret = -ENXIO; 229 goto undo_platform_dev_alloc; 230 } 231 232 dwc3_data->syscfg_reg_off = res->start; 233 234 dev_vdbg(&pdev->dev, "glue-logic addr 0x%p, syscfg-reg offset 0x%x\n", 235 dwc3_data->glue_base, dwc3_data->syscfg_reg_off); 236 237 dwc3_data->rstc_pwrdn = 238 devm_reset_control_get_exclusive(dev, "powerdown"); 239 if (IS_ERR(dwc3_data->rstc_pwrdn)) { 240 dev_err(&pdev->dev, "could not get power controller\n"); 241 ret = PTR_ERR(dwc3_data->rstc_pwrdn); 242 goto undo_platform_dev_alloc; 243 } 244 245 /* Manage PowerDown */ 246 reset_control_deassert(dwc3_data->rstc_pwrdn); 247 248 dwc3_data->rstc_rst = 249 devm_reset_control_get_shared(dev, "softreset"); 250 if (IS_ERR(dwc3_data->rstc_rst)) { 251 dev_err(&pdev->dev, "could not get reset controller\n"); 252 ret = PTR_ERR(dwc3_data->rstc_rst); 253 goto undo_powerdown; 254 } 255 256 /* Manage SoftReset */ 257 reset_control_deassert(dwc3_data->rstc_rst); 258 259 child = of_get_child_by_name(node, "dwc3"); 260 if (!child) { 261 dev_err(&pdev->dev, "failed to find dwc3 core node\n"); 262 ret = -ENODEV; 263 goto undo_softreset; 264 } 265 266 /* Allocate and initialize the core */ 267 ret = of_platform_populate(node, NULL, NULL, dev); 268 if (ret) { 269 dev_err(dev, "failed to add dwc3 core\n"); 270 goto undo_softreset; 271 } 272 273 child_pdev = of_find_device_by_node(child); 274 if (!child_pdev) { 275 dev_err(dev, "failed to find dwc3 core device\n"); 276 ret = -ENODEV; 277 goto undo_softreset; 278 } 279 280 dwc3_data->dr_mode = usb_get_dr_mode(&child_pdev->dev); 281 282 /* 283 * Configure the USB port as device or host according to the static 284 * configuration passed from DT. 285 * DRD is the only mode currently supported so this will be enhanced 286 * as soon as OTG is available. 287 */ 288 ret = st_dwc3_drd_init(dwc3_data); 289 if (ret) { 290 dev_err(dev, "drd initialisation failed\n"); 291 goto undo_softreset; 292 } 293 294 /* ST glue logic init */ 295 st_dwc3_init(dwc3_data); 296 297 platform_set_drvdata(pdev, dwc3_data); 298 return 0; 299 300 undo_softreset: 301 reset_control_assert(dwc3_data->rstc_rst); 302 undo_powerdown: 303 reset_control_assert(dwc3_data->rstc_pwrdn); 304 undo_platform_dev_alloc: 305 platform_device_put(pdev); 306 return ret; 307 } 308 309 static int st_dwc3_remove(struct platform_device *pdev) 310 { 311 struct st_dwc3 *dwc3_data = platform_get_drvdata(pdev); 312 313 of_platform_depopulate(&pdev->dev); 314 315 reset_control_assert(dwc3_data->rstc_pwrdn); 316 reset_control_assert(dwc3_data->rstc_rst); 317 318 return 0; 319 } 320 321 #ifdef CONFIG_PM_SLEEP 322 static int st_dwc3_suspend(struct device *dev) 323 { 324 struct st_dwc3 *dwc3_data = dev_get_drvdata(dev); 325 326 reset_control_assert(dwc3_data->rstc_pwrdn); 327 reset_control_assert(dwc3_data->rstc_rst); 328 329 pinctrl_pm_select_sleep_state(dev); 330 331 return 0; 332 } 333 334 static int st_dwc3_resume(struct device *dev) 335 { 336 struct st_dwc3 *dwc3_data = dev_get_drvdata(dev); 337 int ret; 338 339 pinctrl_pm_select_default_state(dev); 340 341 reset_control_deassert(dwc3_data->rstc_pwrdn); 342 reset_control_deassert(dwc3_data->rstc_rst); 343 344 ret = st_dwc3_drd_init(dwc3_data); 345 if (ret) { 346 dev_err(dev, "drd initialisation failed\n"); 347 return ret; 348 } 349 350 /* ST glue logic init */ 351 st_dwc3_init(dwc3_data); 352 353 return 0; 354 } 355 #endif /* CONFIG_PM_SLEEP */ 356 357 static SIMPLE_DEV_PM_OPS(st_dwc3_dev_pm_ops, st_dwc3_suspend, st_dwc3_resume); 358 359 static const struct of_device_id st_dwc3_match[] = { 360 { .compatible = "st,stih407-dwc3" }, 361 { /* sentinel */ }, 362 }; 363 364 MODULE_DEVICE_TABLE(of, st_dwc3_match); 365 366 static struct platform_driver st_dwc3_driver = { 367 .probe = st_dwc3_probe, 368 .remove = st_dwc3_remove, 369 .driver = { 370 .name = "usb-st-dwc3", 371 .of_match_table = st_dwc3_match, 372 .pm = &st_dwc3_dev_pm_ops, 373 }, 374 }; 375 376 module_platform_driver(st_dwc3_driver); 377 378 MODULE_AUTHOR("Giuseppe Cavallaro <peppe.cavallaro@st.com>"); 379 MODULE_DESCRIPTION("DesignWare USB3 STi Glue Layer"); 380 MODULE_LICENSE("GPL v2"); 381