1 // SPDX-License-Identifier: GPL-2.0 2 /* Copyright (c) 2018, The Linux Foundation. All rights reserved. 3 * 4 * Inspired by dwc3-of-simple.c 5 */ 6 7 #include <linux/acpi.h> 8 #include <linux/io.h> 9 #include <linux/of.h> 10 #include <linux/clk.h> 11 #include <linux/irq.h> 12 #include <linux/of_clk.h> 13 #include <linux/module.h> 14 #include <linux/kernel.h> 15 #include <linux/extcon.h> 16 #include <linux/interconnect.h> 17 #include <linux/of_platform.h> 18 #include <linux/platform_device.h> 19 #include <linux/phy/phy.h> 20 #include <linux/usb/of.h> 21 #include <linux/reset.h> 22 #include <linux/iopoll.h> 23 #include <linux/usb/hcd.h> 24 #include <linux/usb.h> 25 #include "core.h" 26 27 /* USB QSCRATCH Hardware registers */ 28 #define QSCRATCH_HS_PHY_CTRL 0x10 29 #define UTMI_OTG_VBUS_VALID BIT(20) 30 #define SW_SESSVLD_SEL BIT(28) 31 32 #define QSCRATCH_SS_PHY_CTRL 0x30 33 #define LANE0_PWR_PRESENT BIT(24) 34 35 #define QSCRATCH_GENERAL_CFG 0x08 36 #define PIPE_UTMI_CLK_SEL BIT(0) 37 #define PIPE3_PHYSTATUS_SW BIT(3) 38 #define PIPE_UTMI_CLK_DIS BIT(8) 39 40 #define PWR_EVNT_IRQ_STAT_REG 0x58 41 #define PWR_EVNT_LPM_IN_L2_MASK BIT(4) 42 #define PWR_EVNT_LPM_OUT_L2_MASK BIT(5) 43 44 #define SDM845_QSCRATCH_BASE_OFFSET 0xf8800 45 #define SDM845_QSCRATCH_SIZE 0x400 46 #define SDM845_DWC3_CORE_SIZE 0xcd00 47 48 /* Interconnect path bandwidths in MBps */ 49 #define USB_MEMORY_AVG_HS_BW MBps_to_icc(240) 50 #define USB_MEMORY_PEAK_HS_BW MBps_to_icc(700) 51 #define USB_MEMORY_AVG_SS_BW MBps_to_icc(1000) 52 #define USB_MEMORY_PEAK_SS_BW MBps_to_icc(2500) 53 #define APPS_USB_AVG_BW 0 54 #define APPS_USB_PEAK_BW MBps_to_icc(40) 55 56 struct dwc3_acpi_pdata { 57 u32 qscratch_base_offset; 58 u32 qscratch_base_size; 59 u32 dwc3_core_base_size; 60 int hs_phy_irq_index; 61 int dp_hs_phy_irq_index; 62 int dm_hs_phy_irq_index; 63 int ss_phy_irq_index; 64 bool is_urs; 65 }; 66 67 struct dwc3_qcom { 68 struct device *dev; 69 void __iomem *qscratch_base; 70 struct platform_device *dwc3; 71 struct platform_device *urs_usb; 72 struct clk **clks; 73 int num_clocks; 74 struct reset_control *resets; 75 76 int hs_phy_irq; 77 int dp_hs_phy_irq; 78 int dm_hs_phy_irq; 79 int ss_phy_irq; 80 enum usb_device_speed usb2_speed; 81 82 struct extcon_dev *edev; 83 struct extcon_dev *host_edev; 84 struct notifier_block vbus_nb; 85 struct notifier_block host_nb; 86 87 const struct dwc3_acpi_pdata *acpi_pdata; 88 89 enum usb_dr_mode mode; 90 bool is_suspended; 91 bool pm_suspended; 92 struct icc_path *icc_path_ddr; 93 struct icc_path *icc_path_apps; 94 }; 95 96 static inline void dwc3_qcom_setbits(void __iomem *base, u32 offset, u32 val) 97 { 98 u32 reg; 99 100 reg = readl(base + offset); 101 reg |= val; 102 writel(reg, base + offset); 103 104 /* ensure that above write is through */ 105 readl(base + offset); 106 } 107 108 static inline void dwc3_qcom_clrbits(void __iomem *base, u32 offset, u32 val) 109 { 110 u32 reg; 111 112 reg = readl(base + offset); 113 reg &= ~val; 114 writel(reg, base + offset); 115 116 /* ensure that above write is through */ 117 readl(base + offset); 118 } 119 120 static void dwc3_qcom_vbus_override_enable(struct dwc3_qcom *qcom, bool enable) 121 { 122 if (enable) { 123 dwc3_qcom_setbits(qcom->qscratch_base, QSCRATCH_SS_PHY_CTRL, 124 LANE0_PWR_PRESENT); 125 dwc3_qcom_setbits(qcom->qscratch_base, QSCRATCH_HS_PHY_CTRL, 126 UTMI_OTG_VBUS_VALID | SW_SESSVLD_SEL); 127 } else { 128 dwc3_qcom_clrbits(qcom->qscratch_base, QSCRATCH_SS_PHY_CTRL, 129 LANE0_PWR_PRESENT); 130 dwc3_qcom_clrbits(qcom->qscratch_base, QSCRATCH_HS_PHY_CTRL, 131 UTMI_OTG_VBUS_VALID | SW_SESSVLD_SEL); 132 } 133 } 134 135 static int dwc3_qcom_vbus_notifier(struct notifier_block *nb, 136 unsigned long event, void *ptr) 137 { 138 struct dwc3_qcom *qcom = container_of(nb, struct dwc3_qcom, vbus_nb); 139 140 /* enable vbus override for device mode */ 141 dwc3_qcom_vbus_override_enable(qcom, event); 142 qcom->mode = event ? USB_DR_MODE_PERIPHERAL : USB_DR_MODE_HOST; 143 144 return NOTIFY_DONE; 145 } 146 147 static int dwc3_qcom_host_notifier(struct notifier_block *nb, 148 unsigned long event, void *ptr) 149 { 150 struct dwc3_qcom *qcom = container_of(nb, struct dwc3_qcom, host_nb); 151 152 /* disable vbus override in host mode */ 153 dwc3_qcom_vbus_override_enable(qcom, !event); 154 qcom->mode = event ? USB_DR_MODE_HOST : USB_DR_MODE_PERIPHERAL; 155 156 return NOTIFY_DONE; 157 } 158 159 static int dwc3_qcom_register_extcon(struct dwc3_qcom *qcom) 160 { 161 struct device *dev = qcom->dev; 162 struct extcon_dev *host_edev; 163 int ret; 164 165 if (!of_property_read_bool(dev->of_node, "extcon")) 166 return 0; 167 168 qcom->edev = extcon_get_edev_by_phandle(dev, 0); 169 if (IS_ERR(qcom->edev)) 170 return PTR_ERR(qcom->edev); 171 172 qcom->vbus_nb.notifier_call = dwc3_qcom_vbus_notifier; 173 174 qcom->host_edev = extcon_get_edev_by_phandle(dev, 1); 175 if (IS_ERR(qcom->host_edev)) 176 qcom->host_edev = NULL; 177 178 ret = devm_extcon_register_notifier(dev, qcom->edev, EXTCON_USB, 179 &qcom->vbus_nb); 180 if (ret < 0) { 181 dev_err(dev, "VBUS notifier register failed\n"); 182 return ret; 183 } 184 185 if (qcom->host_edev) 186 host_edev = qcom->host_edev; 187 else 188 host_edev = qcom->edev; 189 190 qcom->host_nb.notifier_call = dwc3_qcom_host_notifier; 191 ret = devm_extcon_register_notifier(dev, host_edev, EXTCON_USB_HOST, 192 &qcom->host_nb); 193 if (ret < 0) { 194 dev_err(dev, "Host notifier register failed\n"); 195 return ret; 196 } 197 198 /* Update initial VBUS override based on extcon state */ 199 if (extcon_get_state(qcom->edev, EXTCON_USB) || 200 !extcon_get_state(host_edev, EXTCON_USB_HOST)) 201 dwc3_qcom_vbus_notifier(&qcom->vbus_nb, true, qcom->edev); 202 else 203 dwc3_qcom_vbus_notifier(&qcom->vbus_nb, false, qcom->edev); 204 205 return 0; 206 } 207 208 static int dwc3_qcom_interconnect_enable(struct dwc3_qcom *qcom) 209 { 210 int ret; 211 212 ret = icc_enable(qcom->icc_path_ddr); 213 if (ret) 214 return ret; 215 216 ret = icc_enable(qcom->icc_path_apps); 217 if (ret) 218 icc_disable(qcom->icc_path_ddr); 219 220 return ret; 221 } 222 223 static int dwc3_qcom_interconnect_disable(struct dwc3_qcom *qcom) 224 { 225 int ret; 226 227 ret = icc_disable(qcom->icc_path_ddr); 228 if (ret) 229 return ret; 230 231 ret = icc_disable(qcom->icc_path_apps); 232 if (ret) 233 icc_enable(qcom->icc_path_ddr); 234 235 return ret; 236 } 237 238 /** 239 * dwc3_qcom_interconnect_init() - Get interconnect path handles 240 * and set bandwidth. 241 * @qcom: Pointer to the concerned usb core. 242 * 243 */ 244 static int dwc3_qcom_interconnect_init(struct dwc3_qcom *qcom) 245 { 246 enum usb_device_speed max_speed; 247 struct device *dev = qcom->dev; 248 int ret; 249 250 if (has_acpi_companion(dev)) 251 return 0; 252 253 qcom->icc_path_ddr = of_icc_get(dev, "usb-ddr"); 254 if (IS_ERR(qcom->icc_path_ddr)) { 255 dev_err(dev, "failed to get usb-ddr path: %ld\n", 256 PTR_ERR(qcom->icc_path_ddr)); 257 return PTR_ERR(qcom->icc_path_ddr); 258 } 259 260 qcom->icc_path_apps = of_icc_get(dev, "apps-usb"); 261 if (IS_ERR(qcom->icc_path_apps)) { 262 dev_err(dev, "failed to get apps-usb path: %ld\n", 263 PTR_ERR(qcom->icc_path_apps)); 264 ret = PTR_ERR(qcom->icc_path_apps); 265 goto put_path_ddr; 266 } 267 268 max_speed = usb_get_maximum_speed(&qcom->dwc3->dev); 269 if (max_speed >= USB_SPEED_SUPER || max_speed == USB_SPEED_UNKNOWN) { 270 ret = icc_set_bw(qcom->icc_path_ddr, 271 USB_MEMORY_AVG_SS_BW, USB_MEMORY_PEAK_SS_BW); 272 } else { 273 ret = icc_set_bw(qcom->icc_path_ddr, 274 USB_MEMORY_AVG_HS_BW, USB_MEMORY_PEAK_HS_BW); 275 } 276 if (ret) { 277 dev_err(dev, "failed to set bandwidth for usb-ddr path: %d\n", ret); 278 goto put_path_apps; 279 } 280 281 ret = icc_set_bw(qcom->icc_path_apps, APPS_USB_AVG_BW, APPS_USB_PEAK_BW); 282 if (ret) { 283 dev_err(dev, "failed to set bandwidth for apps-usb path: %d\n", ret); 284 goto put_path_apps; 285 } 286 287 return 0; 288 289 put_path_apps: 290 icc_put(qcom->icc_path_apps); 291 put_path_ddr: 292 icc_put(qcom->icc_path_ddr); 293 return ret; 294 } 295 296 /** 297 * dwc3_qcom_interconnect_exit() - Release interconnect path handles 298 * @qcom: Pointer to the concerned usb core. 299 * 300 * This function is used to release interconnect path handle. 301 */ 302 static void dwc3_qcom_interconnect_exit(struct dwc3_qcom *qcom) 303 { 304 icc_put(qcom->icc_path_ddr); 305 icc_put(qcom->icc_path_apps); 306 } 307 308 /* Only usable in contexts where the role can not change. */ 309 static bool dwc3_qcom_is_host(struct dwc3_qcom *qcom) 310 { 311 struct dwc3 *dwc = platform_get_drvdata(qcom->dwc3); 312 313 return dwc->xhci; 314 } 315 316 static enum usb_device_speed dwc3_qcom_read_usb2_speed(struct dwc3_qcom *qcom) 317 { 318 struct dwc3 *dwc = platform_get_drvdata(qcom->dwc3); 319 struct usb_device *udev; 320 struct usb_hcd __maybe_unused *hcd; 321 322 /* 323 * FIXME: Fix this layering violation. 324 */ 325 hcd = platform_get_drvdata(dwc->xhci); 326 327 /* 328 * It is possible to query the speed of all children of 329 * USB2.0 root hub via usb_hub_for_each_child(). DWC3 code 330 * currently supports only 1 port per controller. So 331 * this is sufficient. 332 */ 333 #ifdef CONFIG_USB 334 udev = usb_hub_find_child(hcd->self.root_hub, 1); 335 #else 336 udev = NULL; 337 #endif 338 if (!udev) 339 return USB_SPEED_UNKNOWN; 340 341 return udev->speed; 342 } 343 344 static void dwc3_qcom_enable_wakeup_irq(int irq, unsigned int polarity) 345 { 346 if (!irq) 347 return; 348 349 if (polarity) 350 irq_set_irq_type(irq, polarity); 351 352 enable_irq(irq); 353 enable_irq_wake(irq); 354 } 355 356 static void dwc3_qcom_disable_wakeup_irq(int irq) 357 { 358 if (!irq) 359 return; 360 361 disable_irq_wake(irq); 362 disable_irq_nosync(irq); 363 } 364 365 static void dwc3_qcom_disable_interrupts(struct dwc3_qcom *qcom) 366 { 367 dwc3_qcom_disable_wakeup_irq(qcom->hs_phy_irq); 368 369 if (qcom->usb2_speed == USB_SPEED_LOW) { 370 dwc3_qcom_disable_wakeup_irq(qcom->dm_hs_phy_irq); 371 } else if ((qcom->usb2_speed == USB_SPEED_HIGH) || 372 (qcom->usb2_speed == USB_SPEED_FULL)) { 373 dwc3_qcom_disable_wakeup_irq(qcom->dp_hs_phy_irq); 374 } else { 375 dwc3_qcom_disable_wakeup_irq(qcom->dp_hs_phy_irq); 376 dwc3_qcom_disable_wakeup_irq(qcom->dm_hs_phy_irq); 377 } 378 379 dwc3_qcom_disable_wakeup_irq(qcom->ss_phy_irq); 380 } 381 382 static void dwc3_qcom_enable_interrupts(struct dwc3_qcom *qcom) 383 { 384 dwc3_qcom_enable_wakeup_irq(qcom->hs_phy_irq, 0); 385 386 /* 387 * Configure DP/DM line interrupts based on the USB2 device attached to 388 * the root hub port. When HS/FS device is connected, configure the DP line 389 * as falling edge to detect both disconnect and remote wakeup scenarios. When 390 * LS device is connected, configure DM line as falling edge to detect both 391 * disconnect and remote wakeup. When no device is connected, configure both 392 * DP and DM lines as rising edge to detect HS/HS/LS device connect scenario. 393 */ 394 395 if (qcom->usb2_speed == USB_SPEED_LOW) { 396 dwc3_qcom_enable_wakeup_irq(qcom->dm_hs_phy_irq, 397 IRQ_TYPE_EDGE_FALLING); 398 } else if ((qcom->usb2_speed == USB_SPEED_HIGH) || 399 (qcom->usb2_speed == USB_SPEED_FULL)) { 400 dwc3_qcom_enable_wakeup_irq(qcom->dp_hs_phy_irq, 401 IRQ_TYPE_EDGE_FALLING); 402 } else { 403 dwc3_qcom_enable_wakeup_irq(qcom->dp_hs_phy_irq, 404 IRQ_TYPE_EDGE_RISING); 405 dwc3_qcom_enable_wakeup_irq(qcom->dm_hs_phy_irq, 406 IRQ_TYPE_EDGE_RISING); 407 } 408 409 dwc3_qcom_enable_wakeup_irq(qcom->ss_phy_irq, 0); 410 } 411 412 static int dwc3_qcom_suspend(struct dwc3_qcom *qcom, bool wakeup) 413 { 414 u32 val; 415 int i, ret; 416 417 if (qcom->is_suspended) 418 return 0; 419 420 val = readl(qcom->qscratch_base + PWR_EVNT_IRQ_STAT_REG); 421 if (!(val & PWR_EVNT_LPM_IN_L2_MASK)) 422 dev_err(qcom->dev, "HS-PHY not in L2\n"); 423 424 for (i = qcom->num_clocks - 1; i >= 0; i--) 425 clk_disable_unprepare(qcom->clks[i]); 426 427 ret = dwc3_qcom_interconnect_disable(qcom); 428 if (ret) 429 dev_warn(qcom->dev, "failed to disable interconnect: %d\n", ret); 430 431 /* 432 * The role is stable during suspend as role switching is done from a 433 * freezable workqueue. 434 */ 435 if (dwc3_qcom_is_host(qcom) && wakeup) { 436 qcom->usb2_speed = dwc3_qcom_read_usb2_speed(qcom); 437 dwc3_qcom_enable_interrupts(qcom); 438 } 439 440 qcom->is_suspended = true; 441 442 return 0; 443 } 444 445 static int dwc3_qcom_resume(struct dwc3_qcom *qcom, bool wakeup) 446 { 447 int ret; 448 int i; 449 450 if (!qcom->is_suspended) 451 return 0; 452 453 if (dwc3_qcom_is_host(qcom) && wakeup) 454 dwc3_qcom_disable_interrupts(qcom); 455 456 for (i = 0; i < qcom->num_clocks; i++) { 457 ret = clk_prepare_enable(qcom->clks[i]); 458 if (ret < 0) { 459 while (--i >= 0) 460 clk_disable_unprepare(qcom->clks[i]); 461 return ret; 462 } 463 } 464 465 ret = dwc3_qcom_interconnect_enable(qcom); 466 if (ret) 467 dev_warn(qcom->dev, "failed to enable interconnect: %d\n", ret); 468 469 /* Clear existing events from PHY related to L2 in/out */ 470 dwc3_qcom_setbits(qcom->qscratch_base, PWR_EVNT_IRQ_STAT_REG, 471 PWR_EVNT_LPM_IN_L2_MASK | PWR_EVNT_LPM_OUT_L2_MASK); 472 473 qcom->is_suspended = false; 474 475 return 0; 476 } 477 478 static irqreturn_t qcom_dwc3_resume_irq(int irq, void *data) 479 { 480 struct dwc3_qcom *qcom = data; 481 struct dwc3 *dwc = platform_get_drvdata(qcom->dwc3); 482 483 /* If pm_suspended then let pm_resume take care of resuming h/w */ 484 if (qcom->pm_suspended) 485 return IRQ_HANDLED; 486 487 /* 488 * This is safe as role switching is done from a freezable workqueue 489 * and the wakeup interrupts are disabled as part of resume. 490 */ 491 if (dwc3_qcom_is_host(qcom)) 492 pm_runtime_resume(&dwc->xhci->dev); 493 494 return IRQ_HANDLED; 495 } 496 497 static void dwc3_qcom_select_utmi_clk(struct dwc3_qcom *qcom) 498 { 499 /* Configure dwc3 to use UTMI clock as PIPE clock not present */ 500 dwc3_qcom_setbits(qcom->qscratch_base, QSCRATCH_GENERAL_CFG, 501 PIPE_UTMI_CLK_DIS); 502 503 usleep_range(100, 1000); 504 505 dwc3_qcom_setbits(qcom->qscratch_base, QSCRATCH_GENERAL_CFG, 506 PIPE_UTMI_CLK_SEL | PIPE3_PHYSTATUS_SW); 507 508 usleep_range(100, 1000); 509 510 dwc3_qcom_clrbits(qcom->qscratch_base, QSCRATCH_GENERAL_CFG, 511 PIPE_UTMI_CLK_DIS); 512 } 513 514 static int dwc3_qcom_get_irq(struct platform_device *pdev, 515 const char *name, int num) 516 { 517 struct dwc3_qcom *qcom = platform_get_drvdata(pdev); 518 struct platform_device *pdev_irq = qcom->urs_usb ? qcom->urs_usb : pdev; 519 struct device_node *np = pdev->dev.of_node; 520 int ret; 521 522 if (np) 523 ret = platform_get_irq_byname_optional(pdev_irq, name); 524 else 525 ret = platform_get_irq_optional(pdev_irq, num); 526 527 return ret; 528 } 529 530 static int dwc3_qcom_setup_irq(struct platform_device *pdev) 531 { 532 struct dwc3_qcom *qcom = platform_get_drvdata(pdev); 533 const struct dwc3_acpi_pdata *pdata = qcom->acpi_pdata; 534 int irq; 535 int ret; 536 537 irq = dwc3_qcom_get_irq(pdev, "hs_phy_irq", 538 pdata ? pdata->hs_phy_irq_index : -1); 539 if (irq > 0) { 540 /* Keep wakeup interrupts disabled until suspend */ 541 irq_set_status_flags(irq, IRQ_NOAUTOEN); 542 ret = devm_request_threaded_irq(qcom->dev, irq, NULL, 543 qcom_dwc3_resume_irq, 544 IRQF_TRIGGER_HIGH | IRQF_ONESHOT, 545 "qcom_dwc3 HS", qcom); 546 if (ret) { 547 dev_err(qcom->dev, "hs_phy_irq failed: %d\n", ret); 548 return ret; 549 } 550 qcom->hs_phy_irq = irq; 551 } 552 553 irq = dwc3_qcom_get_irq(pdev, "dp_hs_phy_irq", 554 pdata ? pdata->dp_hs_phy_irq_index : -1); 555 if (irq > 0) { 556 irq_set_status_flags(irq, IRQ_NOAUTOEN); 557 ret = devm_request_threaded_irq(qcom->dev, irq, NULL, 558 qcom_dwc3_resume_irq, 559 IRQF_TRIGGER_HIGH | IRQF_ONESHOT, 560 "qcom_dwc3 DP_HS", qcom); 561 if (ret) { 562 dev_err(qcom->dev, "dp_hs_phy_irq failed: %d\n", ret); 563 return ret; 564 } 565 qcom->dp_hs_phy_irq = irq; 566 } 567 568 irq = dwc3_qcom_get_irq(pdev, "dm_hs_phy_irq", 569 pdata ? pdata->dm_hs_phy_irq_index : -1); 570 if (irq > 0) { 571 irq_set_status_flags(irq, IRQ_NOAUTOEN); 572 ret = devm_request_threaded_irq(qcom->dev, irq, NULL, 573 qcom_dwc3_resume_irq, 574 IRQF_TRIGGER_HIGH | IRQF_ONESHOT, 575 "qcom_dwc3 DM_HS", qcom); 576 if (ret) { 577 dev_err(qcom->dev, "dm_hs_phy_irq failed: %d\n", ret); 578 return ret; 579 } 580 qcom->dm_hs_phy_irq = irq; 581 } 582 583 irq = dwc3_qcom_get_irq(pdev, "ss_phy_irq", 584 pdata ? pdata->ss_phy_irq_index : -1); 585 if (irq > 0) { 586 irq_set_status_flags(irq, IRQ_NOAUTOEN); 587 ret = devm_request_threaded_irq(qcom->dev, irq, NULL, 588 qcom_dwc3_resume_irq, 589 IRQF_TRIGGER_HIGH | IRQF_ONESHOT, 590 "qcom_dwc3 SS", qcom); 591 if (ret) { 592 dev_err(qcom->dev, "ss_phy_irq failed: %d\n", ret); 593 return ret; 594 } 595 qcom->ss_phy_irq = irq; 596 } 597 598 return 0; 599 } 600 601 static int dwc3_qcom_clk_init(struct dwc3_qcom *qcom, int count) 602 { 603 struct device *dev = qcom->dev; 604 struct device_node *np = dev->of_node; 605 int i; 606 607 if (!np || !count) 608 return 0; 609 610 if (count < 0) 611 return count; 612 613 qcom->num_clocks = count; 614 615 qcom->clks = devm_kcalloc(dev, qcom->num_clocks, 616 sizeof(struct clk *), GFP_KERNEL); 617 if (!qcom->clks) 618 return -ENOMEM; 619 620 for (i = 0; i < qcom->num_clocks; i++) { 621 struct clk *clk; 622 int ret; 623 624 clk = of_clk_get(np, i); 625 if (IS_ERR(clk)) { 626 while (--i >= 0) 627 clk_put(qcom->clks[i]); 628 return PTR_ERR(clk); 629 } 630 631 ret = clk_prepare_enable(clk); 632 if (ret < 0) { 633 while (--i >= 0) { 634 clk_disable_unprepare(qcom->clks[i]); 635 clk_put(qcom->clks[i]); 636 } 637 clk_put(clk); 638 639 return ret; 640 } 641 642 qcom->clks[i] = clk; 643 } 644 645 return 0; 646 } 647 648 static const struct property_entry dwc3_qcom_acpi_properties[] = { 649 PROPERTY_ENTRY_STRING("dr_mode", "host"), 650 {} 651 }; 652 653 static const struct software_node dwc3_qcom_swnode = { 654 .properties = dwc3_qcom_acpi_properties, 655 }; 656 657 static int dwc3_qcom_acpi_register_core(struct platform_device *pdev) 658 { 659 struct dwc3_qcom *qcom = platform_get_drvdata(pdev); 660 struct device *dev = &pdev->dev; 661 struct resource *res, *child_res = NULL; 662 struct platform_device *pdev_irq = qcom->urs_usb ? qcom->urs_usb : 663 pdev; 664 int irq; 665 int ret; 666 667 qcom->dwc3 = platform_device_alloc("dwc3", PLATFORM_DEVID_AUTO); 668 if (!qcom->dwc3) 669 return -ENOMEM; 670 671 qcom->dwc3->dev.parent = dev; 672 qcom->dwc3->dev.type = dev->type; 673 qcom->dwc3->dev.dma_mask = dev->dma_mask; 674 qcom->dwc3->dev.dma_parms = dev->dma_parms; 675 qcom->dwc3->dev.coherent_dma_mask = dev->coherent_dma_mask; 676 677 child_res = kcalloc(2, sizeof(*child_res), GFP_KERNEL); 678 if (!child_res) { 679 platform_device_put(qcom->dwc3); 680 return -ENOMEM; 681 } 682 683 res = platform_get_resource(pdev, IORESOURCE_MEM, 0); 684 if (!res) { 685 dev_err(&pdev->dev, "failed to get memory resource\n"); 686 ret = -ENODEV; 687 goto out; 688 } 689 690 child_res[0].flags = res->flags; 691 child_res[0].start = res->start; 692 child_res[0].end = child_res[0].start + 693 qcom->acpi_pdata->dwc3_core_base_size; 694 695 irq = platform_get_irq(pdev_irq, 0); 696 if (irq < 0) { 697 ret = irq; 698 goto out; 699 } 700 child_res[1].flags = IORESOURCE_IRQ; 701 child_res[1].start = child_res[1].end = irq; 702 703 ret = platform_device_add_resources(qcom->dwc3, child_res, 2); 704 if (ret) { 705 dev_err(&pdev->dev, "failed to add resources\n"); 706 goto out; 707 } 708 709 ret = device_add_software_node(&qcom->dwc3->dev, &dwc3_qcom_swnode); 710 if (ret < 0) { 711 dev_err(&pdev->dev, "failed to add properties\n"); 712 goto out; 713 } 714 715 ret = platform_device_add(qcom->dwc3); 716 if (ret) { 717 dev_err(&pdev->dev, "failed to add device\n"); 718 device_remove_software_node(&qcom->dwc3->dev); 719 goto out; 720 } 721 kfree(child_res); 722 return 0; 723 724 out: 725 platform_device_put(qcom->dwc3); 726 kfree(child_res); 727 return ret; 728 } 729 730 static int dwc3_qcom_of_register_core(struct platform_device *pdev) 731 { 732 struct dwc3_qcom *qcom = platform_get_drvdata(pdev); 733 struct device_node *np = pdev->dev.of_node, *dwc3_np; 734 struct device *dev = &pdev->dev; 735 int ret; 736 737 dwc3_np = of_get_compatible_child(np, "snps,dwc3"); 738 if (!dwc3_np) { 739 dev_err(dev, "failed to find dwc3 core child\n"); 740 return -ENODEV; 741 } 742 743 ret = of_platform_populate(np, NULL, NULL, dev); 744 if (ret) { 745 dev_err(dev, "failed to register dwc3 core - %d\n", ret); 746 goto node_put; 747 } 748 749 qcom->dwc3 = of_find_device_by_node(dwc3_np); 750 if (!qcom->dwc3) { 751 ret = -ENODEV; 752 dev_err(dev, "failed to get dwc3 platform device\n"); 753 } 754 755 node_put: 756 of_node_put(dwc3_np); 757 758 return ret; 759 } 760 761 static struct platform_device * 762 dwc3_qcom_create_urs_usb_platdev(struct device *dev) 763 { 764 struct fwnode_handle *fwh; 765 struct acpi_device *adev; 766 char name[8]; 767 int ret; 768 int id; 769 770 /* Figure out device id */ 771 ret = sscanf(fwnode_get_name(dev->fwnode), "URS%d", &id); 772 if (!ret) 773 return NULL; 774 775 /* Find the child using name */ 776 snprintf(name, sizeof(name), "USB%d", id); 777 fwh = fwnode_get_named_child_node(dev->fwnode, name); 778 if (!fwh) 779 return NULL; 780 781 adev = to_acpi_device_node(fwh); 782 if (!adev) 783 return NULL; 784 785 return acpi_create_platform_device(adev, NULL); 786 } 787 788 static int dwc3_qcom_probe(struct platform_device *pdev) 789 { 790 struct device_node *np = pdev->dev.of_node; 791 struct device *dev = &pdev->dev; 792 struct dwc3_qcom *qcom; 793 struct resource *res, *parent_res = NULL; 794 int ret, i; 795 bool ignore_pipe_clk; 796 bool wakeup_source; 797 798 qcom = devm_kzalloc(&pdev->dev, sizeof(*qcom), GFP_KERNEL); 799 if (!qcom) 800 return -ENOMEM; 801 802 platform_set_drvdata(pdev, qcom); 803 qcom->dev = &pdev->dev; 804 805 if (has_acpi_companion(dev)) { 806 qcom->acpi_pdata = acpi_device_get_match_data(dev); 807 if (!qcom->acpi_pdata) { 808 dev_err(&pdev->dev, "no supporting ACPI device data\n"); 809 return -EINVAL; 810 } 811 } 812 813 qcom->resets = devm_reset_control_array_get_optional_exclusive(dev); 814 if (IS_ERR(qcom->resets)) { 815 ret = PTR_ERR(qcom->resets); 816 dev_err(&pdev->dev, "failed to get resets, err=%d\n", ret); 817 return ret; 818 } 819 820 ret = reset_control_assert(qcom->resets); 821 if (ret) { 822 dev_err(&pdev->dev, "failed to assert resets, err=%d\n", ret); 823 return ret; 824 } 825 826 usleep_range(10, 1000); 827 828 ret = reset_control_deassert(qcom->resets); 829 if (ret) { 830 dev_err(&pdev->dev, "failed to deassert resets, err=%d\n", ret); 831 goto reset_assert; 832 } 833 834 ret = dwc3_qcom_clk_init(qcom, of_clk_get_parent_count(np)); 835 if (ret) { 836 dev_err(dev, "failed to get clocks\n"); 837 goto reset_assert; 838 } 839 840 res = platform_get_resource(pdev, IORESOURCE_MEM, 0); 841 842 if (np) { 843 parent_res = res; 844 } else { 845 parent_res = kmemdup(res, sizeof(struct resource), GFP_KERNEL); 846 if (!parent_res) 847 return -ENOMEM; 848 849 parent_res->start = res->start + 850 qcom->acpi_pdata->qscratch_base_offset; 851 parent_res->end = parent_res->start + 852 qcom->acpi_pdata->qscratch_base_size; 853 854 if (qcom->acpi_pdata->is_urs) { 855 qcom->urs_usb = dwc3_qcom_create_urs_usb_platdev(dev); 856 if (IS_ERR_OR_NULL(qcom->urs_usb)) { 857 dev_err(dev, "failed to create URS USB platdev\n"); 858 if (!qcom->urs_usb) 859 return -ENODEV; 860 else 861 return PTR_ERR(qcom->urs_usb); 862 } 863 } 864 } 865 866 qcom->qscratch_base = devm_ioremap_resource(dev, parent_res); 867 if (IS_ERR(qcom->qscratch_base)) { 868 ret = PTR_ERR(qcom->qscratch_base); 869 goto clk_disable; 870 } 871 872 ret = dwc3_qcom_setup_irq(pdev); 873 if (ret) { 874 dev_err(dev, "failed to setup IRQs, err=%d\n", ret); 875 goto clk_disable; 876 } 877 878 /* 879 * Disable pipe_clk requirement if specified. Used when dwc3 880 * operates without SSPHY and only HS/FS/LS modes are supported. 881 */ 882 ignore_pipe_clk = device_property_read_bool(dev, 883 "qcom,select-utmi-as-pipe-clk"); 884 if (ignore_pipe_clk) 885 dwc3_qcom_select_utmi_clk(qcom); 886 887 if (np) 888 ret = dwc3_qcom_of_register_core(pdev); 889 else 890 ret = dwc3_qcom_acpi_register_core(pdev); 891 892 if (ret) { 893 dev_err(dev, "failed to register DWC3 Core, err=%d\n", ret); 894 goto depopulate; 895 } 896 897 ret = dwc3_qcom_interconnect_init(qcom); 898 if (ret) 899 goto depopulate; 900 901 qcom->mode = usb_get_dr_mode(&qcom->dwc3->dev); 902 903 /* enable vbus override for device mode */ 904 if (qcom->mode == USB_DR_MODE_PERIPHERAL) 905 dwc3_qcom_vbus_override_enable(qcom, true); 906 907 /* register extcon to override sw_vbus on Vbus change later */ 908 ret = dwc3_qcom_register_extcon(qcom); 909 if (ret) 910 goto interconnect_exit; 911 912 wakeup_source = of_property_read_bool(dev->of_node, "wakeup-source"); 913 device_init_wakeup(&pdev->dev, wakeup_source); 914 device_init_wakeup(&qcom->dwc3->dev, wakeup_source); 915 916 qcom->is_suspended = false; 917 pm_runtime_set_active(dev); 918 pm_runtime_enable(dev); 919 pm_runtime_forbid(dev); 920 921 return 0; 922 923 interconnect_exit: 924 dwc3_qcom_interconnect_exit(qcom); 925 depopulate: 926 if (np) 927 of_platform_depopulate(&pdev->dev); 928 else 929 platform_device_put(pdev); 930 clk_disable: 931 for (i = qcom->num_clocks - 1; i >= 0; i--) { 932 clk_disable_unprepare(qcom->clks[i]); 933 clk_put(qcom->clks[i]); 934 } 935 reset_assert: 936 reset_control_assert(qcom->resets); 937 938 return ret; 939 } 940 941 static int dwc3_qcom_remove(struct platform_device *pdev) 942 { 943 struct dwc3_qcom *qcom = platform_get_drvdata(pdev); 944 struct device *dev = &pdev->dev; 945 int i; 946 947 device_remove_software_node(&qcom->dwc3->dev); 948 of_platform_depopulate(dev); 949 950 for (i = qcom->num_clocks - 1; i >= 0; i--) { 951 clk_disable_unprepare(qcom->clks[i]); 952 clk_put(qcom->clks[i]); 953 } 954 qcom->num_clocks = 0; 955 956 dwc3_qcom_interconnect_exit(qcom); 957 reset_control_assert(qcom->resets); 958 959 pm_runtime_allow(dev); 960 pm_runtime_disable(dev); 961 962 return 0; 963 } 964 965 static int __maybe_unused dwc3_qcom_pm_suspend(struct device *dev) 966 { 967 struct dwc3_qcom *qcom = dev_get_drvdata(dev); 968 bool wakeup = device_may_wakeup(dev); 969 int ret; 970 971 ret = dwc3_qcom_suspend(qcom, wakeup); 972 if (ret) 973 return ret; 974 975 qcom->pm_suspended = true; 976 977 return 0; 978 } 979 980 static int __maybe_unused dwc3_qcom_pm_resume(struct device *dev) 981 { 982 struct dwc3_qcom *qcom = dev_get_drvdata(dev); 983 bool wakeup = device_may_wakeup(dev); 984 int ret; 985 986 ret = dwc3_qcom_resume(qcom, wakeup); 987 if (ret) 988 return ret; 989 990 qcom->pm_suspended = false; 991 992 return 0; 993 } 994 995 static int __maybe_unused dwc3_qcom_runtime_suspend(struct device *dev) 996 { 997 struct dwc3_qcom *qcom = dev_get_drvdata(dev); 998 999 return dwc3_qcom_suspend(qcom, true); 1000 } 1001 1002 static int __maybe_unused dwc3_qcom_runtime_resume(struct device *dev) 1003 { 1004 struct dwc3_qcom *qcom = dev_get_drvdata(dev); 1005 1006 return dwc3_qcom_resume(qcom, true); 1007 } 1008 1009 static const struct dev_pm_ops dwc3_qcom_dev_pm_ops = { 1010 SET_SYSTEM_SLEEP_PM_OPS(dwc3_qcom_pm_suspend, dwc3_qcom_pm_resume) 1011 SET_RUNTIME_PM_OPS(dwc3_qcom_runtime_suspend, dwc3_qcom_runtime_resume, 1012 NULL) 1013 }; 1014 1015 static const struct of_device_id dwc3_qcom_of_match[] = { 1016 { .compatible = "qcom,dwc3" }, 1017 { } 1018 }; 1019 MODULE_DEVICE_TABLE(of, dwc3_qcom_of_match); 1020 1021 #ifdef CONFIG_ACPI 1022 static const struct dwc3_acpi_pdata sdm845_acpi_pdata = { 1023 .qscratch_base_offset = SDM845_QSCRATCH_BASE_OFFSET, 1024 .qscratch_base_size = SDM845_QSCRATCH_SIZE, 1025 .dwc3_core_base_size = SDM845_DWC3_CORE_SIZE, 1026 .hs_phy_irq_index = 1, 1027 .dp_hs_phy_irq_index = 4, 1028 .dm_hs_phy_irq_index = 3, 1029 .ss_phy_irq_index = 2 1030 }; 1031 1032 static const struct dwc3_acpi_pdata sdm845_acpi_urs_pdata = { 1033 .qscratch_base_offset = SDM845_QSCRATCH_BASE_OFFSET, 1034 .qscratch_base_size = SDM845_QSCRATCH_SIZE, 1035 .dwc3_core_base_size = SDM845_DWC3_CORE_SIZE, 1036 .hs_phy_irq_index = 1, 1037 .dp_hs_phy_irq_index = 4, 1038 .dm_hs_phy_irq_index = 3, 1039 .ss_phy_irq_index = 2, 1040 .is_urs = true, 1041 }; 1042 1043 static const struct acpi_device_id dwc3_qcom_acpi_match[] = { 1044 { "QCOM2430", (unsigned long)&sdm845_acpi_pdata }, 1045 { "QCOM0304", (unsigned long)&sdm845_acpi_urs_pdata }, 1046 { "QCOM0497", (unsigned long)&sdm845_acpi_urs_pdata }, 1047 { "QCOM04A6", (unsigned long)&sdm845_acpi_pdata }, 1048 { }, 1049 }; 1050 MODULE_DEVICE_TABLE(acpi, dwc3_qcom_acpi_match); 1051 #endif 1052 1053 static struct platform_driver dwc3_qcom_driver = { 1054 .probe = dwc3_qcom_probe, 1055 .remove = dwc3_qcom_remove, 1056 .driver = { 1057 .name = "dwc3-qcom", 1058 .pm = &dwc3_qcom_dev_pm_ops, 1059 .of_match_table = dwc3_qcom_of_match, 1060 .acpi_match_table = ACPI_PTR(dwc3_qcom_acpi_match), 1061 }, 1062 }; 1063 1064 module_platform_driver(dwc3_qcom_driver); 1065 1066 MODULE_LICENSE("GPL v2"); 1067 MODULE_DESCRIPTION("DesignWare DWC3 QCOM Glue Driver"); 1068