1 // SPDX-License-Identifier: GPL-2.0 2 /* Copyright (c) 2018, The Linux Foundation. All rights reserved. 3 * 4 * Inspired by dwc3-of-simple.c 5 */ 6 7 #include <linux/acpi.h> 8 #include <linux/io.h> 9 #include <linux/of.h> 10 #include <linux/clk.h> 11 #include <linux/irq.h> 12 #include <linux/of_clk.h> 13 #include <linux/module.h> 14 #include <linux/kernel.h> 15 #include <linux/extcon.h> 16 #include <linux/interconnect.h> 17 #include <linux/of_platform.h> 18 #include <linux/platform_device.h> 19 #include <linux/phy/phy.h> 20 #include <linux/usb/of.h> 21 #include <linux/reset.h> 22 #include <linux/iopoll.h> 23 24 #include "core.h" 25 26 /* USB QSCRATCH Hardware registers */ 27 #define QSCRATCH_HS_PHY_CTRL 0x10 28 #define UTMI_OTG_VBUS_VALID BIT(20) 29 #define SW_SESSVLD_SEL BIT(28) 30 31 #define QSCRATCH_SS_PHY_CTRL 0x30 32 #define LANE0_PWR_PRESENT BIT(24) 33 34 #define QSCRATCH_GENERAL_CFG 0x08 35 #define PIPE_UTMI_CLK_SEL BIT(0) 36 #define PIPE3_PHYSTATUS_SW BIT(3) 37 #define PIPE_UTMI_CLK_DIS BIT(8) 38 39 #define PWR_EVNT_IRQ_STAT_REG 0x58 40 #define PWR_EVNT_LPM_IN_L2_MASK BIT(4) 41 #define PWR_EVNT_LPM_OUT_L2_MASK BIT(5) 42 43 #define SDM845_QSCRATCH_BASE_OFFSET 0xf8800 44 #define SDM845_QSCRATCH_SIZE 0x400 45 #define SDM845_DWC3_CORE_SIZE 0xcd00 46 47 /* Interconnect path bandwidths in MBps */ 48 #define USB_MEMORY_AVG_HS_BW MBps_to_icc(240) 49 #define USB_MEMORY_PEAK_HS_BW MBps_to_icc(700) 50 #define USB_MEMORY_AVG_SS_BW MBps_to_icc(1000) 51 #define USB_MEMORY_PEAK_SS_BW MBps_to_icc(2500) 52 #define APPS_USB_AVG_BW 0 53 #define APPS_USB_PEAK_BW MBps_to_icc(40) 54 55 struct dwc3_acpi_pdata { 56 u32 qscratch_base_offset; 57 u32 qscratch_base_size; 58 u32 dwc3_core_base_size; 59 int hs_phy_irq_index; 60 int dp_hs_phy_irq_index; 61 int dm_hs_phy_irq_index; 62 int ss_phy_irq_index; 63 bool is_urs; 64 }; 65 66 struct dwc3_qcom { 67 struct device *dev; 68 void __iomem *qscratch_base; 69 struct platform_device *dwc3; 70 struct platform_device *urs_usb; 71 struct clk **clks; 72 int num_clocks; 73 struct reset_control *resets; 74 75 int hs_phy_irq; 76 int dp_hs_phy_irq; 77 int dm_hs_phy_irq; 78 int ss_phy_irq; 79 80 struct extcon_dev *edev; 81 struct extcon_dev *host_edev; 82 struct notifier_block vbus_nb; 83 struct notifier_block host_nb; 84 85 const struct dwc3_acpi_pdata *acpi_pdata; 86 87 enum usb_dr_mode mode; 88 bool is_suspended; 89 bool pm_suspended; 90 struct icc_path *icc_path_ddr; 91 struct icc_path *icc_path_apps; 92 }; 93 94 static inline void dwc3_qcom_setbits(void __iomem *base, u32 offset, u32 val) 95 { 96 u32 reg; 97 98 reg = readl(base + offset); 99 reg |= val; 100 writel(reg, base + offset); 101 102 /* ensure that above write is through */ 103 readl(base + offset); 104 } 105 106 static inline void dwc3_qcom_clrbits(void __iomem *base, u32 offset, u32 val) 107 { 108 u32 reg; 109 110 reg = readl(base + offset); 111 reg &= ~val; 112 writel(reg, base + offset); 113 114 /* ensure that above write is through */ 115 readl(base + offset); 116 } 117 118 static void dwc3_qcom_vbus_overrride_enable(struct dwc3_qcom *qcom, bool enable) 119 { 120 if (enable) { 121 dwc3_qcom_setbits(qcom->qscratch_base, QSCRATCH_SS_PHY_CTRL, 122 LANE0_PWR_PRESENT); 123 dwc3_qcom_setbits(qcom->qscratch_base, QSCRATCH_HS_PHY_CTRL, 124 UTMI_OTG_VBUS_VALID | SW_SESSVLD_SEL); 125 } else { 126 dwc3_qcom_clrbits(qcom->qscratch_base, QSCRATCH_SS_PHY_CTRL, 127 LANE0_PWR_PRESENT); 128 dwc3_qcom_clrbits(qcom->qscratch_base, QSCRATCH_HS_PHY_CTRL, 129 UTMI_OTG_VBUS_VALID | SW_SESSVLD_SEL); 130 } 131 } 132 133 static int dwc3_qcom_vbus_notifier(struct notifier_block *nb, 134 unsigned long event, void *ptr) 135 { 136 struct dwc3_qcom *qcom = container_of(nb, struct dwc3_qcom, vbus_nb); 137 138 /* enable vbus override for device mode */ 139 dwc3_qcom_vbus_overrride_enable(qcom, event); 140 qcom->mode = event ? USB_DR_MODE_PERIPHERAL : USB_DR_MODE_HOST; 141 142 return NOTIFY_DONE; 143 } 144 145 static int dwc3_qcom_host_notifier(struct notifier_block *nb, 146 unsigned long event, void *ptr) 147 { 148 struct dwc3_qcom *qcom = container_of(nb, struct dwc3_qcom, host_nb); 149 150 /* disable vbus override in host mode */ 151 dwc3_qcom_vbus_overrride_enable(qcom, !event); 152 qcom->mode = event ? USB_DR_MODE_HOST : USB_DR_MODE_PERIPHERAL; 153 154 return NOTIFY_DONE; 155 } 156 157 static int dwc3_qcom_register_extcon(struct dwc3_qcom *qcom) 158 { 159 struct device *dev = qcom->dev; 160 struct extcon_dev *host_edev; 161 int ret; 162 163 if (!of_property_read_bool(dev->of_node, "extcon")) 164 return 0; 165 166 qcom->edev = extcon_get_edev_by_phandle(dev, 0); 167 if (IS_ERR(qcom->edev)) 168 return PTR_ERR(qcom->edev); 169 170 qcom->vbus_nb.notifier_call = dwc3_qcom_vbus_notifier; 171 172 qcom->host_edev = extcon_get_edev_by_phandle(dev, 1); 173 if (IS_ERR(qcom->host_edev)) 174 qcom->host_edev = NULL; 175 176 ret = devm_extcon_register_notifier(dev, qcom->edev, EXTCON_USB, 177 &qcom->vbus_nb); 178 if (ret < 0) { 179 dev_err(dev, "VBUS notifier register failed\n"); 180 return ret; 181 } 182 183 if (qcom->host_edev) 184 host_edev = qcom->host_edev; 185 else 186 host_edev = qcom->edev; 187 188 qcom->host_nb.notifier_call = dwc3_qcom_host_notifier; 189 ret = devm_extcon_register_notifier(dev, host_edev, EXTCON_USB_HOST, 190 &qcom->host_nb); 191 if (ret < 0) { 192 dev_err(dev, "Host notifier register failed\n"); 193 return ret; 194 } 195 196 /* Update initial VBUS override based on extcon state */ 197 if (extcon_get_state(qcom->edev, EXTCON_USB) || 198 !extcon_get_state(host_edev, EXTCON_USB_HOST)) 199 dwc3_qcom_vbus_notifier(&qcom->vbus_nb, true, qcom->edev); 200 else 201 dwc3_qcom_vbus_notifier(&qcom->vbus_nb, false, qcom->edev); 202 203 return 0; 204 } 205 206 static int dwc3_qcom_interconnect_enable(struct dwc3_qcom *qcom) 207 { 208 int ret; 209 210 ret = icc_enable(qcom->icc_path_ddr); 211 if (ret) 212 return ret; 213 214 ret = icc_enable(qcom->icc_path_apps); 215 if (ret) 216 icc_disable(qcom->icc_path_ddr); 217 218 return ret; 219 } 220 221 static int dwc3_qcom_interconnect_disable(struct dwc3_qcom *qcom) 222 { 223 int ret; 224 225 ret = icc_disable(qcom->icc_path_ddr); 226 if (ret) 227 return ret; 228 229 ret = icc_disable(qcom->icc_path_apps); 230 if (ret) 231 icc_enable(qcom->icc_path_ddr); 232 233 return ret; 234 } 235 236 /** 237 * dwc3_qcom_interconnect_init() - Get interconnect path handles 238 * and set bandwidhth. 239 * @qcom: Pointer to the concerned usb core. 240 * 241 */ 242 static int dwc3_qcom_interconnect_init(struct dwc3_qcom *qcom) 243 { 244 struct device *dev = qcom->dev; 245 int ret; 246 247 qcom->icc_path_ddr = of_icc_get(dev, "usb-ddr"); 248 if (IS_ERR(qcom->icc_path_ddr)) { 249 dev_err(dev, "failed to get usb-ddr path: %ld\n", 250 PTR_ERR(qcom->icc_path_ddr)); 251 return PTR_ERR(qcom->icc_path_ddr); 252 } 253 254 qcom->icc_path_apps = of_icc_get(dev, "apps-usb"); 255 if (IS_ERR(qcom->icc_path_apps)) { 256 dev_err(dev, "failed to get apps-usb path: %ld\n", 257 PTR_ERR(qcom->icc_path_apps)); 258 return PTR_ERR(qcom->icc_path_apps); 259 } 260 261 if (usb_get_maximum_speed(&qcom->dwc3->dev) >= USB_SPEED_SUPER || 262 usb_get_maximum_speed(&qcom->dwc3->dev) == USB_SPEED_UNKNOWN) 263 ret = icc_set_bw(qcom->icc_path_ddr, 264 USB_MEMORY_AVG_SS_BW, USB_MEMORY_PEAK_SS_BW); 265 else 266 ret = icc_set_bw(qcom->icc_path_ddr, 267 USB_MEMORY_AVG_HS_BW, USB_MEMORY_PEAK_HS_BW); 268 269 if (ret) { 270 dev_err(dev, "failed to set bandwidth for usb-ddr path: %d\n", ret); 271 return ret; 272 } 273 274 ret = icc_set_bw(qcom->icc_path_apps, 275 APPS_USB_AVG_BW, APPS_USB_PEAK_BW); 276 if (ret) { 277 dev_err(dev, "failed to set bandwidth for apps-usb path: %d\n", ret); 278 return ret; 279 } 280 281 return 0; 282 } 283 284 /** 285 * dwc3_qcom_interconnect_exit() - Release interconnect path handles 286 * @qcom: Pointer to the concerned usb core. 287 * 288 * This function is used to release interconnect path handle. 289 */ 290 static void dwc3_qcom_interconnect_exit(struct dwc3_qcom *qcom) 291 { 292 icc_put(qcom->icc_path_ddr); 293 icc_put(qcom->icc_path_apps); 294 } 295 296 static void dwc3_qcom_disable_interrupts(struct dwc3_qcom *qcom) 297 { 298 if (qcom->hs_phy_irq) { 299 disable_irq_wake(qcom->hs_phy_irq); 300 disable_irq_nosync(qcom->hs_phy_irq); 301 } 302 303 if (qcom->dp_hs_phy_irq) { 304 disable_irq_wake(qcom->dp_hs_phy_irq); 305 disable_irq_nosync(qcom->dp_hs_phy_irq); 306 } 307 308 if (qcom->dm_hs_phy_irq) { 309 disable_irq_wake(qcom->dm_hs_phy_irq); 310 disable_irq_nosync(qcom->dm_hs_phy_irq); 311 } 312 313 if (qcom->ss_phy_irq) { 314 disable_irq_wake(qcom->ss_phy_irq); 315 disable_irq_nosync(qcom->ss_phy_irq); 316 } 317 } 318 319 static void dwc3_qcom_enable_interrupts(struct dwc3_qcom *qcom) 320 { 321 if (qcom->hs_phy_irq) { 322 enable_irq(qcom->hs_phy_irq); 323 enable_irq_wake(qcom->hs_phy_irq); 324 } 325 326 if (qcom->dp_hs_phy_irq) { 327 enable_irq(qcom->dp_hs_phy_irq); 328 enable_irq_wake(qcom->dp_hs_phy_irq); 329 } 330 331 if (qcom->dm_hs_phy_irq) { 332 enable_irq(qcom->dm_hs_phy_irq); 333 enable_irq_wake(qcom->dm_hs_phy_irq); 334 } 335 336 if (qcom->ss_phy_irq) { 337 enable_irq(qcom->ss_phy_irq); 338 enable_irq_wake(qcom->ss_phy_irq); 339 } 340 } 341 342 static int dwc3_qcom_suspend(struct dwc3_qcom *qcom) 343 { 344 u32 val; 345 int i, ret; 346 347 if (qcom->is_suspended) 348 return 0; 349 350 val = readl(qcom->qscratch_base + PWR_EVNT_IRQ_STAT_REG); 351 if (!(val & PWR_EVNT_LPM_IN_L2_MASK)) 352 dev_err(qcom->dev, "HS-PHY not in L2\n"); 353 354 for (i = qcom->num_clocks - 1; i >= 0; i--) 355 clk_disable_unprepare(qcom->clks[i]); 356 357 ret = dwc3_qcom_interconnect_disable(qcom); 358 if (ret) 359 dev_warn(qcom->dev, "failed to disable interconnect: %d\n", ret); 360 361 if (device_may_wakeup(qcom->dev)) 362 dwc3_qcom_enable_interrupts(qcom); 363 364 qcom->is_suspended = true; 365 366 return 0; 367 } 368 369 static int dwc3_qcom_resume(struct dwc3_qcom *qcom) 370 { 371 int ret; 372 int i; 373 374 if (!qcom->is_suspended) 375 return 0; 376 377 if (device_may_wakeup(qcom->dev)) 378 dwc3_qcom_disable_interrupts(qcom); 379 380 for (i = 0; i < qcom->num_clocks; i++) { 381 ret = clk_prepare_enable(qcom->clks[i]); 382 if (ret < 0) { 383 while (--i >= 0) 384 clk_disable_unprepare(qcom->clks[i]); 385 return ret; 386 } 387 } 388 389 ret = dwc3_qcom_interconnect_enable(qcom); 390 if (ret) 391 dev_warn(qcom->dev, "failed to enable interconnect: %d\n", ret); 392 393 /* Clear existing events from PHY related to L2 in/out */ 394 dwc3_qcom_setbits(qcom->qscratch_base, PWR_EVNT_IRQ_STAT_REG, 395 PWR_EVNT_LPM_IN_L2_MASK | PWR_EVNT_LPM_OUT_L2_MASK); 396 397 qcom->is_suspended = false; 398 399 return 0; 400 } 401 402 static irqreturn_t qcom_dwc3_resume_irq(int irq, void *data) 403 { 404 struct dwc3_qcom *qcom = data; 405 struct dwc3 *dwc = platform_get_drvdata(qcom->dwc3); 406 407 /* If pm_suspended then let pm_resume take care of resuming h/w */ 408 if (qcom->pm_suspended) 409 return IRQ_HANDLED; 410 411 if (dwc->xhci) 412 pm_runtime_resume(&dwc->xhci->dev); 413 414 return IRQ_HANDLED; 415 } 416 417 static void dwc3_qcom_select_utmi_clk(struct dwc3_qcom *qcom) 418 { 419 /* Configure dwc3 to use UTMI clock as PIPE clock not present */ 420 dwc3_qcom_setbits(qcom->qscratch_base, QSCRATCH_GENERAL_CFG, 421 PIPE_UTMI_CLK_DIS); 422 423 usleep_range(100, 1000); 424 425 dwc3_qcom_setbits(qcom->qscratch_base, QSCRATCH_GENERAL_CFG, 426 PIPE_UTMI_CLK_SEL | PIPE3_PHYSTATUS_SW); 427 428 usleep_range(100, 1000); 429 430 dwc3_qcom_clrbits(qcom->qscratch_base, QSCRATCH_GENERAL_CFG, 431 PIPE_UTMI_CLK_DIS); 432 } 433 434 static int dwc3_qcom_get_irq(struct platform_device *pdev, 435 const char *name, int num) 436 { 437 struct dwc3_qcom *qcom = platform_get_drvdata(pdev); 438 struct platform_device *pdev_irq = qcom->urs_usb ? qcom->urs_usb : pdev; 439 struct device_node *np = pdev->dev.of_node; 440 int ret; 441 442 if (np) 443 ret = platform_get_irq_byname(pdev_irq, name); 444 else 445 ret = platform_get_irq(pdev_irq, num); 446 447 return ret; 448 } 449 450 static int dwc3_qcom_setup_irq(struct platform_device *pdev) 451 { 452 struct dwc3_qcom *qcom = platform_get_drvdata(pdev); 453 const struct dwc3_acpi_pdata *pdata = qcom->acpi_pdata; 454 int irq; 455 int ret; 456 457 irq = dwc3_qcom_get_irq(pdev, "hs_phy_irq", 458 pdata ? pdata->hs_phy_irq_index : -1); 459 if (irq > 0) { 460 /* Keep wakeup interrupts disabled until suspend */ 461 irq_set_status_flags(irq, IRQ_NOAUTOEN); 462 ret = devm_request_threaded_irq(qcom->dev, irq, NULL, 463 qcom_dwc3_resume_irq, 464 IRQF_TRIGGER_HIGH | IRQF_ONESHOT, 465 "qcom_dwc3 HS", qcom); 466 if (ret) { 467 dev_err(qcom->dev, "hs_phy_irq failed: %d\n", ret); 468 return ret; 469 } 470 qcom->hs_phy_irq = irq; 471 } 472 473 irq = dwc3_qcom_get_irq(pdev, "dp_hs_phy_irq", 474 pdata ? pdata->dp_hs_phy_irq_index : -1); 475 if (irq > 0) { 476 irq_set_status_flags(irq, IRQ_NOAUTOEN); 477 ret = devm_request_threaded_irq(qcom->dev, irq, NULL, 478 qcom_dwc3_resume_irq, 479 IRQF_TRIGGER_HIGH | IRQF_ONESHOT, 480 "qcom_dwc3 DP_HS", qcom); 481 if (ret) { 482 dev_err(qcom->dev, "dp_hs_phy_irq failed: %d\n", ret); 483 return ret; 484 } 485 qcom->dp_hs_phy_irq = irq; 486 } 487 488 irq = dwc3_qcom_get_irq(pdev, "dm_hs_phy_irq", 489 pdata ? pdata->dm_hs_phy_irq_index : -1); 490 if (irq > 0) { 491 irq_set_status_flags(irq, IRQ_NOAUTOEN); 492 ret = devm_request_threaded_irq(qcom->dev, irq, NULL, 493 qcom_dwc3_resume_irq, 494 IRQF_TRIGGER_HIGH | IRQF_ONESHOT, 495 "qcom_dwc3 DM_HS", qcom); 496 if (ret) { 497 dev_err(qcom->dev, "dm_hs_phy_irq failed: %d\n", ret); 498 return ret; 499 } 500 qcom->dm_hs_phy_irq = irq; 501 } 502 503 irq = dwc3_qcom_get_irq(pdev, "ss_phy_irq", 504 pdata ? pdata->ss_phy_irq_index : -1); 505 if (irq > 0) { 506 irq_set_status_flags(irq, IRQ_NOAUTOEN); 507 ret = devm_request_threaded_irq(qcom->dev, irq, NULL, 508 qcom_dwc3_resume_irq, 509 IRQF_TRIGGER_HIGH | IRQF_ONESHOT, 510 "qcom_dwc3 SS", qcom); 511 if (ret) { 512 dev_err(qcom->dev, "ss_phy_irq failed: %d\n", ret); 513 return ret; 514 } 515 qcom->ss_phy_irq = irq; 516 } 517 518 return 0; 519 } 520 521 static int dwc3_qcom_clk_init(struct dwc3_qcom *qcom, int count) 522 { 523 struct device *dev = qcom->dev; 524 struct device_node *np = dev->of_node; 525 int i; 526 527 if (!np || !count) 528 return 0; 529 530 if (count < 0) 531 return count; 532 533 qcom->num_clocks = count; 534 535 qcom->clks = devm_kcalloc(dev, qcom->num_clocks, 536 sizeof(struct clk *), GFP_KERNEL); 537 if (!qcom->clks) 538 return -ENOMEM; 539 540 for (i = 0; i < qcom->num_clocks; i++) { 541 struct clk *clk; 542 int ret; 543 544 clk = of_clk_get(np, i); 545 if (IS_ERR(clk)) { 546 while (--i >= 0) 547 clk_put(qcom->clks[i]); 548 return PTR_ERR(clk); 549 } 550 551 ret = clk_prepare_enable(clk); 552 if (ret < 0) { 553 while (--i >= 0) { 554 clk_disable_unprepare(qcom->clks[i]); 555 clk_put(qcom->clks[i]); 556 } 557 clk_put(clk); 558 559 return ret; 560 } 561 562 qcom->clks[i] = clk; 563 } 564 565 return 0; 566 } 567 568 static const struct property_entry dwc3_qcom_acpi_properties[] = { 569 PROPERTY_ENTRY_STRING("dr_mode", "host"), 570 {} 571 }; 572 573 static const struct software_node dwc3_qcom_swnode = { 574 .properties = dwc3_qcom_acpi_properties, 575 }; 576 577 static int dwc3_qcom_acpi_register_core(struct platform_device *pdev) 578 { 579 struct dwc3_qcom *qcom = platform_get_drvdata(pdev); 580 struct device *dev = &pdev->dev; 581 struct resource *res, *child_res = NULL; 582 struct platform_device *pdev_irq = qcom->urs_usb ? qcom->urs_usb : 583 pdev; 584 int irq; 585 int ret; 586 587 qcom->dwc3 = platform_device_alloc("dwc3", PLATFORM_DEVID_AUTO); 588 if (!qcom->dwc3) 589 return -ENOMEM; 590 591 qcom->dwc3->dev.parent = dev; 592 qcom->dwc3->dev.type = dev->type; 593 qcom->dwc3->dev.dma_mask = dev->dma_mask; 594 qcom->dwc3->dev.dma_parms = dev->dma_parms; 595 qcom->dwc3->dev.coherent_dma_mask = dev->coherent_dma_mask; 596 597 child_res = kcalloc(2, sizeof(*child_res), GFP_KERNEL); 598 if (!child_res) 599 return -ENOMEM; 600 601 res = platform_get_resource(pdev, IORESOURCE_MEM, 0); 602 if (!res) { 603 dev_err(&pdev->dev, "failed to get memory resource\n"); 604 ret = -ENODEV; 605 goto out; 606 } 607 608 child_res[0].flags = res->flags; 609 child_res[0].start = res->start; 610 child_res[0].end = child_res[0].start + 611 qcom->acpi_pdata->dwc3_core_base_size; 612 613 irq = platform_get_irq(pdev_irq, 0); 614 child_res[1].flags = IORESOURCE_IRQ; 615 child_res[1].start = child_res[1].end = irq; 616 617 ret = platform_device_add_resources(qcom->dwc3, child_res, 2); 618 if (ret) { 619 dev_err(&pdev->dev, "failed to add resources\n"); 620 goto out; 621 } 622 623 ret = device_add_software_node(&qcom->dwc3->dev, &dwc3_qcom_swnode); 624 if (ret < 0) { 625 dev_err(&pdev->dev, "failed to add properties\n"); 626 goto out; 627 } 628 629 ret = platform_device_add(qcom->dwc3); 630 if (ret) { 631 dev_err(&pdev->dev, "failed to add device\n"); 632 device_remove_software_node(&qcom->dwc3->dev); 633 } 634 635 out: 636 kfree(child_res); 637 return ret; 638 } 639 640 static int dwc3_qcom_of_register_core(struct platform_device *pdev) 641 { 642 struct dwc3_qcom *qcom = platform_get_drvdata(pdev); 643 struct device_node *np = pdev->dev.of_node, *dwc3_np; 644 struct device *dev = &pdev->dev; 645 int ret; 646 647 dwc3_np = of_get_child_by_name(np, "dwc3"); 648 if (!dwc3_np) { 649 dev_err(dev, "failed to find dwc3 core child\n"); 650 return -ENODEV; 651 } 652 653 ret = of_platform_populate(np, NULL, NULL, dev); 654 if (ret) { 655 dev_err(dev, "failed to register dwc3 core - %d\n", ret); 656 goto node_put; 657 } 658 659 qcom->dwc3 = of_find_device_by_node(dwc3_np); 660 if (!qcom->dwc3) { 661 ret = -ENODEV; 662 dev_err(dev, "failed to get dwc3 platform device\n"); 663 } 664 665 node_put: 666 of_node_put(dwc3_np); 667 668 return ret; 669 } 670 671 static struct platform_device * 672 dwc3_qcom_create_urs_usb_platdev(struct device *dev) 673 { 674 struct fwnode_handle *fwh; 675 struct acpi_device *adev; 676 char name[8]; 677 int ret; 678 int id; 679 680 /* Figure out device id */ 681 ret = sscanf(fwnode_get_name(dev->fwnode), "URS%d", &id); 682 if (!ret) 683 return NULL; 684 685 /* Find the child using name */ 686 snprintf(name, sizeof(name), "USB%d", id); 687 fwh = fwnode_get_named_child_node(dev->fwnode, name); 688 if (!fwh) 689 return NULL; 690 691 adev = to_acpi_device_node(fwh); 692 if (!adev) 693 return NULL; 694 695 return acpi_create_platform_device(adev, NULL); 696 } 697 698 static int dwc3_qcom_probe(struct platform_device *pdev) 699 { 700 struct device_node *np = pdev->dev.of_node; 701 struct device *dev = &pdev->dev; 702 struct dwc3_qcom *qcom; 703 struct resource *res, *parent_res = NULL; 704 int ret, i; 705 bool ignore_pipe_clk; 706 707 qcom = devm_kzalloc(&pdev->dev, sizeof(*qcom), GFP_KERNEL); 708 if (!qcom) 709 return -ENOMEM; 710 711 platform_set_drvdata(pdev, qcom); 712 qcom->dev = &pdev->dev; 713 714 if (has_acpi_companion(dev)) { 715 qcom->acpi_pdata = acpi_device_get_match_data(dev); 716 if (!qcom->acpi_pdata) { 717 dev_err(&pdev->dev, "no supporting ACPI device data\n"); 718 return -EINVAL; 719 } 720 } 721 722 qcom->resets = devm_reset_control_array_get_optional_exclusive(dev); 723 if (IS_ERR(qcom->resets)) { 724 ret = PTR_ERR(qcom->resets); 725 dev_err(&pdev->dev, "failed to get resets, err=%d\n", ret); 726 return ret; 727 } 728 729 ret = reset_control_assert(qcom->resets); 730 if (ret) { 731 dev_err(&pdev->dev, "failed to assert resets, err=%d\n", ret); 732 return ret; 733 } 734 735 usleep_range(10, 1000); 736 737 ret = reset_control_deassert(qcom->resets); 738 if (ret) { 739 dev_err(&pdev->dev, "failed to deassert resets, err=%d\n", ret); 740 goto reset_assert; 741 } 742 743 ret = dwc3_qcom_clk_init(qcom, of_clk_get_parent_count(np)); 744 if (ret) { 745 dev_err(dev, "failed to get clocks\n"); 746 goto reset_assert; 747 } 748 749 res = platform_get_resource(pdev, IORESOURCE_MEM, 0); 750 751 if (np) { 752 parent_res = res; 753 } else { 754 parent_res = kmemdup(res, sizeof(struct resource), GFP_KERNEL); 755 if (!parent_res) 756 return -ENOMEM; 757 758 parent_res->start = res->start + 759 qcom->acpi_pdata->qscratch_base_offset; 760 parent_res->end = parent_res->start + 761 qcom->acpi_pdata->qscratch_base_size; 762 763 if (qcom->acpi_pdata->is_urs) { 764 qcom->urs_usb = dwc3_qcom_create_urs_usb_platdev(dev); 765 if (!qcom->urs_usb) { 766 dev_err(dev, "failed to create URS USB platdev\n"); 767 return -ENODEV; 768 } 769 } 770 } 771 772 qcom->qscratch_base = devm_ioremap_resource(dev, parent_res); 773 if (IS_ERR(qcom->qscratch_base)) { 774 dev_err(dev, "failed to map qscratch, err=%d\n", ret); 775 ret = PTR_ERR(qcom->qscratch_base); 776 goto clk_disable; 777 } 778 779 ret = dwc3_qcom_setup_irq(pdev); 780 if (ret) { 781 dev_err(dev, "failed to setup IRQs, err=%d\n", ret); 782 goto clk_disable; 783 } 784 785 /* 786 * Disable pipe_clk requirement if specified. Used when dwc3 787 * operates without SSPHY and only HS/FS/LS modes are supported. 788 */ 789 ignore_pipe_clk = device_property_read_bool(dev, 790 "qcom,select-utmi-as-pipe-clk"); 791 if (ignore_pipe_clk) 792 dwc3_qcom_select_utmi_clk(qcom); 793 794 if (np) 795 ret = dwc3_qcom_of_register_core(pdev); 796 else 797 ret = dwc3_qcom_acpi_register_core(pdev); 798 799 if (ret) { 800 dev_err(dev, "failed to register DWC3 Core, err=%d\n", ret); 801 goto depopulate; 802 } 803 804 ret = dwc3_qcom_interconnect_init(qcom); 805 if (ret) 806 goto depopulate; 807 808 qcom->mode = usb_get_dr_mode(&qcom->dwc3->dev); 809 810 /* enable vbus override for device mode */ 811 if (qcom->mode == USB_DR_MODE_PERIPHERAL) 812 dwc3_qcom_vbus_overrride_enable(qcom, true); 813 814 /* register extcon to override sw_vbus on Vbus change later */ 815 ret = dwc3_qcom_register_extcon(qcom); 816 if (ret) 817 goto interconnect_exit; 818 819 device_init_wakeup(&pdev->dev, 1); 820 qcom->is_suspended = false; 821 pm_runtime_set_active(dev); 822 pm_runtime_enable(dev); 823 pm_runtime_forbid(dev); 824 825 return 0; 826 827 interconnect_exit: 828 dwc3_qcom_interconnect_exit(qcom); 829 depopulate: 830 if (np) 831 of_platform_depopulate(&pdev->dev); 832 else 833 platform_device_put(pdev); 834 clk_disable: 835 for (i = qcom->num_clocks - 1; i >= 0; i--) { 836 clk_disable_unprepare(qcom->clks[i]); 837 clk_put(qcom->clks[i]); 838 } 839 reset_assert: 840 reset_control_assert(qcom->resets); 841 842 return ret; 843 } 844 845 static int dwc3_qcom_remove(struct platform_device *pdev) 846 { 847 struct dwc3_qcom *qcom = platform_get_drvdata(pdev); 848 struct device *dev = &pdev->dev; 849 int i; 850 851 device_remove_software_node(&qcom->dwc3->dev); 852 of_platform_depopulate(dev); 853 854 for (i = qcom->num_clocks - 1; i >= 0; i--) { 855 clk_disable_unprepare(qcom->clks[i]); 856 clk_put(qcom->clks[i]); 857 } 858 qcom->num_clocks = 0; 859 860 dwc3_qcom_interconnect_exit(qcom); 861 reset_control_assert(qcom->resets); 862 863 pm_runtime_allow(dev); 864 pm_runtime_disable(dev); 865 866 return 0; 867 } 868 869 static int __maybe_unused dwc3_qcom_pm_suspend(struct device *dev) 870 { 871 struct dwc3_qcom *qcom = dev_get_drvdata(dev); 872 int ret = 0; 873 874 ret = dwc3_qcom_suspend(qcom); 875 if (!ret) 876 qcom->pm_suspended = true; 877 878 return ret; 879 } 880 881 static int __maybe_unused dwc3_qcom_pm_resume(struct device *dev) 882 { 883 struct dwc3_qcom *qcom = dev_get_drvdata(dev); 884 int ret; 885 886 ret = dwc3_qcom_resume(qcom); 887 if (!ret) 888 qcom->pm_suspended = false; 889 890 return ret; 891 } 892 893 static int __maybe_unused dwc3_qcom_runtime_suspend(struct device *dev) 894 { 895 struct dwc3_qcom *qcom = dev_get_drvdata(dev); 896 897 return dwc3_qcom_suspend(qcom); 898 } 899 900 static int __maybe_unused dwc3_qcom_runtime_resume(struct device *dev) 901 { 902 struct dwc3_qcom *qcom = dev_get_drvdata(dev); 903 904 return dwc3_qcom_resume(qcom); 905 } 906 907 static const struct dev_pm_ops dwc3_qcom_dev_pm_ops = { 908 SET_SYSTEM_SLEEP_PM_OPS(dwc3_qcom_pm_suspend, dwc3_qcom_pm_resume) 909 SET_RUNTIME_PM_OPS(dwc3_qcom_runtime_suspend, dwc3_qcom_runtime_resume, 910 NULL) 911 }; 912 913 static const struct of_device_id dwc3_qcom_of_match[] = { 914 { .compatible = "qcom,dwc3" }, 915 { .compatible = "qcom,msm8996-dwc3" }, 916 { .compatible = "qcom,msm8998-dwc3" }, 917 { .compatible = "qcom,sdm845-dwc3" }, 918 { } 919 }; 920 MODULE_DEVICE_TABLE(of, dwc3_qcom_of_match); 921 922 #ifdef CONFIG_ACPI 923 static const struct dwc3_acpi_pdata sdm845_acpi_pdata = { 924 .qscratch_base_offset = SDM845_QSCRATCH_BASE_OFFSET, 925 .qscratch_base_size = SDM845_QSCRATCH_SIZE, 926 .dwc3_core_base_size = SDM845_DWC3_CORE_SIZE, 927 .hs_phy_irq_index = 1, 928 .dp_hs_phy_irq_index = 4, 929 .dm_hs_phy_irq_index = 3, 930 .ss_phy_irq_index = 2 931 }; 932 933 static const struct dwc3_acpi_pdata sdm845_acpi_urs_pdata = { 934 .qscratch_base_offset = SDM845_QSCRATCH_BASE_OFFSET, 935 .qscratch_base_size = SDM845_QSCRATCH_SIZE, 936 .dwc3_core_base_size = SDM845_DWC3_CORE_SIZE, 937 .hs_phy_irq_index = 1, 938 .dp_hs_phy_irq_index = 4, 939 .dm_hs_phy_irq_index = 3, 940 .ss_phy_irq_index = 2, 941 .is_urs = true, 942 }; 943 944 static const struct acpi_device_id dwc3_qcom_acpi_match[] = { 945 { "QCOM2430", (unsigned long)&sdm845_acpi_pdata }, 946 { "QCOM0304", (unsigned long)&sdm845_acpi_urs_pdata }, 947 { "QCOM0497", (unsigned long)&sdm845_acpi_urs_pdata }, 948 { "QCOM04A6", (unsigned long)&sdm845_acpi_pdata }, 949 { }, 950 }; 951 MODULE_DEVICE_TABLE(acpi, dwc3_qcom_acpi_match); 952 #endif 953 954 static struct platform_driver dwc3_qcom_driver = { 955 .probe = dwc3_qcom_probe, 956 .remove = dwc3_qcom_remove, 957 .driver = { 958 .name = "dwc3-qcom", 959 .pm = &dwc3_qcom_dev_pm_ops, 960 .of_match_table = dwc3_qcom_of_match, 961 .acpi_match_table = ACPI_PTR(dwc3_qcom_acpi_match), 962 }, 963 }; 964 965 module_platform_driver(dwc3_qcom_driver); 966 967 MODULE_LICENSE("GPL v2"); 968 MODULE_DESCRIPTION("DesignWare DWC3 QCOM Glue Driver"); 969