1 // SPDX-License-Identifier: GPL-2.0 2 /** 3 * dwc3-pci.c - PCI Specific glue layer 4 * 5 * Copyright (C) 2010-2011 Texas Instruments Incorporated - http://www.ti.com 6 * 7 * Authors: Felipe Balbi <balbi@ti.com>, 8 * Sebastian Andrzej Siewior <bigeasy@linutronix.de> 9 */ 10 11 #include <linux/kernel.h> 12 #include <linux/module.h> 13 #include <linux/slab.h> 14 #include <linux/pci.h> 15 #include <linux/workqueue.h> 16 #include <linux/pm_runtime.h> 17 #include <linux/platform_device.h> 18 #include <linux/gpio/consumer.h> 19 #include <linux/gpio/machine.h> 20 #include <linux/acpi.h> 21 #include <linux/delay.h> 22 23 #define PCI_DEVICE_ID_INTEL_BYT 0x0f37 24 #define PCI_DEVICE_ID_INTEL_MRFLD 0x119e 25 #define PCI_DEVICE_ID_INTEL_BSW 0x22b7 26 #define PCI_DEVICE_ID_INTEL_SPTLP 0x9d30 27 #define PCI_DEVICE_ID_INTEL_SPTH 0xa130 28 #define PCI_DEVICE_ID_INTEL_BXT 0x0aaa 29 #define PCI_DEVICE_ID_INTEL_BXT_M 0x1aaa 30 #define PCI_DEVICE_ID_INTEL_APL 0x5aaa 31 #define PCI_DEVICE_ID_INTEL_KBP 0xa2b0 32 #define PCI_DEVICE_ID_INTEL_CMLLP 0x02ee 33 #define PCI_DEVICE_ID_INTEL_CMLH 0x06ee 34 #define PCI_DEVICE_ID_INTEL_GLK 0x31aa 35 #define PCI_DEVICE_ID_INTEL_CNPLP 0x9dee 36 #define PCI_DEVICE_ID_INTEL_CNPH 0xa36e 37 #define PCI_DEVICE_ID_INTEL_CNPV 0xa3b0 38 #define PCI_DEVICE_ID_INTEL_ICLLP 0x34ee 39 #define PCI_DEVICE_ID_INTEL_EHLLP 0x4b7e 40 #define PCI_DEVICE_ID_INTEL_TGPLP 0xa0ee 41 42 #define PCI_INTEL_BXT_DSM_GUID "732b85d5-b7a7-4a1b-9ba0-4bbd00ffd511" 43 #define PCI_INTEL_BXT_FUNC_PMU_PWR 4 44 #define PCI_INTEL_BXT_STATE_D0 0 45 #define PCI_INTEL_BXT_STATE_D3 3 46 47 #define GP_RWBAR 1 48 #define GP_RWREG1 0xa0 49 #define GP_RWREG1_ULPI_REFCLK_DISABLE (1 << 17) 50 51 /** 52 * struct dwc3_pci - Driver private structure 53 * @dwc3: child dwc3 platform_device 54 * @pci: our link to PCI bus 55 * @guid: _DSM GUID 56 * @has_dsm_for_pm: true for devices which need to run _DSM on runtime PM 57 * @wakeup_work: work for asynchronous resume 58 */ 59 struct dwc3_pci { 60 struct platform_device *dwc3; 61 struct pci_dev *pci; 62 63 guid_t guid; 64 65 unsigned int has_dsm_for_pm:1; 66 struct work_struct wakeup_work; 67 }; 68 69 static const struct acpi_gpio_params reset_gpios = { 0, 0, false }; 70 static const struct acpi_gpio_params cs_gpios = { 1, 0, false }; 71 72 static const struct acpi_gpio_mapping acpi_dwc3_byt_gpios[] = { 73 { "reset-gpios", &reset_gpios, 1 }, 74 { "cs-gpios", &cs_gpios, 1 }, 75 { }, 76 }; 77 78 static struct gpiod_lookup_table platform_bytcr_gpios = { 79 .dev_id = "0000:00:16.0", 80 .table = { 81 GPIO_LOOKUP("INT33FC:00", 54, "reset", GPIO_ACTIVE_HIGH), 82 GPIO_LOOKUP("INT33FC:02", 14, "cs", GPIO_ACTIVE_HIGH), 83 {} 84 }, 85 }; 86 87 static int dwc3_byt_enable_ulpi_refclock(struct pci_dev *pci) 88 { 89 void __iomem *reg; 90 u32 value; 91 92 reg = pcim_iomap(pci, GP_RWBAR, 0); 93 if (!reg) 94 return -ENOMEM; 95 96 value = readl(reg + GP_RWREG1); 97 if (!(value & GP_RWREG1_ULPI_REFCLK_DISABLE)) 98 goto unmap; /* ULPI refclk already enabled */ 99 100 value &= ~GP_RWREG1_ULPI_REFCLK_DISABLE; 101 writel(value, reg + GP_RWREG1); 102 /* This comes from the Intel Android x86 tree w/o any explanation */ 103 msleep(100); 104 unmap: 105 pcim_iounmap(pci, reg); 106 return 0; 107 } 108 109 static const struct property_entry dwc3_pci_intel_properties[] = { 110 PROPERTY_ENTRY_STRING("dr_mode", "peripheral"), 111 PROPERTY_ENTRY_BOOL("linux,sysdev_is_parent"), 112 {} 113 }; 114 115 static const struct property_entry dwc3_pci_mrfld_properties[] = { 116 PROPERTY_ENTRY_STRING("dr_mode", "otg"), 117 PROPERTY_ENTRY_STRING("linux,extcon-name", "mrfld_bcove_pwrsrc"), 118 PROPERTY_ENTRY_BOOL("linux,sysdev_is_parent"), 119 {} 120 }; 121 122 static const struct property_entry dwc3_pci_amd_properties[] = { 123 PROPERTY_ENTRY_BOOL("snps,has-lpm-erratum"), 124 PROPERTY_ENTRY_U8("snps,lpm-nyet-threshold", 0xf), 125 PROPERTY_ENTRY_BOOL("snps,u2exit_lfps_quirk"), 126 PROPERTY_ENTRY_BOOL("snps,u2ss_inp3_quirk"), 127 PROPERTY_ENTRY_BOOL("snps,req_p1p2p3_quirk"), 128 PROPERTY_ENTRY_BOOL("snps,del_p1p2p3_quirk"), 129 PROPERTY_ENTRY_BOOL("snps,del_phy_power_chg_quirk"), 130 PROPERTY_ENTRY_BOOL("snps,lfps_filter_quirk"), 131 PROPERTY_ENTRY_BOOL("snps,rx_detect_poll_quirk"), 132 PROPERTY_ENTRY_BOOL("snps,tx_de_emphasis_quirk"), 133 PROPERTY_ENTRY_U8("snps,tx_de_emphasis", 1), 134 /* FIXME these quirks should be removed when AMD NL tapes out */ 135 PROPERTY_ENTRY_BOOL("snps,disable_scramble_quirk"), 136 PROPERTY_ENTRY_BOOL("snps,dis_u3_susphy_quirk"), 137 PROPERTY_ENTRY_BOOL("snps,dis_u2_susphy_quirk"), 138 PROPERTY_ENTRY_BOOL("linux,sysdev_is_parent"), 139 {} 140 }; 141 142 static int dwc3_pci_quirks(struct dwc3_pci *dwc) 143 { 144 struct pci_dev *pdev = dwc->pci; 145 146 if (pdev->vendor == PCI_VENDOR_ID_INTEL) { 147 if (pdev->device == PCI_DEVICE_ID_INTEL_BXT || 148 pdev->device == PCI_DEVICE_ID_INTEL_BXT_M) { 149 guid_parse(PCI_INTEL_BXT_DSM_GUID, &dwc->guid); 150 dwc->has_dsm_for_pm = true; 151 } 152 153 if (pdev->device == PCI_DEVICE_ID_INTEL_BYT) { 154 struct gpio_desc *gpio; 155 int ret; 156 157 /* On BYT the FW does not always enable the refclock */ 158 ret = dwc3_byt_enable_ulpi_refclock(pdev); 159 if (ret) 160 return ret; 161 162 ret = devm_acpi_dev_add_driver_gpios(&pdev->dev, 163 acpi_dwc3_byt_gpios); 164 if (ret) 165 dev_dbg(&pdev->dev, "failed to add mapping table\n"); 166 167 /* 168 * A lot of BYT devices lack ACPI resource entries for 169 * the GPIOs, add a fallback mapping to the reference 170 * design GPIOs which all boards seem to use. 171 */ 172 gpiod_add_lookup_table(&platform_bytcr_gpios); 173 174 /* 175 * These GPIOs will turn on the USB2 PHY. Note that we have to 176 * put the gpio descriptors again here because the phy driver 177 * might want to grab them, too. 178 */ 179 gpio = gpiod_get_optional(&pdev->dev, "cs", GPIOD_OUT_LOW); 180 if (IS_ERR(gpio)) 181 return PTR_ERR(gpio); 182 183 gpiod_set_value_cansleep(gpio, 1); 184 gpiod_put(gpio); 185 186 gpio = gpiod_get_optional(&pdev->dev, "reset", GPIOD_OUT_LOW); 187 if (IS_ERR(gpio)) 188 return PTR_ERR(gpio); 189 190 if (gpio) { 191 gpiod_set_value_cansleep(gpio, 1); 192 gpiod_put(gpio); 193 usleep_range(10000, 11000); 194 } 195 } 196 } 197 198 return 0; 199 } 200 201 #ifdef CONFIG_PM 202 static void dwc3_pci_resume_work(struct work_struct *work) 203 { 204 struct dwc3_pci *dwc = container_of(work, struct dwc3_pci, wakeup_work); 205 struct platform_device *dwc3 = dwc->dwc3; 206 int ret; 207 208 ret = pm_runtime_get_sync(&dwc3->dev); 209 if (ret) 210 return; 211 212 pm_runtime_mark_last_busy(&dwc3->dev); 213 pm_runtime_put_sync_autosuspend(&dwc3->dev); 214 } 215 #endif 216 217 static int dwc3_pci_probe(struct pci_dev *pci, const struct pci_device_id *id) 218 { 219 struct property_entry *p = (struct property_entry *)id->driver_data; 220 struct dwc3_pci *dwc; 221 struct resource res[2]; 222 int ret; 223 struct device *dev = &pci->dev; 224 225 ret = pcim_enable_device(pci); 226 if (ret) { 227 dev_err(dev, "failed to enable pci device\n"); 228 return -ENODEV; 229 } 230 231 pci_set_master(pci); 232 233 dwc = devm_kzalloc(dev, sizeof(*dwc), GFP_KERNEL); 234 if (!dwc) 235 return -ENOMEM; 236 237 dwc->dwc3 = platform_device_alloc("dwc3", PLATFORM_DEVID_AUTO); 238 if (!dwc->dwc3) 239 return -ENOMEM; 240 241 memset(res, 0x00, sizeof(struct resource) * ARRAY_SIZE(res)); 242 243 res[0].start = pci_resource_start(pci, 0); 244 res[0].end = pci_resource_end(pci, 0); 245 res[0].name = "dwc_usb3"; 246 res[0].flags = IORESOURCE_MEM; 247 248 res[1].start = pci->irq; 249 res[1].name = "dwc_usb3"; 250 res[1].flags = IORESOURCE_IRQ; 251 252 ret = platform_device_add_resources(dwc->dwc3, res, ARRAY_SIZE(res)); 253 if (ret) { 254 dev_err(dev, "couldn't add resources to dwc3 device\n"); 255 goto err; 256 } 257 258 dwc->pci = pci; 259 dwc->dwc3->dev.parent = dev; 260 ACPI_COMPANION_SET(&dwc->dwc3->dev, ACPI_COMPANION(dev)); 261 262 ret = platform_device_add_properties(dwc->dwc3, p); 263 if (ret < 0) 264 goto err; 265 266 ret = dwc3_pci_quirks(dwc); 267 if (ret) 268 goto err; 269 270 ret = platform_device_add(dwc->dwc3); 271 if (ret) { 272 dev_err(dev, "failed to register dwc3 device\n"); 273 goto err; 274 } 275 276 device_init_wakeup(dev, true); 277 pci_set_drvdata(pci, dwc); 278 pm_runtime_put(dev); 279 #ifdef CONFIG_PM 280 INIT_WORK(&dwc->wakeup_work, dwc3_pci_resume_work); 281 #endif 282 283 return 0; 284 err: 285 platform_device_put(dwc->dwc3); 286 return ret; 287 } 288 289 static void dwc3_pci_remove(struct pci_dev *pci) 290 { 291 struct dwc3_pci *dwc = pci_get_drvdata(pci); 292 struct pci_dev *pdev = dwc->pci; 293 294 if (pdev->device == PCI_DEVICE_ID_INTEL_BYT) 295 gpiod_remove_lookup_table(&platform_bytcr_gpios); 296 #ifdef CONFIG_PM 297 cancel_work_sync(&dwc->wakeup_work); 298 #endif 299 device_init_wakeup(&pci->dev, false); 300 pm_runtime_get(&pci->dev); 301 platform_device_unregister(dwc->dwc3); 302 } 303 304 static const struct pci_device_id dwc3_pci_id_table[] = { 305 { PCI_VDEVICE(INTEL, PCI_DEVICE_ID_INTEL_BSW), 306 (kernel_ulong_t) &dwc3_pci_intel_properties }, 307 308 { PCI_VDEVICE(INTEL, PCI_DEVICE_ID_INTEL_BYT), 309 (kernel_ulong_t) &dwc3_pci_intel_properties, }, 310 311 { PCI_VDEVICE(INTEL, PCI_DEVICE_ID_INTEL_MRFLD), 312 (kernel_ulong_t) &dwc3_pci_mrfld_properties, }, 313 314 { PCI_VDEVICE(INTEL, PCI_DEVICE_ID_INTEL_CMLLP), 315 (kernel_ulong_t) &dwc3_pci_intel_properties, }, 316 317 { PCI_VDEVICE(INTEL, PCI_DEVICE_ID_INTEL_CMLH), 318 (kernel_ulong_t) &dwc3_pci_intel_properties, }, 319 320 { PCI_VDEVICE(INTEL, PCI_DEVICE_ID_INTEL_SPTLP), 321 (kernel_ulong_t) &dwc3_pci_intel_properties, }, 322 323 { PCI_VDEVICE(INTEL, PCI_DEVICE_ID_INTEL_SPTH), 324 (kernel_ulong_t) &dwc3_pci_intel_properties, }, 325 326 { PCI_VDEVICE(INTEL, PCI_DEVICE_ID_INTEL_BXT), 327 (kernel_ulong_t) &dwc3_pci_intel_properties, }, 328 329 { PCI_VDEVICE(INTEL, PCI_DEVICE_ID_INTEL_BXT_M), 330 (kernel_ulong_t) &dwc3_pci_intel_properties, }, 331 332 { PCI_VDEVICE(INTEL, PCI_DEVICE_ID_INTEL_APL), 333 (kernel_ulong_t) &dwc3_pci_intel_properties, }, 334 335 { PCI_VDEVICE(INTEL, PCI_DEVICE_ID_INTEL_KBP), 336 (kernel_ulong_t) &dwc3_pci_intel_properties, }, 337 338 { PCI_VDEVICE(INTEL, PCI_DEVICE_ID_INTEL_GLK), 339 (kernel_ulong_t) &dwc3_pci_intel_properties, }, 340 341 { PCI_VDEVICE(INTEL, PCI_DEVICE_ID_INTEL_CNPLP), 342 (kernel_ulong_t) &dwc3_pci_intel_properties, }, 343 344 { PCI_VDEVICE(INTEL, PCI_DEVICE_ID_INTEL_CNPH), 345 (kernel_ulong_t) &dwc3_pci_intel_properties, }, 346 347 { PCI_VDEVICE(INTEL, PCI_DEVICE_ID_INTEL_CNPV), 348 (kernel_ulong_t) &dwc3_pci_intel_properties, }, 349 350 { PCI_VDEVICE(INTEL, PCI_DEVICE_ID_INTEL_ICLLP), 351 (kernel_ulong_t) &dwc3_pci_intel_properties, }, 352 353 { PCI_VDEVICE(INTEL, PCI_DEVICE_ID_INTEL_EHLLP), 354 (kernel_ulong_t) &dwc3_pci_intel_properties, }, 355 356 { PCI_VDEVICE(INTEL, PCI_DEVICE_ID_INTEL_TGPLP), 357 (kernel_ulong_t) &dwc3_pci_intel_properties, }, 358 359 { PCI_VDEVICE(AMD, PCI_DEVICE_ID_AMD_NL_USB), 360 (kernel_ulong_t) &dwc3_pci_amd_properties, }, 361 { } /* Terminating Entry */ 362 }; 363 MODULE_DEVICE_TABLE(pci, dwc3_pci_id_table); 364 365 #if defined(CONFIG_PM) || defined(CONFIG_PM_SLEEP) 366 static int dwc3_pci_dsm(struct dwc3_pci *dwc, int param) 367 { 368 union acpi_object *obj; 369 union acpi_object tmp; 370 union acpi_object argv4 = ACPI_INIT_DSM_ARGV4(1, &tmp); 371 372 if (!dwc->has_dsm_for_pm) 373 return 0; 374 375 tmp.type = ACPI_TYPE_INTEGER; 376 tmp.integer.value = param; 377 378 obj = acpi_evaluate_dsm(ACPI_HANDLE(&dwc->pci->dev), &dwc->guid, 379 1, PCI_INTEL_BXT_FUNC_PMU_PWR, &argv4); 380 if (!obj) { 381 dev_err(&dwc->pci->dev, "failed to evaluate _DSM\n"); 382 return -EIO; 383 } 384 385 ACPI_FREE(obj); 386 387 return 0; 388 } 389 #endif /* CONFIG_PM || CONFIG_PM_SLEEP */ 390 391 #ifdef CONFIG_PM 392 static int dwc3_pci_runtime_suspend(struct device *dev) 393 { 394 struct dwc3_pci *dwc = dev_get_drvdata(dev); 395 396 if (device_can_wakeup(dev)) 397 return dwc3_pci_dsm(dwc, PCI_INTEL_BXT_STATE_D3); 398 399 return -EBUSY; 400 } 401 402 static int dwc3_pci_runtime_resume(struct device *dev) 403 { 404 struct dwc3_pci *dwc = dev_get_drvdata(dev); 405 int ret; 406 407 ret = dwc3_pci_dsm(dwc, PCI_INTEL_BXT_STATE_D0); 408 if (ret) 409 return ret; 410 411 queue_work(pm_wq, &dwc->wakeup_work); 412 413 return 0; 414 } 415 #endif /* CONFIG_PM */ 416 417 #ifdef CONFIG_PM_SLEEP 418 static int dwc3_pci_suspend(struct device *dev) 419 { 420 struct dwc3_pci *dwc = dev_get_drvdata(dev); 421 422 return dwc3_pci_dsm(dwc, PCI_INTEL_BXT_STATE_D3); 423 } 424 425 static int dwc3_pci_resume(struct device *dev) 426 { 427 struct dwc3_pci *dwc = dev_get_drvdata(dev); 428 429 return dwc3_pci_dsm(dwc, PCI_INTEL_BXT_STATE_D0); 430 } 431 #endif /* CONFIG_PM_SLEEP */ 432 433 static const struct dev_pm_ops dwc3_pci_dev_pm_ops = { 434 SET_SYSTEM_SLEEP_PM_OPS(dwc3_pci_suspend, dwc3_pci_resume) 435 SET_RUNTIME_PM_OPS(dwc3_pci_runtime_suspend, dwc3_pci_runtime_resume, 436 NULL) 437 }; 438 439 static struct pci_driver dwc3_pci_driver = { 440 .name = "dwc3-pci", 441 .id_table = dwc3_pci_id_table, 442 .probe = dwc3_pci_probe, 443 .remove = dwc3_pci_remove, 444 .driver = { 445 .pm = &dwc3_pci_dev_pm_ops, 446 } 447 }; 448 449 MODULE_AUTHOR("Felipe Balbi <balbi@ti.com>"); 450 MODULE_LICENSE("GPL v2"); 451 MODULE_DESCRIPTION("DesignWare USB3 PCI Glue Layer"); 452 453 module_pci_driver(dwc3_pci_driver); 454